1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Felix Fietkau <nbd@nbd.name> 7 * Lorenzo Bianconi <lorenzo@kernel.org> 8 */ 9 10 #include <linux/devcoredump.h> 11 #include <linux/etherdevice.h> 12 #include <linux/timekeeping.h> 13 #include "mt7615.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 #include "mt7615_trace.h" 17 #include "mac.h" 18 #include "mcu.h" 19 20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 21 22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = { 23 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 }, 24 .radar_pattern = { 25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, 26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, 27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, 28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, 29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, 30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, 31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, 32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, 33 }, 34 }; 35 36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = { 37 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 }, 38 .radar_pattern = { 39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, 40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, 44 }, 45 }; 46 47 static const struct mt7615_dfs_radar_spec jp_radar_specs = { 48 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 }, 49 .radar_pattern = { 50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, 51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, 55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, 56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, 57 }, 58 }; 59 60 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, 61 u8 idx, bool unicast) 62 { 63 struct mt7615_sta *sta; 64 struct mt76_wcid *wcid; 65 66 if (idx >= MT7615_WTBL_SIZE) 67 return NULL; 68 69 wcid = rcu_dereference(dev->mt76.wcid[idx]); 70 if (unicast || !wcid) 71 return wcid; 72 73 if (!wcid->sta) 74 return NULL; 75 76 sta = container_of(wcid, struct mt7615_sta, wcid); 77 if (!sta->vif) 78 return NULL; 79 80 return &sta->vif->sta.wcid; 81 } 82 83 void mt7615_mac_reset_counters(struct mt7615_dev *dev) 84 { 85 int i; 86 87 for (i = 0; i < 4; i++) { 88 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 89 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); 90 } 91 92 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); 93 dev->mt76.phy.survey_time = ktime_get_boottime(); 94 if (dev->mt76.phy2) 95 dev->mt76.phy2->survey_time = ktime_get_boottime(); 96 97 /* reset airtime counters */ 98 mt76_rr(dev, MT_MIB_SDR9(0)); 99 mt76_rr(dev, MT_MIB_SDR9(1)); 100 101 mt76_rr(dev, MT_MIB_SDR36(0)); 102 mt76_rr(dev, MT_MIB_SDR36(1)); 103 104 mt76_rr(dev, MT_MIB_SDR37(0)); 105 mt76_rr(dev, MT_MIB_SDR37(1)); 106 107 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 108 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 109 } 110 111 void mt7615_mac_set_timing(struct mt7615_phy *phy) 112 { 113 s16 coverage_class = phy->coverage_class; 114 struct mt7615_dev *dev = phy->dev; 115 bool ext_phy = phy != &dev->phy; 116 u32 val, reg_offset; 117 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 119 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 120 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 121 int sifs, offset; 122 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 123 124 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 125 return; 126 127 if (is_5ghz) 128 sifs = 16; 129 else 130 sifs = 10; 131 132 if (ext_phy) { 133 coverage_class = max_t(s16, dev->phy.coverage_class, 134 coverage_class); 135 mt76_set(dev, MT_ARB_SCR, 136 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 137 } else { 138 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); 139 140 if (phy_ext) 141 coverage_class = max_t(s16, phy_ext->coverage_class, 142 coverage_class); 143 mt76_set(dev, MT_ARB_SCR, 144 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 145 } 146 udelay(1); 147 148 offset = 3 * coverage_class; 149 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 150 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 151 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); 152 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); 153 154 mt76_wr(dev, MT_TMAC_ICR(ext_phy), 155 FIELD_PREP(MT_IFS_EIFS, 360) | 156 FIELD_PREP(MT_IFS_RIFS, 2) | 157 FIELD_PREP(MT_IFS_SIFS, sifs) | 158 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 159 160 if (phy->slottime < 20 || is_5ghz) 161 val = MT7615_CFEND_RATE_DEFAULT; 162 else 163 val = MT7615_CFEND_RATE_11B; 164 165 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 166 if (ext_phy) 167 mt76_clear(dev, MT_ARB_SCR, 168 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 169 else 170 mt76_clear(dev, MT_ARB_SCR, 171 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 172 173 } 174 175 static void 176 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, 177 struct mt76_rx_status *status, u8 chfreq) 178 { 179 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 180 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 181 !test_bit(MT76_STATE_ROC, &mphy->state)) { 182 status->freq = mphy->chandef.chan->center_freq; 183 status->band = mphy->chandef.chan->band; 184 return; 185 } 186 187 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 188 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 189 } 190 191 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) 192 { 193 #ifdef CONFIG_NL80211_TESTMODE 194 u32 rxv1 = le32_to_cpu(rxv[0]); 195 u32 rxv3 = le32_to_cpu(rxv[2]); 196 u32 rxv4 = le32_to_cpu(rxv[3]); 197 u32 rxv5 = le32_to_cpu(rxv[4]); 198 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); 199 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); 200 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); 201 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; 202 203 if (!mode) { 204 /* CCK */ 205 foe &= ~BIT(11); 206 foe *= 1000; 207 foe >>= 11; 208 } else { 209 if (foe > 2048) 210 foe -= 4096; 211 212 foe = (foe * foe_const) >> 15; 213 } 214 215 phy->test.last_freq_offset = foe; 216 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); 217 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); 218 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); 219 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); 220 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); 221 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); 222 #endif 223 } 224 225 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) 226 { 227 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 228 struct mt76_phy *mphy = &dev->mt76.phy; 229 struct mt7615_phy *phy = &dev->phy; 230 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL; 231 struct ieee80211_supported_band *sband; 232 struct ieee80211_hdr *hdr; 233 __le32 *rxd = (__le32 *)skb->data; 234 u32 rxd0 = le32_to_cpu(rxd[0]); 235 u32 rxd1 = le32_to_cpu(rxd[1]); 236 u32 rxd2 = le32_to_cpu(rxd[2]); 237 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 238 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; 239 int phy_idx; 240 int i, idx; 241 u8 chfreq, amsdu_info, qos_ctl = 0; 242 u16 seq_ctrl = 0; 243 __le16 fc = 0; 244 245 memset(status, 0, sizeof(*status)); 246 247 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 248 if (!phy2) 249 phy_idx = 0; 250 else if (phy2->chfreq == phy->chfreq) 251 phy_idx = -1; 252 else if (phy->chfreq == chfreq) 253 phy_idx = 0; 254 else if (phy2->chfreq == chfreq) 255 phy_idx = 1; 256 else 257 phy_idx = -1; 258 259 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 260 return -EINVAL; 261 262 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; 263 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 264 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; 265 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); 266 267 if (status->wcid) { 268 struct mt7615_sta *msta; 269 270 msta = container_of(status->wcid, struct mt7615_sta, wcid); 271 spin_lock_bh(&dev->sta_poll_lock); 272 if (list_empty(&msta->poll_list)) 273 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 274 spin_unlock_bh(&dev->sta_poll_lock); 275 } 276 277 if ((rxd0 & csum_mask) == csum_mask) 278 skb->ip_summed = CHECKSUM_UNNECESSARY; 279 280 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 281 status->flag |= RX_FLAG_FAILED_FCS_CRC; 282 283 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 284 status->flag |= RX_FLAG_MMIC_ERROR; 285 286 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 287 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 288 status->flag |= RX_FLAG_DECRYPTED; 289 status->flag |= RX_FLAG_IV_STRIPPED; 290 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 291 } 292 293 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 294 295 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 296 return -EINVAL; 297 298 rxd += 4; 299 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 300 u32 v0 = le32_to_cpu(rxd[0]); 301 u32 v2 = le32_to_cpu(rxd[2]); 302 303 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); 304 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); 305 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); 306 307 rxd += 4; 308 if ((u8 *)rxd - skb->data >= skb->len) 309 return -EINVAL; 310 } 311 312 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 313 u8 *data = (u8 *)rxd; 314 315 if (status->flag & RX_FLAG_DECRYPTED) { 316 status->iv[0] = data[5]; 317 status->iv[1] = data[4]; 318 status->iv[2] = data[3]; 319 status->iv[3] = data[2]; 320 status->iv[4] = data[1]; 321 status->iv[5] = data[0]; 322 323 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 324 } 325 rxd += 4; 326 if ((u8 *)rxd - skb->data >= skb->len) 327 return -EINVAL; 328 } 329 330 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 331 status->timestamp = le32_to_cpu(rxd[0]); 332 status->flag |= RX_FLAG_MACTIME_START; 333 334 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 335 MT_RXD2_NORMAL_NON_AMPDU))) { 336 status->flag |= RX_FLAG_AMPDU_DETAILS; 337 338 /* all subframes of an A-MPDU have the same timestamp */ 339 if (phy->rx_ampdu_ts != status->timestamp) { 340 if (!++phy->ampdu_ref) 341 phy->ampdu_ref++; 342 } 343 phy->rx_ampdu_ts = status->timestamp; 344 345 status->ampdu_ref = phy->ampdu_ref; 346 } 347 348 rxd += 2; 349 if ((u8 *)rxd - skb->data >= skb->len) 350 return -EINVAL; 351 } 352 353 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 354 u32 rxdg5 = le32_to_cpu(rxd[5]); 355 356 /* 357 * If both PHYs are on the same channel and we don't have a WCID, 358 * we need to figure out which PHY this packet was received on. 359 * On the primary PHY, the noise value for the chains belonging to the 360 * second PHY will be set to the noise value of the last packet from 361 * that PHY. 362 */ 363 if (phy_idx < 0) { 364 int first_chain = ffs(phy2->mt76->chainmask) - 1; 365 366 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; 367 } 368 } 369 370 if (phy_idx == 1 && phy2) { 371 mphy = dev->mt76.phy2; 372 phy = phy2; 373 status->ext_phy = true; 374 } 375 376 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) 377 return -EINVAL; 378 379 mt7615_get_status_freq_info(dev, mphy, status, chfreq); 380 if (status->band == NL80211_BAND_5GHZ) 381 sband = &mphy->sband_5g.sband; 382 else 383 sband = &mphy->sband_2g.sband; 384 385 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 386 return -EINVAL; 387 388 if (!sband->channels) 389 return -EINVAL; 390 391 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 392 u32 rxdg0 = le32_to_cpu(rxd[0]); 393 u32 rxdg1 = le32_to_cpu(rxd[1]); 394 u32 rxdg3 = le32_to_cpu(rxd[3]); 395 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 396 bool cck = false; 397 398 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 399 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 400 case MT_PHY_TYPE_CCK: 401 cck = true; 402 fallthrough; 403 case MT_PHY_TYPE_OFDM: 404 i = mt76_get_rate(&dev->mt76, sband, i, cck); 405 break; 406 case MT_PHY_TYPE_HT_GF: 407 case MT_PHY_TYPE_HT: 408 status->encoding = RX_ENC_HT; 409 if (i > 31) 410 return -EINVAL; 411 break; 412 case MT_PHY_TYPE_VHT: 413 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; 414 status->encoding = RX_ENC_VHT; 415 break; 416 default: 417 return -EINVAL; 418 } 419 status->rate_idx = i; 420 421 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { 422 case MT_PHY_BW_20: 423 break; 424 case MT_PHY_BW_40: 425 status->bw = RATE_INFO_BW_40; 426 break; 427 case MT_PHY_BW_80: 428 status->bw = RATE_INFO_BW_80; 429 break; 430 case MT_PHY_BW_160: 431 status->bw = RATE_INFO_BW_160; 432 break; 433 default: 434 return -EINVAL; 435 } 436 437 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 438 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 439 if (rxdg0 & MT_RXV1_HT_AD_CODE) 440 status->enc_flags |= RX_ENC_FLAG_LDPC; 441 442 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 443 444 status->chains = mphy->antenna_mask; 445 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); 446 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); 447 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); 448 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); 449 status->signal = status->chain_signal[0]; 450 451 for (i = 1; i < hweight8(mphy->antenna_mask); i++) { 452 if (!(status->chains & BIT(i))) 453 continue; 454 455 status->signal = max(status->signal, 456 status->chain_signal[i]); 457 } 458 459 mt7615_mac_fill_tm_rx(mphy->priv, rxd); 460 461 rxd += 6; 462 if ((u8 *)rxd - skb->data >= skb->len) 463 return -EINVAL; 464 } 465 466 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 467 468 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); 469 status->amsdu = !!amsdu_info; 470 if (status->amsdu) { 471 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; 472 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; 473 if (!hdr_trans) { 474 memmove(skb->data + 2, skb->data, 475 ieee80211_get_hdrlen_from_skb(skb)); 476 skb_pull(skb, 2); 477 } 478 } 479 480 if (insert_ccmp_hdr && !hdr_trans) { 481 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 482 483 mt76_insert_ccmp_hdr(skb, key_id); 484 } 485 486 if (!hdr_trans) { 487 hdr = (struct ieee80211_hdr *)skb->data; 488 fc = hdr->frame_control; 489 if (ieee80211_is_data_qos(fc)) { 490 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 491 qos_ctl = *ieee80211_get_qos_ctl(hdr); 492 } 493 } else { 494 status->flag |= RX_FLAG_8023; 495 } 496 497 if (!status->wcid || !ieee80211_is_data_qos(fc)) 498 return 0; 499 500 status->aggr = unicast && 501 !ieee80211_is_qos_nullfunc(fc); 502 status->qos_ctl = qos_ctl; 503 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 504 505 return 0; 506 } 507 508 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 509 { 510 } 511 EXPORT_SYMBOL_GPL(mt7615_sta_ps); 512 513 static u16 514 mt7615_mac_tx_rate_val(struct mt7615_dev *dev, 515 struct mt76_phy *mphy, 516 const struct ieee80211_tx_rate *rate, 517 bool stbc, u8 *bw) 518 { 519 u8 phy, nss, rate_idx; 520 u16 rateval = 0; 521 522 *bw = 0; 523 524 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 525 rate_idx = ieee80211_rate_get_vht_mcs(rate); 526 nss = ieee80211_rate_get_vht_nss(rate); 527 phy = MT_PHY_TYPE_VHT; 528 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 529 *bw = 1; 530 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 531 *bw = 2; 532 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 533 *bw = 3; 534 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 535 rate_idx = rate->idx; 536 nss = 1 + (rate->idx >> 3); 537 phy = MT_PHY_TYPE_HT; 538 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 539 phy = MT_PHY_TYPE_HT_GF; 540 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 541 *bw = 1; 542 } else { 543 const struct ieee80211_rate *r; 544 int band = mphy->chandef.chan->band; 545 u16 val; 546 547 nss = 1; 548 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; 549 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 550 val = r->hw_value_short; 551 else 552 val = r->hw_value; 553 554 phy = val >> 8; 555 rate_idx = val & 0xff; 556 } 557 558 if (stbc && nss == 1) { 559 nss++; 560 rateval |= MT_TX_RATE_STBC; 561 } 562 563 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 564 FIELD_PREP(MT_TX_RATE_MODE, phy) | 565 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); 566 567 return rateval; 568 } 569 570 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, 571 struct sk_buff *skb, struct mt76_wcid *wcid, 572 struct ieee80211_sta *sta, int pid, 573 struct ieee80211_key_conf *key, bool beacon) 574 { 575 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 576 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 577 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 578 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 579 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 580 bool multicast = is_multicast_ether_addr(hdr->addr1); 581 struct ieee80211_vif *vif = info->control.vif; 582 bool is_mmio = mt76_is_mmio(&dev->mt76); 583 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; 584 struct mt76_phy *mphy = &dev->mphy; 585 __le16 fc = hdr->frame_control; 586 int tx_count = 8; 587 u16 seqno = 0; 588 589 if (vif) { 590 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 591 592 omac_idx = mvif->omac_idx; 593 wmm_idx = mvif->wmm_idx; 594 } 595 596 if (sta) { 597 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 598 599 tx_count = msta->rate_count; 600 } 601 602 if (ext_phy && dev->mt76.phy2) 603 mphy = dev->mt76.phy2; 604 605 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 606 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 607 608 if (beacon) { 609 p_fmt = MT_TX_TYPE_FW; 610 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0; 611 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 612 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 613 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; 614 } else { 615 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 616 q_idx = wmm_idx * MT7615_MAX_WMM_SETS + 617 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); 618 } 619 620 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 621 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | 622 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 623 txwi[0] = cpu_to_le32(val); 624 625 val = MT_TXD1_LONG_FORMAT | 626 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 627 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 628 FIELD_PREP(MT_TXD1_HDR_INFO, 629 ieee80211_get_hdrlen_from_skb(skb) / 2) | 630 FIELD_PREP(MT_TXD1_TID, 631 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 632 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | 633 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 634 txwi[1] = cpu_to_le32(val); 635 636 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 637 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 638 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 639 if (key) { 640 if (multicast && ieee80211_is_robust_mgmt_frame(skb) && 641 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 642 val |= MT_TXD2_BIP; 643 txwi[3] = 0; 644 } else { 645 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); 646 } 647 } else { 648 txwi[3] = 0; 649 } 650 txwi[2] = cpu_to_le32(val); 651 652 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 653 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 654 655 txwi[4] = 0; 656 txwi[6] = 0; 657 658 if (rate->idx >= 0 && rate->count && 659 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 660 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 661 u8 bw; 662 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, 663 &bw); 664 665 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 666 667 val = MT_TXD6_FIXED_BW | 668 FIELD_PREP(MT_TXD6_BW, bw) | 669 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 670 txwi[6] |= cpu_to_le32(val); 671 672 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 673 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 674 675 if (info->flags & IEEE80211_TX_CTL_LDPC) 676 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); 677 678 if (!(rate->flags & (IEEE80211_TX_RC_MCS | 679 IEEE80211_TX_RC_VHT_MCS))) 680 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 681 682 tx_count = rate->count; 683 } 684 685 if (!ieee80211_is_beacon(fc)) { 686 struct ieee80211_hw *hw = mt76_hw(dev); 687 688 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); 689 if (!ieee80211_hw_check(hw, SUPPORTS_PS)) 690 val |= MT_TXD5_SW_POWER_MGMT; 691 txwi[5] = cpu_to_le32(val); 692 } else { 693 txwi[5] = 0; 694 /* use maximum tx count for beacons */ 695 tx_count = 0x1f; 696 } 697 698 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 699 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 700 seqno = le16_to_cpu(hdr->seq_ctrl); 701 702 if (ieee80211_is_back_req(hdr->frame_control)) { 703 struct ieee80211_bar *bar; 704 705 bar = (struct ieee80211_bar *)skb->data; 706 seqno = le16_to_cpu(bar->start_seq_num); 707 } 708 709 val |= MT_TXD3_SN_VALID | 710 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 711 } 712 713 txwi[3] |= cpu_to_le32(val); 714 715 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 716 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); 717 718 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 719 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | 720 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); 721 if (!is_mmio) 722 txwi[8] = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | 723 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); 724 725 return 0; 726 } 727 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); 728 729 static void 730 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp) 731 { 732 int i; 733 734 for (i = 0; i < txp->nbuf; i++) 735 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 736 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 737 } 738 739 static void 740 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp) 741 { 742 u32 last_mask; 743 int i; 744 745 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST; 746 747 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) { 748 struct mt7615_txp_ptr *ptr = &txp->ptr[i]; 749 bool last; 750 u16 len; 751 752 len = le16_to_cpu(ptr->len0); 753 last = len & last_mask; 754 len &= MT_TXD_LEN_MASK; 755 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len, 756 DMA_TO_DEVICE); 757 if (last) 758 break; 759 760 len = le16_to_cpu(ptr->len1); 761 last = len & last_mask; 762 len &= MT_TXD_LEN_MASK; 763 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len, 764 DMA_TO_DEVICE); 765 if (last) 766 break; 767 } 768 } 769 770 void mt7615_txp_skb_unmap(struct mt76_dev *dev, 771 struct mt76_txwi_cache *t) 772 { 773 struct mt7615_txp_common *txp; 774 775 txp = mt7615_txwi_to_txp(dev, t); 776 if (is_mt7615(dev)) 777 mt7615_txp_skb_unmap_fw(dev, &txp->fw); 778 else 779 mt7615_txp_skb_unmap_hw(dev, &txp->hw); 780 } 781 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap); 782 783 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) 784 { 785 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 786 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 787 788 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 789 0, 5000); 790 } 791 792 void mt7615_mac_sta_poll(struct mt7615_dev *dev) 793 { 794 static const u8 ac_to_tid[4] = { 795 [IEEE80211_AC_BE] = 0, 796 [IEEE80211_AC_BK] = 1, 797 [IEEE80211_AC_VI] = 4, 798 [IEEE80211_AC_VO] = 6 799 }; 800 static const u8 hw_queue_map[] = { 801 [IEEE80211_AC_BK] = 0, 802 [IEEE80211_AC_BE] = 1, 803 [IEEE80211_AC_VI] = 2, 804 [IEEE80211_AC_VO] = 3, 805 }; 806 struct ieee80211_sta *sta; 807 struct mt7615_sta *msta; 808 u32 addr, tx_time[4], rx_time[4]; 809 struct list_head sta_poll_list; 810 int i; 811 812 INIT_LIST_HEAD(&sta_poll_list); 813 spin_lock_bh(&dev->sta_poll_lock); 814 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 815 spin_unlock_bh(&dev->sta_poll_lock); 816 817 while (!list_empty(&sta_poll_list)) { 818 bool clear = false; 819 820 msta = list_first_entry(&sta_poll_list, struct mt7615_sta, 821 poll_list); 822 list_del_init(&msta->poll_list); 823 824 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; 825 826 for (i = 0; i < 4; i++, addr += 8) { 827 u32 tx_last = msta->airtime_ac[i]; 828 u32 rx_last = msta->airtime_ac[i + 4]; 829 830 msta->airtime_ac[i] = mt76_rr(dev, addr); 831 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 832 tx_time[i] = msta->airtime_ac[i] - tx_last; 833 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 834 835 if ((tx_last | rx_last) & BIT(30)) 836 clear = true; 837 } 838 839 if (clear) { 840 mt7615_mac_wtbl_update(dev, msta->wcid.idx, 841 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 842 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 843 } 844 845 if (!msta->wcid.sta) 846 continue; 847 848 sta = container_of((void *)msta, struct ieee80211_sta, 849 drv_priv); 850 for (i = 0; i < 4; i++) { 851 u32 tx_cur = tx_time[i]; 852 u32 rx_cur = rx_time[hw_queue_map[i]]; 853 u8 tid = ac_to_tid[i]; 854 855 if (!tx_cur && !rx_cur) 856 continue; 857 858 ieee80211_sta_register_airtime(sta, tid, tx_cur, 859 rx_cur); 860 } 861 } 862 } 863 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); 864 865 static void 866 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, 867 struct ieee80211_tx_rate *probe_rate, 868 struct ieee80211_tx_rate *rates, 869 struct mt7615_rate_desc *rd) 870 { 871 struct mt7615_dev *dev = phy->dev; 872 struct mt76_phy *mphy = phy->mt76; 873 struct ieee80211_tx_rate *ref; 874 bool rateset, stbc = false; 875 int n_rates = sta->n_rates; 876 u8 bw, bw_prev; 877 int i, j; 878 879 for (i = n_rates; i < 4; i++) 880 rates[i] = rates[n_rates - 1]; 881 882 rateset = !(sta->rate_set_tsf & BIT(0)); 883 memcpy(sta->rateset[rateset].rates, rates, 884 sizeof(sta->rateset[rateset].rates)); 885 if (probe_rate) { 886 sta->rateset[rateset].probe_rate = *probe_rate; 887 ref = &sta->rateset[rateset].probe_rate; 888 } else { 889 sta->rateset[rateset].probe_rate.idx = -1; 890 ref = &sta->rateset[rateset].rates[0]; 891 } 892 893 rates = sta->rateset[rateset].rates; 894 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 895 /* 896 * We don't support switching between short and long GI 897 * within the rate set. For accurate tx status reporting, we 898 * need to make sure that flags match. 899 * For improved performance, avoid duplicate entries by 900 * decrementing the MCS index if necessary 901 */ 902 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 903 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 904 905 for (j = 0; j < i; j++) { 906 if (rates[i].idx != rates[j].idx) 907 continue; 908 if ((rates[i].flags ^ rates[j].flags) & 909 (IEEE80211_TX_RC_40_MHZ_WIDTH | 910 IEEE80211_TX_RC_80_MHZ_WIDTH | 911 IEEE80211_TX_RC_160_MHZ_WIDTH)) 912 continue; 913 914 if (!rates[i].idx) 915 continue; 916 917 rates[i].idx--; 918 } 919 } 920 921 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); 922 bw_prev = bw; 923 924 if (probe_rate) { 925 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, 926 stbc, &bw); 927 if (bw) 928 rd->bw_idx = 1; 929 else 930 bw_prev = 0; 931 } else { 932 rd->probe_val = rd->val[0]; 933 } 934 935 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); 936 if (bw_prev) { 937 rd->bw_idx = 3; 938 bw_prev = bw; 939 } 940 941 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); 942 if (bw_prev) { 943 rd->bw_idx = 5; 944 bw_prev = bw; 945 } 946 947 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); 948 if (bw_prev) 949 rd->bw_idx = 7; 950 951 rd->rateset = rateset; 952 rd->bw = bw; 953 } 954 955 static int 956 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, 957 struct ieee80211_tx_rate *probe_rate, 958 struct ieee80211_tx_rate *rates) 959 { 960 struct mt7615_dev *dev = phy->dev; 961 struct mt7615_wtbl_rate_desc *wrd; 962 963 if (work_pending(&dev->rate_work)) 964 return -EBUSY; 965 966 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); 967 if (!wrd) 968 return -ENOMEM; 969 970 wrd->sta = sta; 971 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, 972 &wrd->rate); 973 list_add_tail(&wrd->node, &dev->wrd_head); 974 queue_work(dev->mt76.wq, &dev->rate_work); 975 976 return 0; 977 } 978 979 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) 980 { 981 u32 addr, val, val2; 982 u8 offset; 983 984 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; 985 986 offset = tid * 12; 987 addr += 4 * (offset / 32); 988 offset %= 32; 989 990 val = mt76_rr(dev, addr); 991 val >>= (tid % 32); 992 993 if (offset > 20) { 994 addr += 4; 995 val2 = mt76_rr(dev, addr); 996 val |= val2 << (32 - offset); 997 } 998 999 return val & GENMASK(11, 0); 1000 } 1001 1002 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, 1003 struct ieee80211_tx_rate *probe_rate, 1004 struct ieee80211_tx_rate *rates) 1005 { 1006 int wcid = sta->wcid.idx, n_rates = sta->n_rates; 1007 struct mt7615_dev *dev = phy->dev; 1008 struct mt7615_rate_desc rd; 1009 u32 w5, w27, addr; 1010 u16 idx = sta->vif->mt76.omac_idx; 1011 1012 if (!mt76_is_mmio(&dev->mt76)) { 1013 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); 1014 return; 1015 } 1016 1017 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1018 return; 1019 1020 memset(&rd, 0, sizeof(struct mt7615_rate_desc)); 1021 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); 1022 1023 addr = mt7615_mac_wtbl_addr(dev, wcid); 1024 w27 = mt76_rr(dev, addr + 27 * 4); 1025 w27 &= ~MT_WTBL_W27_CC_BW_SEL; 1026 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); 1027 1028 w5 = mt76_rr(dev, addr + 5 * 4); 1029 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | 1030 MT_WTBL_W5_MPDU_OK_COUNT | 1031 MT_WTBL_W5_MPDU_FAIL_COUNT | 1032 MT_WTBL_W5_RATE_IDX); 1033 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | 1034 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, 1035 rd.bw_idx ? rd.bw_idx - 1 : 7); 1036 1037 mt76_wr(dev, MT_WTBL_RIUCR0, w5); 1038 1039 mt76_wr(dev, MT_WTBL_RIUCR1, 1040 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | 1041 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | 1042 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); 1043 1044 mt76_wr(dev, MT_WTBL_RIUCR2, 1045 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | 1046 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | 1047 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | 1048 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); 1049 1050 mt76_wr(dev, MT_WTBL_RIUCR3, 1051 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | 1052 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | 1053 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); 1054 1055 mt76_wr(dev, MT_WTBL_UPDATE, 1056 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 1057 MT_WTBL_UPDATE_RATE_UPDATE | 1058 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 1059 1060 mt76_wr(dev, addr + 27 * 4, w27); 1061 1062 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; 1063 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); 1064 1065 mt76_set(dev, addr, MT_LPON_TCR_MODE); /* TSF read */ 1066 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); 1067 sta->rate_set_tsf |= rd.rateset; 1068 1069 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 1070 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 1071 1072 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; 1073 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 1074 sta->rate_probe = !!probe_rate; 1075 } 1076 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); 1077 1078 static int 1079 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1080 struct ieee80211_key_conf *key, 1081 enum mt7615_cipher_type cipher, u16 cipher_mask, 1082 enum set_key_cmd cmd) 1083 { 1084 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; 1085 u8 data[32] = {}; 1086 1087 if (key->keylen > sizeof(data)) 1088 return -EINVAL; 1089 1090 mt76_rr_copy(dev, addr, data, sizeof(data)); 1091 if (cmd == SET_KEY) { 1092 if (cipher == MT_CIPHER_TKIP) { 1093 /* Rx/Tx MIC keys are swapped */ 1094 memcpy(data, key->key, 16); 1095 memcpy(data + 16, key->key + 24, 8); 1096 memcpy(data + 24, key->key + 16, 8); 1097 } else { 1098 if (cipher_mask == BIT(cipher)) 1099 memcpy(data, key->key, key->keylen); 1100 else if (cipher != MT_CIPHER_BIP_CMAC_128) 1101 memcpy(data, key->key, 16); 1102 if (cipher == MT_CIPHER_BIP_CMAC_128) 1103 memcpy(data + 16, key->key, 16); 1104 } 1105 } else { 1106 if (cipher == MT_CIPHER_BIP_CMAC_128) 1107 memset(data + 16, 0, 16); 1108 else if (cipher_mask) 1109 memset(data, 0, 16); 1110 if (!cipher_mask) 1111 memset(data, 0, sizeof(data)); 1112 } 1113 1114 mt76_wr_copy(dev, addr, data, sizeof(data)); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1121 enum mt7615_cipher_type cipher, u16 cipher_mask, 1122 int keyidx, enum set_key_cmd cmd) 1123 { 1124 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; 1125 1126 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1127 return -ETIMEDOUT; 1128 1129 w0 = mt76_rr(dev, addr); 1130 w1 = mt76_rr(dev, addr + 4); 1131 1132 if (cipher_mask) 1133 w0 |= MT_WTBL_W0_RX_KEY_VALID; 1134 else 1135 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); 1136 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) 1137 w0 |= MT_WTBL_W0_RX_IK_VALID; 1138 else 1139 w0 &= ~MT_WTBL_W0_RX_IK_VALID; 1140 1141 if (cmd == SET_KEY && 1142 (cipher != MT_CIPHER_BIP_CMAC_128 || 1143 cipher_mask == BIT(cipher))) { 1144 w0 &= ~MT_WTBL_W0_KEY_IDX; 1145 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); 1146 } 1147 1148 mt76_wr(dev, MT_WTBL_RICR0, w0); 1149 mt76_wr(dev, MT_WTBL_RICR1, w1); 1150 1151 if (!mt7615_mac_wtbl_update(dev, wcid->idx, 1152 MT_WTBL_UPDATE_RXINFO_UPDATE)) 1153 return -ETIMEDOUT; 1154 1155 return 0; 1156 } 1157 1158 static void 1159 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1160 enum mt7615_cipher_type cipher, u16 cipher_mask, 1161 enum set_key_cmd cmd) 1162 { 1163 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); 1164 1165 if (!cipher_mask) { 1166 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); 1167 return; 1168 } 1169 1170 if (cmd != SET_KEY) 1171 return; 1172 1173 if (cipher == MT_CIPHER_BIP_CMAC_128 && 1174 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) 1175 return; 1176 1177 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, 1178 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); 1179 } 1180 1181 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1182 struct mt76_wcid *wcid, 1183 struct ieee80211_key_conf *key, 1184 enum set_key_cmd cmd) 1185 { 1186 enum mt7615_cipher_type cipher; 1187 u16 cipher_mask = wcid->cipher; 1188 int err; 1189 1190 cipher = mt7615_mac_get_cipher(key->cipher); 1191 if (cipher == MT_CIPHER_NONE) 1192 return -EOPNOTSUPP; 1193 1194 if (cmd == SET_KEY) 1195 cipher_mask |= BIT(cipher); 1196 else 1197 cipher_mask &= ~BIT(cipher); 1198 1199 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd); 1200 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask, 1201 cmd); 1202 if (err < 0) 1203 return err; 1204 1205 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, 1206 key->keyidx, cmd); 1207 if (err < 0) 1208 return err; 1209 1210 wcid->cipher = cipher_mask; 1211 1212 return 0; 1213 } 1214 1215 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1216 struct mt76_wcid *wcid, 1217 struct ieee80211_key_conf *key, 1218 enum set_key_cmd cmd) 1219 { 1220 int err; 1221 1222 spin_lock_bh(&dev->mt76.lock); 1223 err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); 1224 spin_unlock_bh(&dev->mt76.lock); 1225 1226 return err; 1227 } 1228 1229 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, 1230 struct ieee80211_tx_info *info, __le32 *txs_data) 1231 { 1232 struct ieee80211_supported_band *sband; 1233 struct mt7615_rate_set *rs; 1234 struct mt76_phy *mphy; 1235 int first_idx = 0, last_idx; 1236 int i, idx, count; 1237 bool fixed_rate, ack_timeout; 1238 bool probe, ampdu, cck = false; 1239 bool rs_idx; 1240 u32 rate_set_tsf; 1241 u32 final_rate, final_rate_flags, final_nss, txs; 1242 1243 fixed_rate = info->status.rates[0].count; 1244 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1245 1246 txs = le32_to_cpu(txs_data[1]); 1247 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU); 1248 1249 txs = le32_to_cpu(txs_data[3]); 1250 count = FIELD_GET(MT_TXS3_TX_COUNT, txs); 1251 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); 1252 1253 txs = le32_to_cpu(txs_data[0]); 1254 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1255 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1256 1257 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1258 return false; 1259 1260 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1261 return false; 1262 1263 if (!ack_timeout) 1264 info->flags |= IEEE80211_TX_STAT_ACK; 1265 1266 info->status.ampdu_len = 1; 1267 info->status.ampdu_ack_len = !!(info->flags & 1268 IEEE80211_TX_STAT_ACK); 1269 1270 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1271 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1272 1273 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); 1274 1275 if (fixed_rate && !probe) { 1276 info->status.rates[0].count = count; 1277 i = 0; 1278 goto out; 1279 } 1280 1281 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1282 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) - 1283 rate_set_tsf) < 1000000); 1284 rs_idx ^= rate_set_tsf & BIT(0); 1285 rs = &sta->rateset[rs_idx]; 1286 1287 if (!first_idx && rs->probe_rate.idx >= 0) { 1288 info->status.rates[0] = rs->probe_rate; 1289 1290 spin_lock_bh(&dev->mt76.lock); 1291 if (sta->rate_probe) { 1292 struct mt7615_phy *phy = &dev->phy; 1293 1294 if (sta->wcid.ext_phy && dev->mt76.phy2) 1295 phy = dev->mt76.phy2->priv; 1296 1297 mt7615_mac_set_rates(phy, sta, NULL, sta->rates); 1298 } 1299 spin_unlock_bh(&dev->mt76.lock); 1300 } else { 1301 info->status.rates[0] = rs->rates[first_idx / 2]; 1302 } 1303 info->status.rates[0].count = 0; 1304 1305 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1306 struct ieee80211_tx_rate *cur_rate; 1307 int cur_count; 1308 1309 cur_rate = &rs->rates[idx / 2]; 1310 cur_count = min_t(int, MT7615_RATE_RETRY, count); 1311 count -= cur_count; 1312 1313 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1314 cur_rate->flags != info->status.rates[i].flags)) { 1315 i++; 1316 if (i == ARRAY_SIZE(info->status.rates)) { 1317 i--; 1318 break; 1319 } 1320 1321 info->status.rates[i] = *cur_rate; 1322 info->status.rates[i].count = 0; 1323 } 1324 1325 info->status.rates[i].count += cur_count; 1326 } 1327 1328 out: 1329 final_rate_flags = info->status.rates[i].flags; 1330 1331 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1332 case MT_PHY_TYPE_CCK: 1333 cck = true; 1334 fallthrough; 1335 case MT_PHY_TYPE_OFDM: 1336 mphy = &dev->mphy; 1337 if (sta->wcid.ext_phy && dev->mt76.phy2) 1338 mphy = dev->mt76.phy2; 1339 1340 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1341 sband = &mphy->sband_5g.sband; 1342 else 1343 sband = &mphy->sband_2g.sband; 1344 final_rate &= MT_TX_RATE_IDX; 1345 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1346 cck); 1347 final_rate_flags = 0; 1348 break; 1349 case MT_PHY_TYPE_HT_GF: 1350 case MT_PHY_TYPE_HT: 1351 final_rate_flags |= IEEE80211_TX_RC_MCS; 1352 final_rate &= MT_TX_RATE_IDX; 1353 if (final_rate > 31) 1354 return false; 1355 break; 1356 case MT_PHY_TYPE_VHT: 1357 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); 1358 1359 if ((final_rate & MT_TX_RATE_STBC) && final_nss) 1360 final_nss--; 1361 1362 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; 1363 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); 1364 break; 1365 default: 1366 return false; 1367 } 1368 1369 info->status.rates[i].idx = final_rate; 1370 info->status.rates[i].flags = final_rate_flags; 1371 1372 return true; 1373 } 1374 1375 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, 1376 struct mt7615_sta *sta, int pid, 1377 __le32 *txs_data) 1378 { 1379 struct mt76_dev *mdev = &dev->mt76; 1380 struct sk_buff_head list; 1381 struct sk_buff *skb; 1382 1383 if (pid < MT_PACKET_ID_FIRST) 1384 return false; 1385 1386 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1387 1388 mt76_tx_status_lock(mdev, &list); 1389 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1390 if (skb) { 1391 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1392 1393 if (!mt7615_fill_txs(dev, sta, info, txs_data)) { 1394 ieee80211_tx_info_clear_status(info); 1395 info->status.rates[0].idx = -1; 1396 } 1397 1398 mt76_tx_status_skb_done(mdev, skb, &list); 1399 } 1400 mt76_tx_status_unlock(mdev, &list); 1401 1402 return !!skb; 1403 } 1404 1405 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) 1406 { 1407 struct ieee80211_tx_info info = {}; 1408 struct ieee80211_sta *sta = NULL; 1409 struct mt7615_sta *msta = NULL; 1410 struct mt76_wcid *wcid; 1411 struct mt76_phy *mphy = &dev->mt76.phy; 1412 __le32 *txs_data = data; 1413 u32 txs; 1414 u8 wcidx; 1415 u8 pid; 1416 1417 txs = le32_to_cpu(txs_data[0]); 1418 pid = FIELD_GET(MT_TXS0_PID, txs); 1419 txs = le32_to_cpu(txs_data[2]); 1420 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1421 1422 if (pid == MT_PACKET_ID_NO_ACK) 1423 return; 1424 1425 if (wcidx >= MT7615_WTBL_SIZE) 1426 return; 1427 1428 rcu_read_lock(); 1429 1430 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1431 if (!wcid) 1432 goto out; 1433 1434 msta = container_of(wcid, struct mt7615_sta, wcid); 1435 sta = wcid_to_sta(wcid); 1436 1437 spin_lock_bh(&dev->sta_poll_lock); 1438 if (list_empty(&msta->poll_list)) 1439 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1440 spin_unlock_bh(&dev->sta_poll_lock); 1441 1442 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) 1443 goto out; 1444 1445 if (wcidx >= MT7615_WTBL_STA || !sta) 1446 goto out; 1447 1448 if (wcid->ext_phy && dev->mt76.phy2) 1449 mphy = dev->mt76.phy2; 1450 1451 if (mt7615_fill_txs(dev, msta, &info, txs_data)) 1452 ieee80211_tx_status_noskb(mphy->hw, sta, &info); 1453 1454 out: 1455 rcu_read_unlock(); 1456 } 1457 1458 static void 1459 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) 1460 { 1461 struct mt76_dev *mdev = &dev->mt76; 1462 struct mt76_txwi_cache *txwi; 1463 __le32 *txwi_data; 1464 u32 val; 1465 u8 wcid; 1466 1467 trace_mac_tx_free(dev, token); 1468 txwi = mt76_token_put(mdev, token); 1469 if (!txwi) 1470 return; 1471 1472 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); 1473 val = le32_to_cpu(txwi_data[1]); 1474 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); 1475 1476 mt7615_txp_skb_unmap(mdev, txwi); 1477 if (txwi->skb) { 1478 mt76_tx_complete_skb(mdev, wcid, txwi->skb); 1479 txwi->skb = NULL; 1480 } 1481 1482 mt76_put_txwi(mdev, txwi); 1483 } 1484 1485 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb) 1486 { 1487 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data; 1488 u8 i, count; 1489 1490 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1491 if (is_mt7615(&dev->mt76)) { 1492 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1493 } else { 1494 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1495 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); 1496 } 1497 1498 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl)); 1499 if (is_mt7615(&dev->mt76)) { 1500 __le16 *token = &free->token[0]; 1501 1502 for (i = 0; i < count; i++) 1503 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); 1504 } else { 1505 __le32 *token = (__le32 *)&free->token[0]; 1506 1507 for (i = 0; i < count; i++) 1508 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); 1509 } 1510 1511 dev_kfree_skb(skb); 1512 1513 rcu_read_lock(); 1514 mt7615_mac_sta_poll(dev); 1515 rcu_read_unlock(); 1516 1517 mt76_worker_schedule(&dev->mt76.tx_worker); 1518 } 1519 1520 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1521 struct sk_buff *skb) 1522 { 1523 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1524 __le32 *rxd = (__le32 *)skb->data; 1525 __le32 *end = (__le32 *)&skb->data[skb->len]; 1526 enum rx_pkt_type type; 1527 u16 flag; 1528 1529 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1530 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); 1531 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1532 type = PKT_TYPE_NORMAL_MCU; 1533 1534 switch (type) { 1535 case PKT_TYPE_TXS: 1536 for (rxd++; rxd + 7 <= end; rxd += 7) 1537 mt7615_mac_add_txs(dev, rxd); 1538 dev_kfree_skb(skb); 1539 break; 1540 case PKT_TYPE_TXRX_NOTIFY: 1541 mt7615_mac_tx_free(dev, skb); 1542 break; 1543 case PKT_TYPE_RX_EVENT: 1544 mt7615_mcu_rx_event(dev, skb); 1545 break; 1546 case PKT_TYPE_NORMAL_MCU: 1547 case PKT_TYPE_NORMAL: 1548 if (!mt7615_mac_fill_rx(dev, skb)) { 1549 mt76_rx(&dev->mt76, q, skb); 1550 return; 1551 } 1552 fallthrough; 1553 default: 1554 dev_kfree_skb(skb); 1555 break; 1556 } 1557 } 1558 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); 1559 1560 static void 1561 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) 1562 { 1563 struct mt7615_dev *dev = phy->dev; 1564 bool ext_phy = phy != &dev->phy; 1565 1566 if (is_mt7663(&dev->mt76)) { 1567 if (ofdm) 1568 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), 1569 MT_WF_PHY_PD_OFDM_MASK(0), 1570 MT_WF_PHY_PD_OFDM(0, val)); 1571 else 1572 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), 1573 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1574 MT_WF_PHY_PD_CCK(ext_phy, val)); 1575 return; 1576 } 1577 1578 if (ofdm) 1579 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), 1580 MT_WF_PHY_PD_OFDM_MASK(ext_phy), 1581 MT_WF_PHY_PD_OFDM(ext_phy, val)); 1582 else 1583 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), 1584 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1585 MT_WF_PHY_PD_CCK(ext_phy, val)); 1586 } 1587 1588 static void 1589 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) 1590 { 1591 /* ofdm */ 1592 mt7615_mac_set_sensitivity(phy, 0x13c, true); 1593 /* cck */ 1594 mt7615_mac_set_sensitivity(phy, 0x92, false); 1595 1596 phy->ofdm_sensitivity = -98; 1597 phy->cck_sensitivity = -110; 1598 phy->last_cca_adj = jiffies; 1599 } 1600 1601 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) 1602 { 1603 struct mt7615_dev *dev = phy->dev; 1604 bool ext_phy = phy != &dev->phy; 1605 u32 reg, mask; 1606 1607 mt7615_mutex_acquire(dev); 1608 1609 if (phy->scs_en == enable) 1610 goto out; 1611 1612 if (is_mt7663(&dev->mt76)) { 1613 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); 1614 mask = MT_WF_PHY_PD_BLK(0); 1615 } else { 1616 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); 1617 mask = MT_WF_PHY_PD_BLK(ext_phy); 1618 } 1619 1620 if (enable) { 1621 mt76_set(dev, reg, mask); 1622 if (is_mt7622(&dev->mt76)) { 1623 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); 1624 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); 1625 } 1626 } else { 1627 mt76_clear(dev, reg, mask); 1628 } 1629 1630 mt7615_mac_set_default_sensitivity(phy); 1631 phy->scs_en = enable; 1632 1633 out: 1634 mt7615_mutex_release(dev); 1635 } 1636 1637 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 1638 { 1639 u32 rxtd, reg; 1640 1641 if (is_mt7663(&dev->mt76)) 1642 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1643 else 1644 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1645 1646 if (ext_phy) 1647 rxtd = MT_WF_PHY_RXTD2(10); 1648 else 1649 rxtd = MT_WF_PHY_RXTD(12); 1650 1651 mt76_set(dev, rxtd, BIT(18) | BIT(29)); 1652 mt76_set(dev, reg, 0x5 << 12); 1653 } 1654 1655 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) 1656 { 1657 struct mt7615_dev *dev = phy->dev; 1658 bool ext_phy = phy != &dev->phy; 1659 u32 reg; 1660 1661 if (is_mt7663(&dev->mt76)) 1662 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1663 else 1664 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1665 1666 /* reset PD and MDRDY counters */ 1667 mt76_clear(dev, reg, GENMASK(22, 20)); 1668 mt76_set(dev, reg, BIT(22) | BIT(20)); 1669 } 1670 1671 static void 1672 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, 1673 u32 rts_err_rate, bool ofdm) 1674 { 1675 struct mt7615_dev *dev = phy->dev; 1676 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; 1677 bool ext_phy = phy != &dev->phy; 1678 u16 def_th = ofdm ? -98 : -110; 1679 bool update = false; 1680 s8 *sensitivity; 1681 int signal; 1682 1683 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; 1684 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); 1685 if (!signal) { 1686 mt7615_mac_set_default_sensitivity(phy); 1687 return; 1688 } 1689 1690 signal = min(signal, -72); 1691 if (false_cca > 500) { 1692 if (rts_err_rate > MT_FRAC(40, 100)) 1693 return; 1694 1695 /* decrease coverage */ 1696 if (*sensitivity == def_th && signal > -90) { 1697 *sensitivity = -90; 1698 update = true; 1699 } else if (*sensitivity + 2 < signal) { 1700 *sensitivity += 2; 1701 update = true; 1702 } 1703 } else if ((false_cca > 0 && false_cca < 50) || 1704 rts_err_rate > MT_FRAC(60, 100)) { 1705 /* increase coverage */ 1706 if (*sensitivity - 2 >= def_th) { 1707 *sensitivity -= 2; 1708 update = true; 1709 } 1710 } 1711 1712 if (*sensitivity > signal) { 1713 *sensitivity = signal; 1714 update = true; 1715 } 1716 1717 if (update) { 1718 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; 1719 1720 mt7615_mac_set_sensitivity(phy, val, ofdm); 1721 phy->last_cca_adj = jiffies; 1722 } 1723 } 1724 1725 static void 1726 mt7615_mac_scs_check(struct mt7615_phy *phy) 1727 { 1728 struct mt7615_dev *dev = phy->dev; 1729 struct mib_stats *mib = &phy->mib; 1730 u32 val, rts_err_rate = 0; 1731 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; 1732 bool ext_phy = phy != &dev->phy; 1733 1734 if (!phy->scs_en) 1735 return; 1736 1737 if (is_mt7663(&dev->mt76)) 1738 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1739 else 1740 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1741 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); 1742 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); 1743 1744 if (is_mt7663(&dev->mt76)) 1745 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1746 else 1747 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1748 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); 1749 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); 1750 1751 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1752 phy->false_cca_cck = pd_cck - mdrdy_cck; 1753 mt7615_mac_cca_stats_reset(phy); 1754 1755 if (mib->rts_cnt + mib->rts_retries_cnt) 1756 rts_err_rate = MT_FRAC(mib->rts_retries_cnt, 1757 mib->rts_cnt + mib->rts_retries_cnt); 1758 1759 /* cck */ 1760 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); 1761 /* ofdm */ 1762 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); 1763 1764 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) 1765 mt7615_mac_set_default_sensitivity(phy); 1766 } 1767 1768 static u8 1769 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) 1770 { 1771 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1772 u32 reg, val, sum = 0, n = 0; 1773 int i; 1774 1775 if (is_mt7663(&dev->mt76)) 1776 reg = MT7663_WF_PHY_RXTD(20); 1777 else 1778 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); 1779 1780 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1781 val = mt76_rr(dev, reg); 1782 sum += val * nf_power[i]; 1783 n += val; 1784 } 1785 1786 if (!n) 1787 return 0; 1788 1789 return sum / n; 1790 } 1791 1792 static void 1793 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) 1794 { 1795 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1796 struct mt7615_phy *phy = mphy->priv; 1797 struct mt76_channel_state *state; 1798 u64 busy_time, tx_time, rx_time, obss_time; 1799 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; 1800 int nf; 1801 1802 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1803 MT_MIB_SDR9_BUSY_MASK); 1804 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1805 MT_MIB_SDR36_TXTIME_MASK); 1806 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1807 MT_MIB_SDR37_RXTIME_MASK); 1808 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); 1809 1810 nf = mt7615_phy_get_nf(dev, idx); 1811 if (!phy->noise) 1812 phy->noise = nf << 4; 1813 else if (nf) 1814 phy->noise += nf - (phy->noise >> 4); 1815 1816 state = mphy->chan_state; 1817 state->cc_busy += busy_time; 1818 state->cc_tx += tx_time; 1819 state->cc_rx += rx_time + obss_time; 1820 state->cc_bss_rx += rx_time; 1821 state->noise = -(phy->noise >> 4); 1822 } 1823 1824 static void __mt7615_update_channel(struct mt7615_dev *dev) 1825 { 1826 struct mt76_dev *mdev = &dev->mt76; 1827 1828 mt7615_phy_update_channel(&mdev->phy, 0); 1829 if (mdev->phy2) 1830 mt7615_phy_update_channel(mdev->phy2, 1); 1831 1832 /* reset obss airtime */ 1833 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 1834 } 1835 1836 void mt7615_update_channel(struct mt76_dev *mdev) 1837 { 1838 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1839 1840 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) 1841 return; 1842 1843 __mt7615_update_channel(dev); 1844 mt76_connac_power_save_sched(&dev->mphy, &dev->pm); 1845 } 1846 EXPORT_SYMBOL_GPL(mt7615_update_channel); 1847 1848 static void mt7615_update_survey(struct mt7615_dev *dev) 1849 { 1850 struct mt76_dev *mdev = &dev->mt76; 1851 ktime_t cur_time; 1852 1853 __mt7615_update_channel(dev); 1854 cur_time = ktime_get_boottime(); 1855 1856 mt76_update_survey_active_time(&mdev->phy, cur_time); 1857 if (mdev->phy2) 1858 mt76_update_survey_active_time(mdev->phy2, cur_time); 1859 } 1860 1861 static void 1862 mt7615_mac_update_mib_stats(struct mt7615_phy *phy) 1863 { 1864 struct mt7615_dev *dev = phy->dev; 1865 struct mib_stats *mib = &phy->mib; 1866 bool ext_phy = phy != &dev->phy; 1867 int i, aggr; 1868 u32 val, val2; 1869 1870 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 1871 MT_MIB_SDR3_FCS_ERR_MASK); 1872 1873 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), 1874 MT_MIB_AMPDU_MPDU_COUNT); 1875 if (val) { 1876 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), 1877 MT_MIB_AMPDU_ACK_COUNT); 1878 mib->aggr_per = 1000 * (val - val2) / val; 1879 } 1880 1881 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 1882 for (i = 0; i < 4; i++) { 1883 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 1884 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1885 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, 1886 val); 1887 1888 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 1889 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1890 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, 1891 val); 1892 1893 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 1894 dev->mt76.aggr_stats[aggr++] += val & 0xffff; 1895 dev->mt76.aggr_stats[aggr++] += val >> 16; 1896 } 1897 } 1898 1899 void mt7615_pm_wake_work(struct work_struct *work) 1900 { 1901 struct mt7615_dev *dev; 1902 struct mt76_phy *mphy; 1903 1904 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 1905 pm.wake_work); 1906 mphy = dev->phy.mt76; 1907 1908 if (!mt7615_mcu_set_drv_ctrl(dev)) { 1909 int i; 1910 1911 mt76_for_each_q_rx(&dev->mt76, i) 1912 napi_schedule(&dev->mt76.napi[i]); 1913 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 1914 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 1915 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1916 MT7615_WATCHDOG_TIME); 1917 } 1918 1919 ieee80211_wake_queues(mphy->hw); 1920 wake_up(&dev->pm.wait); 1921 } 1922 1923 void mt7615_pm_power_save_work(struct work_struct *work) 1924 { 1925 struct mt7615_dev *dev; 1926 unsigned long delta; 1927 1928 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 1929 pm.ps_work.work); 1930 1931 delta = dev->pm.idle_timeout; 1932 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || 1933 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) 1934 goto out; 1935 1936 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 1937 delta = dev->pm.last_activity + delta - jiffies; 1938 goto out; 1939 } 1940 1941 if (!mt7615_mcu_set_fw_ctrl(dev)) 1942 return; 1943 out: 1944 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 1945 } 1946 1947 void mt7615_mac_work(struct work_struct *work) 1948 { 1949 struct mt7615_phy *phy; 1950 struct mt76_phy *mphy; 1951 1952 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 1953 mac_work.work); 1954 phy = mphy->priv; 1955 1956 mt7615_mutex_acquire(phy->dev); 1957 1958 mt7615_update_survey(phy->dev); 1959 if (++mphy->mac_work_count == 5) { 1960 mphy->mac_work_count = 0; 1961 1962 mt7615_mac_update_mib_stats(phy); 1963 mt7615_mac_scs_check(phy); 1964 } 1965 1966 mt7615_mutex_release(phy->dev); 1967 1968 mt76_tx_status_check(mphy->dev, NULL, false); 1969 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 1970 MT7615_WATCHDOG_TIME); 1971 } 1972 1973 void mt7615_tx_token_put(struct mt7615_dev *dev) 1974 { 1975 struct mt76_txwi_cache *txwi; 1976 int id; 1977 1978 spin_lock_bh(&dev->mt76.token_lock); 1979 idr_for_each_entry(&dev->mt76.token, txwi, id) { 1980 mt7615_txp_skb_unmap(&dev->mt76, txwi); 1981 if (txwi->skb) { 1982 struct ieee80211_hw *hw; 1983 1984 hw = mt76_tx_status_get_hw(&dev->mt76, txwi->skb); 1985 ieee80211_free_txskb(hw, txwi->skb); 1986 } 1987 mt76_put_txwi(&dev->mt76, txwi); 1988 } 1989 spin_unlock_bh(&dev->mt76.token_lock); 1990 idr_destroy(&dev->mt76.token); 1991 } 1992 EXPORT_SYMBOL_GPL(mt7615_tx_token_put); 1993 1994 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) 1995 { 1996 struct mt7615_dev *dev = phy->dev; 1997 1998 if (phy->rdd_state & BIT(0)) 1999 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0); 2000 if (phy->rdd_state & BIT(1)) 2001 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0); 2002 } 2003 2004 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) 2005 { 2006 int err; 2007 2008 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0); 2009 if (err < 0) 2010 return err; 2011 2012 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2013 MT_RX_SEL0, 1); 2014 } 2015 2016 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) 2017 { 2018 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2019 struct mt7615_dev *dev = phy->dev; 2020 bool ext_phy = phy != &dev->phy; 2021 int err; 2022 2023 /* start CAC */ 2024 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0); 2025 if (err < 0) 2026 return err; 2027 2028 err = mt7615_dfs_start_rdd(dev, ext_phy); 2029 if (err < 0) 2030 return err; 2031 2032 phy->rdd_state |= BIT(ext_phy); 2033 2034 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2035 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2036 err = mt7615_dfs_start_rdd(dev, 1); 2037 if (err < 0) 2038 return err; 2039 2040 phy->rdd_state |= BIT(1); 2041 } 2042 2043 return 0; 2044 } 2045 2046 static int 2047 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) 2048 { 2049 const struct mt7615_dfs_radar_spec *radar_specs; 2050 struct mt7615_dev *dev = phy->dev; 2051 int err, i; 2052 2053 switch (dev->mt76.region) { 2054 case NL80211_DFS_FCC: 2055 radar_specs = &fcc_radar_specs; 2056 err = mt7615_mcu_set_fcc5_lpn(dev, 8); 2057 if (err < 0) 2058 return err; 2059 break; 2060 case NL80211_DFS_ETSI: 2061 radar_specs = &etsi_radar_specs; 2062 break; 2063 case NL80211_DFS_JP: 2064 radar_specs = &jp_radar_specs; 2065 break; 2066 default: 2067 return -EINVAL; 2068 } 2069 2070 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2071 err = mt7615_mcu_set_radar_th(dev, i, 2072 &radar_specs->radar_pattern[i]); 2073 if (err < 0) 2074 return err; 2075 } 2076 2077 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2078 } 2079 2080 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) 2081 { 2082 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2083 struct mt7615_dev *dev = phy->dev; 2084 bool ext_phy = phy != &dev->phy; 2085 int err; 2086 2087 if (is_mt7663(&dev->mt76)) 2088 return 0; 2089 2090 if (dev->mt76.region == NL80211_DFS_UNSET) { 2091 phy->dfs_state = -1; 2092 if (phy->rdd_state) 2093 goto stop; 2094 2095 return 0; 2096 } 2097 2098 if (test_bit(MT76_SCANNING, &phy->mt76->state)) 2099 return 0; 2100 2101 if (phy->dfs_state == chandef->chan->dfs_state) 2102 return 0; 2103 2104 err = mt7615_dfs_init_radar_specs(phy); 2105 if (err < 0) { 2106 phy->dfs_state = -1; 2107 goto stop; 2108 } 2109 2110 phy->dfs_state = chandef->chan->dfs_state; 2111 2112 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) { 2113 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2114 return mt7615_dfs_start_radar_detector(phy); 2115 2116 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy, 2117 MT_RX_SEL0, 0); 2118 } 2119 2120 stop: 2121 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0); 2122 if (err < 0) 2123 return err; 2124 2125 mt7615_dfs_stop_radar_detector(phy); 2126 return 0; 2127 } 2128 2129 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, 2130 struct ieee80211_vif *vif, 2131 bool enable) 2132 { 2133 struct mt7615_dev *dev = phy->dev; 2134 bool ext_phy = phy != &dev->phy; 2135 int err; 2136 2137 if (!mt7615_firmware_offload(dev)) 2138 return -EOPNOTSUPP; 2139 2140 switch (vif->type) { 2141 case NL80211_IFTYPE_MONITOR: 2142 return 0; 2143 case NL80211_IFTYPE_MESH_POINT: 2144 case NL80211_IFTYPE_ADHOC: 2145 case NL80211_IFTYPE_AP: 2146 if (enable) 2147 phy->n_beacon_vif++; 2148 else 2149 phy->n_beacon_vif--; 2150 fallthrough; 2151 default: 2152 break; 2153 } 2154 2155 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); 2156 if (err) 2157 return err; 2158 2159 if (phy->n_beacon_vif) { 2160 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; 2161 mt76_clear(dev, MT_WF_RFCR(ext_phy), 2162 MT_WF_RFCR_DROP_OTHER_BEACON); 2163 } else { 2164 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; 2165 mt76_set(dev, MT_WF_RFCR(ext_phy), 2166 MT_WF_RFCR_DROP_OTHER_BEACON); 2167 } 2168 2169 return 0; 2170 } 2171 2172 void mt7615_coredump_work(struct work_struct *work) 2173 { 2174 struct mt7615_dev *dev; 2175 char *dump, *data; 2176 2177 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2178 coredump.work.work); 2179 2180 if (time_is_after_jiffies(dev->coredump.last_activity + 2181 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 2182 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 2183 MT76_CONNAC_COREDUMP_TIMEOUT); 2184 return; 2185 } 2186 2187 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 2188 data = dump; 2189 2190 while (true) { 2191 struct sk_buff *skb; 2192 2193 spin_lock_bh(&dev->mt76.lock); 2194 skb = __skb_dequeue(&dev->coredump.msg_list); 2195 spin_unlock_bh(&dev->mt76.lock); 2196 2197 if (!skb) 2198 break; 2199 2200 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 2201 if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 2202 dev_kfree_skb(skb); 2203 continue; 2204 } 2205 2206 memcpy(data, skb->data, skb->len); 2207 data += skb->len; 2208 2209 dev_kfree_skb(skb); 2210 } 2211 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 2212 GFP_KERNEL); 2213 } 2214