1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Felix Fietkau <nbd@nbd.name> 7 * Lorenzo Bianconi <lorenzo@kernel.org> 8 */ 9 10 #include <linux/devcoredump.h> 11 #include <linux/etherdevice.h> 12 #include <linux/timekeeping.h> 13 #include "mt7615.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 #include "mt7615_trace.h" 17 #include "mac.h" 18 #include "mcu.h" 19 20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 21 22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = { 23 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 24 .radar_pattern = { 25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, 26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, 27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, 28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, 29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, 30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, 31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, 32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, 33 }, 34 }; 35 36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = { 37 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 38 .radar_pattern = { 39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, 40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, 44 }, 45 }; 46 47 static const struct mt7615_dfs_radar_spec jp_radar_specs = { 48 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 49 .radar_pattern = { 50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, 51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, 55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, 56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, 57 }, 58 }; 59 60 static enum mt76_cipher_type 61 mt7615_mac_get_cipher(int cipher) 62 { 63 switch (cipher) { 64 case WLAN_CIPHER_SUITE_WEP40: 65 return MT_CIPHER_WEP40; 66 case WLAN_CIPHER_SUITE_WEP104: 67 return MT_CIPHER_WEP104; 68 case WLAN_CIPHER_SUITE_TKIP: 69 return MT_CIPHER_TKIP; 70 case WLAN_CIPHER_SUITE_AES_CMAC: 71 return MT_CIPHER_BIP_CMAC_128; 72 case WLAN_CIPHER_SUITE_CCMP: 73 return MT_CIPHER_AES_CCMP; 74 case WLAN_CIPHER_SUITE_CCMP_256: 75 return MT_CIPHER_CCMP_256; 76 case WLAN_CIPHER_SUITE_GCMP: 77 return MT_CIPHER_GCMP; 78 case WLAN_CIPHER_SUITE_GCMP_256: 79 return MT_CIPHER_GCMP_256; 80 case WLAN_CIPHER_SUITE_SMS4: 81 return MT_CIPHER_WAPI; 82 default: 83 return MT_CIPHER_NONE; 84 } 85 } 86 87 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, 88 u8 idx, bool unicast) 89 { 90 struct mt7615_sta *sta; 91 struct mt76_wcid *wcid; 92 93 if (idx >= MT7615_WTBL_SIZE) 94 return NULL; 95 96 wcid = rcu_dereference(dev->mt76.wcid[idx]); 97 if (unicast || !wcid) 98 return wcid; 99 100 if (!wcid->sta) 101 return NULL; 102 103 sta = container_of(wcid, struct mt7615_sta, wcid); 104 if (!sta->vif) 105 return NULL; 106 107 return &sta->vif->sta.wcid; 108 } 109 110 void mt7615_mac_reset_counters(struct mt7615_phy *phy) 111 { 112 struct mt7615_dev *dev = phy->dev; 113 int i; 114 115 for (i = 0; i < 4; i++) { 116 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 117 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); 118 } 119 120 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 121 phy->mt76->survey_time = ktime_get_boottime(); 122 123 /* reset airtime counters */ 124 mt76_rr(dev, MT_MIB_SDR9(0)); 125 mt76_rr(dev, MT_MIB_SDR9(1)); 126 127 mt76_rr(dev, MT_MIB_SDR36(0)); 128 mt76_rr(dev, MT_MIB_SDR36(1)); 129 130 mt76_rr(dev, MT_MIB_SDR37(0)); 131 mt76_rr(dev, MT_MIB_SDR37(1)); 132 133 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 134 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 135 } 136 137 void mt7615_mac_set_timing(struct mt7615_phy *phy) 138 { 139 s16 coverage_class = phy->coverage_class; 140 struct mt7615_dev *dev = phy->dev; 141 bool ext_phy = phy != &dev->phy; 142 u32 val, reg_offset; 143 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 144 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 145 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 146 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 147 int sifs, offset; 148 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 149 150 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 151 return; 152 153 if (is_5ghz) 154 sifs = 16; 155 else 156 sifs = 10; 157 158 if (ext_phy) { 159 coverage_class = max_t(s16, dev->phy.coverage_class, 160 coverage_class); 161 mt76_set(dev, MT_ARB_SCR, 162 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 163 } else { 164 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); 165 166 if (phy_ext) 167 coverage_class = max_t(s16, phy_ext->coverage_class, 168 coverage_class); 169 mt76_set(dev, MT_ARB_SCR, 170 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 171 } 172 udelay(1); 173 174 offset = 3 * coverage_class; 175 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 176 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 177 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); 178 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); 179 180 mt76_wr(dev, MT_TMAC_ICR(ext_phy), 181 FIELD_PREP(MT_IFS_EIFS, 360) | 182 FIELD_PREP(MT_IFS_RIFS, 2) | 183 FIELD_PREP(MT_IFS_SIFS, sifs) | 184 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 185 186 if (phy->slottime < 20 || is_5ghz) 187 val = MT7615_CFEND_RATE_DEFAULT; 188 else 189 val = MT7615_CFEND_RATE_11B; 190 191 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 192 if (ext_phy) 193 mt76_clear(dev, MT_ARB_SCR, 194 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 195 else 196 mt76_clear(dev, MT_ARB_SCR, 197 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 198 199 } 200 201 static void 202 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, 203 struct mt76_rx_status *status, u8 chfreq) 204 { 205 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 206 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 207 !test_bit(MT76_STATE_ROC, &mphy->state)) { 208 status->freq = mphy->chandef.chan->center_freq; 209 status->band = mphy->chandef.chan->band; 210 return; 211 } 212 213 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 214 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 215 } 216 217 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) 218 { 219 #ifdef CONFIG_NL80211_TESTMODE 220 u32 rxv1 = le32_to_cpu(rxv[0]); 221 u32 rxv3 = le32_to_cpu(rxv[2]); 222 u32 rxv4 = le32_to_cpu(rxv[3]); 223 u32 rxv5 = le32_to_cpu(rxv[4]); 224 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); 225 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); 226 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); 227 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; 228 229 if (!mode) { 230 /* CCK */ 231 foe &= ~BIT(11); 232 foe *= 1000; 233 foe >>= 11; 234 } else { 235 if (foe > 2048) 236 foe -= 4096; 237 238 foe = (foe * foe_const) >> 15; 239 } 240 241 phy->test.last_freq_offset = foe; 242 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); 243 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); 244 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); 245 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); 246 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); 247 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); 248 #endif 249 } 250 251 /* The HW does not translate the mac header to 802.3 for mesh point */ 252 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 253 { 254 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 255 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 256 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid; 257 __le32 *rxd = (__le32 *)skb->data; 258 struct ieee80211_sta *sta; 259 struct ieee80211_vif *vif; 260 struct ieee80211_hdr hdr; 261 u16 frame_control; 262 263 if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) != 264 MT_RXD1_NORMAL_U2M) 265 return -EINVAL; 266 267 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4)) 268 return -EINVAL; 269 270 if (!msta || !msta->vif) 271 return -EINVAL; 272 273 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 274 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 275 276 /* store the info from RXD and ethhdr to avoid being overridden */ 277 frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL); 278 hdr.frame_control = cpu_to_le16(frame_control); 279 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL)); 280 hdr.duration_id = 0; 281 282 ether_addr_copy(hdr.addr1, vif->addr); 283 ether_addr_copy(hdr.addr2, sta->addr); 284 switch (frame_control & (IEEE80211_FCTL_TODS | 285 IEEE80211_FCTL_FROMDS)) { 286 case 0: 287 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 288 break; 289 case IEEE80211_FCTL_FROMDS: 290 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 291 break; 292 case IEEE80211_FCTL_TODS: 293 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 294 break; 295 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 296 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 297 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 298 break; 299 default: 300 break; 301 } 302 303 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 304 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 305 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 306 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 307 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 308 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 309 else 310 skb_pull(skb, 2); 311 312 if (ieee80211_has_order(hdr.frame_control)) 313 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7], 314 IEEE80211_HT_CTL_LEN); 315 316 if (ieee80211_is_data_qos(hdr.frame_control)) { 317 __le16 qos_ctrl; 318 319 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL)); 320 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 321 IEEE80211_QOS_CTL_LEN); 322 } 323 324 if (ieee80211_has_a4(hdr.frame_control)) 325 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 326 else 327 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 328 329 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU); 330 return 0; 331 } 332 333 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) 334 { 335 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 336 struct mt76_phy *mphy = &dev->mt76.phy; 337 struct mt7615_phy *phy = &dev->phy; 338 struct ieee80211_supported_band *sband; 339 struct ieee80211_hdr *hdr; 340 struct mt7615_phy *phy2; 341 __le32 *rxd = (__le32 *)skb->data; 342 u32 rxd0 = le32_to_cpu(rxd[0]); 343 u32 rxd1 = le32_to_cpu(rxd[1]); 344 u32 rxd2 = le32_to_cpu(rxd[2]); 345 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 346 u32 csum_status = *(u32 *)skb->cb; 347 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; 348 u16 hdr_gap; 349 int phy_idx; 350 int i, idx; 351 u8 chfreq, amsdu_info, qos_ctl = 0; 352 u16 seq_ctrl = 0; 353 __le16 fc = 0; 354 355 memset(status, 0, sizeof(*status)); 356 357 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 358 359 phy2 = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 360 if (!phy2) 361 phy_idx = 0; 362 else if (phy2->chfreq == phy->chfreq) 363 phy_idx = -1; 364 else if (phy->chfreq == chfreq) 365 phy_idx = 0; 366 else if (phy2->chfreq == chfreq) 367 phy_idx = 1; 368 else 369 phy_idx = -1; 370 371 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 372 return -EINVAL; 373 374 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; 375 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM)) 376 return -EINVAL; 377 378 /* ICV error or CCMP/BIP/WPI MIC error */ 379 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 380 status->flag |= RX_FLAG_ONLY_MONITOR; 381 382 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; 383 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 384 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); 385 386 if (status->wcid) { 387 struct mt7615_sta *msta; 388 389 msta = container_of(status->wcid, struct mt7615_sta, wcid); 390 spin_lock_bh(&dev->sta_poll_lock); 391 if (list_empty(&msta->poll_list)) 392 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 393 spin_unlock_bh(&dev->sta_poll_lock); 394 } 395 396 if (mt76_is_mmio(&dev->mt76) && (rxd0 & csum_mask) == csum_mask && 397 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 398 skb->ip_summed = CHECKSUM_UNNECESSARY; 399 400 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 401 status->flag |= RX_FLAG_FAILED_FCS_CRC; 402 403 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 404 status->flag |= RX_FLAG_MMIC_ERROR; 405 406 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 407 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 408 status->flag |= RX_FLAG_DECRYPTED; 409 status->flag |= RX_FLAG_IV_STRIPPED; 410 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 411 } 412 413 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 414 415 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 416 return -EINVAL; 417 418 rxd += 4; 419 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 420 u32 v0 = le32_to_cpu(rxd[0]); 421 u32 v2 = le32_to_cpu(rxd[2]); 422 423 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); 424 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); 425 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); 426 427 rxd += 4; 428 if ((u8 *)rxd - skb->data >= skb->len) 429 return -EINVAL; 430 } 431 432 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 433 u8 *data = (u8 *)rxd; 434 435 if (status->flag & RX_FLAG_DECRYPTED) { 436 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 437 case MT_CIPHER_AES_CCMP: 438 case MT_CIPHER_CCMP_CCX: 439 case MT_CIPHER_CCMP_256: 440 insert_ccmp_hdr = 441 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 442 fallthrough; 443 case MT_CIPHER_TKIP: 444 case MT_CIPHER_TKIP_NO_MIC: 445 case MT_CIPHER_GCMP: 446 case MT_CIPHER_GCMP_256: 447 status->iv[0] = data[5]; 448 status->iv[1] = data[4]; 449 status->iv[2] = data[3]; 450 status->iv[3] = data[2]; 451 status->iv[4] = data[1]; 452 status->iv[5] = data[0]; 453 break; 454 default: 455 break; 456 } 457 } 458 rxd += 4; 459 if ((u8 *)rxd - skb->data >= skb->len) 460 return -EINVAL; 461 } 462 463 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 464 status->timestamp = le32_to_cpu(rxd[0]); 465 status->flag |= RX_FLAG_MACTIME_START; 466 467 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 468 MT_RXD2_NORMAL_NON_AMPDU))) { 469 status->flag |= RX_FLAG_AMPDU_DETAILS; 470 471 /* all subframes of an A-MPDU have the same timestamp */ 472 if (phy->rx_ampdu_ts != status->timestamp) { 473 if (!++phy->ampdu_ref) 474 phy->ampdu_ref++; 475 } 476 phy->rx_ampdu_ts = status->timestamp; 477 478 status->ampdu_ref = phy->ampdu_ref; 479 } 480 481 rxd += 2; 482 if ((u8 *)rxd - skb->data >= skb->len) 483 return -EINVAL; 484 } 485 486 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 487 u32 rxdg5 = le32_to_cpu(rxd[5]); 488 489 /* 490 * If both PHYs are on the same channel and we don't have a WCID, 491 * we need to figure out which PHY this packet was received on. 492 * On the primary PHY, the noise value for the chains belonging to the 493 * second PHY will be set to the noise value of the last packet from 494 * that PHY. 495 */ 496 if (phy_idx < 0) { 497 int first_chain = ffs(phy2->mt76->chainmask) - 1; 498 499 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; 500 } 501 } 502 503 if (phy_idx == 1 && phy2) { 504 mphy = dev->mt76.phys[MT_BAND1]; 505 phy = phy2; 506 status->phy_idx = phy_idx; 507 } 508 509 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) 510 return -EINVAL; 511 512 mt7615_get_status_freq_info(dev, mphy, status, chfreq); 513 if (status->band == NL80211_BAND_5GHZ) 514 sband = &mphy->sband_5g.sband; 515 else 516 sband = &mphy->sband_2g.sband; 517 518 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 519 return -EINVAL; 520 521 if (!sband->channels) 522 return -EINVAL; 523 524 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 525 u32 rxdg0 = le32_to_cpu(rxd[0]); 526 u32 rxdg1 = le32_to_cpu(rxd[1]); 527 u32 rxdg3 = le32_to_cpu(rxd[3]); 528 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 529 bool cck = false; 530 531 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 532 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 533 case MT_PHY_TYPE_CCK: 534 cck = true; 535 fallthrough; 536 case MT_PHY_TYPE_OFDM: 537 i = mt76_get_rate(&dev->mt76, sband, i, cck); 538 break; 539 case MT_PHY_TYPE_HT_GF: 540 case MT_PHY_TYPE_HT: 541 status->encoding = RX_ENC_HT; 542 if (i > 31) 543 return -EINVAL; 544 break; 545 case MT_PHY_TYPE_VHT: 546 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; 547 status->encoding = RX_ENC_VHT; 548 break; 549 default: 550 return -EINVAL; 551 } 552 status->rate_idx = i; 553 554 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { 555 case MT_PHY_BW_20: 556 break; 557 case MT_PHY_BW_40: 558 status->bw = RATE_INFO_BW_40; 559 break; 560 case MT_PHY_BW_80: 561 status->bw = RATE_INFO_BW_80; 562 break; 563 case MT_PHY_BW_160: 564 status->bw = RATE_INFO_BW_160; 565 break; 566 default: 567 return -EINVAL; 568 } 569 570 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 571 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 572 if (rxdg0 & MT_RXV1_HT_AD_CODE) 573 status->enc_flags |= RX_ENC_FLAG_LDPC; 574 575 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 576 577 status->chains = mphy->antenna_mask; 578 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); 579 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); 580 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); 581 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); 582 583 mt7615_mac_fill_tm_rx(mphy->priv, rxd); 584 585 rxd += 6; 586 if ((u8 *)rxd - skb->data >= skb->len) 587 return -EINVAL; 588 } 589 590 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); 591 status->amsdu = !!amsdu_info; 592 if (status->amsdu) { 593 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; 594 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; 595 } 596 597 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 598 if (hdr_trans && ieee80211_has_morefrags(fc)) { 599 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap)) 600 return -EINVAL; 601 hdr_trans = false; 602 } else { 603 int pad_start = 0; 604 605 skb_pull(skb, hdr_gap); 606 if (!hdr_trans && status->amsdu) { 607 pad_start = ieee80211_get_hdrlen_from_skb(skb); 608 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 609 /* 610 * When header translation failure is indicated, 611 * the hardware will insert an extra 2-byte field 612 * containing the data length after the protocol 613 * type field. This happens either when the LLC-SNAP 614 * pattern did not match, or if a VLAN header was 615 * detected. 616 */ 617 pad_start = 12; 618 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 619 pad_start += 4; 620 else 621 pad_start = 0; 622 } 623 624 if (pad_start) { 625 memmove(skb->data + 2, skb->data, pad_start); 626 skb_pull(skb, 2); 627 } 628 } 629 630 if (insert_ccmp_hdr && !hdr_trans) { 631 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 632 633 mt76_insert_ccmp_hdr(skb, key_id); 634 } 635 636 if (!hdr_trans) { 637 hdr = (struct ieee80211_hdr *)skb->data; 638 fc = hdr->frame_control; 639 if (ieee80211_is_data_qos(fc)) { 640 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 641 qos_ctl = *ieee80211_get_qos_ctl(hdr); 642 } 643 } else { 644 status->flag |= RX_FLAG_8023; 645 } 646 647 if (!status->wcid || !ieee80211_is_data_qos(fc)) 648 return 0; 649 650 status->aggr = unicast && 651 !ieee80211_is_qos_nullfunc(fc); 652 status->qos_ctl = qos_ctl; 653 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 654 655 return 0; 656 } 657 658 static u16 659 mt7615_mac_tx_rate_val(struct mt7615_dev *dev, 660 struct mt76_phy *mphy, 661 const struct ieee80211_tx_rate *rate, 662 bool stbc, u8 *bw) 663 { 664 u8 phy, nss, rate_idx; 665 u16 rateval = 0; 666 667 *bw = 0; 668 669 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 670 rate_idx = ieee80211_rate_get_vht_mcs(rate); 671 nss = ieee80211_rate_get_vht_nss(rate); 672 phy = MT_PHY_TYPE_VHT; 673 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 674 *bw = 1; 675 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 676 *bw = 2; 677 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 678 *bw = 3; 679 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 680 rate_idx = rate->idx; 681 nss = 1 + (rate->idx >> 3); 682 phy = MT_PHY_TYPE_HT; 683 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 684 phy = MT_PHY_TYPE_HT_GF; 685 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 686 *bw = 1; 687 } else { 688 const struct ieee80211_rate *r; 689 int band = mphy->chandef.chan->band; 690 u16 val; 691 692 nss = 1; 693 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; 694 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 695 val = r->hw_value_short; 696 else 697 val = r->hw_value; 698 699 phy = val >> 8; 700 rate_idx = val & 0xff; 701 } 702 703 if (stbc && nss == 1) { 704 nss++; 705 rateval |= MT_TX_RATE_STBC; 706 } 707 708 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 709 FIELD_PREP(MT_TX_RATE_MODE, phy) | 710 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); 711 712 return rateval; 713 } 714 715 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, 716 struct sk_buff *skb, struct mt76_wcid *wcid, 717 struct ieee80211_sta *sta, int pid, 718 struct ieee80211_key_conf *key, 719 enum mt76_txq_id qid, bool beacon) 720 { 721 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 722 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 724 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 725 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 726 bool multicast = is_multicast_ether_addr(hdr->addr1); 727 struct ieee80211_vif *vif = info->control.vif; 728 bool is_mmio = mt76_is_mmio(&dev->mt76); 729 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; 730 struct mt76_phy *mphy = &dev->mphy; 731 __le16 fc = hdr->frame_control; 732 int tx_count = 8; 733 u16 seqno = 0; 734 735 if (vif) { 736 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 737 738 omac_idx = mvif->omac_idx; 739 wmm_idx = mvif->wmm_idx; 740 } 741 742 if (sta) { 743 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 744 745 tx_count = msta->rate_count; 746 } 747 748 if (phy_idx && dev->mt76.phys[MT_BAND1]) 749 mphy = dev->mt76.phys[MT_BAND1]; 750 751 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 752 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 753 754 if (beacon) { 755 p_fmt = MT_TX_TYPE_FW; 756 q_idx = phy_idx ? MT_LMAC_BCN1 : MT_LMAC_BCN0; 757 } else if (qid >= MT_TXQ_PSD) { 758 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 759 q_idx = phy_idx ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; 760 } else { 761 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 762 q_idx = wmm_idx * MT7615_MAX_WMM_SETS + 763 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); 764 } 765 766 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 767 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | 768 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 769 txwi[0] = cpu_to_le32(val); 770 771 val = MT_TXD1_LONG_FORMAT | 772 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 773 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 774 FIELD_PREP(MT_TXD1_HDR_INFO, 775 ieee80211_get_hdrlen_from_skb(skb) / 2) | 776 FIELD_PREP(MT_TXD1_TID, 777 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 778 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | 779 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 780 txwi[1] = cpu_to_le32(val); 781 782 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 783 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 784 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 785 if (key) { 786 if (multicast && ieee80211_is_robust_mgmt_frame(skb) && 787 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 788 val |= MT_TXD2_BIP; 789 txwi[3] = 0; 790 } else { 791 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); 792 } 793 } else { 794 txwi[3] = 0; 795 } 796 txwi[2] = cpu_to_le32(val); 797 798 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 799 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 800 801 txwi[4] = 0; 802 txwi[6] = 0; 803 804 if (rate->idx >= 0 && rate->count && 805 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 806 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 807 u8 bw; 808 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, 809 &bw); 810 811 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 812 813 val = MT_TXD6_FIXED_BW | 814 FIELD_PREP(MT_TXD6_BW, bw) | 815 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 816 txwi[6] |= cpu_to_le32(val); 817 818 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 819 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 820 821 if (info->flags & IEEE80211_TX_CTL_LDPC) 822 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); 823 824 if (!(rate->flags & (IEEE80211_TX_RC_MCS | 825 IEEE80211_TX_RC_VHT_MCS))) 826 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 827 828 tx_count = rate->count; 829 } 830 831 if (!ieee80211_is_beacon(fc)) { 832 struct ieee80211_hw *hw = mt76_hw(dev); 833 834 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); 835 if (!ieee80211_hw_check(hw, SUPPORTS_PS)) 836 val |= MT_TXD5_SW_POWER_MGMT; 837 txwi[5] = cpu_to_le32(val); 838 } else { 839 txwi[5] = 0; 840 /* use maximum tx count for beacons */ 841 tx_count = 0x1f; 842 } 843 844 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 845 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 846 seqno = le16_to_cpu(hdr->seq_ctrl); 847 848 if (ieee80211_is_back_req(hdr->frame_control)) { 849 struct ieee80211_bar *bar; 850 851 bar = (struct ieee80211_bar *)skb->data; 852 seqno = le16_to_cpu(bar->start_seq_num); 853 } 854 855 val |= MT_TXD3_SN_VALID | 856 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 857 } 858 859 txwi[3] |= cpu_to_le32(val); 860 861 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 862 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); 863 864 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 865 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | 866 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); 867 txwi[7] = cpu_to_le32(val); 868 if (!is_mmio) { 869 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | 870 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); 871 txwi[8] = cpu_to_le32(val); 872 } 873 874 return 0; 875 } 876 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); 877 878 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) 879 { 880 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 881 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 882 883 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 884 0, 5000); 885 } 886 887 void mt7615_mac_sta_poll(struct mt7615_dev *dev) 888 { 889 static const u8 ac_to_tid[4] = { 890 [IEEE80211_AC_BE] = 0, 891 [IEEE80211_AC_BK] = 1, 892 [IEEE80211_AC_VI] = 4, 893 [IEEE80211_AC_VO] = 6 894 }; 895 static const u8 hw_queue_map[] = { 896 [IEEE80211_AC_BK] = 0, 897 [IEEE80211_AC_BE] = 1, 898 [IEEE80211_AC_VI] = 2, 899 [IEEE80211_AC_VO] = 3, 900 }; 901 struct ieee80211_sta *sta; 902 struct mt7615_sta *msta; 903 u32 addr, tx_time[4], rx_time[4]; 904 struct list_head sta_poll_list; 905 int i; 906 907 INIT_LIST_HEAD(&sta_poll_list); 908 spin_lock_bh(&dev->sta_poll_lock); 909 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 910 spin_unlock_bh(&dev->sta_poll_lock); 911 912 while (!list_empty(&sta_poll_list)) { 913 bool clear = false; 914 915 msta = list_first_entry(&sta_poll_list, struct mt7615_sta, 916 poll_list); 917 918 spin_lock_bh(&dev->sta_poll_lock); 919 list_del_init(&msta->poll_list); 920 spin_unlock_bh(&dev->sta_poll_lock); 921 922 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; 923 924 for (i = 0; i < 4; i++, addr += 8) { 925 u32 tx_last = msta->airtime_ac[i]; 926 u32 rx_last = msta->airtime_ac[i + 4]; 927 928 msta->airtime_ac[i] = mt76_rr(dev, addr); 929 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 930 tx_time[i] = msta->airtime_ac[i] - tx_last; 931 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 932 933 if ((tx_last | rx_last) & BIT(30)) 934 clear = true; 935 } 936 937 if (clear) { 938 mt7615_mac_wtbl_update(dev, msta->wcid.idx, 939 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 940 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 941 } 942 943 if (!msta->wcid.sta) 944 continue; 945 946 sta = container_of((void *)msta, struct ieee80211_sta, 947 drv_priv); 948 for (i = 0; i < 4; i++) { 949 u32 tx_cur = tx_time[i]; 950 u32 rx_cur = rx_time[hw_queue_map[i]]; 951 u8 tid = ac_to_tid[i]; 952 953 if (!tx_cur && !rx_cur) 954 continue; 955 956 ieee80211_sta_register_airtime(sta, tid, tx_cur, 957 rx_cur); 958 } 959 } 960 } 961 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); 962 963 static void 964 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, 965 struct ieee80211_tx_rate *probe_rate, 966 struct ieee80211_tx_rate *rates, 967 struct mt7615_rate_desc *rd) 968 { 969 struct mt7615_dev *dev = phy->dev; 970 struct mt76_phy *mphy = phy->mt76; 971 struct ieee80211_tx_rate *ref; 972 bool rateset, stbc = false; 973 int n_rates = sta->n_rates; 974 u8 bw, bw_prev; 975 int i, j; 976 977 for (i = n_rates; i < 4; i++) 978 rates[i] = rates[n_rates - 1]; 979 980 rateset = !(sta->rate_set_tsf & BIT(0)); 981 memcpy(sta->rateset[rateset].rates, rates, 982 sizeof(sta->rateset[rateset].rates)); 983 if (probe_rate) { 984 sta->rateset[rateset].probe_rate = *probe_rate; 985 ref = &sta->rateset[rateset].probe_rate; 986 } else { 987 sta->rateset[rateset].probe_rate.idx = -1; 988 ref = &sta->rateset[rateset].rates[0]; 989 } 990 991 rates = sta->rateset[rateset].rates; 992 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 993 /* 994 * We don't support switching between short and long GI 995 * within the rate set. For accurate tx status reporting, we 996 * need to make sure that flags match. 997 * For improved performance, avoid duplicate entries by 998 * decrementing the MCS index if necessary 999 */ 1000 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 1001 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 1002 1003 for (j = 0; j < i; j++) { 1004 if (rates[i].idx != rates[j].idx) 1005 continue; 1006 if ((rates[i].flags ^ rates[j].flags) & 1007 (IEEE80211_TX_RC_40_MHZ_WIDTH | 1008 IEEE80211_TX_RC_80_MHZ_WIDTH | 1009 IEEE80211_TX_RC_160_MHZ_WIDTH)) 1010 continue; 1011 1012 if (!rates[i].idx) 1013 continue; 1014 1015 rates[i].idx--; 1016 } 1017 } 1018 1019 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); 1020 bw_prev = bw; 1021 1022 if (probe_rate) { 1023 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, 1024 stbc, &bw); 1025 if (bw) 1026 rd->bw_idx = 1; 1027 else 1028 bw_prev = 0; 1029 } else { 1030 rd->probe_val = rd->val[0]; 1031 } 1032 1033 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); 1034 if (bw_prev) { 1035 rd->bw_idx = 3; 1036 bw_prev = bw; 1037 } 1038 1039 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); 1040 if (bw_prev) { 1041 rd->bw_idx = 5; 1042 bw_prev = bw; 1043 } 1044 1045 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); 1046 if (bw_prev) 1047 rd->bw_idx = 7; 1048 1049 rd->rateset = rateset; 1050 rd->bw = bw; 1051 } 1052 1053 static int 1054 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, 1055 struct ieee80211_tx_rate *probe_rate, 1056 struct ieee80211_tx_rate *rates) 1057 { 1058 struct mt7615_dev *dev = phy->dev; 1059 struct mt7615_wtbl_rate_desc *wrd; 1060 1061 if (work_pending(&dev->rate_work)) 1062 return -EBUSY; 1063 1064 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); 1065 if (!wrd) 1066 return -ENOMEM; 1067 1068 wrd->sta = sta; 1069 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, 1070 &wrd->rate); 1071 list_add_tail(&wrd->node, &dev->wrd_head); 1072 queue_work(dev->mt76.wq, &dev->rate_work); 1073 1074 return 0; 1075 } 1076 1077 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) 1078 { 1079 u32 addr, val, val2; 1080 u8 offset; 1081 1082 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; 1083 1084 offset = tid * 12; 1085 addr += 4 * (offset / 32); 1086 offset %= 32; 1087 1088 val = mt76_rr(dev, addr); 1089 val >>= offset; 1090 1091 if (offset > 20) { 1092 addr += 4; 1093 val2 = mt76_rr(dev, addr); 1094 val |= val2 << (32 - offset); 1095 } 1096 1097 return val & GENMASK(11, 0); 1098 } 1099 1100 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, 1101 struct ieee80211_tx_rate *probe_rate, 1102 struct ieee80211_tx_rate *rates) 1103 { 1104 int wcid = sta->wcid.idx, n_rates = sta->n_rates; 1105 struct mt7615_dev *dev = phy->dev; 1106 struct mt7615_rate_desc rd; 1107 u32 w5, w27, addr; 1108 u16 idx = sta->vif->mt76.omac_idx; 1109 1110 if (!mt76_is_mmio(&dev->mt76)) { 1111 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); 1112 return; 1113 } 1114 1115 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1116 return; 1117 1118 memset(&rd, 0, sizeof(struct mt7615_rate_desc)); 1119 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); 1120 1121 addr = mt7615_mac_wtbl_addr(dev, wcid); 1122 w27 = mt76_rr(dev, addr + 27 * 4); 1123 w27 &= ~MT_WTBL_W27_CC_BW_SEL; 1124 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); 1125 1126 w5 = mt76_rr(dev, addr + 5 * 4); 1127 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | 1128 MT_WTBL_W5_MPDU_OK_COUNT | 1129 MT_WTBL_W5_MPDU_FAIL_COUNT | 1130 MT_WTBL_W5_RATE_IDX); 1131 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | 1132 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, 1133 rd.bw_idx ? rd.bw_idx - 1 : 7); 1134 1135 mt76_wr(dev, MT_WTBL_RIUCR0, w5); 1136 1137 mt76_wr(dev, MT_WTBL_RIUCR1, 1138 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | 1139 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | 1140 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); 1141 1142 mt76_wr(dev, MT_WTBL_RIUCR2, 1143 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | 1144 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | 1145 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | 1146 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); 1147 1148 mt76_wr(dev, MT_WTBL_RIUCR3, 1149 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | 1150 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | 1151 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); 1152 1153 mt76_wr(dev, MT_WTBL_UPDATE, 1154 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 1155 MT_WTBL_UPDATE_RATE_UPDATE | 1156 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 1157 1158 mt76_wr(dev, addr + 27 * 4, w27); 1159 1160 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; 1161 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); 1162 1163 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */ 1164 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); 1165 sta->rate_set_tsf |= rd.rateset; 1166 1167 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 1168 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 1169 1170 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; 1171 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 1172 sta->rate_probe = !!probe_rate; 1173 } 1174 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); 1175 1176 void mt7615_mac_enable_rtscts(struct mt7615_dev *dev, 1177 struct ieee80211_vif *vif, bool enable) 1178 { 1179 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1180 u32 addr; 1181 1182 addr = mt7615_mac_wtbl_addr(dev, mvif->sta.wcid.idx) + 3 * 4; 1183 1184 if (enable) 1185 mt76_set(dev, addr, MT_WTBL_W3_RTS); 1186 else 1187 mt76_clear(dev, addr, MT_WTBL_W3_RTS); 1188 } 1189 EXPORT_SYMBOL_GPL(mt7615_mac_enable_rtscts); 1190 1191 static int 1192 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1193 struct ieee80211_key_conf *key, 1194 enum mt76_cipher_type cipher, u16 cipher_mask) 1195 { 1196 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; 1197 u8 data[32] = {}; 1198 1199 if (key->keylen > sizeof(data)) 1200 return -EINVAL; 1201 1202 mt76_rr_copy(dev, addr, data, sizeof(data)); 1203 if (cipher == MT_CIPHER_TKIP) { 1204 /* Rx/Tx MIC keys are swapped */ 1205 memcpy(data, key->key, 16); 1206 memcpy(data + 16, key->key + 24, 8); 1207 memcpy(data + 24, key->key + 16, 8); 1208 } else { 1209 if (cipher_mask == BIT(cipher)) 1210 memcpy(data, key->key, key->keylen); 1211 else if (cipher != MT_CIPHER_BIP_CMAC_128) 1212 memcpy(data, key->key, 16); 1213 if (cipher == MT_CIPHER_BIP_CMAC_128) 1214 memcpy(data + 16, key->key, 16); 1215 } 1216 1217 mt76_wr_copy(dev, addr, data, sizeof(data)); 1218 1219 return 0; 1220 } 1221 1222 static int 1223 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1224 enum mt76_cipher_type cipher, u16 cipher_mask, 1225 int keyidx) 1226 { 1227 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; 1228 1229 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1230 return -ETIMEDOUT; 1231 1232 w0 = mt76_rr(dev, addr); 1233 w1 = mt76_rr(dev, addr + 4); 1234 1235 if (cipher_mask) 1236 w0 |= MT_WTBL_W0_RX_KEY_VALID; 1237 else 1238 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); 1239 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) 1240 w0 |= MT_WTBL_W0_RX_IK_VALID; 1241 else 1242 w0 &= ~MT_WTBL_W0_RX_IK_VALID; 1243 1244 if (cipher != MT_CIPHER_BIP_CMAC_128 || cipher_mask == BIT(cipher)) { 1245 w0 &= ~MT_WTBL_W0_KEY_IDX; 1246 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); 1247 } 1248 1249 mt76_wr(dev, MT_WTBL_RICR0, w0); 1250 mt76_wr(dev, MT_WTBL_RICR1, w1); 1251 1252 if (!mt7615_mac_wtbl_update(dev, wcid->idx, 1253 MT_WTBL_UPDATE_RXINFO_UPDATE)) 1254 return -ETIMEDOUT; 1255 1256 return 0; 1257 } 1258 1259 static void 1260 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1261 enum mt76_cipher_type cipher, u16 cipher_mask) 1262 { 1263 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); 1264 1265 if (cipher == MT_CIPHER_BIP_CMAC_128 && 1266 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) 1267 return; 1268 1269 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, 1270 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); 1271 } 1272 1273 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1274 struct mt76_wcid *wcid, 1275 struct ieee80211_key_conf *key) 1276 { 1277 enum mt76_cipher_type cipher; 1278 u16 cipher_mask = wcid->cipher; 1279 int err; 1280 1281 cipher = mt7615_mac_get_cipher(key->cipher); 1282 if (cipher == MT_CIPHER_NONE) 1283 return -EOPNOTSUPP; 1284 1285 cipher_mask |= BIT(cipher); 1286 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask); 1287 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask); 1288 if (err < 0) 1289 return err; 1290 1291 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, 1292 key->keyidx); 1293 if (err < 0) 1294 return err; 1295 1296 wcid->cipher = cipher_mask; 1297 1298 return 0; 1299 } 1300 1301 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1302 struct mt76_wcid *wcid, 1303 struct ieee80211_key_conf *key) 1304 { 1305 int err; 1306 1307 spin_lock_bh(&dev->mt76.lock); 1308 err = __mt7615_mac_wtbl_set_key(dev, wcid, key); 1309 spin_unlock_bh(&dev->mt76.lock); 1310 1311 return err; 1312 } 1313 1314 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, 1315 struct ieee80211_tx_info *info, __le32 *txs_data) 1316 { 1317 struct ieee80211_supported_band *sband; 1318 struct mt7615_rate_set *rs; 1319 struct mt76_phy *mphy; 1320 int first_idx = 0, last_idx; 1321 int i, idx, count; 1322 bool fixed_rate, ack_timeout; 1323 bool ampdu, cck = false; 1324 bool rs_idx; 1325 u32 rate_set_tsf; 1326 u32 final_rate, final_rate_flags, final_nss, txs; 1327 1328 txs = le32_to_cpu(txs_data[1]); 1329 ampdu = txs & MT_TXS1_AMPDU; 1330 1331 txs = le32_to_cpu(txs_data[3]); 1332 count = FIELD_GET(MT_TXS3_TX_COUNT, txs); 1333 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); 1334 1335 txs = le32_to_cpu(txs_data[0]); 1336 fixed_rate = txs & MT_TXS0_FIXED_RATE; 1337 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1338 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1339 1340 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1341 return false; 1342 1343 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1344 return false; 1345 1346 if (!ack_timeout) 1347 info->flags |= IEEE80211_TX_STAT_ACK; 1348 1349 info->status.ampdu_len = 1; 1350 info->status.ampdu_ack_len = !!(info->flags & 1351 IEEE80211_TX_STAT_ACK); 1352 1353 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1354 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1355 1356 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); 1357 1358 if (fixed_rate) { 1359 info->status.rates[0].count = count; 1360 i = 0; 1361 goto out; 1362 } 1363 1364 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1365 rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) - 1366 rate_set_tsf) < 1000000); 1367 rs_idx ^= rate_set_tsf & BIT(0); 1368 rs = &sta->rateset[rs_idx]; 1369 1370 if (!first_idx && rs->probe_rate.idx >= 0) { 1371 info->status.rates[0] = rs->probe_rate; 1372 1373 spin_lock_bh(&dev->mt76.lock); 1374 if (sta->rate_probe) { 1375 struct mt7615_phy *phy = &dev->phy; 1376 1377 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1378 phy = dev->mt76.phys[MT_BAND1]->priv; 1379 1380 mt7615_mac_set_rates(phy, sta, NULL, sta->rates); 1381 } 1382 spin_unlock_bh(&dev->mt76.lock); 1383 } else { 1384 info->status.rates[0] = rs->rates[first_idx / 2]; 1385 } 1386 info->status.rates[0].count = 0; 1387 1388 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1389 struct ieee80211_tx_rate *cur_rate; 1390 int cur_count; 1391 1392 cur_rate = &rs->rates[idx / 2]; 1393 cur_count = min_t(int, MT7615_RATE_RETRY, count); 1394 count -= cur_count; 1395 1396 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1397 cur_rate->flags != info->status.rates[i].flags)) { 1398 i++; 1399 if (i == ARRAY_SIZE(info->status.rates)) { 1400 i--; 1401 break; 1402 } 1403 1404 info->status.rates[i] = *cur_rate; 1405 info->status.rates[i].count = 0; 1406 } 1407 1408 info->status.rates[i].count += cur_count; 1409 } 1410 1411 out: 1412 final_rate_flags = info->status.rates[i].flags; 1413 1414 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1415 case MT_PHY_TYPE_CCK: 1416 cck = true; 1417 fallthrough; 1418 case MT_PHY_TYPE_OFDM: 1419 mphy = &dev->mphy; 1420 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1421 mphy = dev->mt76.phys[MT_BAND1]; 1422 1423 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1424 sband = &mphy->sband_5g.sband; 1425 else 1426 sband = &mphy->sband_2g.sband; 1427 final_rate &= MT_TX_RATE_IDX; 1428 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1429 cck); 1430 final_rate_flags = 0; 1431 break; 1432 case MT_PHY_TYPE_HT_GF: 1433 case MT_PHY_TYPE_HT: 1434 final_rate_flags |= IEEE80211_TX_RC_MCS; 1435 final_rate &= MT_TX_RATE_IDX; 1436 if (final_rate > 31) 1437 return false; 1438 break; 1439 case MT_PHY_TYPE_VHT: 1440 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); 1441 1442 if ((final_rate & MT_TX_RATE_STBC) && final_nss) 1443 final_nss--; 1444 1445 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; 1446 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); 1447 break; 1448 default: 1449 return false; 1450 } 1451 1452 info->status.rates[i].idx = final_rate; 1453 info->status.rates[i].flags = final_rate_flags; 1454 1455 return true; 1456 } 1457 1458 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, 1459 struct mt7615_sta *sta, int pid, 1460 __le32 *txs_data) 1461 { 1462 struct mt76_dev *mdev = &dev->mt76; 1463 struct sk_buff_head list; 1464 struct sk_buff *skb; 1465 1466 if (pid < MT_PACKET_ID_FIRST) 1467 return false; 1468 1469 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1470 1471 mt76_tx_status_lock(mdev, &list); 1472 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1473 if (skb) { 1474 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1475 1476 if (!mt7615_fill_txs(dev, sta, info, txs_data)) { 1477 info->status.rates[0].count = 0; 1478 info->status.rates[0].idx = -1; 1479 } 1480 1481 mt76_tx_status_skb_done(mdev, skb, &list); 1482 } 1483 mt76_tx_status_unlock(mdev, &list); 1484 1485 return !!skb; 1486 } 1487 1488 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) 1489 { 1490 struct ieee80211_tx_info info = {}; 1491 struct ieee80211_sta *sta = NULL; 1492 struct mt7615_sta *msta = NULL; 1493 struct mt76_wcid *wcid; 1494 struct mt76_phy *mphy = &dev->mt76.phy; 1495 __le32 *txs_data = data; 1496 u8 wcidx; 1497 u8 pid; 1498 1499 pid = le32_get_bits(txs_data[0], MT_TXS0_PID); 1500 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1501 1502 if (pid == MT_PACKET_ID_NO_ACK) 1503 return; 1504 1505 if (wcidx >= MT7615_WTBL_SIZE) 1506 return; 1507 1508 rcu_read_lock(); 1509 1510 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1511 if (!wcid) 1512 goto out; 1513 1514 msta = container_of(wcid, struct mt7615_sta, wcid); 1515 sta = wcid_to_sta(wcid); 1516 1517 spin_lock_bh(&dev->sta_poll_lock); 1518 if (list_empty(&msta->poll_list)) 1519 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1520 spin_unlock_bh(&dev->sta_poll_lock); 1521 1522 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) 1523 goto out; 1524 1525 if (wcidx >= MT7615_WTBL_STA || !sta) 1526 goto out; 1527 1528 if (wcid->phy_idx && dev->mt76.phys[MT_BAND1]) 1529 mphy = dev->mt76.phys[MT_BAND1]; 1530 1531 if (mt7615_fill_txs(dev, msta, &info, txs_data)) { 1532 spin_lock_bh(&dev->mt76.rx_lock); 1533 ieee80211_tx_status_noskb(mphy->hw, sta, &info); 1534 spin_unlock_bh(&dev->mt76.rx_lock); 1535 } 1536 1537 out: 1538 rcu_read_unlock(); 1539 } 1540 1541 static void 1542 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi) 1543 { 1544 struct mt76_dev *mdev = &dev->mt76; 1545 __le32 *txwi_data; 1546 u32 val; 1547 u8 wcid; 1548 1549 mt76_connac_txp_skb_unmap(mdev, txwi); 1550 if (!txwi->skb) 1551 goto out; 1552 1553 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); 1554 val = le32_to_cpu(txwi_data[1]); 1555 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); 1556 mt76_tx_complete_skb(mdev, wcid, txwi->skb); 1557 1558 out: 1559 txwi->skb = NULL; 1560 mt76_put_txwi(mdev, txwi); 1561 } 1562 1563 static void 1564 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) 1565 { 1566 struct mt76_dev *mdev = &dev->mt76; 1567 struct mt76_txwi_cache *txwi; 1568 1569 trace_mac_tx_free(dev, token); 1570 txwi = mt76_token_put(mdev, token); 1571 if (!txwi) 1572 return; 1573 1574 mt7615_txwi_free(dev, txwi); 1575 } 1576 1577 static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len) 1578 { 1579 struct mt76_connac_tx_free *free = data; 1580 void *tx_token = data + sizeof(*free); 1581 void *end = data + len; 1582 u8 i, count; 1583 1584 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1585 if (is_mt7615(&dev->mt76)) { 1586 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1587 } else { 1588 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1589 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); 1590 } 1591 1592 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT); 1593 if (is_mt7615(&dev->mt76)) { 1594 __le16 *token = tx_token; 1595 1596 if (WARN_ON_ONCE((void *)&token[count] > end)) 1597 return; 1598 1599 for (i = 0; i < count; i++) 1600 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); 1601 } else { 1602 __le32 *token = tx_token; 1603 1604 if (WARN_ON_ONCE((void *)&token[count] > end)) 1605 return; 1606 1607 for (i = 0; i < count; i++) 1608 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); 1609 } 1610 1611 rcu_read_lock(); 1612 mt7615_mac_sta_poll(dev); 1613 rcu_read_unlock(); 1614 1615 mt76_worker_schedule(&dev->mt76.tx_worker); 1616 } 1617 1618 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len) 1619 { 1620 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1621 __le32 *rxd = (__le32 *)data; 1622 __le32 *end = (__le32 *)&rxd[len / 4]; 1623 enum rx_pkt_type type; 1624 1625 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1626 1627 switch (type) { 1628 case PKT_TYPE_TXRX_NOTIFY: 1629 mt7615_mac_tx_free(dev, data, len); 1630 return false; 1631 case PKT_TYPE_TXS: 1632 for (rxd++; rxd + 7 <= end; rxd += 7) 1633 mt7615_mac_add_txs(dev, rxd); 1634 return false; 1635 default: 1636 return true; 1637 } 1638 } 1639 EXPORT_SYMBOL_GPL(mt7615_rx_check); 1640 1641 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1642 struct sk_buff *skb, u32 *info) 1643 { 1644 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1645 __le32 *rxd = (__le32 *)skb->data; 1646 __le32 *end = (__le32 *)&skb->data[skb->len]; 1647 enum rx_pkt_type type; 1648 u16 flag; 1649 1650 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1651 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG); 1652 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1653 type = PKT_TYPE_NORMAL_MCU; 1654 1655 switch (type) { 1656 case PKT_TYPE_TXS: 1657 for (rxd++; rxd + 7 <= end; rxd += 7) 1658 mt7615_mac_add_txs(dev, rxd); 1659 dev_kfree_skb(skb); 1660 break; 1661 case PKT_TYPE_TXRX_NOTIFY: 1662 mt7615_mac_tx_free(dev, skb->data, skb->len); 1663 dev_kfree_skb(skb); 1664 break; 1665 case PKT_TYPE_RX_EVENT: 1666 mt7615_mcu_rx_event(dev, skb); 1667 break; 1668 case PKT_TYPE_NORMAL_MCU: 1669 case PKT_TYPE_NORMAL: 1670 if (!mt7615_mac_fill_rx(dev, skb)) { 1671 mt76_rx(&dev->mt76, q, skb); 1672 return; 1673 } 1674 fallthrough; 1675 default: 1676 dev_kfree_skb(skb); 1677 break; 1678 } 1679 } 1680 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); 1681 1682 static void 1683 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) 1684 { 1685 struct mt7615_dev *dev = phy->dev; 1686 bool ext_phy = phy != &dev->phy; 1687 1688 if (is_mt7663(&dev->mt76)) { 1689 if (ofdm) 1690 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), 1691 MT_WF_PHY_PD_OFDM_MASK(0), 1692 MT_WF_PHY_PD_OFDM(0, val)); 1693 else 1694 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), 1695 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1696 MT_WF_PHY_PD_CCK(ext_phy, val)); 1697 return; 1698 } 1699 1700 if (ofdm) 1701 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), 1702 MT_WF_PHY_PD_OFDM_MASK(ext_phy), 1703 MT_WF_PHY_PD_OFDM(ext_phy, val)); 1704 else 1705 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), 1706 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1707 MT_WF_PHY_PD_CCK(ext_phy, val)); 1708 } 1709 1710 static void 1711 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) 1712 { 1713 /* ofdm */ 1714 mt7615_mac_set_sensitivity(phy, 0x13c, true); 1715 /* cck */ 1716 mt7615_mac_set_sensitivity(phy, 0x92, false); 1717 1718 phy->ofdm_sensitivity = -98; 1719 phy->cck_sensitivity = -110; 1720 phy->last_cca_adj = jiffies; 1721 } 1722 1723 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) 1724 { 1725 struct mt7615_dev *dev = phy->dev; 1726 bool ext_phy = phy != &dev->phy; 1727 u32 reg, mask; 1728 1729 mt7615_mutex_acquire(dev); 1730 1731 if (phy->scs_en == enable) 1732 goto out; 1733 1734 if (is_mt7663(&dev->mt76)) { 1735 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); 1736 mask = MT_WF_PHY_PD_BLK(0); 1737 } else { 1738 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); 1739 mask = MT_WF_PHY_PD_BLK(ext_phy); 1740 } 1741 1742 if (enable) { 1743 mt76_set(dev, reg, mask); 1744 if (is_mt7622(&dev->mt76)) { 1745 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); 1746 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); 1747 } 1748 } else { 1749 mt76_clear(dev, reg, mask); 1750 } 1751 1752 mt7615_mac_set_default_sensitivity(phy); 1753 phy->scs_en = enable; 1754 1755 out: 1756 mt7615_mutex_release(dev); 1757 } 1758 1759 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 1760 { 1761 u32 rxtd, reg; 1762 1763 if (is_mt7663(&dev->mt76)) 1764 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1765 else 1766 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1767 1768 if (ext_phy) 1769 rxtd = MT_WF_PHY_RXTD2(10); 1770 else 1771 rxtd = MT_WF_PHY_RXTD(12); 1772 1773 mt76_set(dev, rxtd, BIT(18) | BIT(29)); 1774 mt76_set(dev, reg, 0x5 << 12); 1775 } 1776 1777 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) 1778 { 1779 struct mt7615_dev *dev = phy->dev; 1780 bool ext_phy = phy != &dev->phy; 1781 u32 reg; 1782 1783 if (is_mt7663(&dev->mt76)) 1784 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1785 else 1786 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1787 1788 /* reset PD and MDRDY counters */ 1789 mt76_clear(dev, reg, GENMASK(22, 20)); 1790 mt76_set(dev, reg, BIT(22) | BIT(20)); 1791 } 1792 1793 static void 1794 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, 1795 u32 rts_err_rate, bool ofdm) 1796 { 1797 struct mt7615_dev *dev = phy->dev; 1798 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; 1799 bool ext_phy = phy != &dev->phy; 1800 s16 def_th = ofdm ? -98 : -110; 1801 bool update = false; 1802 s8 *sensitivity; 1803 int signal; 1804 1805 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; 1806 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); 1807 if (!signal) { 1808 mt7615_mac_set_default_sensitivity(phy); 1809 return; 1810 } 1811 1812 signal = min(signal, -72); 1813 if (false_cca > 500) { 1814 if (rts_err_rate > MT_FRAC(40, 100)) 1815 return; 1816 1817 /* decrease coverage */ 1818 if (*sensitivity == def_th && signal > -90) { 1819 *sensitivity = -90; 1820 update = true; 1821 } else if (*sensitivity + 2 < signal) { 1822 *sensitivity += 2; 1823 update = true; 1824 } 1825 } else if ((false_cca > 0 && false_cca < 50) || 1826 rts_err_rate > MT_FRAC(60, 100)) { 1827 /* increase coverage */ 1828 if (*sensitivity - 2 >= def_th) { 1829 *sensitivity -= 2; 1830 update = true; 1831 } 1832 } 1833 1834 if (*sensitivity > signal) { 1835 *sensitivity = signal; 1836 update = true; 1837 } 1838 1839 if (update) { 1840 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; 1841 1842 mt7615_mac_set_sensitivity(phy, val, ofdm); 1843 phy->last_cca_adj = jiffies; 1844 } 1845 } 1846 1847 static void 1848 mt7615_mac_scs_check(struct mt7615_phy *phy) 1849 { 1850 struct mt7615_dev *dev = phy->dev; 1851 struct mib_stats *mib = &phy->mib; 1852 u32 val, rts_err_rate = 0; 1853 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; 1854 bool ext_phy = phy != &dev->phy; 1855 1856 if (!phy->scs_en) 1857 return; 1858 1859 if (is_mt7663(&dev->mt76)) 1860 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1861 else 1862 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1863 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); 1864 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); 1865 1866 if (is_mt7663(&dev->mt76)) 1867 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1868 else 1869 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1870 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); 1871 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); 1872 1873 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1874 phy->false_cca_cck = pd_cck - mdrdy_cck; 1875 mt7615_mac_cca_stats_reset(phy); 1876 1877 if (mib->rts_cnt + mib->rts_retries_cnt) 1878 rts_err_rate = MT_FRAC(mib->rts_retries_cnt, 1879 mib->rts_cnt + mib->rts_retries_cnt); 1880 1881 /* cck */ 1882 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); 1883 /* ofdm */ 1884 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); 1885 1886 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) 1887 mt7615_mac_set_default_sensitivity(phy); 1888 } 1889 1890 static u8 1891 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) 1892 { 1893 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1894 u32 reg, val, sum = 0, n = 0; 1895 int i; 1896 1897 if (is_mt7663(&dev->mt76)) 1898 reg = MT7663_WF_PHY_RXTD(20); 1899 else 1900 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); 1901 1902 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1903 val = mt76_rr(dev, reg); 1904 sum += val * nf_power[i]; 1905 n += val; 1906 } 1907 1908 if (!n) 1909 return 0; 1910 1911 return sum / n; 1912 } 1913 1914 static void 1915 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) 1916 { 1917 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1918 struct mt7615_phy *phy = mphy->priv; 1919 struct mt76_channel_state *state; 1920 u64 busy_time, tx_time, rx_time, obss_time; 1921 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; 1922 int nf; 1923 1924 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1925 MT_MIB_SDR9_BUSY_MASK); 1926 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1927 MT_MIB_SDR36_TXTIME_MASK); 1928 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1929 MT_MIB_SDR37_RXTIME_MASK); 1930 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); 1931 1932 nf = mt7615_phy_get_nf(dev, idx); 1933 if (!phy->noise) 1934 phy->noise = nf << 4; 1935 else if (nf) 1936 phy->noise += nf - (phy->noise >> 4); 1937 1938 state = mphy->chan_state; 1939 state->cc_busy += busy_time; 1940 state->cc_tx += tx_time; 1941 state->cc_rx += rx_time + obss_time; 1942 state->cc_bss_rx += rx_time; 1943 state->noise = -(phy->noise >> 4); 1944 } 1945 1946 static void mt7615_update_survey(struct mt7615_dev *dev) 1947 { 1948 struct mt76_dev *mdev = &dev->mt76; 1949 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 1950 ktime_t cur_time; 1951 1952 /* MT7615 can only update both phys simultaneously 1953 * since some reisters are shared across bands. 1954 */ 1955 1956 mt7615_phy_update_channel(&mdev->phy, 0); 1957 if (mphy_ext) 1958 mt7615_phy_update_channel(mphy_ext, 1); 1959 1960 cur_time = ktime_get_boottime(); 1961 1962 mt76_update_survey_active_time(&mdev->phy, cur_time); 1963 if (mphy_ext) 1964 mt76_update_survey_active_time(mphy_ext, cur_time); 1965 1966 /* reset obss airtime */ 1967 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 1968 } 1969 1970 void mt7615_update_channel(struct mt76_phy *mphy) 1971 { 1972 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1973 1974 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) 1975 return; 1976 1977 mt7615_update_survey(dev); 1978 mt76_connac_power_save_sched(&dev->mphy, &dev->pm); 1979 } 1980 EXPORT_SYMBOL_GPL(mt7615_update_channel); 1981 1982 static void 1983 mt7615_mac_update_mib_stats(struct mt7615_phy *phy) 1984 { 1985 struct mt7615_dev *dev = phy->dev; 1986 struct mib_stats *mib = &phy->mib; 1987 bool ext_phy = phy != &dev->phy; 1988 int i, aggr = 0; 1989 u32 val, val2; 1990 1991 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 1992 MT_MIB_SDR3_FCS_ERR_MASK); 1993 1994 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), 1995 MT_MIB_AMPDU_MPDU_COUNT); 1996 if (val) { 1997 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), 1998 MT_MIB_AMPDU_ACK_COUNT); 1999 mib->aggr_per = 1000 * (val - val2) / val; 2000 } 2001 2002 for (i = 0; i < 4; i++) { 2003 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 2004 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2005 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, 2006 val); 2007 2008 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 2009 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2010 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, 2011 val); 2012 2013 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2014 phy->mt76->aggr_stats[aggr++] += val & 0xffff; 2015 phy->mt76->aggr_stats[aggr++] += val >> 16; 2016 } 2017 } 2018 2019 void mt7615_pm_wake_work(struct work_struct *work) 2020 { 2021 struct mt7615_dev *dev; 2022 struct mt76_phy *mphy; 2023 2024 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2025 pm.wake_work); 2026 mphy = dev->phy.mt76; 2027 2028 if (!mt7615_mcu_set_drv_ctrl(dev)) { 2029 struct mt76_dev *mdev = &dev->mt76; 2030 int i; 2031 2032 if (mt76_is_sdio(mdev)) { 2033 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2034 mt76_worker_schedule(&mdev->sdio.txrx_worker); 2035 } else { 2036 local_bh_disable(); 2037 mt76_for_each_q_rx(mdev, i) 2038 napi_schedule(&mdev->napi[i]); 2039 local_bh_enable(); 2040 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2041 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM], 2042 false); 2043 } 2044 2045 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) { 2046 unsigned long timeout; 2047 2048 timeout = mt7615_get_macwork_timeout(dev); 2049 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2050 timeout); 2051 } 2052 } 2053 2054 ieee80211_wake_queues(mphy->hw); 2055 wake_up(&dev->pm.wait); 2056 } 2057 2058 void mt7615_pm_power_save_work(struct work_struct *work) 2059 { 2060 struct mt7615_dev *dev; 2061 unsigned long delta; 2062 2063 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2064 pm.ps_work.work); 2065 2066 delta = dev->pm.idle_timeout; 2067 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || 2068 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) 2069 goto out; 2070 2071 if (mutex_is_locked(&dev->mt76.mutex)) 2072 /* if mt76 mutex is held we should not put the device 2073 * to sleep since we are currently accessing device 2074 * register map. We need to wait for the next power_save 2075 * trigger. 2076 */ 2077 goto out; 2078 2079 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 2080 delta = dev->pm.last_activity + delta - jiffies; 2081 goto out; 2082 } 2083 2084 if (!mt7615_mcu_set_fw_ctrl(dev)) 2085 return; 2086 out: 2087 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 2088 } 2089 2090 void mt7615_mac_work(struct work_struct *work) 2091 { 2092 struct mt7615_phy *phy; 2093 struct mt76_phy *mphy; 2094 unsigned long timeout; 2095 2096 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2097 mac_work.work); 2098 phy = mphy->priv; 2099 2100 mt7615_mutex_acquire(phy->dev); 2101 2102 mt7615_update_survey(phy->dev); 2103 if (++mphy->mac_work_count == 5) { 2104 mphy->mac_work_count = 0; 2105 2106 mt7615_mac_update_mib_stats(phy); 2107 mt7615_mac_scs_check(phy); 2108 } 2109 2110 mt7615_mutex_release(phy->dev); 2111 2112 mt76_tx_status_check(mphy->dev, false); 2113 2114 timeout = mt7615_get_macwork_timeout(phy->dev); 2115 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout); 2116 } 2117 2118 void mt7615_tx_token_put(struct mt7615_dev *dev) 2119 { 2120 struct mt76_txwi_cache *txwi; 2121 int id; 2122 2123 spin_lock_bh(&dev->mt76.token_lock); 2124 idr_for_each_entry(&dev->mt76.token, txwi, id) 2125 mt7615_txwi_free(dev, txwi); 2126 spin_unlock_bh(&dev->mt76.token_lock); 2127 idr_destroy(&dev->mt76.token); 2128 } 2129 EXPORT_SYMBOL_GPL(mt7615_tx_token_put); 2130 2131 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) 2132 { 2133 struct mt7615_dev *dev = phy->dev; 2134 2135 if (phy->rdd_state & BIT(0)) 2136 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2137 MT_RX_SEL0, 0); 2138 if (phy->rdd_state & BIT(1)) 2139 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2140 MT_RX_SEL0, 0); 2141 } 2142 2143 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) 2144 { 2145 int err; 2146 2147 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2148 MT_RX_SEL0, 0); 2149 if (err < 0) 2150 return err; 2151 2152 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2153 MT_RX_SEL0, 1); 2154 } 2155 2156 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) 2157 { 2158 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2159 struct mt7615_dev *dev = phy->dev; 2160 bool ext_phy = phy != &dev->phy; 2161 int err; 2162 2163 /* start CAC */ 2164 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy, 2165 MT_RX_SEL0, 0); 2166 if (err < 0) 2167 return err; 2168 2169 err = mt7615_dfs_start_rdd(dev, ext_phy); 2170 if (err < 0) 2171 return err; 2172 2173 phy->rdd_state |= BIT(ext_phy); 2174 2175 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2176 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2177 err = mt7615_dfs_start_rdd(dev, 1); 2178 if (err < 0) 2179 return err; 2180 2181 phy->rdd_state |= BIT(1); 2182 } 2183 2184 return 0; 2185 } 2186 2187 static int 2188 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) 2189 { 2190 const struct mt7615_dfs_radar_spec *radar_specs; 2191 struct mt7615_dev *dev = phy->dev; 2192 int err, i, lpn = 500; 2193 2194 switch (dev->mt76.region) { 2195 case NL80211_DFS_FCC: 2196 radar_specs = &fcc_radar_specs; 2197 lpn = 8; 2198 break; 2199 case NL80211_DFS_ETSI: 2200 radar_specs = &etsi_radar_specs; 2201 break; 2202 case NL80211_DFS_JP: 2203 radar_specs = &jp_radar_specs; 2204 break; 2205 default: 2206 return -EINVAL; 2207 } 2208 2209 /* avoid FCC radar detection in non-FCC region */ 2210 err = mt7615_mcu_set_fcc5_lpn(dev, lpn); 2211 if (err < 0) 2212 return err; 2213 2214 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2215 err = mt7615_mcu_set_radar_th(dev, i, 2216 &radar_specs->radar_pattern[i]); 2217 if (err < 0) 2218 return err; 2219 } 2220 2221 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2222 } 2223 2224 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) 2225 { 2226 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2227 struct mt7615_dev *dev = phy->dev; 2228 bool ext_phy = phy != &dev->phy; 2229 enum mt76_dfs_state dfs_state, prev_state; 2230 int err; 2231 2232 if (is_mt7663(&dev->mt76)) 2233 return 0; 2234 2235 prev_state = phy->mt76->dfs_state; 2236 dfs_state = mt76_phy_dfs_state(phy->mt76); 2237 if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2238 dfs_state < MT_DFS_STATE_CAC) 2239 dfs_state = MT_DFS_STATE_ACTIVE; 2240 2241 if (prev_state == dfs_state) 2242 return 0; 2243 2244 if (dfs_state == MT_DFS_STATE_DISABLED) 2245 goto stop; 2246 2247 if (prev_state <= MT_DFS_STATE_DISABLED) { 2248 err = mt7615_dfs_init_radar_specs(phy); 2249 if (err < 0) 2250 return err; 2251 2252 err = mt7615_dfs_start_radar_detector(phy); 2253 if (err < 0) 2254 return err; 2255 2256 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2257 } 2258 2259 if (dfs_state == MT_DFS_STATE_CAC) 2260 return 0; 2261 2262 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2263 ext_phy, MT_RX_SEL0, 0); 2264 if (err < 0) { 2265 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2266 return err; 2267 } 2268 2269 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2270 return 0; 2271 2272 stop: 2273 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy, 2274 MT_RX_SEL0, 0); 2275 if (err < 0) 2276 return err; 2277 2278 mt7615_dfs_stop_radar_detector(phy); 2279 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2280 2281 return 0; 2282 } 2283 2284 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, 2285 struct ieee80211_vif *vif, 2286 bool enable) 2287 { 2288 struct mt7615_dev *dev = phy->dev; 2289 bool ext_phy = phy != &dev->phy; 2290 int err; 2291 2292 if (!mt7615_firmware_offload(dev)) 2293 return -EOPNOTSUPP; 2294 2295 switch (vif->type) { 2296 case NL80211_IFTYPE_MONITOR: 2297 return 0; 2298 case NL80211_IFTYPE_MESH_POINT: 2299 case NL80211_IFTYPE_ADHOC: 2300 case NL80211_IFTYPE_AP: 2301 if (enable) 2302 phy->n_beacon_vif++; 2303 else 2304 phy->n_beacon_vif--; 2305 fallthrough; 2306 default: 2307 break; 2308 } 2309 2310 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); 2311 if (err) 2312 return err; 2313 2314 if (phy->n_beacon_vif) { 2315 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; 2316 mt76_clear(dev, MT_WF_RFCR(ext_phy), 2317 MT_WF_RFCR_DROP_OTHER_BEACON); 2318 } else { 2319 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; 2320 mt76_set(dev, MT_WF_RFCR(ext_phy), 2321 MT_WF_RFCR_DROP_OTHER_BEACON); 2322 } 2323 2324 return 0; 2325 } 2326 2327 void mt7615_coredump_work(struct work_struct *work) 2328 { 2329 struct mt7615_dev *dev; 2330 char *dump, *data; 2331 2332 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2333 coredump.work.work); 2334 2335 if (time_is_after_jiffies(dev->coredump.last_activity + 2336 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 2337 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 2338 MT76_CONNAC_COREDUMP_TIMEOUT); 2339 return; 2340 } 2341 2342 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 2343 data = dump; 2344 2345 while (true) { 2346 struct sk_buff *skb; 2347 2348 spin_lock_bh(&dev->mt76.lock); 2349 skb = __skb_dequeue(&dev->coredump.msg_list); 2350 spin_unlock_bh(&dev->mt76.lock); 2351 2352 if (!skb) 2353 break; 2354 2355 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 2356 if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 2357 dev_kfree_skb(skb); 2358 continue; 2359 } 2360 2361 memcpy(data, skb->data, skb->len); 2362 data += skb->len; 2363 2364 dev_kfree_skb(skb); 2365 } 2366 2367 if (dump) 2368 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 2369 GFP_KERNEL); 2370 } 2371