1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Felix Fietkau <nbd@nbd.name> 7 * Lorenzo Bianconi <lorenzo@kernel.org> 8 */ 9 10 #include <linux/devcoredump.h> 11 #include <linux/etherdevice.h> 12 #include <linux/timekeeping.h> 13 #include "mt7615.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 #include "mt7615_trace.h" 17 #include "mac.h" 18 #include "mcu.h" 19 20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 21 22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = { 23 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 24 .radar_pattern = { 25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, 26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, 27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, 28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, 29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, 30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, 31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, 32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, 33 }, 34 }; 35 36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = { 37 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 38 .radar_pattern = { 39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, 40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, 44 }, 45 }; 46 47 static const struct mt7615_dfs_radar_spec jp_radar_specs = { 48 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 49 .radar_pattern = { 50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, 51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, 55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, 56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, 57 }, 58 }; 59 60 static enum mt76_cipher_type 61 mt7615_mac_get_cipher(int cipher) 62 { 63 switch (cipher) { 64 case WLAN_CIPHER_SUITE_WEP40: 65 return MT_CIPHER_WEP40; 66 case WLAN_CIPHER_SUITE_WEP104: 67 return MT_CIPHER_WEP104; 68 case WLAN_CIPHER_SUITE_TKIP: 69 return MT_CIPHER_TKIP; 70 case WLAN_CIPHER_SUITE_AES_CMAC: 71 return MT_CIPHER_BIP_CMAC_128; 72 case WLAN_CIPHER_SUITE_CCMP: 73 return MT_CIPHER_AES_CCMP; 74 case WLAN_CIPHER_SUITE_CCMP_256: 75 return MT_CIPHER_CCMP_256; 76 case WLAN_CIPHER_SUITE_GCMP: 77 return MT_CIPHER_GCMP; 78 case WLAN_CIPHER_SUITE_GCMP_256: 79 return MT_CIPHER_GCMP_256; 80 case WLAN_CIPHER_SUITE_SMS4: 81 return MT_CIPHER_WAPI; 82 default: 83 return MT_CIPHER_NONE; 84 } 85 } 86 87 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, 88 u8 idx, bool unicast) 89 { 90 struct mt7615_sta *sta; 91 struct mt76_wcid *wcid; 92 93 if (idx >= MT7615_WTBL_SIZE) 94 return NULL; 95 96 wcid = rcu_dereference(dev->mt76.wcid[idx]); 97 if (unicast || !wcid) 98 return wcid; 99 100 if (!wcid->sta) 101 return NULL; 102 103 sta = container_of(wcid, struct mt7615_sta, wcid); 104 if (!sta->vif) 105 return NULL; 106 107 return &sta->vif->sta.wcid; 108 } 109 110 void mt7615_mac_reset_counters(struct mt7615_dev *dev) 111 { 112 int i; 113 114 for (i = 0; i < 4; i++) { 115 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 116 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); 117 } 118 119 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); 120 dev->mt76.phy.survey_time = ktime_get_boottime(); 121 if (dev->mt76.phy2) 122 dev->mt76.phy2->survey_time = ktime_get_boottime(); 123 124 /* reset airtime counters */ 125 mt76_rr(dev, MT_MIB_SDR9(0)); 126 mt76_rr(dev, MT_MIB_SDR9(1)); 127 128 mt76_rr(dev, MT_MIB_SDR36(0)); 129 mt76_rr(dev, MT_MIB_SDR36(1)); 130 131 mt76_rr(dev, MT_MIB_SDR37(0)); 132 mt76_rr(dev, MT_MIB_SDR37(1)); 133 134 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 135 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 136 } 137 138 void mt7615_mac_set_timing(struct mt7615_phy *phy) 139 { 140 s16 coverage_class = phy->coverage_class; 141 struct mt7615_dev *dev = phy->dev; 142 bool ext_phy = phy != &dev->phy; 143 u32 val, reg_offset; 144 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 145 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 146 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 147 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 148 int sifs, offset; 149 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 150 151 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 152 return; 153 154 if (is_5ghz) 155 sifs = 16; 156 else 157 sifs = 10; 158 159 if (ext_phy) { 160 coverage_class = max_t(s16, dev->phy.coverage_class, 161 coverage_class); 162 mt76_set(dev, MT_ARB_SCR, 163 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 164 } else { 165 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); 166 167 if (phy_ext) 168 coverage_class = max_t(s16, phy_ext->coverage_class, 169 coverage_class); 170 mt76_set(dev, MT_ARB_SCR, 171 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 172 } 173 udelay(1); 174 175 offset = 3 * coverage_class; 176 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 177 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 178 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); 179 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); 180 181 mt76_wr(dev, MT_TMAC_ICR(ext_phy), 182 FIELD_PREP(MT_IFS_EIFS, 360) | 183 FIELD_PREP(MT_IFS_RIFS, 2) | 184 FIELD_PREP(MT_IFS_SIFS, sifs) | 185 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 186 187 if (phy->slottime < 20 || is_5ghz) 188 val = MT7615_CFEND_RATE_DEFAULT; 189 else 190 val = MT7615_CFEND_RATE_11B; 191 192 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 193 if (ext_phy) 194 mt76_clear(dev, MT_ARB_SCR, 195 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 196 else 197 mt76_clear(dev, MT_ARB_SCR, 198 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 199 200 } 201 202 static void 203 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, 204 struct mt76_rx_status *status, u8 chfreq) 205 { 206 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 207 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 208 !test_bit(MT76_STATE_ROC, &mphy->state)) { 209 status->freq = mphy->chandef.chan->center_freq; 210 status->band = mphy->chandef.chan->band; 211 return; 212 } 213 214 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 215 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 216 } 217 218 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) 219 { 220 #ifdef CONFIG_NL80211_TESTMODE 221 u32 rxv1 = le32_to_cpu(rxv[0]); 222 u32 rxv3 = le32_to_cpu(rxv[2]); 223 u32 rxv4 = le32_to_cpu(rxv[3]); 224 u32 rxv5 = le32_to_cpu(rxv[4]); 225 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); 226 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); 227 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); 228 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; 229 230 if (!mode) { 231 /* CCK */ 232 foe &= ~BIT(11); 233 foe *= 1000; 234 foe >>= 11; 235 } else { 236 if (foe > 2048) 237 foe -= 4096; 238 239 foe = (foe * foe_const) >> 15; 240 } 241 242 phy->test.last_freq_offset = foe; 243 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); 244 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); 245 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); 246 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); 247 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); 248 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); 249 #endif 250 } 251 252 /* The HW does not translate the mac header to 802.3 for mesh point */ 253 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 254 { 255 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 256 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid; 257 struct ieee80211_sta *sta; 258 struct ieee80211_vif *vif; 259 struct ieee80211_hdr hdr; 260 struct ethhdr eth_hdr; 261 __le32 *rxd = (__le32 *)skb->data; 262 __le32 qos_ctrl, ht_ctrl; 263 264 if (FIELD_GET(MT_RXD1_NORMAL_ADDR_TYPE, le32_to_cpu(rxd[1])) != 265 MT_RXD1_NORMAL_U2M) 266 return -EINVAL; 267 268 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4)) 269 return -EINVAL; 270 271 if (!msta || !msta->vif) 272 return -EINVAL; 273 274 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 275 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 276 277 /* store the info from RXD and ethhdr to avoid being overridden */ 278 memcpy(ð_hdr, skb->data + hdr_gap, sizeof(eth_hdr)); 279 hdr.frame_control = FIELD_GET(MT_RXD4_FRAME_CONTROL, rxd[4]); 280 hdr.seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, rxd[6]); 281 qos_ctrl = FIELD_GET(MT_RXD6_QOS_CTL, rxd[6]); 282 ht_ctrl = FIELD_GET(MT_RXD7_HT_CONTROL, rxd[7]); 283 284 hdr.duration_id = 0; 285 ether_addr_copy(hdr.addr1, vif->addr); 286 ether_addr_copy(hdr.addr2, sta->addr); 287 switch (le16_to_cpu(hdr.frame_control) & 288 (IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS)) { 289 case 0: 290 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 291 break; 292 case IEEE80211_FCTL_FROMDS: 293 ether_addr_copy(hdr.addr3, eth_hdr.h_source); 294 break; 295 case IEEE80211_FCTL_TODS: 296 ether_addr_copy(hdr.addr3, eth_hdr.h_dest); 297 break; 298 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 299 ether_addr_copy(hdr.addr3, eth_hdr.h_dest); 300 ether_addr_copy(hdr.addr4, eth_hdr.h_source); 301 break; 302 default: 303 break; 304 } 305 306 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 307 if (eth_hdr.h_proto == htons(ETH_P_AARP) || 308 eth_hdr.h_proto == htons(ETH_P_IPX)) 309 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 310 else if (eth_hdr.h_proto >= htons(ETH_P_802_3_MIN)) 311 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 312 else 313 skb_pull(skb, 2); 314 315 if (ieee80211_has_order(hdr.frame_control)) 316 memcpy(skb_push(skb, 2), &ht_ctrl, 2); 317 if (ieee80211_is_data_qos(hdr.frame_control)) 318 memcpy(skb_push(skb, 2), &qos_ctrl, 2); 319 if (ieee80211_has_a4(hdr.frame_control)) 320 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 321 else 322 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 323 324 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU); 325 return 0; 326 } 327 328 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) 329 { 330 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 331 struct mt76_phy *mphy = &dev->mt76.phy; 332 struct mt7615_phy *phy = &dev->phy; 333 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL; 334 struct ieee80211_supported_band *sband; 335 struct ieee80211_hdr *hdr; 336 __le32 *rxd = (__le32 *)skb->data; 337 u32 rxd0 = le32_to_cpu(rxd[0]); 338 u32 rxd1 = le32_to_cpu(rxd[1]); 339 u32 rxd2 = le32_to_cpu(rxd[2]); 340 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 341 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; 342 u16 hdr_gap; 343 int phy_idx; 344 int i, idx; 345 u8 chfreq, amsdu_info, qos_ctl = 0; 346 u16 seq_ctrl = 0; 347 __le16 fc = 0; 348 349 memset(status, 0, sizeof(*status)); 350 351 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 352 if (!phy2) 353 phy_idx = 0; 354 else if (phy2->chfreq == phy->chfreq) 355 phy_idx = -1; 356 else if (phy->chfreq == chfreq) 357 phy_idx = 0; 358 else if (phy2->chfreq == chfreq) 359 phy_idx = 1; 360 else 361 phy_idx = -1; 362 363 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 364 return -EINVAL; 365 366 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; 367 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM)) 368 return -EINVAL; 369 370 /* ICV error or CCMP/BIP/WPI MIC error */ 371 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 372 status->flag |= RX_FLAG_ONLY_MONITOR; 373 374 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; 375 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 376 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); 377 378 if (status->wcid) { 379 struct mt7615_sta *msta; 380 381 msta = container_of(status->wcid, struct mt7615_sta, wcid); 382 spin_lock_bh(&dev->sta_poll_lock); 383 if (list_empty(&msta->poll_list)) 384 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 385 spin_unlock_bh(&dev->sta_poll_lock); 386 } 387 388 if ((rxd0 & csum_mask) == csum_mask) 389 skb->ip_summed = CHECKSUM_UNNECESSARY; 390 391 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 392 status->flag |= RX_FLAG_FAILED_FCS_CRC; 393 394 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 395 status->flag |= RX_FLAG_MMIC_ERROR; 396 397 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 398 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 399 status->flag |= RX_FLAG_DECRYPTED; 400 status->flag |= RX_FLAG_IV_STRIPPED; 401 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 402 } 403 404 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 405 406 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 407 return -EINVAL; 408 409 rxd += 4; 410 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 411 u32 v0 = le32_to_cpu(rxd[0]); 412 u32 v2 = le32_to_cpu(rxd[2]); 413 414 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); 415 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); 416 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); 417 418 rxd += 4; 419 if ((u8 *)rxd - skb->data >= skb->len) 420 return -EINVAL; 421 } 422 423 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 424 u8 *data = (u8 *)rxd; 425 426 if (status->flag & RX_FLAG_DECRYPTED) { 427 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 428 case MT_CIPHER_AES_CCMP: 429 case MT_CIPHER_CCMP_CCX: 430 case MT_CIPHER_CCMP_256: 431 insert_ccmp_hdr = 432 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 433 fallthrough; 434 case MT_CIPHER_TKIP: 435 case MT_CIPHER_TKIP_NO_MIC: 436 case MT_CIPHER_GCMP: 437 case MT_CIPHER_GCMP_256: 438 status->iv[0] = data[5]; 439 status->iv[1] = data[4]; 440 status->iv[2] = data[3]; 441 status->iv[3] = data[2]; 442 status->iv[4] = data[1]; 443 status->iv[5] = data[0]; 444 break; 445 default: 446 break; 447 } 448 } 449 rxd += 4; 450 if ((u8 *)rxd - skb->data >= skb->len) 451 return -EINVAL; 452 } 453 454 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 455 status->timestamp = le32_to_cpu(rxd[0]); 456 status->flag |= RX_FLAG_MACTIME_START; 457 458 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 459 MT_RXD2_NORMAL_NON_AMPDU))) { 460 status->flag |= RX_FLAG_AMPDU_DETAILS; 461 462 /* all subframes of an A-MPDU have the same timestamp */ 463 if (phy->rx_ampdu_ts != status->timestamp) { 464 if (!++phy->ampdu_ref) 465 phy->ampdu_ref++; 466 } 467 phy->rx_ampdu_ts = status->timestamp; 468 469 status->ampdu_ref = phy->ampdu_ref; 470 } 471 472 rxd += 2; 473 if ((u8 *)rxd - skb->data >= skb->len) 474 return -EINVAL; 475 } 476 477 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 478 u32 rxdg5 = le32_to_cpu(rxd[5]); 479 480 /* 481 * If both PHYs are on the same channel and we don't have a WCID, 482 * we need to figure out which PHY this packet was received on. 483 * On the primary PHY, the noise value for the chains belonging to the 484 * second PHY will be set to the noise value of the last packet from 485 * that PHY. 486 */ 487 if (phy_idx < 0) { 488 int first_chain = ffs(phy2->mt76->chainmask) - 1; 489 490 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; 491 } 492 } 493 494 if (phy_idx == 1 && phy2) { 495 mphy = dev->mt76.phy2; 496 phy = phy2; 497 status->ext_phy = true; 498 } 499 500 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) 501 return -EINVAL; 502 503 mt7615_get_status_freq_info(dev, mphy, status, chfreq); 504 if (status->band == NL80211_BAND_5GHZ) 505 sband = &mphy->sband_5g.sband; 506 else 507 sband = &mphy->sband_2g.sband; 508 509 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 510 return -EINVAL; 511 512 if (!sband->channels) 513 return -EINVAL; 514 515 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 516 u32 rxdg0 = le32_to_cpu(rxd[0]); 517 u32 rxdg1 = le32_to_cpu(rxd[1]); 518 u32 rxdg3 = le32_to_cpu(rxd[3]); 519 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 520 bool cck = false; 521 522 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 523 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 524 case MT_PHY_TYPE_CCK: 525 cck = true; 526 fallthrough; 527 case MT_PHY_TYPE_OFDM: 528 i = mt76_get_rate(&dev->mt76, sband, i, cck); 529 break; 530 case MT_PHY_TYPE_HT_GF: 531 case MT_PHY_TYPE_HT: 532 status->encoding = RX_ENC_HT; 533 if (i > 31) 534 return -EINVAL; 535 break; 536 case MT_PHY_TYPE_VHT: 537 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; 538 status->encoding = RX_ENC_VHT; 539 break; 540 default: 541 return -EINVAL; 542 } 543 status->rate_idx = i; 544 545 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { 546 case MT_PHY_BW_20: 547 break; 548 case MT_PHY_BW_40: 549 status->bw = RATE_INFO_BW_40; 550 break; 551 case MT_PHY_BW_80: 552 status->bw = RATE_INFO_BW_80; 553 break; 554 case MT_PHY_BW_160: 555 status->bw = RATE_INFO_BW_160; 556 break; 557 default: 558 return -EINVAL; 559 } 560 561 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 562 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 563 if (rxdg0 & MT_RXV1_HT_AD_CODE) 564 status->enc_flags |= RX_ENC_FLAG_LDPC; 565 566 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 567 568 status->chains = mphy->antenna_mask; 569 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); 570 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); 571 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); 572 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); 573 status->signal = status->chain_signal[0]; 574 575 for (i = 1; i < hweight8(mphy->antenna_mask); i++) { 576 if (!(status->chains & BIT(i))) 577 continue; 578 579 status->signal = max(status->signal, 580 status->chain_signal[i]); 581 } 582 583 mt7615_mac_fill_tm_rx(mphy->priv, rxd); 584 585 rxd += 6; 586 if ((u8 *)rxd - skb->data >= skb->len) 587 return -EINVAL; 588 } 589 590 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); 591 status->amsdu = !!amsdu_info; 592 if (status->amsdu) { 593 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; 594 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; 595 } 596 597 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 598 if (hdr_trans && ieee80211_has_morefrags(fc)) { 599 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap)) 600 return -EINVAL; 601 hdr_trans = false; 602 } else { 603 int pad_start = 0; 604 605 skb_pull(skb, hdr_gap); 606 if (!hdr_trans && status->amsdu) { 607 pad_start = ieee80211_get_hdrlen_from_skb(skb); 608 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 609 /* 610 * When header translation failure is indicated, 611 * the hardware will insert an extra 2-byte field 612 * containing the data length after the protocol 613 * type field. 614 */ 615 pad_start = 12; 616 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 617 pad_start += 4; 618 619 if (get_unaligned_be16(skb->data + pad_start) != 620 skb->len - pad_start - 2) 621 pad_start = 0; 622 } 623 624 if (pad_start) { 625 memmove(skb->data + 2, skb->data, pad_start); 626 skb_pull(skb, 2); 627 } 628 } 629 630 if (insert_ccmp_hdr && !hdr_trans) { 631 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 632 633 mt76_insert_ccmp_hdr(skb, key_id); 634 } 635 636 if (!hdr_trans) { 637 hdr = (struct ieee80211_hdr *)skb->data; 638 fc = hdr->frame_control; 639 if (ieee80211_is_data_qos(fc)) { 640 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 641 qos_ctl = *ieee80211_get_qos_ctl(hdr); 642 } 643 } else { 644 status->flag |= RX_FLAG_8023; 645 } 646 647 if (!status->wcid || !ieee80211_is_data_qos(fc)) 648 return 0; 649 650 status->aggr = unicast && 651 !ieee80211_is_qos_nullfunc(fc); 652 status->qos_ctl = qos_ctl; 653 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 654 655 return 0; 656 } 657 658 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 659 { 660 } 661 EXPORT_SYMBOL_GPL(mt7615_sta_ps); 662 663 static u16 664 mt7615_mac_tx_rate_val(struct mt7615_dev *dev, 665 struct mt76_phy *mphy, 666 const struct ieee80211_tx_rate *rate, 667 bool stbc, u8 *bw) 668 { 669 u8 phy, nss, rate_idx; 670 u16 rateval = 0; 671 672 *bw = 0; 673 674 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 675 rate_idx = ieee80211_rate_get_vht_mcs(rate); 676 nss = ieee80211_rate_get_vht_nss(rate); 677 phy = MT_PHY_TYPE_VHT; 678 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 679 *bw = 1; 680 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 681 *bw = 2; 682 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 683 *bw = 3; 684 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 685 rate_idx = rate->idx; 686 nss = 1 + (rate->idx >> 3); 687 phy = MT_PHY_TYPE_HT; 688 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 689 phy = MT_PHY_TYPE_HT_GF; 690 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 691 *bw = 1; 692 } else { 693 const struct ieee80211_rate *r; 694 int band = mphy->chandef.chan->band; 695 u16 val; 696 697 nss = 1; 698 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; 699 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 700 val = r->hw_value_short; 701 else 702 val = r->hw_value; 703 704 phy = val >> 8; 705 rate_idx = val & 0xff; 706 } 707 708 if (stbc && nss == 1) { 709 nss++; 710 rateval |= MT_TX_RATE_STBC; 711 } 712 713 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 714 FIELD_PREP(MT_TX_RATE_MODE, phy) | 715 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); 716 717 return rateval; 718 } 719 720 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, 721 struct sk_buff *skb, struct mt76_wcid *wcid, 722 struct ieee80211_sta *sta, int pid, 723 struct ieee80211_key_conf *key, bool beacon) 724 { 725 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 726 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 728 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 729 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY; 730 bool multicast = is_multicast_ether_addr(hdr->addr1); 731 struct ieee80211_vif *vif = info->control.vif; 732 bool is_mmio = mt76_is_mmio(&dev->mt76); 733 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; 734 struct mt76_phy *mphy = &dev->mphy; 735 __le16 fc = hdr->frame_control; 736 int tx_count = 8; 737 u16 seqno = 0; 738 739 if (vif) { 740 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 741 742 omac_idx = mvif->omac_idx; 743 wmm_idx = mvif->wmm_idx; 744 } 745 746 if (sta) { 747 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 748 749 tx_count = msta->rate_count; 750 } 751 752 if (ext_phy && dev->mt76.phy2) 753 mphy = dev->mt76.phy2; 754 755 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 756 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 757 758 if (beacon) { 759 p_fmt = MT_TX_TYPE_FW; 760 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0; 761 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) { 762 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 763 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; 764 } else { 765 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 766 q_idx = wmm_idx * MT7615_MAX_WMM_SETS + 767 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); 768 } 769 770 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 771 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | 772 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 773 txwi[0] = cpu_to_le32(val); 774 775 val = MT_TXD1_LONG_FORMAT | 776 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 777 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 778 FIELD_PREP(MT_TXD1_HDR_INFO, 779 ieee80211_get_hdrlen_from_skb(skb) / 2) | 780 FIELD_PREP(MT_TXD1_TID, 781 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 782 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | 783 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 784 txwi[1] = cpu_to_le32(val); 785 786 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 787 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 788 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 789 if (key) { 790 if (multicast && ieee80211_is_robust_mgmt_frame(skb) && 791 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 792 val |= MT_TXD2_BIP; 793 txwi[3] = 0; 794 } else { 795 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); 796 } 797 } else { 798 txwi[3] = 0; 799 } 800 txwi[2] = cpu_to_le32(val); 801 802 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 803 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 804 805 txwi[4] = 0; 806 txwi[6] = 0; 807 808 if (rate->idx >= 0 && rate->count && 809 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 810 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 811 u8 bw; 812 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, 813 &bw); 814 815 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 816 817 val = MT_TXD6_FIXED_BW | 818 FIELD_PREP(MT_TXD6_BW, bw) | 819 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 820 txwi[6] |= cpu_to_le32(val); 821 822 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 823 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 824 825 if (info->flags & IEEE80211_TX_CTL_LDPC) 826 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); 827 828 if (!(rate->flags & (IEEE80211_TX_RC_MCS | 829 IEEE80211_TX_RC_VHT_MCS))) 830 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 831 832 tx_count = rate->count; 833 } 834 835 if (!ieee80211_is_beacon(fc)) { 836 struct ieee80211_hw *hw = mt76_hw(dev); 837 838 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); 839 if (!ieee80211_hw_check(hw, SUPPORTS_PS)) 840 val |= MT_TXD5_SW_POWER_MGMT; 841 txwi[5] = cpu_to_le32(val); 842 } else { 843 txwi[5] = 0; 844 /* use maximum tx count for beacons */ 845 tx_count = 0x1f; 846 } 847 848 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 849 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 850 seqno = le16_to_cpu(hdr->seq_ctrl); 851 852 if (ieee80211_is_back_req(hdr->frame_control)) { 853 struct ieee80211_bar *bar; 854 855 bar = (struct ieee80211_bar *)skb->data; 856 seqno = le16_to_cpu(bar->start_seq_num); 857 } 858 859 val |= MT_TXD3_SN_VALID | 860 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 861 } 862 863 txwi[3] |= cpu_to_le32(val); 864 865 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 866 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); 867 868 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 869 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | 870 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); 871 txwi[7] = cpu_to_le32(val); 872 if (!is_mmio) { 873 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | 874 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); 875 txwi[8] = cpu_to_le32(val); 876 } 877 878 return 0; 879 } 880 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); 881 882 static void 883 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp) 884 { 885 int i; 886 887 for (i = 0; i < txp->nbuf; i++) 888 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]), 889 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE); 890 } 891 892 static void 893 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp) 894 { 895 u32 last_mask; 896 int i; 897 898 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST; 899 900 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) { 901 struct mt7615_txp_ptr *ptr = &txp->ptr[i]; 902 bool last; 903 u16 len; 904 905 len = le16_to_cpu(ptr->len0); 906 last = len & last_mask; 907 len &= MT_TXD_LEN_MASK; 908 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len, 909 DMA_TO_DEVICE); 910 if (last) 911 break; 912 913 len = le16_to_cpu(ptr->len1); 914 last = len & last_mask; 915 len &= MT_TXD_LEN_MASK; 916 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len, 917 DMA_TO_DEVICE); 918 if (last) 919 break; 920 } 921 } 922 923 void mt7615_txp_skb_unmap(struct mt76_dev *dev, 924 struct mt76_txwi_cache *t) 925 { 926 struct mt7615_txp_common *txp; 927 928 txp = mt7615_txwi_to_txp(dev, t); 929 if (is_mt7615(dev)) 930 mt7615_txp_skb_unmap_fw(dev, &txp->fw); 931 else 932 mt7615_txp_skb_unmap_hw(dev, &txp->hw); 933 } 934 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap); 935 936 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) 937 { 938 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 939 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 940 941 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 942 0, 5000); 943 } 944 945 void mt7615_mac_sta_poll(struct mt7615_dev *dev) 946 { 947 static const u8 ac_to_tid[4] = { 948 [IEEE80211_AC_BE] = 0, 949 [IEEE80211_AC_BK] = 1, 950 [IEEE80211_AC_VI] = 4, 951 [IEEE80211_AC_VO] = 6 952 }; 953 static const u8 hw_queue_map[] = { 954 [IEEE80211_AC_BK] = 0, 955 [IEEE80211_AC_BE] = 1, 956 [IEEE80211_AC_VI] = 2, 957 [IEEE80211_AC_VO] = 3, 958 }; 959 struct ieee80211_sta *sta; 960 struct mt7615_sta *msta; 961 u32 addr, tx_time[4], rx_time[4]; 962 struct list_head sta_poll_list; 963 int i; 964 965 INIT_LIST_HEAD(&sta_poll_list); 966 spin_lock_bh(&dev->sta_poll_lock); 967 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 968 spin_unlock_bh(&dev->sta_poll_lock); 969 970 while (!list_empty(&sta_poll_list)) { 971 bool clear = false; 972 973 msta = list_first_entry(&sta_poll_list, struct mt7615_sta, 974 poll_list); 975 list_del_init(&msta->poll_list); 976 977 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; 978 979 for (i = 0; i < 4; i++, addr += 8) { 980 u32 tx_last = msta->airtime_ac[i]; 981 u32 rx_last = msta->airtime_ac[i + 4]; 982 983 msta->airtime_ac[i] = mt76_rr(dev, addr); 984 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 985 tx_time[i] = msta->airtime_ac[i] - tx_last; 986 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 987 988 if ((tx_last | rx_last) & BIT(30)) 989 clear = true; 990 } 991 992 if (clear) { 993 mt7615_mac_wtbl_update(dev, msta->wcid.idx, 994 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 995 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 996 } 997 998 if (!msta->wcid.sta) 999 continue; 1000 1001 sta = container_of((void *)msta, struct ieee80211_sta, 1002 drv_priv); 1003 for (i = 0; i < 4; i++) { 1004 u32 tx_cur = tx_time[i]; 1005 u32 rx_cur = rx_time[hw_queue_map[i]]; 1006 u8 tid = ac_to_tid[i]; 1007 1008 if (!tx_cur && !rx_cur) 1009 continue; 1010 1011 ieee80211_sta_register_airtime(sta, tid, tx_cur, 1012 rx_cur); 1013 } 1014 } 1015 } 1016 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); 1017 1018 static void 1019 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, 1020 struct ieee80211_tx_rate *probe_rate, 1021 struct ieee80211_tx_rate *rates, 1022 struct mt7615_rate_desc *rd) 1023 { 1024 struct mt7615_dev *dev = phy->dev; 1025 struct mt76_phy *mphy = phy->mt76; 1026 struct ieee80211_tx_rate *ref; 1027 bool rateset, stbc = false; 1028 int n_rates = sta->n_rates; 1029 u8 bw, bw_prev; 1030 int i, j; 1031 1032 for (i = n_rates; i < 4; i++) 1033 rates[i] = rates[n_rates - 1]; 1034 1035 rateset = !(sta->rate_set_tsf & BIT(0)); 1036 memcpy(sta->rateset[rateset].rates, rates, 1037 sizeof(sta->rateset[rateset].rates)); 1038 if (probe_rate) { 1039 sta->rateset[rateset].probe_rate = *probe_rate; 1040 ref = &sta->rateset[rateset].probe_rate; 1041 } else { 1042 sta->rateset[rateset].probe_rate.idx = -1; 1043 ref = &sta->rateset[rateset].rates[0]; 1044 } 1045 1046 rates = sta->rateset[rateset].rates; 1047 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 1048 /* 1049 * We don't support switching between short and long GI 1050 * within the rate set. For accurate tx status reporting, we 1051 * need to make sure that flags match. 1052 * For improved performance, avoid duplicate entries by 1053 * decrementing the MCS index if necessary 1054 */ 1055 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 1056 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 1057 1058 for (j = 0; j < i; j++) { 1059 if (rates[i].idx != rates[j].idx) 1060 continue; 1061 if ((rates[i].flags ^ rates[j].flags) & 1062 (IEEE80211_TX_RC_40_MHZ_WIDTH | 1063 IEEE80211_TX_RC_80_MHZ_WIDTH | 1064 IEEE80211_TX_RC_160_MHZ_WIDTH)) 1065 continue; 1066 1067 if (!rates[i].idx) 1068 continue; 1069 1070 rates[i].idx--; 1071 } 1072 } 1073 1074 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); 1075 bw_prev = bw; 1076 1077 if (probe_rate) { 1078 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, 1079 stbc, &bw); 1080 if (bw) 1081 rd->bw_idx = 1; 1082 else 1083 bw_prev = 0; 1084 } else { 1085 rd->probe_val = rd->val[0]; 1086 } 1087 1088 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); 1089 if (bw_prev) { 1090 rd->bw_idx = 3; 1091 bw_prev = bw; 1092 } 1093 1094 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); 1095 if (bw_prev) { 1096 rd->bw_idx = 5; 1097 bw_prev = bw; 1098 } 1099 1100 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); 1101 if (bw_prev) 1102 rd->bw_idx = 7; 1103 1104 rd->rateset = rateset; 1105 rd->bw = bw; 1106 } 1107 1108 static int 1109 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, 1110 struct ieee80211_tx_rate *probe_rate, 1111 struct ieee80211_tx_rate *rates) 1112 { 1113 struct mt7615_dev *dev = phy->dev; 1114 struct mt7615_wtbl_rate_desc *wrd; 1115 1116 if (work_pending(&dev->rate_work)) 1117 return -EBUSY; 1118 1119 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); 1120 if (!wrd) 1121 return -ENOMEM; 1122 1123 wrd->sta = sta; 1124 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, 1125 &wrd->rate); 1126 list_add_tail(&wrd->node, &dev->wrd_head); 1127 queue_work(dev->mt76.wq, &dev->rate_work); 1128 1129 return 0; 1130 } 1131 1132 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) 1133 { 1134 u32 addr, val, val2; 1135 u8 offset; 1136 1137 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; 1138 1139 offset = tid * 12; 1140 addr += 4 * (offset / 32); 1141 offset %= 32; 1142 1143 val = mt76_rr(dev, addr); 1144 val >>= (tid % 32); 1145 1146 if (offset > 20) { 1147 addr += 4; 1148 val2 = mt76_rr(dev, addr); 1149 val |= val2 << (32 - offset); 1150 } 1151 1152 return val & GENMASK(11, 0); 1153 } 1154 1155 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, 1156 struct ieee80211_tx_rate *probe_rate, 1157 struct ieee80211_tx_rate *rates) 1158 { 1159 int wcid = sta->wcid.idx, n_rates = sta->n_rates; 1160 struct mt7615_dev *dev = phy->dev; 1161 struct mt7615_rate_desc rd; 1162 u32 w5, w27, addr; 1163 u16 idx = sta->vif->mt76.omac_idx; 1164 1165 if (!mt76_is_mmio(&dev->mt76)) { 1166 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); 1167 return; 1168 } 1169 1170 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1171 return; 1172 1173 memset(&rd, 0, sizeof(struct mt7615_rate_desc)); 1174 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); 1175 1176 addr = mt7615_mac_wtbl_addr(dev, wcid); 1177 w27 = mt76_rr(dev, addr + 27 * 4); 1178 w27 &= ~MT_WTBL_W27_CC_BW_SEL; 1179 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); 1180 1181 w5 = mt76_rr(dev, addr + 5 * 4); 1182 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | 1183 MT_WTBL_W5_MPDU_OK_COUNT | 1184 MT_WTBL_W5_MPDU_FAIL_COUNT | 1185 MT_WTBL_W5_RATE_IDX); 1186 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | 1187 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, 1188 rd.bw_idx ? rd.bw_idx - 1 : 7); 1189 1190 mt76_wr(dev, MT_WTBL_RIUCR0, w5); 1191 1192 mt76_wr(dev, MT_WTBL_RIUCR1, 1193 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | 1194 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | 1195 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); 1196 1197 mt76_wr(dev, MT_WTBL_RIUCR2, 1198 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | 1199 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | 1200 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | 1201 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); 1202 1203 mt76_wr(dev, MT_WTBL_RIUCR3, 1204 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | 1205 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | 1206 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); 1207 1208 mt76_wr(dev, MT_WTBL_UPDATE, 1209 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 1210 MT_WTBL_UPDATE_RATE_UPDATE | 1211 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 1212 1213 mt76_wr(dev, addr + 27 * 4, w27); 1214 1215 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; 1216 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); 1217 1218 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */ 1219 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); 1220 sta->rate_set_tsf |= rd.rateset; 1221 1222 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 1223 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 1224 1225 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; 1226 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 1227 sta->rate_probe = !!probe_rate; 1228 } 1229 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); 1230 1231 static int 1232 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1233 struct ieee80211_key_conf *key, 1234 enum mt76_cipher_type cipher, u16 cipher_mask, 1235 enum set_key_cmd cmd) 1236 { 1237 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; 1238 u8 data[32] = {}; 1239 1240 if (key->keylen > sizeof(data)) 1241 return -EINVAL; 1242 1243 mt76_rr_copy(dev, addr, data, sizeof(data)); 1244 if (cmd == SET_KEY) { 1245 if (cipher == MT_CIPHER_TKIP) { 1246 /* Rx/Tx MIC keys are swapped */ 1247 memcpy(data, key->key, 16); 1248 memcpy(data + 16, key->key + 24, 8); 1249 memcpy(data + 24, key->key + 16, 8); 1250 } else { 1251 if (cipher_mask == BIT(cipher)) 1252 memcpy(data, key->key, key->keylen); 1253 else if (cipher != MT_CIPHER_BIP_CMAC_128) 1254 memcpy(data, key->key, 16); 1255 if (cipher == MT_CIPHER_BIP_CMAC_128) 1256 memcpy(data + 16, key->key, 16); 1257 } 1258 } else { 1259 if (cipher == MT_CIPHER_BIP_CMAC_128) 1260 memset(data + 16, 0, 16); 1261 else if (cipher_mask) 1262 memset(data, 0, 16); 1263 if (!cipher_mask) 1264 memset(data, 0, sizeof(data)); 1265 } 1266 1267 mt76_wr_copy(dev, addr, data, sizeof(data)); 1268 1269 return 0; 1270 } 1271 1272 static int 1273 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1274 enum mt76_cipher_type cipher, u16 cipher_mask, 1275 int keyidx, enum set_key_cmd cmd) 1276 { 1277 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; 1278 1279 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1280 return -ETIMEDOUT; 1281 1282 w0 = mt76_rr(dev, addr); 1283 w1 = mt76_rr(dev, addr + 4); 1284 1285 if (cipher_mask) 1286 w0 |= MT_WTBL_W0_RX_KEY_VALID; 1287 else 1288 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); 1289 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) 1290 w0 |= MT_WTBL_W0_RX_IK_VALID; 1291 else 1292 w0 &= ~MT_WTBL_W0_RX_IK_VALID; 1293 1294 if (cmd == SET_KEY && 1295 (cipher != MT_CIPHER_BIP_CMAC_128 || 1296 cipher_mask == BIT(cipher))) { 1297 w0 &= ~MT_WTBL_W0_KEY_IDX; 1298 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); 1299 } 1300 1301 mt76_wr(dev, MT_WTBL_RICR0, w0); 1302 mt76_wr(dev, MT_WTBL_RICR1, w1); 1303 1304 if (!mt7615_mac_wtbl_update(dev, wcid->idx, 1305 MT_WTBL_UPDATE_RXINFO_UPDATE)) 1306 return -ETIMEDOUT; 1307 1308 return 0; 1309 } 1310 1311 static void 1312 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1313 enum mt76_cipher_type cipher, u16 cipher_mask, 1314 enum set_key_cmd cmd) 1315 { 1316 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); 1317 1318 if (!cipher_mask) { 1319 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); 1320 return; 1321 } 1322 1323 if (cmd != SET_KEY) 1324 return; 1325 1326 if (cipher == MT_CIPHER_BIP_CMAC_128 && 1327 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) 1328 return; 1329 1330 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, 1331 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); 1332 } 1333 1334 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1335 struct mt76_wcid *wcid, 1336 struct ieee80211_key_conf *key, 1337 enum set_key_cmd cmd) 1338 { 1339 enum mt76_cipher_type cipher; 1340 u16 cipher_mask = wcid->cipher; 1341 int err; 1342 1343 cipher = mt7615_mac_get_cipher(key->cipher); 1344 if (cipher == MT_CIPHER_NONE) 1345 return -EOPNOTSUPP; 1346 1347 if (cmd == SET_KEY) 1348 cipher_mask |= BIT(cipher); 1349 else 1350 cipher_mask &= ~BIT(cipher); 1351 1352 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd); 1353 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask, 1354 cmd); 1355 if (err < 0) 1356 return err; 1357 1358 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, 1359 key->keyidx, cmd); 1360 if (err < 0) 1361 return err; 1362 1363 wcid->cipher = cipher_mask; 1364 1365 return 0; 1366 } 1367 1368 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1369 struct mt76_wcid *wcid, 1370 struct ieee80211_key_conf *key, 1371 enum set_key_cmd cmd) 1372 { 1373 int err; 1374 1375 spin_lock_bh(&dev->mt76.lock); 1376 err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); 1377 spin_unlock_bh(&dev->mt76.lock); 1378 1379 return err; 1380 } 1381 1382 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, 1383 struct ieee80211_tx_info *info, __le32 *txs_data) 1384 { 1385 struct ieee80211_supported_band *sband; 1386 struct mt7615_rate_set *rs; 1387 struct mt76_phy *mphy; 1388 int first_idx = 0, last_idx; 1389 int i, idx, count; 1390 bool fixed_rate, ack_timeout; 1391 bool ampdu, cck = false; 1392 bool rs_idx; 1393 u32 rate_set_tsf; 1394 u32 final_rate, final_rate_flags, final_nss, txs; 1395 1396 txs = le32_to_cpu(txs_data[1]); 1397 ampdu = txs & MT_TXS1_AMPDU; 1398 1399 txs = le32_to_cpu(txs_data[3]); 1400 count = FIELD_GET(MT_TXS3_TX_COUNT, txs); 1401 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); 1402 1403 txs = le32_to_cpu(txs_data[0]); 1404 fixed_rate = txs & MT_TXS0_FIXED_RATE; 1405 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1406 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1407 1408 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1409 return false; 1410 1411 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1412 return false; 1413 1414 if (!ack_timeout) 1415 info->flags |= IEEE80211_TX_STAT_ACK; 1416 1417 info->status.ampdu_len = 1; 1418 info->status.ampdu_ack_len = !!(info->flags & 1419 IEEE80211_TX_STAT_ACK); 1420 1421 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1422 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1423 1424 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); 1425 1426 if (fixed_rate) { 1427 info->status.rates[0].count = count; 1428 i = 0; 1429 goto out; 1430 } 1431 1432 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1433 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) - 1434 rate_set_tsf) < 1000000); 1435 rs_idx ^= rate_set_tsf & BIT(0); 1436 rs = &sta->rateset[rs_idx]; 1437 1438 if (!first_idx && rs->probe_rate.idx >= 0) { 1439 info->status.rates[0] = rs->probe_rate; 1440 1441 spin_lock_bh(&dev->mt76.lock); 1442 if (sta->rate_probe) { 1443 struct mt7615_phy *phy = &dev->phy; 1444 1445 if (sta->wcid.ext_phy && dev->mt76.phy2) 1446 phy = dev->mt76.phy2->priv; 1447 1448 mt7615_mac_set_rates(phy, sta, NULL, sta->rates); 1449 } 1450 spin_unlock_bh(&dev->mt76.lock); 1451 } else { 1452 info->status.rates[0] = rs->rates[first_idx / 2]; 1453 } 1454 info->status.rates[0].count = 0; 1455 1456 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1457 struct ieee80211_tx_rate *cur_rate; 1458 int cur_count; 1459 1460 cur_rate = &rs->rates[idx / 2]; 1461 cur_count = min_t(int, MT7615_RATE_RETRY, count); 1462 count -= cur_count; 1463 1464 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1465 cur_rate->flags != info->status.rates[i].flags)) { 1466 i++; 1467 if (i == ARRAY_SIZE(info->status.rates)) { 1468 i--; 1469 break; 1470 } 1471 1472 info->status.rates[i] = *cur_rate; 1473 info->status.rates[i].count = 0; 1474 } 1475 1476 info->status.rates[i].count += cur_count; 1477 } 1478 1479 out: 1480 final_rate_flags = info->status.rates[i].flags; 1481 1482 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1483 case MT_PHY_TYPE_CCK: 1484 cck = true; 1485 fallthrough; 1486 case MT_PHY_TYPE_OFDM: 1487 mphy = &dev->mphy; 1488 if (sta->wcid.ext_phy && dev->mt76.phy2) 1489 mphy = dev->mt76.phy2; 1490 1491 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1492 sband = &mphy->sband_5g.sband; 1493 else 1494 sband = &mphy->sband_2g.sband; 1495 final_rate &= MT_TX_RATE_IDX; 1496 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1497 cck); 1498 final_rate_flags = 0; 1499 break; 1500 case MT_PHY_TYPE_HT_GF: 1501 case MT_PHY_TYPE_HT: 1502 final_rate_flags |= IEEE80211_TX_RC_MCS; 1503 final_rate &= MT_TX_RATE_IDX; 1504 if (final_rate > 31) 1505 return false; 1506 break; 1507 case MT_PHY_TYPE_VHT: 1508 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); 1509 1510 if ((final_rate & MT_TX_RATE_STBC) && final_nss) 1511 final_nss--; 1512 1513 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; 1514 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); 1515 break; 1516 default: 1517 return false; 1518 } 1519 1520 info->status.rates[i].idx = final_rate; 1521 info->status.rates[i].flags = final_rate_flags; 1522 1523 return true; 1524 } 1525 1526 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, 1527 struct mt7615_sta *sta, int pid, 1528 __le32 *txs_data) 1529 { 1530 struct mt76_dev *mdev = &dev->mt76; 1531 struct sk_buff_head list; 1532 struct sk_buff *skb; 1533 1534 if (pid < MT_PACKET_ID_FIRST) 1535 return false; 1536 1537 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1538 1539 mt76_tx_status_lock(mdev, &list); 1540 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1541 if (skb) { 1542 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1543 1544 if (!mt7615_fill_txs(dev, sta, info, txs_data)) { 1545 info->status.rates[0].count = 0; 1546 info->status.rates[0].idx = -1; 1547 } 1548 1549 mt76_tx_status_skb_done(mdev, skb, &list); 1550 } 1551 mt76_tx_status_unlock(mdev, &list); 1552 1553 return !!skb; 1554 } 1555 1556 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) 1557 { 1558 struct ieee80211_tx_info info = {}; 1559 struct ieee80211_sta *sta = NULL; 1560 struct mt7615_sta *msta = NULL; 1561 struct mt76_wcid *wcid; 1562 struct mt76_phy *mphy = &dev->mt76.phy; 1563 __le32 *txs_data = data; 1564 u32 txs; 1565 u8 wcidx; 1566 u8 pid; 1567 1568 txs = le32_to_cpu(txs_data[0]); 1569 pid = FIELD_GET(MT_TXS0_PID, txs); 1570 txs = le32_to_cpu(txs_data[2]); 1571 wcidx = FIELD_GET(MT_TXS2_WCID, txs); 1572 1573 if (pid == MT_PACKET_ID_NO_ACK) 1574 return; 1575 1576 if (wcidx >= MT7615_WTBL_SIZE) 1577 return; 1578 1579 rcu_read_lock(); 1580 1581 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1582 if (!wcid) 1583 goto out; 1584 1585 msta = container_of(wcid, struct mt7615_sta, wcid); 1586 sta = wcid_to_sta(wcid); 1587 1588 spin_lock_bh(&dev->sta_poll_lock); 1589 if (list_empty(&msta->poll_list)) 1590 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1591 spin_unlock_bh(&dev->sta_poll_lock); 1592 1593 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) 1594 goto out; 1595 1596 if (wcidx >= MT7615_WTBL_STA || !sta) 1597 goto out; 1598 1599 if (wcid->ext_phy && dev->mt76.phy2) 1600 mphy = dev->mt76.phy2; 1601 1602 if (mt7615_fill_txs(dev, msta, &info, txs_data)) 1603 ieee80211_tx_status_noskb(mphy->hw, sta, &info); 1604 1605 out: 1606 rcu_read_unlock(); 1607 } 1608 1609 static void 1610 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi) 1611 { 1612 struct mt76_dev *mdev = &dev->mt76; 1613 __le32 *txwi_data; 1614 u32 val; 1615 u8 wcid; 1616 1617 mt7615_txp_skb_unmap(mdev, txwi); 1618 if (!txwi->skb) 1619 goto out; 1620 1621 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); 1622 val = le32_to_cpu(txwi_data[1]); 1623 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); 1624 mt76_tx_complete_skb(mdev, wcid, txwi->skb); 1625 1626 out: 1627 txwi->skb = NULL; 1628 mt76_put_txwi(mdev, txwi); 1629 } 1630 1631 static void 1632 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) 1633 { 1634 struct mt76_dev *mdev = &dev->mt76; 1635 struct mt76_txwi_cache *txwi; 1636 1637 trace_mac_tx_free(dev, token); 1638 txwi = mt76_token_put(mdev, token); 1639 if (!txwi) 1640 return; 1641 1642 mt7615_txwi_free(dev, txwi); 1643 } 1644 1645 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb) 1646 { 1647 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data; 1648 u8 i, count; 1649 1650 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1651 if (is_mt7615(&dev->mt76)) { 1652 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1653 } else { 1654 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1655 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); 1656 } 1657 1658 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl)); 1659 if (is_mt7615(&dev->mt76)) { 1660 __le16 *token = &free->token[0]; 1661 1662 for (i = 0; i < count; i++) 1663 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); 1664 } else { 1665 __le32 *token = (__le32 *)&free->token[0]; 1666 1667 for (i = 0; i < count; i++) 1668 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); 1669 } 1670 1671 dev_kfree_skb(skb); 1672 1673 rcu_read_lock(); 1674 mt7615_mac_sta_poll(dev); 1675 rcu_read_unlock(); 1676 1677 mt76_worker_schedule(&dev->mt76.tx_worker); 1678 } 1679 1680 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1681 struct sk_buff *skb) 1682 { 1683 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1684 __le32 *rxd = (__le32 *)skb->data; 1685 __le32 *end = (__le32 *)&skb->data[skb->len]; 1686 enum rx_pkt_type type; 1687 u16 flag; 1688 1689 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0])); 1690 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0])); 1691 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1692 type = PKT_TYPE_NORMAL_MCU; 1693 1694 switch (type) { 1695 case PKT_TYPE_TXS: 1696 for (rxd++; rxd + 7 <= end; rxd += 7) 1697 mt7615_mac_add_txs(dev, rxd); 1698 dev_kfree_skb(skb); 1699 break; 1700 case PKT_TYPE_TXRX_NOTIFY: 1701 mt7615_mac_tx_free(dev, skb); 1702 break; 1703 case PKT_TYPE_RX_EVENT: 1704 mt7615_mcu_rx_event(dev, skb); 1705 break; 1706 case PKT_TYPE_NORMAL_MCU: 1707 case PKT_TYPE_NORMAL: 1708 if (!mt7615_mac_fill_rx(dev, skb)) { 1709 mt76_rx(&dev->mt76, q, skb); 1710 return; 1711 } 1712 fallthrough; 1713 default: 1714 dev_kfree_skb(skb); 1715 break; 1716 } 1717 } 1718 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); 1719 1720 static void 1721 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) 1722 { 1723 struct mt7615_dev *dev = phy->dev; 1724 bool ext_phy = phy != &dev->phy; 1725 1726 if (is_mt7663(&dev->mt76)) { 1727 if (ofdm) 1728 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), 1729 MT_WF_PHY_PD_OFDM_MASK(0), 1730 MT_WF_PHY_PD_OFDM(0, val)); 1731 else 1732 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), 1733 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1734 MT_WF_PHY_PD_CCK(ext_phy, val)); 1735 return; 1736 } 1737 1738 if (ofdm) 1739 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), 1740 MT_WF_PHY_PD_OFDM_MASK(ext_phy), 1741 MT_WF_PHY_PD_OFDM(ext_phy, val)); 1742 else 1743 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), 1744 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1745 MT_WF_PHY_PD_CCK(ext_phy, val)); 1746 } 1747 1748 static void 1749 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) 1750 { 1751 /* ofdm */ 1752 mt7615_mac_set_sensitivity(phy, 0x13c, true); 1753 /* cck */ 1754 mt7615_mac_set_sensitivity(phy, 0x92, false); 1755 1756 phy->ofdm_sensitivity = -98; 1757 phy->cck_sensitivity = -110; 1758 phy->last_cca_adj = jiffies; 1759 } 1760 1761 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) 1762 { 1763 struct mt7615_dev *dev = phy->dev; 1764 bool ext_phy = phy != &dev->phy; 1765 u32 reg, mask; 1766 1767 mt7615_mutex_acquire(dev); 1768 1769 if (phy->scs_en == enable) 1770 goto out; 1771 1772 if (is_mt7663(&dev->mt76)) { 1773 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); 1774 mask = MT_WF_PHY_PD_BLK(0); 1775 } else { 1776 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); 1777 mask = MT_WF_PHY_PD_BLK(ext_phy); 1778 } 1779 1780 if (enable) { 1781 mt76_set(dev, reg, mask); 1782 if (is_mt7622(&dev->mt76)) { 1783 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); 1784 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); 1785 } 1786 } else { 1787 mt76_clear(dev, reg, mask); 1788 } 1789 1790 mt7615_mac_set_default_sensitivity(phy); 1791 phy->scs_en = enable; 1792 1793 out: 1794 mt7615_mutex_release(dev); 1795 } 1796 1797 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 1798 { 1799 u32 rxtd, reg; 1800 1801 if (is_mt7663(&dev->mt76)) 1802 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1803 else 1804 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1805 1806 if (ext_phy) 1807 rxtd = MT_WF_PHY_RXTD2(10); 1808 else 1809 rxtd = MT_WF_PHY_RXTD(12); 1810 1811 mt76_set(dev, rxtd, BIT(18) | BIT(29)); 1812 mt76_set(dev, reg, 0x5 << 12); 1813 } 1814 1815 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) 1816 { 1817 struct mt7615_dev *dev = phy->dev; 1818 bool ext_phy = phy != &dev->phy; 1819 u32 reg; 1820 1821 if (is_mt7663(&dev->mt76)) 1822 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1823 else 1824 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1825 1826 /* reset PD and MDRDY counters */ 1827 mt76_clear(dev, reg, GENMASK(22, 20)); 1828 mt76_set(dev, reg, BIT(22) | BIT(20)); 1829 } 1830 1831 static void 1832 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, 1833 u32 rts_err_rate, bool ofdm) 1834 { 1835 struct mt7615_dev *dev = phy->dev; 1836 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; 1837 bool ext_phy = phy != &dev->phy; 1838 u16 def_th = ofdm ? -98 : -110; 1839 bool update = false; 1840 s8 *sensitivity; 1841 int signal; 1842 1843 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; 1844 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); 1845 if (!signal) { 1846 mt7615_mac_set_default_sensitivity(phy); 1847 return; 1848 } 1849 1850 signal = min(signal, -72); 1851 if (false_cca > 500) { 1852 if (rts_err_rate > MT_FRAC(40, 100)) 1853 return; 1854 1855 /* decrease coverage */ 1856 if (*sensitivity == def_th && signal > -90) { 1857 *sensitivity = -90; 1858 update = true; 1859 } else if (*sensitivity + 2 < signal) { 1860 *sensitivity += 2; 1861 update = true; 1862 } 1863 } else if ((false_cca > 0 && false_cca < 50) || 1864 rts_err_rate > MT_FRAC(60, 100)) { 1865 /* increase coverage */ 1866 if (*sensitivity - 2 >= def_th) { 1867 *sensitivity -= 2; 1868 update = true; 1869 } 1870 } 1871 1872 if (*sensitivity > signal) { 1873 *sensitivity = signal; 1874 update = true; 1875 } 1876 1877 if (update) { 1878 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; 1879 1880 mt7615_mac_set_sensitivity(phy, val, ofdm); 1881 phy->last_cca_adj = jiffies; 1882 } 1883 } 1884 1885 static void 1886 mt7615_mac_scs_check(struct mt7615_phy *phy) 1887 { 1888 struct mt7615_dev *dev = phy->dev; 1889 struct mib_stats *mib = &phy->mib; 1890 u32 val, rts_err_rate = 0; 1891 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; 1892 bool ext_phy = phy != &dev->phy; 1893 1894 if (!phy->scs_en) 1895 return; 1896 1897 if (is_mt7663(&dev->mt76)) 1898 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1899 else 1900 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1901 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); 1902 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); 1903 1904 if (is_mt7663(&dev->mt76)) 1905 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1906 else 1907 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1908 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); 1909 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); 1910 1911 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1912 phy->false_cca_cck = pd_cck - mdrdy_cck; 1913 mt7615_mac_cca_stats_reset(phy); 1914 1915 if (mib->rts_cnt + mib->rts_retries_cnt) 1916 rts_err_rate = MT_FRAC(mib->rts_retries_cnt, 1917 mib->rts_cnt + mib->rts_retries_cnt); 1918 1919 /* cck */ 1920 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); 1921 /* ofdm */ 1922 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); 1923 1924 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) 1925 mt7615_mac_set_default_sensitivity(phy); 1926 } 1927 1928 static u8 1929 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) 1930 { 1931 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1932 u32 reg, val, sum = 0, n = 0; 1933 int i; 1934 1935 if (is_mt7663(&dev->mt76)) 1936 reg = MT7663_WF_PHY_RXTD(20); 1937 else 1938 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); 1939 1940 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1941 val = mt76_rr(dev, reg); 1942 sum += val * nf_power[i]; 1943 n += val; 1944 } 1945 1946 if (!n) 1947 return 0; 1948 1949 return sum / n; 1950 } 1951 1952 static void 1953 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) 1954 { 1955 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1956 struct mt7615_phy *phy = mphy->priv; 1957 struct mt76_channel_state *state; 1958 u64 busy_time, tx_time, rx_time, obss_time; 1959 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; 1960 int nf; 1961 1962 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1963 MT_MIB_SDR9_BUSY_MASK); 1964 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1965 MT_MIB_SDR36_TXTIME_MASK); 1966 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1967 MT_MIB_SDR37_RXTIME_MASK); 1968 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); 1969 1970 nf = mt7615_phy_get_nf(dev, idx); 1971 if (!phy->noise) 1972 phy->noise = nf << 4; 1973 else if (nf) 1974 phy->noise += nf - (phy->noise >> 4); 1975 1976 state = mphy->chan_state; 1977 state->cc_busy += busy_time; 1978 state->cc_tx += tx_time; 1979 state->cc_rx += rx_time + obss_time; 1980 state->cc_bss_rx += rx_time; 1981 state->noise = -(phy->noise >> 4); 1982 } 1983 1984 static void mt7615_update_survey(struct mt7615_dev *dev) 1985 { 1986 struct mt76_dev *mdev = &dev->mt76; 1987 ktime_t cur_time; 1988 1989 /* MT7615 can only update both phys simultaneously 1990 * since some reisters are shared across bands. 1991 */ 1992 1993 mt7615_phy_update_channel(&mdev->phy, 0); 1994 if (mdev->phy2) 1995 mt7615_phy_update_channel(mdev->phy2, 1); 1996 1997 cur_time = ktime_get_boottime(); 1998 1999 mt76_update_survey_active_time(&mdev->phy, cur_time); 2000 if (mdev->phy2) 2001 mt76_update_survey_active_time(mdev->phy2, cur_time); 2002 2003 /* reset obss airtime */ 2004 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 2005 } 2006 2007 void mt7615_update_channel(struct mt76_phy *mphy) 2008 { 2009 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 2010 2011 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) 2012 return; 2013 2014 mt7615_update_survey(dev); 2015 mt76_connac_power_save_sched(&dev->mphy, &dev->pm); 2016 } 2017 EXPORT_SYMBOL_GPL(mt7615_update_channel); 2018 2019 static void 2020 mt7615_mac_update_mib_stats(struct mt7615_phy *phy) 2021 { 2022 struct mt7615_dev *dev = phy->dev; 2023 struct mib_stats *mib = &phy->mib; 2024 bool ext_phy = phy != &dev->phy; 2025 int i, aggr; 2026 u32 val, val2; 2027 2028 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 2029 MT_MIB_SDR3_FCS_ERR_MASK); 2030 2031 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), 2032 MT_MIB_AMPDU_MPDU_COUNT); 2033 if (val) { 2034 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), 2035 MT_MIB_AMPDU_ACK_COUNT); 2036 mib->aggr_per = 1000 * (val - val2) / val; 2037 } 2038 2039 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 2040 for (i = 0; i < 4; i++) { 2041 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 2042 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2043 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, 2044 val); 2045 2046 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 2047 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2048 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, 2049 val); 2050 2051 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2052 dev->mt76.aggr_stats[aggr++] += val & 0xffff; 2053 dev->mt76.aggr_stats[aggr++] += val >> 16; 2054 } 2055 } 2056 2057 void mt7615_pm_wake_work(struct work_struct *work) 2058 { 2059 struct mt7615_dev *dev; 2060 struct mt76_phy *mphy; 2061 2062 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2063 pm.wake_work); 2064 mphy = dev->phy.mt76; 2065 2066 if (!mt7615_mcu_set_drv_ctrl(dev)) { 2067 struct mt76_dev *mdev = &dev->mt76; 2068 int i; 2069 2070 if (mt76_is_sdio(mdev)) { 2071 mt76_worker_schedule(&mdev->sdio.txrx_worker); 2072 } else { 2073 mt76_for_each_q_rx(mdev, i) 2074 napi_schedule(&mdev->napi[i]); 2075 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2076 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM], 2077 false); 2078 } 2079 2080 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) { 2081 unsigned long timeout; 2082 2083 timeout = mt7615_get_macwork_timeout(dev); 2084 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2085 timeout); 2086 } 2087 } 2088 2089 ieee80211_wake_queues(mphy->hw); 2090 wake_up(&dev->pm.wait); 2091 } 2092 2093 void mt7615_pm_power_save_work(struct work_struct *work) 2094 { 2095 struct mt7615_dev *dev; 2096 unsigned long delta; 2097 2098 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2099 pm.ps_work.work); 2100 2101 delta = dev->pm.idle_timeout; 2102 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || 2103 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) 2104 goto out; 2105 2106 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 2107 delta = dev->pm.last_activity + delta - jiffies; 2108 goto out; 2109 } 2110 2111 if (!mt7615_mcu_set_fw_ctrl(dev)) 2112 return; 2113 out: 2114 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 2115 } 2116 2117 void mt7615_mac_work(struct work_struct *work) 2118 { 2119 struct mt7615_phy *phy; 2120 struct mt76_phy *mphy; 2121 unsigned long timeout; 2122 2123 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2124 mac_work.work); 2125 phy = mphy->priv; 2126 2127 mt7615_mutex_acquire(phy->dev); 2128 2129 mt7615_update_survey(phy->dev); 2130 if (++mphy->mac_work_count == 5) { 2131 mphy->mac_work_count = 0; 2132 2133 mt7615_mac_update_mib_stats(phy); 2134 mt7615_mac_scs_check(phy); 2135 } 2136 2137 mt7615_mutex_release(phy->dev); 2138 2139 mt76_tx_status_check(mphy->dev, false); 2140 2141 timeout = mt7615_get_macwork_timeout(phy->dev); 2142 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout); 2143 } 2144 2145 void mt7615_tx_token_put(struct mt7615_dev *dev) 2146 { 2147 struct mt76_txwi_cache *txwi; 2148 int id; 2149 2150 spin_lock_bh(&dev->mt76.token_lock); 2151 idr_for_each_entry(&dev->mt76.token, txwi, id) 2152 mt7615_txwi_free(dev, txwi); 2153 spin_unlock_bh(&dev->mt76.token_lock); 2154 idr_destroy(&dev->mt76.token); 2155 } 2156 EXPORT_SYMBOL_GPL(mt7615_tx_token_put); 2157 2158 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) 2159 { 2160 struct mt7615_dev *dev = phy->dev; 2161 2162 if (phy->rdd_state & BIT(0)) 2163 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0); 2164 if (phy->rdd_state & BIT(1)) 2165 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0); 2166 } 2167 2168 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) 2169 { 2170 int err; 2171 2172 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0); 2173 if (err < 0) 2174 return err; 2175 2176 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, 2177 MT_RX_SEL0, 1); 2178 } 2179 2180 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) 2181 { 2182 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2183 struct mt7615_dev *dev = phy->dev; 2184 bool ext_phy = phy != &dev->phy; 2185 int err; 2186 2187 /* start CAC */ 2188 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0); 2189 if (err < 0) 2190 return err; 2191 2192 err = mt7615_dfs_start_rdd(dev, ext_phy); 2193 if (err < 0) 2194 return err; 2195 2196 phy->rdd_state |= BIT(ext_phy); 2197 2198 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2199 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2200 err = mt7615_dfs_start_rdd(dev, 1); 2201 if (err < 0) 2202 return err; 2203 2204 phy->rdd_state |= BIT(1); 2205 } 2206 2207 return 0; 2208 } 2209 2210 static int 2211 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) 2212 { 2213 const struct mt7615_dfs_radar_spec *radar_specs; 2214 struct mt7615_dev *dev = phy->dev; 2215 int err, i, lpn = 500; 2216 2217 switch (dev->mt76.region) { 2218 case NL80211_DFS_FCC: 2219 radar_specs = &fcc_radar_specs; 2220 lpn = 8; 2221 break; 2222 case NL80211_DFS_ETSI: 2223 radar_specs = &etsi_radar_specs; 2224 break; 2225 case NL80211_DFS_JP: 2226 radar_specs = &jp_radar_specs; 2227 break; 2228 default: 2229 return -EINVAL; 2230 } 2231 2232 /* avoid FCC radar detection in non-FCC region */ 2233 err = mt7615_mcu_set_fcc5_lpn(dev, lpn); 2234 if (err < 0) 2235 return err; 2236 2237 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2238 err = mt7615_mcu_set_radar_th(dev, i, 2239 &radar_specs->radar_pattern[i]); 2240 if (err < 0) 2241 return err; 2242 } 2243 2244 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2245 } 2246 2247 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) 2248 { 2249 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2250 struct mt7615_dev *dev = phy->dev; 2251 bool ext_phy = phy != &dev->phy; 2252 int err; 2253 2254 if (is_mt7663(&dev->mt76)) 2255 return 0; 2256 2257 if (dev->mt76.region == NL80211_DFS_UNSET) { 2258 phy->dfs_state = -1; 2259 if (phy->rdd_state) 2260 goto stop; 2261 2262 return 0; 2263 } 2264 2265 if (test_bit(MT76_SCANNING, &phy->mt76->state)) 2266 return 0; 2267 2268 if (phy->dfs_state == chandef->chan->dfs_state) 2269 return 0; 2270 2271 err = mt7615_dfs_init_radar_specs(phy); 2272 if (err < 0) { 2273 phy->dfs_state = -1; 2274 goto stop; 2275 } 2276 2277 phy->dfs_state = chandef->chan->dfs_state; 2278 2279 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) { 2280 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE) 2281 return mt7615_dfs_start_radar_detector(phy); 2282 2283 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy, 2284 MT_RX_SEL0, 0); 2285 } 2286 2287 stop: 2288 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0); 2289 if (err < 0) 2290 return err; 2291 2292 mt7615_dfs_stop_radar_detector(phy); 2293 return 0; 2294 } 2295 2296 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, 2297 struct ieee80211_vif *vif, 2298 bool enable) 2299 { 2300 struct mt7615_dev *dev = phy->dev; 2301 bool ext_phy = phy != &dev->phy; 2302 int err; 2303 2304 if (!mt7615_firmware_offload(dev)) 2305 return -EOPNOTSUPP; 2306 2307 switch (vif->type) { 2308 case NL80211_IFTYPE_MONITOR: 2309 return 0; 2310 case NL80211_IFTYPE_MESH_POINT: 2311 case NL80211_IFTYPE_ADHOC: 2312 case NL80211_IFTYPE_AP: 2313 if (enable) 2314 phy->n_beacon_vif++; 2315 else 2316 phy->n_beacon_vif--; 2317 fallthrough; 2318 default: 2319 break; 2320 } 2321 2322 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); 2323 if (err) 2324 return err; 2325 2326 if (phy->n_beacon_vif) { 2327 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; 2328 mt76_clear(dev, MT_WF_RFCR(ext_phy), 2329 MT_WF_RFCR_DROP_OTHER_BEACON); 2330 } else { 2331 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; 2332 mt76_set(dev, MT_WF_RFCR(ext_phy), 2333 MT_WF_RFCR_DROP_OTHER_BEACON); 2334 } 2335 2336 return 0; 2337 } 2338 2339 void mt7615_coredump_work(struct work_struct *work) 2340 { 2341 struct mt7615_dev *dev; 2342 char *dump, *data; 2343 2344 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2345 coredump.work.work); 2346 2347 if (time_is_after_jiffies(dev->coredump.last_activity + 2348 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 2349 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 2350 MT76_CONNAC_COREDUMP_TIMEOUT); 2351 return; 2352 } 2353 2354 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 2355 data = dump; 2356 2357 while (true) { 2358 struct sk_buff *skb; 2359 2360 spin_lock_bh(&dev->mt76.lock); 2361 skb = __skb_dequeue(&dev->coredump.msg_list); 2362 spin_unlock_bh(&dev->mt76.lock); 2363 2364 if (!skb) 2365 break; 2366 2367 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 2368 if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 2369 dev_kfree_skb(skb); 2370 continue; 2371 } 2372 2373 memcpy(data, skb->data, skb->len); 2374 data += skb->len; 2375 2376 dev_kfree_skb(skb); 2377 } 2378 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 2379 GFP_KERNEL); 2380 } 2381