1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Felix Fietkau <nbd@nbd.name> 7 * Lorenzo Bianconi <lorenzo@kernel.org> 8 */ 9 10 #include <linux/devcoredump.h> 11 #include <linux/etherdevice.h> 12 #include <linux/timekeeping.h> 13 #include "mt7615.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 #include "mt7615_trace.h" 17 #include "mac.h" 18 #include "mcu.h" 19 20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2) 21 22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = { 23 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 24 .radar_pattern = { 25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 }, 26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 }, 27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 }, 28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 }, 29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 }, 30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 }, 31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 }, 32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 }, 33 }, 34 }; 35 36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = { 37 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 38 .radar_pattern = { 39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 }, 40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 }, 44 }, 45 }; 46 47 static const struct mt7615_dfs_radar_spec jp_radar_specs = { 48 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 49 .radar_pattern = { 50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 }, 51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 }, 52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 }, 53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 }, 54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 }, 55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 }, 56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 }, 57 }, 58 }; 59 60 static enum mt76_cipher_type 61 mt7615_mac_get_cipher(int cipher) 62 { 63 switch (cipher) { 64 case WLAN_CIPHER_SUITE_WEP40: 65 return MT_CIPHER_WEP40; 66 case WLAN_CIPHER_SUITE_WEP104: 67 return MT_CIPHER_WEP104; 68 case WLAN_CIPHER_SUITE_TKIP: 69 return MT_CIPHER_TKIP; 70 case WLAN_CIPHER_SUITE_AES_CMAC: 71 return MT_CIPHER_BIP_CMAC_128; 72 case WLAN_CIPHER_SUITE_CCMP: 73 return MT_CIPHER_AES_CCMP; 74 case WLAN_CIPHER_SUITE_CCMP_256: 75 return MT_CIPHER_CCMP_256; 76 case WLAN_CIPHER_SUITE_GCMP: 77 return MT_CIPHER_GCMP; 78 case WLAN_CIPHER_SUITE_GCMP_256: 79 return MT_CIPHER_GCMP_256; 80 case WLAN_CIPHER_SUITE_SMS4: 81 return MT_CIPHER_WAPI; 82 default: 83 return MT_CIPHER_NONE; 84 } 85 } 86 87 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev, 88 u8 idx, bool unicast) 89 { 90 struct mt7615_sta *sta; 91 struct mt76_wcid *wcid; 92 93 if (idx >= MT7615_WTBL_SIZE) 94 return NULL; 95 96 wcid = rcu_dereference(dev->mt76.wcid[idx]); 97 if (unicast || !wcid) 98 return wcid; 99 100 if (!wcid->sta) 101 return NULL; 102 103 sta = container_of(wcid, struct mt7615_sta, wcid); 104 if (!sta->vif) 105 return NULL; 106 107 return &sta->vif->sta.wcid; 108 } 109 110 void mt7615_mac_reset_counters(struct mt7615_dev *dev) 111 { 112 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 113 int i; 114 115 for (i = 0; i < 4; i++) { 116 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); 117 mt76_rr(dev, MT_TX_AGG_CNT(1, i)); 118 } 119 120 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); 121 dev->mt76.phy.survey_time = ktime_get_boottime(); 122 if (mphy_ext) 123 mphy_ext->survey_time = ktime_get_boottime(); 124 125 /* reset airtime counters */ 126 mt76_rr(dev, MT_MIB_SDR9(0)); 127 mt76_rr(dev, MT_MIB_SDR9(1)); 128 129 mt76_rr(dev, MT_MIB_SDR36(0)); 130 mt76_rr(dev, MT_MIB_SDR36(1)); 131 132 mt76_rr(dev, MT_MIB_SDR37(0)); 133 mt76_rr(dev, MT_MIB_SDR37(1)); 134 135 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 136 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 137 } 138 139 void mt7615_mac_set_timing(struct mt7615_phy *phy) 140 { 141 s16 coverage_class = phy->coverage_class; 142 struct mt7615_dev *dev = phy->dev; 143 bool ext_phy = phy != &dev->phy; 144 u32 val, reg_offset; 145 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 146 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 147 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 149 int sifs, offset; 150 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ; 151 152 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 153 return; 154 155 if (is_5ghz) 156 sifs = 16; 157 else 158 sifs = 10; 159 160 if (ext_phy) { 161 coverage_class = max_t(s16, dev->phy.coverage_class, 162 coverage_class); 163 mt76_set(dev, MT_ARB_SCR, 164 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 165 } else { 166 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev); 167 168 if (phy_ext) 169 coverage_class = max_t(s16, phy_ext->coverage_class, 170 coverage_class); 171 mt76_set(dev, MT_ARB_SCR, 172 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 173 } 174 udelay(1); 175 176 offset = 3 * coverage_class; 177 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 178 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 179 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset); 180 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset); 181 182 mt76_wr(dev, MT_TMAC_ICR(ext_phy), 183 FIELD_PREP(MT_IFS_EIFS, 360) | 184 FIELD_PREP(MT_IFS_RIFS, 2) | 185 FIELD_PREP(MT_IFS_SIFS, sifs) | 186 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 187 188 if (phy->slottime < 20 || is_5ghz) 189 val = MT7615_CFEND_RATE_DEFAULT; 190 else 191 val = MT7615_CFEND_RATE_11B; 192 193 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val); 194 if (ext_phy) 195 mt76_clear(dev, MT_ARB_SCR, 196 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE); 197 else 198 mt76_clear(dev, MT_ARB_SCR, 199 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE); 200 201 } 202 203 static void 204 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy, 205 struct mt76_rx_status *status, u8 chfreq) 206 { 207 if (!test_bit(MT76_HW_SCANNING, &mphy->state) && 208 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) && 209 !test_bit(MT76_STATE_ROC, &mphy->state)) { 210 status->freq = mphy->chandef.chan->center_freq; 211 status->band = mphy->chandef.chan->band; 212 return; 213 } 214 215 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 216 status->freq = ieee80211_channel_to_frequency(chfreq, status->band); 217 } 218 219 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv) 220 { 221 #ifdef CONFIG_NL80211_TESTMODE 222 u32 rxv1 = le32_to_cpu(rxv[0]); 223 u32 rxv3 = le32_to_cpu(rxv[2]); 224 u32 rxv4 = le32_to_cpu(rxv[3]); 225 u32 rxv5 = le32_to_cpu(rxv[4]); 226 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1); 227 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1); 228 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5); 229 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000; 230 231 if (!mode) { 232 /* CCK */ 233 foe &= ~BIT(11); 234 foe *= 1000; 235 foe >>= 11; 236 } else { 237 if (foe > 2048) 238 foe -= 4096; 239 240 foe = (foe * foe_const) >> 15; 241 } 242 243 phy->test.last_freq_offset = foe; 244 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4); 245 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4); 246 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4); 247 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4); 248 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3); 249 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3); 250 #endif 251 } 252 253 /* The HW does not translate the mac header to 802.3 for mesh point */ 254 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap) 255 { 256 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 257 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap); 258 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid; 259 __le32 *rxd = (__le32 *)skb->data; 260 struct ieee80211_sta *sta; 261 struct ieee80211_vif *vif; 262 struct ieee80211_hdr hdr; 263 u16 frame_control; 264 265 if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) != 266 MT_RXD1_NORMAL_U2M) 267 return -EINVAL; 268 269 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4)) 270 return -EINVAL; 271 272 if (!msta || !msta->vif) 273 return -EINVAL; 274 275 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 276 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 277 278 /* store the info from RXD and ethhdr to avoid being overridden */ 279 frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL); 280 hdr.frame_control = cpu_to_le16(frame_control); 281 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL)); 282 hdr.duration_id = 0; 283 284 ether_addr_copy(hdr.addr1, vif->addr); 285 ether_addr_copy(hdr.addr2, sta->addr); 286 switch (frame_control & (IEEE80211_FCTL_TODS | 287 IEEE80211_FCTL_FROMDS)) { 288 case 0: 289 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid); 290 break; 291 case IEEE80211_FCTL_FROMDS: 292 ether_addr_copy(hdr.addr3, eth_hdr->h_source); 293 break; 294 case IEEE80211_FCTL_TODS: 295 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 296 break; 297 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS: 298 ether_addr_copy(hdr.addr3, eth_hdr->h_dest); 299 ether_addr_copy(hdr.addr4, eth_hdr->h_source); 300 break; 301 default: 302 break; 303 } 304 305 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2); 306 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) || 307 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX)) 308 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header); 309 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN) 310 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header); 311 else 312 skb_pull(skb, 2); 313 314 if (ieee80211_has_order(hdr.frame_control)) 315 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7], 316 IEEE80211_HT_CTL_LEN); 317 318 if (ieee80211_is_data_qos(hdr.frame_control)) { 319 __le16 qos_ctrl; 320 321 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL)); 322 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl, 323 IEEE80211_QOS_CTL_LEN); 324 } 325 326 if (ieee80211_has_a4(hdr.frame_control)) 327 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr)); 328 else 329 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6); 330 331 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU); 332 return 0; 333 } 334 335 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb) 336 { 337 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 338 struct mt76_phy *mphy = &dev->mt76.phy; 339 struct mt7615_phy *phy = &dev->phy; 340 struct ieee80211_supported_band *sband; 341 struct ieee80211_hdr *hdr; 342 struct mt7615_phy *phy2; 343 __le32 *rxd = (__le32 *)skb->data; 344 u32 rxd0 = le32_to_cpu(rxd[0]); 345 u32 rxd1 = le32_to_cpu(rxd[1]); 346 u32 rxd2 = le32_to_cpu(rxd[2]); 347 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 348 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false; 349 u16 hdr_gap; 350 int phy_idx; 351 int i, idx; 352 u8 chfreq, amsdu_info, qos_ctl = 0; 353 u16 seq_ctrl = 0; 354 __le16 fc = 0; 355 356 memset(status, 0, sizeof(*status)); 357 358 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 359 360 phy2 = dev->mt76.phys[MT_BAND1] ? dev->mt76.phys[MT_BAND1]->priv : NULL; 361 if (!phy2) 362 phy_idx = 0; 363 else if (phy2->chfreq == phy->chfreq) 364 phy_idx = -1; 365 else if (phy->chfreq == chfreq) 366 phy_idx = 0; 367 else if (phy2->chfreq == chfreq) 368 phy_idx = 1; 369 else 370 phy_idx = -1; 371 372 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 373 return -EINVAL; 374 375 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS; 376 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM)) 377 return -EINVAL; 378 379 /* ICV error or CCMP/BIP/WPI MIC error */ 380 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 381 status->flag |= RX_FLAG_ONLY_MONITOR; 382 383 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M; 384 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 385 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast); 386 387 if (status->wcid) { 388 struct mt7615_sta *msta; 389 390 msta = container_of(status->wcid, struct mt7615_sta, wcid); 391 spin_lock_bh(&dev->sta_poll_lock); 392 if (list_empty(&msta->poll_list)) 393 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 394 spin_unlock_bh(&dev->sta_poll_lock); 395 } 396 397 if ((rxd0 & csum_mask) == csum_mask) 398 skb->ip_summed = CHECKSUM_UNNECESSARY; 399 400 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 401 status->flag |= RX_FLAG_FAILED_FCS_CRC; 402 403 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 404 status->flag |= RX_FLAG_MMIC_ERROR; 405 406 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 407 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 408 status->flag |= RX_FLAG_DECRYPTED; 409 status->flag |= RX_FLAG_IV_STRIPPED; 410 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 411 } 412 413 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 414 415 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 416 return -EINVAL; 417 418 rxd += 4; 419 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 420 u32 v0 = le32_to_cpu(rxd[0]); 421 u32 v2 = le32_to_cpu(rxd[2]); 422 423 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0)); 424 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2); 425 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2); 426 427 rxd += 4; 428 if ((u8 *)rxd - skb->data >= skb->len) 429 return -EINVAL; 430 } 431 432 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 433 u8 *data = (u8 *)rxd; 434 435 if (status->flag & RX_FLAG_DECRYPTED) { 436 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 437 case MT_CIPHER_AES_CCMP: 438 case MT_CIPHER_CCMP_CCX: 439 case MT_CIPHER_CCMP_256: 440 insert_ccmp_hdr = 441 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 442 fallthrough; 443 case MT_CIPHER_TKIP: 444 case MT_CIPHER_TKIP_NO_MIC: 445 case MT_CIPHER_GCMP: 446 case MT_CIPHER_GCMP_256: 447 status->iv[0] = data[5]; 448 status->iv[1] = data[4]; 449 status->iv[2] = data[3]; 450 status->iv[3] = data[2]; 451 status->iv[4] = data[1]; 452 status->iv[5] = data[0]; 453 break; 454 default: 455 break; 456 } 457 } 458 rxd += 4; 459 if ((u8 *)rxd - skb->data >= skb->len) 460 return -EINVAL; 461 } 462 463 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 464 status->timestamp = le32_to_cpu(rxd[0]); 465 status->flag |= RX_FLAG_MACTIME_START; 466 467 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 468 MT_RXD2_NORMAL_NON_AMPDU))) { 469 status->flag |= RX_FLAG_AMPDU_DETAILS; 470 471 /* all subframes of an A-MPDU have the same timestamp */ 472 if (phy->rx_ampdu_ts != status->timestamp) { 473 if (!++phy->ampdu_ref) 474 phy->ampdu_ref++; 475 } 476 phy->rx_ampdu_ts = status->timestamp; 477 478 status->ampdu_ref = phy->ampdu_ref; 479 } 480 481 rxd += 2; 482 if ((u8 *)rxd - skb->data >= skb->len) 483 return -EINVAL; 484 } 485 486 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 487 u32 rxdg5 = le32_to_cpu(rxd[5]); 488 489 /* 490 * If both PHYs are on the same channel and we don't have a WCID, 491 * we need to figure out which PHY this packet was received on. 492 * On the primary PHY, the noise value for the chains belonging to the 493 * second PHY will be set to the noise value of the last packet from 494 * that PHY. 495 */ 496 if (phy_idx < 0) { 497 int first_chain = ffs(phy2->mt76->chainmask) - 1; 498 499 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0; 500 } 501 } 502 503 if (phy_idx == 1 && phy2) { 504 mphy = dev->mt76.phys[MT_BAND1]; 505 phy = phy2; 506 status->phy_idx = phy_idx; 507 } 508 509 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq) 510 return -EINVAL; 511 512 mt7615_get_status_freq_info(dev, mphy, status, chfreq); 513 if (status->band == NL80211_BAND_5GHZ) 514 sband = &mphy->sband_5g.sband; 515 else 516 sband = &mphy->sband_2g.sband; 517 518 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 519 return -EINVAL; 520 521 if (!sband->channels) 522 return -EINVAL; 523 524 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 525 u32 rxdg0 = le32_to_cpu(rxd[0]); 526 u32 rxdg1 = le32_to_cpu(rxd[1]); 527 u32 rxdg3 = le32_to_cpu(rxd[3]); 528 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 529 bool cck = false; 530 531 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 532 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 533 case MT_PHY_TYPE_CCK: 534 cck = true; 535 fallthrough; 536 case MT_PHY_TYPE_OFDM: 537 i = mt76_get_rate(&dev->mt76, sband, i, cck); 538 break; 539 case MT_PHY_TYPE_HT_GF: 540 case MT_PHY_TYPE_HT: 541 status->encoding = RX_ENC_HT; 542 if (i > 31) 543 return -EINVAL; 544 break; 545 case MT_PHY_TYPE_VHT: 546 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1; 547 status->encoding = RX_ENC_VHT; 548 break; 549 default: 550 return -EINVAL; 551 } 552 status->rate_idx = i; 553 554 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) { 555 case MT_PHY_BW_20: 556 break; 557 case MT_PHY_BW_40: 558 status->bw = RATE_INFO_BW_40; 559 break; 560 case MT_PHY_BW_80: 561 status->bw = RATE_INFO_BW_80; 562 break; 563 case MT_PHY_BW_160: 564 status->bw = RATE_INFO_BW_160; 565 break; 566 default: 567 return -EINVAL; 568 } 569 570 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 571 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 572 if (rxdg0 & MT_RXV1_HT_AD_CODE) 573 status->enc_flags |= RX_ENC_FLAG_LDPC; 574 575 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; 576 577 status->chains = mphy->antenna_mask; 578 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3); 579 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3); 580 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3); 581 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3); 582 583 mt7615_mac_fill_tm_rx(mphy->priv, rxd); 584 585 rxd += 6; 586 if ((u8 *)rxd - skb->data >= skb->len) 587 return -EINVAL; 588 } 589 590 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1); 591 status->amsdu = !!amsdu_info; 592 if (status->amsdu) { 593 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME; 594 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME; 595 } 596 597 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 598 if (hdr_trans && ieee80211_has_morefrags(fc)) { 599 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap)) 600 return -EINVAL; 601 hdr_trans = false; 602 } else { 603 int pad_start = 0; 604 605 skb_pull(skb, hdr_gap); 606 if (!hdr_trans && status->amsdu) { 607 pad_start = ieee80211_get_hdrlen_from_skb(skb); 608 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 609 /* 610 * When header translation failure is indicated, 611 * the hardware will insert an extra 2-byte field 612 * containing the data length after the protocol 613 * type field. 614 */ 615 pad_start = 12; 616 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 617 pad_start += 4; 618 619 if (get_unaligned_be16(skb->data + pad_start) != 620 skb->len - pad_start - 2) 621 pad_start = 0; 622 } 623 624 if (pad_start) { 625 memmove(skb->data + 2, skb->data, pad_start); 626 skb_pull(skb, 2); 627 } 628 } 629 630 if (insert_ccmp_hdr && !hdr_trans) { 631 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 632 633 mt76_insert_ccmp_hdr(skb, key_id); 634 } 635 636 if (!hdr_trans) { 637 hdr = (struct ieee80211_hdr *)skb->data; 638 fc = hdr->frame_control; 639 if (ieee80211_is_data_qos(fc)) { 640 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 641 qos_ctl = *ieee80211_get_qos_ctl(hdr); 642 } 643 } else { 644 status->flag |= RX_FLAG_8023; 645 } 646 647 if (!status->wcid || !ieee80211_is_data_qos(fc)) 648 return 0; 649 650 status->aggr = unicast && 651 !ieee80211_is_qos_nullfunc(fc); 652 status->qos_ctl = qos_ctl; 653 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 654 655 return 0; 656 } 657 658 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 659 { 660 } 661 EXPORT_SYMBOL_GPL(mt7615_sta_ps); 662 663 static u16 664 mt7615_mac_tx_rate_val(struct mt7615_dev *dev, 665 struct mt76_phy *mphy, 666 const struct ieee80211_tx_rate *rate, 667 bool stbc, u8 *bw) 668 { 669 u8 phy, nss, rate_idx; 670 u16 rateval = 0; 671 672 *bw = 0; 673 674 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) { 675 rate_idx = ieee80211_rate_get_vht_mcs(rate); 676 nss = ieee80211_rate_get_vht_nss(rate); 677 phy = MT_PHY_TYPE_VHT; 678 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 679 *bw = 1; 680 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 681 *bw = 2; 682 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 683 *bw = 3; 684 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 685 rate_idx = rate->idx; 686 nss = 1 + (rate->idx >> 3); 687 phy = MT_PHY_TYPE_HT; 688 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 689 phy = MT_PHY_TYPE_HT_GF; 690 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 691 *bw = 1; 692 } else { 693 const struct ieee80211_rate *r; 694 int band = mphy->chandef.chan->band; 695 u16 val; 696 697 nss = 1; 698 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx]; 699 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 700 val = r->hw_value_short; 701 else 702 val = r->hw_value; 703 704 phy = val >> 8; 705 rate_idx = val & 0xff; 706 } 707 708 if (stbc && nss == 1) { 709 nss++; 710 rateval |= MT_TX_RATE_STBC; 711 } 712 713 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 714 FIELD_PREP(MT_TX_RATE_MODE, phy) | 715 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); 716 717 return rateval; 718 } 719 720 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi, 721 struct sk_buff *skb, struct mt76_wcid *wcid, 722 struct ieee80211_sta *sta, int pid, 723 struct ieee80211_key_conf *key, 724 enum mt76_txq_id qid, bool beacon) 725 { 726 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 727 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0; 728 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 729 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 730 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 731 bool multicast = is_multicast_ether_addr(hdr->addr1); 732 struct ieee80211_vif *vif = info->control.vif; 733 bool is_mmio = mt76_is_mmio(&dev->mt76); 734 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE; 735 struct mt76_phy *mphy = &dev->mphy; 736 __le16 fc = hdr->frame_control; 737 int tx_count = 8; 738 u16 seqno = 0; 739 740 if (vif) { 741 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; 742 743 omac_idx = mvif->omac_idx; 744 wmm_idx = mvif->wmm_idx; 745 } 746 747 if (sta) { 748 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 749 750 tx_count = msta->rate_count; 751 } 752 753 if (phy_idx && dev->mt76.phys[MT_BAND1]) 754 mphy = dev->mt76.phys[MT_BAND1]; 755 756 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2; 757 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4; 758 759 if (beacon) { 760 p_fmt = MT_TX_TYPE_FW; 761 q_idx = phy_idx ? MT_LMAC_BCN1 : MT_LMAC_BCN0; 762 } else if (qid >= MT_TXQ_PSD) { 763 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 764 q_idx = phy_idx ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0; 765 } else { 766 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF; 767 q_idx = wmm_idx * MT7615_MAX_WMM_SETS + 768 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb)); 769 } 770 771 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) | 772 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | 773 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 774 txwi[0] = cpu_to_le32(val); 775 776 val = MT_TXD1_LONG_FORMAT | 777 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | 778 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 779 FIELD_PREP(MT_TXD1_HDR_INFO, 780 ieee80211_get_hdrlen_from_skb(skb) / 2) | 781 FIELD_PREP(MT_TXD1_TID, 782 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 783 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) | 784 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx); 785 txwi[1] = cpu_to_le32(val); 786 787 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) | 788 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) | 789 FIELD_PREP(MT_TXD2_MULTICAST, multicast); 790 if (key) { 791 if (multicast && ieee80211_is_robust_mgmt_frame(skb) && 792 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) { 793 val |= MT_TXD2_BIP; 794 txwi[3] = 0; 795 } else { 796 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME); 797 } 798 } else { 799 txwi[3] = 0; 800 } 801 txwi[2] = cpu_to_le32(val); 802 803 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 804 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 805 806 txwi[4] = 0; 807 txwi[6] = 0; 808 809 if (rate->idx >= 0 && rate->count && 810 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 811 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 812 u8 bw; 813 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc, 814 &bw); 815 816 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 817 818 val = MT_TXD6_FIXED_BW | 819 FIELD_PREP(MT_TXD6_BW, bw) | 820 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 821 txwi[6] |= cpu_to_le32(val); 822 823 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 824 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 825 826 if (info->flags & IEEE80211_TX_CTL_LDPC) 827 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC); 828 829 if (!(rate->flags & (IEEE80211_TX_RC_MCS | 830 IEEE80211_TX_RC_VHT_MCS))) 831 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 832 833 tx_count = rate->count; 834 } 835 836 if (!ieee80211_is_beacon(fc)) { 837 struct ieee80211_hw *hw = mt76_hw(dev); 838 839 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid); 840 if (!ieee80211_hw_check(hw, SUPPORTS_PS)) 841 val |= MT_TXD5_SW_POWER_MGMT; 842 txwi[5] = cpu_to_le32(val); 843 } else { 844 txwi[5] = 0; 845 /* use maximum tx count for beacons */ 846 tx_count = 0x1f; 847 } 848 849 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count); 850 if (info->flags & IEEE80211_TX_CTL_INJECTED) { 851 seqno = le16_to_cpu(hdr->seq_ctrl); 852 853 if (ieee80211_is_back_req(hdr->frame_control)) { 854 struct ieee80211_bar *bar; 855 856 bar = (struct ieee80211_bar *)skb->data; 857 seqno = le16_to_cpu(bar->start_seq_num); 858 } 859 860 val |= MT_TXD3_SN_VALID | 861 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno)); 862 } 863 864 txwi[3] |= cpu_to_le32(val); 865 866 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 867 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK); 868 869 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) | 870 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) | 871 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18); 872 txwi[7] = cpu_to_le32(val); 873 if (!is_mmio) { 874 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) | 875 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype); 876 txwi[8] = cpu_to_le32(val); 877 } 878 879 return 0; 880 } 881 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi); 882 883 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask) 884 { 885 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 886 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 887 888 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 889 0, 5000); 890 } 891 892 void mt7615_mac_sta_poll(struct mt7615_dev *dev) 893 { 894 static const u8 ac_to_tid[4] = { 895 [IEEE80211_AC_BE] = 0, 896 [IEEE80211_AC_BK] = 1, 897 [IEEE80211_AC_VI] = 4, 898 [IEEE80211_AC_VO] = 6 899 }; 900 static const u8 hw_queue_map[] = { 901 [IEEE80211_AC_BK] = 0, 902 [IEEE80211_AC_BE] = 1, 903 [IEEE80211_AC_VI] = 2, 904 [IEEE80211_AC_VO] = 3, 905 }; 906 struct ieee80211_sta *sta; 907 struct mt7615_sta *msta; 908 u32 addr, tx_time[4], rx_time[4]; 909 struct list_head sta_poll_list; 910 int i; 911 912 INIT_LIST_HEAD(&sta_poll_list); 913 spin_lock_bh(&dev->sta_poll_lock); 914 list_splice_init(&dev->sta_poll_list, &sta_poll_list); 915 spin_unlock_bh(&dev->sta_poll_lock); 916 917 while (!list_empty(&sta_poll_list)) { 918 bool clear = false; 919 920 msta = list_first_entry(&sta_poll_list, struct mt7615_sta, 921 poll_list); 922 list_del_init(&msta->poll_list); 923 924 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4; 925 926 for (i = 0; i < 4; i++, addr += 8) { 927 u32 tx_last = msta->airtime_ac[i]; 928 u32 rx_last = msta->airtime_ac[i + 4]; 929 930 msta->airtime_ac[i] = mt76_rr(dev, addr); 931 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 932 tx_time[i] = msta->airtime_ac[i] - tx_last; 933 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 934 935 if ((tx_last | rx_last) & BIT(30)) 936 clear = true; 937 } 938 939 if (clear) { 940 mt7615_mac_wtbl_update(dev, msta->wcid.idx, 941 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 942 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 943 } 944 945 if (!msta->wcid.sta) 946 continue; 947 948 sta = container_of((void *)msta, struct ieee80211_sta, 949 drv_priv); 950 for (i = 0; i < 4; i++) { 951 u32 tx_cur = tx_time[i]; 952 u32 rx_cur = rx_time[hw_queue_map[i]]; 953 u8 tid = ac_to_tid[i]; 954 955 if (!tx_cur && !rx_cur) 956 continue; 957 958 ieee80211_sta_register_airtime(sta, tid, tx_cur, 959 rx_cur); 960 } 961 } 962 } 963 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll); 964 965 static void 966 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta, 967 struct ieee80211_tx_rate *probe_rate, 968 struct ieee80211_tx_rate *rates, 969 struct mt7615_rate_desc *rd) 970 { 971 struct mt7615_dev *dev = phy->dev; 972 struct mt76_phy *mphy = phy->mt76; 973 struct ieee80211_tx_rate *ref; 974 bool rateset, stbc = false; 975 int n_rates = sta->n_rates; 976 u8 bw, bw_prev; 977 int i, j; 978 979 for (i = n_rates; i < 4; i++) 980 rates[i] = rates[n_rates - 1]; 981 982 rateset = !(sta->rate_set_tsf & BIT(0)); 983 memcpy(sta->rateset[rateset].rates, rates, 984 sizeof(sta->rateset[rateset].rates)); 985 if (probe_rate) { 986 sta->rateset[rateset].probe_rate = *probe_rate; 987 ref = &sta->rateset[rateset].probe_rate; 988 } else { 989 sta->rateset[rateset].probe_rate.idx = -1; 990 ref = &sta->rateset[rateset].rates[0]; 991 } 992 993 rates = sta->rateset[rateset].rates; 994 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 995 /* 996 * We don't support switching between short and long GI 997 * within the rate set. For accurate tx status reporting, we 998 * need to make sure that flags match. 999 * For improved performance, avoid duplicate entries by 1000 * decrementing the MCS index if necessary 1001 */ 1002 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 1003 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 1004 1005 for (j = 0; j < i; j++) { 1006 if (rates[i].idx != rates[j].idx) 1007 continue; 1008 if ((rates[i].flags ^ rates[j].flags) & 1009 (IEEE80211_TX_RC_40_MHZ_WIDTH | 1010 IEEE80211_TX_RC_80_MHZ_WIDTH | 1011 IEEE80211_TX_RC_160_MHZ_WIDTH)) 1012 continue; 1013 1014 if (!rates[i].idx) 1015 continue; 1016 1017 rates[i].idx--; 1018 } 1019 } 1020 1021 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw); 1022 bw_prev = bw; 1023 1024 if (probe_rate) { 1025 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate, 1026 stbc, &bw); 1027 if (bw) 1028 rd->bw_idx = 1; 1029 else 1030 bw_prev = 0; 1031 } else { 1032 rd->probe_val = rd->val[0]; 1033 } 1034 1035 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw); 1036 if (bw_prev) { 1037 rd->bw_idx = 3; 1038 bw_prev = bw; 1039 } 1040 1041 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw); 1042 if (bw_prev) { 1043 rd->bw_idx = 5; 1044 bw_prev = bw; 1045 } 1046 1047 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw); 1048 if (bw_prev) 1049 rd->bw_idx = 7; 1050 1051 rd->rateset = rateset; 1052 rd->bw = bw; 1053 } 1054 1055 static int 1056 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta, 1057 struct ieee80211_tx_rate *probe_rate, 1058 struct ieee80211_tx_rate *rates) 1059 { 1060 struct mt7615_dev *dev = phy->dev; 1061 struct mt7615_wtbl_rate_desc *wrd; 1062 1063 if (work_pending(&dev->rate_work)) 1064 return -EBUSY; 1065 1066 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC); 1067 if (!wrd) 1068 return -ENOMEM; 1069 1070 wrd->sta = sta; 1071 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, 1072 &wrd->rate); 1073 list_add_tail(&wrd->node, &dev->wrd_head); 1074 queue_work(dev->mt76.wq, &dev->rate_work); 1075 1076 return 0; 1077 } 1078 1079 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid) 1080 { 1081 u32 addr, val, val2; 1082 u8 offset; 1083 1084 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4; 1085 1086 offset = tid * 12; 1087 addr += 4 * (offset / 32); 1088 offset %= 32; 1089 1090 val = mt76_rr(dev, addr); 1091 val >>= (tid % 32); 1092 1093 if (offset > 20) { 1094 addr += 4; 1095 val2 = mt76_rr(dev, addr); 1096 val |= val2 << (32 - offset); 1097 } 1098 1099 return val & GENMASK(11, 0); 1100 } 1101 1102 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta, 1103 struct ieee80211_tx_rate *probe_rate, 1104 struct ieee80211_tx_rate *rates) 1105 { 1106 int wcid = sta->wcid.idx, n_rates = sta->n_rates; 1107 struct mt7615_dev *dev = phy->dev; 1108 struct mt7615_rate_desc rd; 1109 u32 w5, w27, addr; 1110 u16 idx = sta->vif->mt76.omac_idx; 1111 1112 if (!mt76_is_mmio(&dev->mt76)) { 1113 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates); 1114 return; 1115 } 1116 1117 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1118 return; 1119 1120 memset(&rd, 0, sizeof(struct mt7615_rate_desc)); 1121 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd); 1122 1123 addr = mt7615_mac_wtbl_addr(dev, wcid); 1124 w27 = mt76_rr(dev, addr + 27 * 4); 1125 w27 &= ~MT_WTBL_W27_CC_BW_SEL; 1126 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw); 1127 1128 w5 = mt76_rr(dev, addr + 5 * 4); 1129 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | 1130 MT_WTBL_W5_MPDU_OK_COUNT | 1131 MT_WTBL_W5_MPDU_FAIL_COUNT | 1132 MT_WTBL_W5_RATE_IDX); 1133 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) | 1134 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, 1135 rd.bw_idx ? rd.bw_idx - 1 : 7); 1136 1137 mt76_wr(dev, MT_WTBL_RIUCR0, w5); 1138 1139 mt76_wr(dev, MT_WTBL_RIUCR1, 1140 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) | 1141 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) | 1142 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1])); 1143 1144 mt76_wr(dev, MT_WTBL_RIUCR2, 1145 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) | 1146 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) | 1147 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) | 1148 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2])); 1149 1150 mt76_wr(dev, MT_WTBL_RIUCR3, 1151 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) | 1152 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) | 1153 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3])); 1154 1155 mt76_wr(dev, MT_WTBL_UPDATE, 1156 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 1157 MT_WTBL_UPDATE_RATE_UPDATE | 1158 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 1159 1160 mt76_wr(dev, addr + 27 * 4, w27); 1161 1162 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx; 1163 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx); 1164 1165 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */ 1166 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0); 1167 sta->rate_set_tsf |= rd.rateset; 1168 1169 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 1170 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 1171 1172 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates; 1173 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 1174 sta->rate_probe = !!probe_rate; 1175 } 1176 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates); 1177 1178 static int 1179 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1180 struct ieee80211_key_conf *key, 1181 enum mt76_cipher_type cipher, u16 cipher_mask, 1182 enum set_key_cmd cmd) 1183 { 1184 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4; 1185 u8 data[32] = {}; 1186 1187 if (key->keylen > sizeof(data)) 1188 return -EINVAL; 1189 1190 mt76_rr_copy(dev, addr, data, sizeof(data)); 1191 if (cmd == SET_KEY) { 1192 if (cipher == MT_CIPHER_TKIP) { 1193 /* Rx/Tx MIC keys are swapped */ 1194 memcpy(data, key->key, 16); 1195 memcpy(data + 16, key->key + 24, 8); 1196 memcpy(data + 24, key->key + 16, 8); 1197 } else { 1198 if (cipher_mask == BIT(cipher)) 1199 memcpy(data, key->key, key->keylen); 1200 else if (cipher != MT_CIPHER_BIP_CMAC_128) 1201 memcpy(data, key->key, 16); 1202 if (cipher == MT_CIPHER_BIP_CMAC_128) 1203 memcpy(data + 16, key->key, 16); 1204 } 1205 } else { 1206 if (cipher == MT_CIPHER_BIP_CMAC_128) 1207 memset(data + 16, 0, 16); 1208 else if (cipher_mask) 1209 memset(data, 0, 16); 1210 if (!cipher_mask) 1211 memset(data, 0, sizeof(data)); 1212 } 1213 1214 mt76_wr_copy(dev, addr, data, sizeof(data)); 1215 1216 return 0; 1217 } 1218 1219 static int 1220 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1221 enum mt76_cipher_type cipher, u16 cipher_mask, 1222 int keyidx, enum set_key_cmd cmd) 1223 { 1224 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1; 1225 1226 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 1227 return -ETIMEDOUT; 1228 1229 w0 = mt76_rr(dev, addr); 1230 w1 = mt76_rr(dev, addr + 4); 1231 1232 if (cipher_mask) 1233 w0 |= MT_WTBL_W0_RX_KEY_VALID; 1234 else 1235 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX); 1236 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128)) 1237 w0 |= MT_WTBL_W0_RX_IK_VALID; 1238 else 1239 w0 &= ~MT_WTBL_W0_RX_IK_VALID; 1240 1241 if (cmd == SET_KEY && 1242 (cipher != MT_CIPHER_BIP_CMAC_128 || 1243 cipher_mask == BIT(cipher))) { 1244 w0 &= ~MT_WTBL_W0_KEY_IDX; 1245 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx); 1246 } 1247 1248 mt76_wr(dev, MT_WTBL_RICR0, w0); 1249 mt76_wr(dev, MT_WTBL_RICR1, w1); 1250 1251 if (!mt7615_mac_wtbl_update(dev, wcid->idx, 1252 MT_WTBL_UPDATE_RXINFO_UPDATE)) 1253 return -ETIMEDOUT; 1254 1255 return 0; 1256 } 1257 1258 static void 1259 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid, 1260 enum mt76_cipher_type cipher, u16 cipher_mask, 1261 enum set_key_cmd cmd) 1262 { 1263 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx); 1264 1265 if (!cipher_mask) { 1266 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE); 1267 return; 1268 } 1269 1270 if (cmd != SET_KEY) 1271 return; 1272 1273 if (cipher == MT_CIPHER_BIP_CMAC_128 && 1274 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128)) 1275 return; 1276 1277 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE, 1278 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher)); 1279 } 1280 1281 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1282 struct mt76_wcid *wcid, 1283 struct ieee80211_key_conf *key, 1284 enum set_key_cmd cmd) 1285 { 1286 enum mt76_cipher_type cipher; 1287 u16 cipher_mask = wcid->cipher; 1288 int err; 1289 1290 cipher = mt7615_mac_get_cipher(key->cipher); 1291 if (cipher == MT_CIPHER_NONE) 1292 return -EOPNOTSUPP; 1293 1294 if (cmd == SET_KEY) 1295 cipher_mask |= BIT(cipher); 1296 else 1297 cipher_mask &= ~BIT(cipher); 1298 1299 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd); 1300 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask, 1301 cmd); 1302 if (err < 0) 1303 return err; 1304 1305 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask, 1306 key->keyidx, cmd); 1307 if (err < 0) 1308 return err; 1309 1310 wcid->cipher = cipher_mask; 1311 1312 return 0; 1313 } 1314 1315 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev, 1316 struct mt76_wcid *wcid, 1317 struct ieee80211_key_conf *key, 1318 enum set_key_cmd cmd) 1319 { 1320 int err; 1321 1322 spin_lock_bh(&dev->mt76.lock); 1323 err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd); 1324 spin_unlock_bh(&dev->mt76.lock); 1325 1326 return err; 1327 } 1328 1329 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta, 1330 struct ieee80211_tx_info *info, __le32 *txs_data) 1331 { 1332 struct ieee80211_supported_band *sband; 1333 struct mt7615_rate_set *rs; 1334 struct mt76_phy *mphy; 1335 int first_idx = 0, last_idx; 1336 int i, idx, count; 1337 bool fixed_rate, ack_timeout; 1338 bool ampdu, cck = false; 1339 bool rs_idx; 1340 u32 rate_set_tsf; 1341 u32 final_rate, final_rate_flags, final_nss, txs; 1342 1343 txs = le32_to_cpu(txs_data[1]); 1344 ampdu = txs & MT_TXS1_AMPDU; 1345 1346 txs = le32_to_cpu(txs_data[3]); 1347 count = FIELD_GET(MT_TXS3_TX_COUNT, txs); 1348 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs); 1349 1350 txs = le32_to_cpu(txs_data[0]); 1351 fixed_rate = txs & MT_TXS0_FIXED_RATE; 1352 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1353 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1354 1355 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1356 return false; 1357 1358 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1359 return false; 1360 1361 if (!ack_timeout) 1362 info->flags |= IEEE80211_TX_STAT_ACK; 1363 1364 info->status.ampdu_len = 1; 1365 info->status.ampdu_ack_len = !!(info->flags & 1366 IEEE80211_TX_STAT_ACK); 1367 1368 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1369 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1370 1371 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY); 1372 1373 if (fixed_rate) { 1374 info->status.rates[0].count = count; 1375 i = 0; 1376 goto out; 1377 } 1378 1379 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1380 rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) - 1381 rate_set_tsf) < 1000000); 1382 rs_idx ^= rate_set_tsf & BIT(0); 1383 rs = &sta->rateset[rs_idx]; 1384 1385 if (!first_idx && rs->probe_rate.idx >= 0) { 1386 info->status.rates[0] = rs->probe_rate; 1387 1388 spin_lock_bh(&dev->mt76.lock); 1389 if (sta->rate_probe) { 1390 struct mt7615_phy *phy = &dev->phy; 1391 1392 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1393 phy = dev->mt76.phys[MT_BAND1]->priv; 1394 1395 mt7615_mac_set_rates(phy, sta, NULL, sta->rates); 1396 } 1397 spin_unlock_bh(&dev->mt76.lock); 1398 } else { 1399 info->status.rates[0] = rs->rates[first_idx / 2]; 1400 } 1401 info->status.rates[0].count = 0; 1402 1403 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1404 struct ieee80211_tx_rate *cur_rate; 1405 int cur_count; 1406 1407 cur_rate = &rs->rates[idx / 2]; 1408 cur_count = min_t(int, MT7615_RATE_RETRY, count); 1409 count -= cur_count; 1410 1411 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1412 cur_rate->flags != info->status.rates[i].flags)) { 1413 i++; 1414 if (i == ARRAY_SIZE(info->status.rates)) { 1415 i--; 1416 break; 1417 } 1418 1419 info->status.rates[i] = *cur_rate; 1420 info->status.rates[i].count = 0; 1421 } 1422 1423 info->status.rates[i].count += cur_count; 1424 } 1425 1426 out: 1427 final_rate_flags = info->status.rates[i].flags; 1428 1429 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1430 case MT_PHY_TYPE_CCK: 1431 cck = true; 1432 fallthrough; 1433 case MT_PHY_TYPE_OFDM: 1434 mphy = &dev->mphy; 1435 if (sta->wcid.phy_idx && dev->mt76.phys[MT_BAND1]) 1436 mphy = dev->mt76.phys[MT_BAND1]; 1437 1438 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ) 1439 sband = &mphy->sband_5g.sband; 1440 else 1441 sband = &mphy->sband_2g.sband; 1442 final_rate &= MT_TX_RATE_IDX; 1443 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1444 cck); 1445 final_rate_flags = 0; 1446 break; 1447 case MT_PHY_TYPE_HT_GF: 1448 case MT_PHY_TYPE_HT: 1449 final_rate_flags |= IEEE80211_TX_RC_MCS; 1450 final_rate &= MT_TX_RATE_IDX; 1451 if (final_rate > 31) 1452 return false; 1453 break; 1454 case MT_PHY_TYPE_VHT: 1455 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate); 1456 1457 if ((final_rate & MT_TX_RATE_STBC) && final_nss) 1458 final_nss--; 1459 1460 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS; 1461 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4); 1462 break; 1463 default: 1464 return false; 1465 } 1466 1467 info->status.rates[i].idx = final_rate; 1468 info->status.rates[i].flags = final_rate_flags; 1469 1470 return true; 1471 } 1472 1473 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev, 1474 struct mt7615_sta *sta, int pid, 1475 __le32 *txs_data) 1476 { 1477 struct mt76_dev *mdev = &dev->mt76; 1478 struct sk_buff_head list; 1479 struct sk_buff *skb; 1480 1481 if (pid < MT_PACKET_ID_FIRST) 1482 return false; 1483 1484 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1485 1486 mt76_tx_status_lock(mdev, &list); 1487 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1488 if (skb) { 1489 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1490 1491 if (!mt7615_fill_txs(dev, sta, info, txs_data)) { 1492 info->status.rates[0].count = 0; 1493 info->status.rates[0].idx = -1; 1494 } 1495 1496 mt76_tx_status_skb_done(mdev, skb, &list); 1497 } 1498 mt76_tx_status_unlock(mdev, &list); 1499 1500 return !!skb; 1501 } 1502 1503 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data) 1504 { 1505 struct ieee80211_tx_info info = {}; 1506 struct ieee80211_sta *sta = NULL; 1507 struct mt7615_sta *msta = NULL; 1508 struct mt76_wcid *wcid; 1509 struct mt76_phy *mphy = &dev->mt76.phy; 1510 __le32 *txs_data = data; 1511 u8 wcidx; 1512 u8 pid; 1513 1514 pid = le32_get_bits(txs_data[0], MT_TXS0_PID); 1515 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1516 1517 if (pid == MT_PACKET_ID_NO_ACK) 1518 return; 1519 1520 if (wcidx >= MT7615_WTBL_SIZE) 1521 return; 1522 1523 rcu_read_lock(); 1524 1525 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1526 if (!wcid) 1527 goto out; 1528 1529 msta = container_of(wcid, struct mt7615_sta, wcid); 1530 sta = wcid_to_sta(wcid); 1531 1532 spin_lock_bh(&dev->sta_poll_lock); 1533 if (list_empty(&msta->poll_list)) 1534 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1535 spin_unlock_bh(&dev->sta_poll_lock); 1536 1537 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data)) 1538 goto out; 1539 1540 if (wcidx >= MT7615_WTBL_STA || !sta) 1541 goto out; 1542 1543 if (wcid->phy_idx && dev->mt76.phys[MT_BAND1]) 1544 mphy = dev->mt76.phys[MT_BAND1]; 1545 1546 if (mt7615_fill_txs(dev, msta, &info, txs_data)) 1547 ieee80211_tx_status_noskb(mphy->hw, sta, &info); 1548 1549 out: 1550 rcu_read_unlock(); 1551 } 1552 1553 static void 1554 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi) 1555 { 1556 struct mt76_dev *mdev = &dev->mt76; 1557 __le32 *txwi_data; 1558 u32 val; 1559 u8 wcid; 1560 1561 mt76_connac_txp_skb_unmap(mdev, txwi); 1562 if (!txwi->skb) 1563 goto out; 1564 1565 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi); 1566 val = le32_to_cpu(txwi_data[1]); 1567 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val); 1568 mt76_tx_complete_skb(mdev, wcid, txwi->skb); 1569 1570 out: 1571 txwi->skb = NULL; 1572 mt76_put_txwi(mdev, txwi); 1573 } 1574 1575 static void 1576 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token) 1577 { 1578 struct mt76_dev *mdev = &dev->mt76; 1579 struct mt76_txwi_cache *txwi; 1580 1581 trace_mac_tx_free(dev, token); 1582 txwi = mt76_token_put(mdev, token); 1583 if (!txwi) 1584 return; 1585 1586 mt7615_txwi_free(dev, txwi); 1587 } 1588 1589 static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len) 1590 { 1591 struct mt76_connac_tx_free *free = data; 1592 void *tx_token = data + sizeof(*free); 1593 void *end = data + len; 1594 u8 i, count; 1595 1596 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 1597 if (is_mt7615(&dev->mt76)) { 1598 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 1599 } else { 1600 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1601 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false); 1602 } 1603 1604 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT); 1605 if (is_mt7615(&dev->mt76)) { 1606 __le16 *token = tx_token; 1607 1608 if (WARN_ON_ONCE((void *)&token[count] > end)) 1609 return; 1610 1611 for (i = 0; i < count; i++) 1612 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i])); 1613 } else { 1614 __le32 *token = tx_token; 1615 1616 if (WARN_ON_ONCE((void *)&token[count] > end)) 1617 return; 1618 1619 for (i = 0; i < count; i++) 1620 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i])); 1621 } 1622 1623 rcu_read_lock(); 1624 mt7615_mac_sta_poll(dev); 1625 rcu_read_unlock(); 1626 1627 mt76_worker_schedule(&dev->mt76.tx_worker); 1628 } 1629 1630 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len) 1631 { 1632 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1633 __le32 *rxd = (__le32 *)data; 1634 __le32 *end = (__le32 *)&rxd[len / 4]; 1635 enum rx_pkt_type type; 1636 1637 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1638 1639 switch (type) { 1640 case PKT_TYPE_TXRX_NOTIFY: 1641 mt7615_mac_tx_free(dev, data, len); 1642 return false; 1643 case PKT_TYPE_TXS: 1644 for (rxd++; rxd + 7 <= end; rxd += 7) 1645 mt7615_mac_add_txs(dev, rxd); 1646 return false; 1647 default: 1648 return true; 1649 } 1650 } 1651 EXPORT_SYMBOL_GPL(mt7615_rx_check); 1652 1653 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1654 struct sk_buff *skb) 1655 { 1656 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 1657 __le32 *rxd = (__le32 *)skb->data; 1658 __le32 *end = (__le32 *)&skb->data[skb->len]; 1659 enum rx_pkt_type type; 1660 u16 flag; 1661 1662 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1663 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG); 1664 if (type == PKT_TYPE_RX_EVENT && flag == 0x1) 1665 type = PKT_TYPE_NORMAL_MCU; 1666 1667 switch (type) { 1668 case PKT_TYPE_TXS: 1669 for (rxd++; rxd + 7 <= end; rxd += 7) 1670 mt7615_mac_add_txs(dev, rxd); 1671 dev_kfree_skb(skb); 1672 break; 1673 case PKT_TYPE_TXRX_NOTIFY: 1674 mt7615_mac_tx_free(dev, skb->data, skb->len); 1675 dev_kfree_skb(skb); 1676 break; 1677 case PKT_TYPE_RX_EVENT: 1678 mt7615_mcu_rx_event(dev, skb); 1679 break; 1680 case PKT_TYPE_NORMAL_MCU: 1681 case PKT_TYPE_NORMAL: 1682 if (!mt7615_mac_fill_rx(dev, skb)) { 1683 mt76_rx(&dev->mt76, q, skb); 1684 return; 1685 } 1686 fallthrough; 1687 default: 1688 dev_kfree_skb(skb); 1689 break; 1690 } 1691 } 1692 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb); 1693 1694 static void 1695 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm) 1696 { 1697 struct mt7615_dev *dev = phy->dev; 1698 bool ext_phy = phy != &dev->phy; 1699 1700 if (is_mt7663(&dev->mt76)) { 1701 if (ofdm) 1702 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy), 1703 MT_WF_PHY_PD_OFDM_MASK(0), 1704 MT_WF_PHY_PD_OFDM(0, val)); 1705 else 1706 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy), 1707 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1708 MT_WF_PHY_PD_CCK(ext_phy, val)); 1709 return; 1710 } 1711 1712 if (ofdm) 1713 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy), 1714 MT_WF_PHY_PD_OFDM_MASK(ext_phy), 1715 MT_WF_PHY_PD_OFDM(ext_phy, val)); 1716 else 1717 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy), 1718 MT_WF_PHY_PD_CCK_MASK(ext_phy), 1719 MT_WF_PHY_PD_CCK(ext_phy, val)); 1720 } 1721 1722 static void 1723 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy) 1724 { 1725 /* ofdm */ 1726 mt7615_mac_set_sensitivity(phy, 0x13c, true); 1727 /* cck */ 1728 mt7615_mac_set_sensitivity(phy, 0x92, false); 1729 1730 phy->ofdm_sensitivity = -98; 1731 phy->cck_sensitivity = -110; 1732 phy->last_cca_adj = jiffies; 1733 } 1734 1735 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable) 1736 { 1737 struct mt7615_dev *dev = phy->dev; 1738 bool ext_phy = phy != &dev->phy; 1739 u32 reg, mask; 1740 1741 mt7615_mutex_acquire(dev); 1742 1743 if (phy->scs_en == enable) 1744 goto out; 1745 1746 if (is_mt7663(&dev->mt76)) { 1747 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy); 1748 mask = MT_WF_PHY_PD_BLK(0); 1749 } else { 1750 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy); 1751 mask = MT_WF_PHY_PD_BLK(ext_phy); 1752 } 1753 1754 if (enable) { 1755 mt76_set(dev, reg, mask); 1756 if (is_mt7622(&dev->mt76)) { 1757 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8); 1758 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7); 1759 } 1760 } else { 1761 mt76_clear(dev, reg, mask); 1762 } 1763 1764 mt7615_mac_set_default_sensitivity(phy); 1765 phy->scs_en = enable; 1766 1767 out: 1768 mt7615_mutex_release(dev); 1769 } 1770 1771 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy) 1772 { 1773 u32 rxtd, reg; 1774 1775 if (is_mt7663(&dev->mt76)) 1776 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1777 else 1778 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1779 1780 if (ext_phy) 1781 rxtd = MT_WF_PHY_RXTD2(10); 1782 else 1783 rxtd = MT_WF_PHY_RXTD(12); 1784 1785 mt76_set(dev, rxtd, BIT(18) | BIT(29)); 1786 mt76_set(dev, reg, 0x5 << 12); 1787 } 1788 1789 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy) 1790 { 1791 struct mt7615_dev *dev = phy->dev; 1792 bool ext_phy = phy != &dev->phy; 1793 u32 reg; 1794 1795 if (is_mt7663(&dev->mt76)) 1796 reg = MT7663_WF_PHY_R0_PHYMUX_5; 1797 else 1798 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy); 1799 1800 /* reset PD and MDRDY counters */ 1801 mt76_clear(dev, reg, GENMASK(22, 20)); 1802 mt76_set(dev, reg, BIT(22) | BIT(20)); 1803 } 1804 1805 static void 1806 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy, 1807 u32 rts_err_rate, bool ofdm) 1808 { 1809 struct mt7615_dev *dev = phy->dev; 1810 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck; 1811 bool ext_phy = phy != &dev->phy; 1812 s16 def_th = ofdm ? -98 : -110; 1813 bool update = false; 1814 s8 *sensitivity; 1815 int signal; 1816 1817 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity; 1818 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy); 1819 if (!signal) { 1820 mt7615_mac_set_default_sensitivity(phy); 1821 return; 1822 } 1823 1824 signal = min(signal, -72); 1825 if (false_cca > 500) { 1826 if (rts_err_rate > MT_FRAC(40, 100)) 1827 return; 1828 1829 /* decrease coverage */ 1830 if (*sensitivity == def_th && signal > -90) { 1831 *sensitivity = -90; 1832 update = true; 1833 } else if (*sensitivity + 2 < signal) { 1834 *sensitivity += 2; 1835 update = true; 1836 } 1837 } else if ((false_cca > 0 && false_cca < 50) || 1838 rts_err_rate > MT_FRAC(60, 100)) { 1839 /* increase coverage */ 1840 if (*sensitivity - 2 >= def_th) { 1841 *sensitivity -= 2; 1842 update = true; 1843 } 1844 } 1845 1846 if (*sensitivity > signal) { 1847 *sensitivity = signal; 1848 update = true; 1849 } 1850 1851 if (update) { 1852 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256; 1853 1854 mt7615_mac_set_sensitivity(phy, val, ofdm); 1855 phy->last_cca_adj = jiffies; 1856 } 1857 } 1858 1859 static void 1860 mt7615_mac_scs_check(struct mt7615_phy *phy) 1861 { 1862 struct mt7615_dev *dev = phy->dev; 1863 struct mib_stats *mib = &phy->mib; 1864 u32 val, rts_err_rate = 0; 1865 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm; 1866 bool ext_phy = phy != &dev->phy; 1867 1868 if (!phy->scs_en) 1869 return; 1870 1871 if (is_mt7663(&dev->mt76)) 1872 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1873 else 1874 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy)); 1875 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val); 1876 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val); 1877 1878 if (is_mt7663(&dev->mt76)) 1879 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1880 else 1881 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy)); 1882 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val); 1883 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val); 1884 1885 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1886 phy->false_cca_cck = pd_cck - mdrdy_cck; 1887 mt7615_mac_cca_stats_reset(phy); 1888 1889 if (mib->rts_cnt + mib->rts_retries_cnt) 1890 rts_err_rate = MT_FRAC(mib->rts_retries_cnt, 1891 mib->rts_cnt + mib->rts_retries_cnt); 1892 1893 /* cck */ 1894 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false); 1895 /* ofdm */ 1896 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true); 1897 1898 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ)) 1899 mt7615_mac_set_default_sensitivity(phy); 1900 } 1901 1902 static u8 1903 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx) 1904 { 1905 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1906 u32 reg, val, sum = 0, n = 0; 1907 int i; 1908 1909 if (is_mt7663(&dev->mt76)) 1910 reg = MT7663_WF_PHY_RXTD(20); 1911 else 1912 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20); 1913 1914 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1915 val = mt76_rr(dev, reg); 1916 sum += val * nf_power[i]; 1917 n += val; 1918 } 1919 1920 if (!n) 1921 return 0; 1922 1923 return sum / n; 1924 } 1925 1926 static void 1927 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx) 1928 { 1929 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1930 struct mt7615_phy *phy = mphy->priv; 1931 struct mt76_channel_state *state; 1932 u64 busy_time, tx_time, rx_time, obss_time; 1933 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5; 1934 int nf; 1935 1936 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx), 1937 MT_MIB_SDR9_BUSY_MASK); 1938 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx), 1939 MT_MIB_SDR36_TXTIME_MASK); 1940 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx), 1941 MT_MIB_SDR37_RXTIME_MASK); 1942 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK); 1943 1944 nf = mt7615_phy_get_nf(dev, idx); 1945 if (!phy->noise) 1946 phy->noise = nf << 4; 1947 else if (nf) 1948 phy->noise += nf - (phy->noise >> 4); 1949 1950 state = mphy->chan_state; 1951 state->cc_busy += busy_time; 1952 state->cc_tx += tx_time; 1953 state->cc_rx += rx_time + obss_time; 1954 state->cc_bss_rx += rx_time; 1955 state->noise = -(phy->noise >> 4); 1956 } 1957 1958 static void mt7615_update_survey(struct mt7615_dev *dev) 1959 { 1960 struct mt76_dev *mdev = &dev->mt76; 1961 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 1962 ktime_t cur_time; 1963 1964 /* MT7615 can only update both phys simultaneously 1965 * since some reisters are shared across bands. 1966 */ 1967 1968 mt7615_phy_update_channel(&mdev->phy, 0); 1969 if (mphy_ext) 1970 mt7615_phy_update_channel(mphy_ext, 1); 1971 1972 cur_time = ktime_get_boottime(); 1973 1974 mt76_update_survey_active_time(&mdev->phy, cur_time); 1975 if (mphy_ext) 1976 mt76_update_survey_active_time(mphy_ext, cur_time); 1977 1978 /* reset obss airtime */ 1979 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR); 1980 } 1981 1982 void mt7615_update_channel(struct mt76_phy *mphy) 1983 { 1984 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76); 1985 1986 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm)) 1987 return; 1988 1989 mt7615_update_survey(dev); 1990 mt76_connac_power_save_sched(&dev->mphy, &dev->pm); 1991 } 1992 EXPORT_SYMBOL_GPL(mt7615_update_channel); 1993 1994 static void 1995 mt7615_mac_update_mib_stats(struct mt7615_phy *phy) 1996 { 1997 struct mt7615_dev *dev = phy->dev; 1998 struct mib_stats *mib = &phy->mib; 1999 bool ext_phy = phy != &dev->phy; 2000 int i, aggr; 2001 u32 val, val2; 2002 2003 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy), 2004 MT_MIB_SDR3_FCS_ERR_MASK); 2005 2006 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy), 2007 MT_MIB_AMPDU_MPDU_COUNT); 2008 if (val) { 2009 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy), 2010 MT_MIB_AMPDU_ACK_COUNT); 2011 mib->aggr_per = 1000 * (val - val2) / val; 2012 } 2013 2014 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0; 2015 for (i = 0; i < 4; i++) { 2016 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i)); 2017 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 2018 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, 2019 val); 2020 2021 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i)); 2022 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 2023 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, 2024 val); 2025 2026 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i)); 2027 dev->mt76.aggr_stats[aggr++] += val & 0xffff; 2028 dev->mt76.aggr_stats[aggr++] += val >> 16; 2029 } 2030 } 2031 2032 void mt7615_pm_wake_work(struct work_struct *work) 2033 { 2034 struct mt7615_dev *dev; 2035 struct mt76_phy *mphy; 2036 2037 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2038 pm.wake_work); 2039 mphy = dev->phy.mt76; 2040 2041 if (!mt7615_mcu_set_drv_ctrl(dev)) { 2042 struct mt76_dev *mdev = &dev->mt76; 2043 int i; 2044 2045 if (mt76_is_sdio(mdev)) { 2046 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2047 mt76_worker_schedule(&mdev->sdio.txrx_worker); 2048 } else { 2049 local_bh_disable(); 2050 mt76_for_each_q_rx(mdev, i) 2051 napi_schedule(&mdev->napi[i]); 2052 local_bh_enable(); 2053 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm); 2054 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM], 2055 false); 2056 } 2057 2058 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) { 2059 unsigned long timeout; 2060 2061 timeout = mt7615_get_macwork_timeout(dev); 2062 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2063 timeout); 2064 } 2065 } 2066 2067 ieee80211_wake_queues(mphy->hw); 2068 wake_up(&dev->pm.wait); 2069 } 2070 2071 void mt7615_pm_power_save_work(struct work_struct *work) 2072 { 2073 struct mt7615_dev *dev; 2074 unsigned long delta; 2075 2076 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2077 pm.ps_work.work); 2078 2079 delta = dev->pm.idle_timeout; 2080 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) || 2081 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state)) 2082 goto out; 2083 2084 if (mutex_is_locked(&dev->mt76.mutex)) 2085 /* if mt76 mutex is held we should not put the device 2086 * to sleep since we are currently accessing device 2087 * register map. We need to wait for the next power_save 2088 * trigger. 2089 */ 2090 goto out; 2091 2092 if (time_is_after_jiffies(dev->pm.last_activity + delta)) { 2093 delta = dev->pm.last_activity + delta - jiffies; 2094 goto out; 2095 } 2096 2097 if (!mt7615_mcu_set_fw_ctrl(dev)) 2098 return; 2099 out: 2100 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta); 2101 } 2102 2103 void mt7615_mac_work(struct work_struct *work) 2104 { 2105 struct mt7615_phy *phy; 2106 struct mt76_phy *mphy; 2107 unsigned long timeout; 2108 2109 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2110 mac_work.work); 2111 phy = mphy->priv; 2112 2113 mt7615_mutex_acquire(phy->dev); 2114 2115 mt7615_update_survey(phy->dev); 2116 if (++mphy->mac_work_count == 5) { 2117 mphy->mac_work_count = 0; 2118 2119 mt7615_mac_update_mib_stats(phy); 2120 mt7615_mac_scs_check(phy); 2121 } 2122 2123 mt7615_mutex_release(phy->dev); 2124 2125 mt76_tx_status_check(mphy->dev, false); 2126 2127 timeout = mt7615_get_macwork_timeout(phy->dev); 2128 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout); 2129 } 2130 2131 void mt7615_tx_token_put(struct mt7615_dev *dev) 2132 { 2133 struct mt76_txwi_cache *txwi; 2134 int id; 2135 2136 spin_lock_bh(&dev->mt76.token_lock); 2137 idr_for_each_entry(&dev->mt76.token, txwi, id) 2138 mt7615_txwi_free(dev, txwi); 2139 spin_unlock_bh(&dev->mt76.token_lock); 2140 idr_destroy(&dev->mt76.token); 2141 } 2142 EXPORT_SYMBOL_GPL(mt7615_tx_token_put); 2143 2144 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy) 2145 { 2146 struct mt7615_dev *dev = phy->dev; 2147 2148 if (phy->rdd_state & BIT(0)) 2149 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2150 MT_RX_SEL0, 0); 2151 if (phy->rdd_state & BIT(1)) 2152 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2153 MT_RX_SEL0, 0); 2154 } 2155 2156 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain) 2157 { 2158 int err; 2159 2160 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2161 MT_RX_SEL0, 0); 2162 if (err < 0) 2163 return err; 2164 2165 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2166 MT_RX_SEL0, 1); 2167 } 2168 2169 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy) 2170 { 2171 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2172 struct mt7615_dev *dev = phy->dev; 2173 bool ext_phy = phy != &dev->phy; 2174 int err; 2175 2176 /* start CAC */ 2177 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy, 2178 MT_RX_SEL0, 0); 2179 if (err < 0) 2180 return err; 2181 2182 err = mt7615_dfs_start_rdd(dev, ext_phy); 2183 if (err < 0) 2184 return err; 2185 2186 phy->rdd_state |= BIT(ext_phy); 2187 2188 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2189 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2190 err = mt7615_dfs_start_rdd(dev, 1); 2191 if (err < 0) 2192 return err; 2193 2194 phy->rdd_state |= BIT(1); 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int 2201 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy) 2202 { 2203 const struct mt7615_dfs_radar_spec *radar_specs; 2204 struct mt7615_dev *dev = phy->dev; 2205 int err, i, lpn = 500; 2206 2207 switch (dev->mt76.region) { 2208 case NL80211_DFS_FCC: 2209 radar_specs = &fcc_radar_specs; 2210 lpn = 8; 2211 break; 2212 case NL80211_DFS_ETSI: 2213 radar_specs = &etsi_radar_specs; 2214 break; 2215 case NL80211_DFS_JP: 2216 radar_specs = &jp_radar_specs; 2217 break; 2218 default: 2219 return -EINVAL; 2220 } 2221 2222 /* avoid FCC radar detection in non-FCC region */ 2223 err = mt7615_mcu_set_fcc5_lpn(dev, lpn); 2224 if (err < 0) 2225 return err; 2226 2227 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2228 err = mt7615_mcu_set_radar_th(dev, i, 2229 &radar_specs->radar_pattern[i]); 2230 if (err < 0) 2231 return err; 2232 } 2233 2234 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2235 } 2236 2237 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy) 2238 { 2239 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2240 struct mt7615_dev *dev = phy->dev; 2241 bool ext_phy = phy != &dev->phy; 2242 enum mt76_dfs_state dfs_state, prev_state; 2243 int err; 2244 2245 if (is_mt7663(&dev->mt76)) 2246 return 0; 2247 2248 prev_state = phy->mt76->dfs_state; 2249 dfs_state = mt76_phy_dfs_state(phy->mt76); 2250 if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) && 2251 dfs_state < MT_DFS_STATE_CAC) 2252 dfs_state = MT_DFS_STATE_ACTIVE; 2253 2254 if (prev_state == dfs_state) 2255 return 0; 2256 2257 if (dfs_state == MT_DFS_STATE_DISABLED) 2258 goto stop; 2259 2260 if (prev_state <= MT_DFS_STATE_DISABLED) { 2261 err = mt7615_dfs_init_radar_specs(phy); 2262 if (err < 0) 2263 return err; 2264 2265 err = mt7615_dfs_start_radar_detector(phy); 2266 if (err < 0) 2267 return err; 2268 2269 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2270 } 2271 2272 if (dfs_state == MT_DFS_STATE_CAC) 2273 return 0; 2274 2275 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2276 ext_phy, MT_RX_SEL0, 0); 2277 if (err < 0) { 2278 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2279 return err; 2280 } 2281 2282 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2283 return 0; 2284 2285 stop: 2286 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy, 2287 MT_RX_SEL0, 0); 2288 if (err < 0) 2289 return err; 2290 2291 mt7615_dfs_stop_radar_detector(phy); 2292 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2293 2294 return 0; 2295 } 2296 2297 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy, 2298 struct ieee80211_vif *vif, 2299 bool enable) 2300 { 2301 struct mt7615_dev *dev = phy->dev; 2302 bool ext_phy = phy != &dev->phy; 2303 int err; 2304 2305 if (!mt7615_firmware_offload(dev)) 2306 return -EOPNOTSUPP; 2307 2308 switch (vif->type) { 2309 case NL80211_IFTYPE_MONITOR: 2310 return 0; 2311 case NL80211_IFTYPE_MESH_POINT: 2312 case NL80211_IFTYPE_ADHOC: 2313 case NL80211_IFTYPE_AP: 2314 if (enable) 2315 phy->n_beacon_vif++; 2316 else 2317 phy->n_beacon_vif--; 2318 fallthrough; 2319 default: 2320 break; 2321 } 2322 2323 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif); 2324 if (err) 2325 return err; 2326 2327 if (phy->n_beacon_vif) { 2328 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER; 2329 mt76_clear(dev, MT_WF_RFCR(ext_phy), 2330 MT_WF_RFCR_DROP_OTHER_BEACON); 2331 } else { 2332 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER; 2333 mt76_set(dev, MT_WF_RFCR(ext_phy), 2334 MT_WF_RFCR_DROP_OTHER_BEACON); 2335 } 2336 2337 return 0; 2338 } 2339 2340 void mt7615_coredump_work(struct work_struct *work) 2341 { 2342 struct mt7615_dev *dev; 2343 char *dump, *data; 2344 2345 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev, 2346 coredump.work.work); 2347 2348 if (time_is_after_jiffies(dev->coredump.last_activity + 2349 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) { 2350 queue_delayed_work(dev->mt76.wq, &dev->coredump.work, 2351 MT76_CONNAC_COREDUMP_TIMEOUT); 2352 return; 2353 } 2354 2355 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ); 2356 data = dump; 2357 2358 while (true) { 2359 struct sk_buff *skb; 2360 2361 spin_lock_bh(&dev->mt76.lock); 2362 skb = __skb_dequeue(&dev->coredump.msg_list); 2363 spin_unlock_bh(&dev->mt76.lock); 2364 2365 if (!skb) 2366 break; 2367 2368 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 2369 if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) { 2370 dev_kfree_skb(skb); 2371 continue; 2372 } 2373 2374 memcpy(data, skb->data, skb->len); 2375 data += skb->len; 2376 2377 dev_kfree_skb(skb); 2378 } 2379 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ, 2380 GFP_KERNEL); 2381 } 2382