1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Lorenzo Bianconi <lorenzo@kernel.org> 7 * Felix Fietkau <nbd@nbd.name> 8 */ 9 10 #include "mt7615.h" 11 #include "../dma.h" 12 #include "mac.h" 13 14 static int 15 mt7615_init_tx_queue(struct mt7615_dev *dev, struct mt76_sw_queue *q, 16 int idx, int n_desc) 17 { 18 struct mt76_queue *hwq; 19 int err; 20 21 hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL); 22 if (!hwq) 23 return -ENOMEM; 24 25 err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE); 26 if (err < 0) 27 return err; 28 29 INIT_LIST_HEAD(&q->swq); 30 q->q = hwq; 31 32 return 0; 33 } 34 35 static int 36 mt7622_init_tx_queues_multi(struct mt7615_dev *dev) 37 { 38 static const u8 wmm_queue_map[] = { 39 [IEEE80211_AC_BK] = MT7622_TXQ_AC0, 40 [IEEE80211_AC_BE] = MT7622_TXQ_AC1, 41 [IEEE80211_AC_VI] = MT7622_TXQ_AC2, 42 [IEEE80211_AC_VO] = MT7622_TXQ_AC3, 43 }; 44 int ret; 45 int i; 46 47 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 48 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[i], 49 wmm_queue_map[i], 50 MT7615_TX_RING_SIZE / 2); 51 if (ret) 52 return ret; 53 } 54 55 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD], 56 MT7622_TXQ_MGMT, MT7615_TX_MGMT_RING_SIZE); 57 if (ret) 58 return ret; 59 60 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU], 61 MT7622_TXQ_MCU, MT7615_TX_MCU_RING_SIZE); 62 return ret; 63 } 64 65 static int 66 mt7615_init_tx_queues(struct mt7615_dev *dev) 67 { 68 struct mt76_sw_queue *q; 69 int ret, i; 70 71 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_FWDL], 72 MT7615_TXQ_FWDL, 73 MT7615_TX_FWDL_RING_SIZE); 74 if (ret) 75 return ret; 76 77 if (!is_mt7615(&dev->mt76)) 78 return mt7622_init_tx_queues_multi(dev); 79 80 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[0], 0, 81 MT7615_TX_RING_SIZE); 82 if (ret) 83 return ret; 84 85 for (i = 1; i < MT_TXQ_MCU; i++) { 86 q = &dev->mt76.q_tx[i]; 87 INIT_LIST_HEAD(&q->swq); 88 q->q = dev->mt76.q_tx[0].q; 89 } 90 91 ret = mt7615_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU], 92 MT7615_TXQ_MCU, 93 MT7615_TX_MCU_RING_SIZE); 94 return 0; 95 } 96 97 static void 98 mt7615_tx_cleanup(struct mt7615_dev *dev) 99 { 100 int i; 101 102 mt76_queue_tx_cleanup(dev, MT_TXQ_MCU, false); 103 mt76_queue_tx_cleanup(dev, MT_TXQ_PSD, false); 104 if (is_mt7615(&dev->mt76)) { 105 mt76_queue_tx_cleanup(dev, MT_TXQ_BE, false); 106 } else { 107 for (i = 0; i < IEEE80211_NUM_ACS; i++) 108 mt76_queue_tx_cleanup(dev, i, false); 109 } 110 } 111 112 static int mt7615_poll_tx(struct napi_struct *napi, int budget) 113 { 114 struct mt7615_dev *dev; 115 116 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); 117 118 mt7615_tx_cleanup(dev); 119 120 if (napi_complete_done(napi, 0)) 121 mt7615_irq_enable(dev, MT_INT_TX_DONE_ALL); 122 123 mt7615_tx_cleanup(dev); 124 125 rcu_read_lock(); 126 mt7615_mac_sta_poll(dev); 127 rcu_read_unlock(); 128 129 tasklet_schedule(&dev->mt76.tx_tasklet); 130 131 return 0; 132 } 133 134 int mt7615_wait_pdma_busy(struct mt7615_dev *dev) 135 { 136 struct mt76_dev *mdev = &dev->mt76; 137 138 if (!is_mt7663(mdev)) { 139 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY; 140 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY); 141 142 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) { 143 dev_err(mdev->dev, "PDMA engine busy\n"); 144 return -EIO; 145 } 146 147 return 0; 148 } 149 150 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 151 MT_PDMA_TX_IDX_BUSY, 0, 1000)) { 152 dev_err(mdev->dev, "PDMA engine tx busy\n"); 153 return -EIO; 154 } 155 156 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO, 157 MT_PSE_SRC_CNT, 0, 1000)) { 158 dev_err(mdev->dev, "PSE engine busy\n"); 159 return -EIO; 160 } 161 162 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 163 MT_PDMA_BUSY_IDX, 0, 1000)) { 164 dev_err(mdev->dev, "PDMA engine busy\n"); 165 return -EIO; 166 } 167 168 return 0; 169 } 170 171 static void mt7622_dma_sched_init(struct mt7615_dev *dev) 172 { 173 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE); 174 int i; 175 176 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE, 177 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 178 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 179 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 180 181 for (i = 0; i <= 5; i++) 182 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i), 183 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) | 184 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 185 186 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210); 187 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210); 188 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5); 189 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0); 190 191 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f); 192 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987); 193 } 194 195 static void mt7663_dma_sched_init(struct mt7615_dev *dev) 196 { 197 int i; 198 199 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), 200 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 201 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 202 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 203 204 /* enable refill control group 0, 1, 2, 4, 5 */ 205 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000); 206 /* enable group 0, 1, 2, 4, 5, 15 */ 207 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037); 208 209 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */ 210 for (i = 0; i < 5; i++) 211 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), 212 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 213 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 214 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)), 215 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 216 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40)); 217 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)), 218 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) | 219 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20)); 220 221 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); 222 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); 223 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005); 224 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0); 225 /* ALTX0 and ALTX1 QID mapping to group 5 */ 226 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f); 227 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987); 228 } 229 230 int mt7615_dma_init(struct mt7615_dev *dev) 231 { 232 int rx_ring_size = MT7615_RX_RING_SIZE; 233 int rx_buf_size = MT_RX_BUF_SIZE; 234 int ret; 235 236 /* Increase buffer size to receive large VHT MPDUs */ 237 if (dev->mt76.cap.has_5ghz) 238 rx_buf_size *= 2; 239 240 mt76_dma_attach(&dev->mt76); 241 242 mt76_wr(dev, MT_WPDMA_GLO_CFG, 243 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE | 244 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN | 245 MT_WPDMA_GLO_CFG_OMIT_TX_INFO); 246 247 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 248 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1); 249 250 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 251 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1); 252 253 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 254 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3); 255 256 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 257 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3); 258 259 if (is_mt7615(&dev->mt76)) { 260 mt76_set(dev, MT_WPDMA_GLO_CFG, 261 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY); 262 263 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1); 264 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000); 265 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000); 266 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026); 267 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881); 268 mt76_set(dev, 0x7158, BIT(16)); 269 mt76_clear(dev, 0x7000, BIT(23)); 270 } 271 272 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 273 274 ret = mt7615_init_tx_queues(dev); 275 if (ret) 276 return ret; 277 278 /* init rx queues */ 279 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 280 MT7615_RX_MCU_RING_SIZE, rx_buf_size, 281 MT_RX_RING_BASE); 282 if (ret) 283 return ret; 284 285 if (!is_mt7615(&dev->mt76)) 286 rx_ring_size /= 2; 287 288 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 289 rx_ring_size, rx_buf_size, MT_RX_RING_BASE); 290 if (ret) 291 return ret; 292 293 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 294 295 ret = mt76_init_queues(dev); 296 if (ret < 0) 297 return ret; 298 299 netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi, 300 mt7615_poll_tx, NAPI_POLL_WEIGHT); 301 napi_enable(&dev->mt76.tx_napi); 302 303 mt76_poll(dev, MT_WPDMA_GLO_CFG, 304 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 305 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000); 306 307 /* start dma engine */ 308 mt76_set(dev, MT_WPDMA_GLO_CFG, 309 MT_WPDMA_GLO_CFG_TX_DMA_EN | 310 MT_WPDMA_GLO_CFG_RX_DMA_EN); 311 312 /* enable interrupts for TX/RX rings */ 313 mt7615_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 314 MT_INT_MCU_CMD); 315 316 if (is_mt7622(&dev->mt76)) 317 mt7622_dma_sched_init(dev); 318 319 if (is_mt7663(&dev->mt76)) 320 mt7663_dma_sched_init(dev); 321 322 return 0; 323 } 324 325 void mt7615_dma_cleanup(struct mt7615_dev *dev) 326 { 327 mt76_clear(dev, MT_WPDMA_GLO_CFG, 328 MT_WPDMA_GLO_CFG_TX_DMA_EN | 329 MT_WPDMA_GLO_CFG_RX_DMA_EN); 330 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 331 332 tasklet_kill(&dev->mt76.tx_tasklet); 333 mt76_dma_cleanup(&dev->mt76); 334 } 335