1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Roy Luo <royluo@google.com> 6 * Lorenzo Bianconi <lorenzo@kernel.org> 7 * Felix Fietkau <nbd@nbd.name> 8 */ 9 10 #include "mt7615.h" 11 #include "../dma.h" 12 #include "mac.h" 13 14 static int 15 mt7622_init_tx_queues_multi(struct mt7615_dev *dev) 16 { 17 static const u8 wmm_queue_map[] = { 18 [IEEE80211_AC_BK] = MT7622_TXQ_AC0, 19 [IEEE80211_AC_BE] = MT7622_TXQ_AC1, 20 [IEEE80211_AC_VI] = MT7622_TXQ_AC2, 21 [IEEE80211_AC_VO] = MT7622_TXQ_AC3, 22 }; 23 int ret; 24 int i; 25 26 for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) { 27 ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i], 28 MT7615_TX_RING_SIZE / 2, 29 MT_TX_RING_BASE); 30 if (ret) 31 return ret; 32 } 33 34 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT, 35 MT7615_TX_MGMT_RING_SIZE, 36 MT_TX_RING_BASE); 37 if (ret) 38 return ret; 39 40 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU, 41 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 42 } 43 44 static int 45 mt7615_init_tx_queues(struct mt7615_dev *dev) 46 { 47 int ret, i; 48 49 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL, 50 MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 51 if (ret) 52 return ret; 53 54 if (!is_mt7615(&dev->mt76)) 55 return mt7622_init_tx_queues_multi(dev); 56 57 ret = mt76_init_tx_queue(&dev->mphy, 0, 0, MT7615_TX_RING_SIZE, 58 MT_TX_RING_BASE); 59 if (ret) 60 return ret; 61 62 for (i = 1; i <= MT_TXQ_PSD ; i++) 63 dev->mphy.q_tx[i] = dev->mphy.q_tx[0]; 64 65 return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU, 66 MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 67 } 68 69 static int mt7615_poll_tx(struct napi_struct *napi, int budget) 70 { 71 struct mt7615_dev *dev; 72 73 dev = container_of(napi, struct mt7615_dev, mt76.tx_napi); 74 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { 75 napi_complete(napi); 76 queue_work(dev->mt76.wq, &dev->pm.wake_work); 77 return 0; 78 } 79 80 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false); 81 if (napi_complete(napi)) 82 mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev)); 83 84 mt76_connac_pm_unref(&dev->pm); 85 86 return 0; 87 } 88 89 static int mt7615_poll_rx(struct napi_struct *napi, int budget) 90 { 91 struct mt7615_dev *dev; 92 int done; 93 94 dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev); 95 96 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) { 97 napi_complete(napi); 98 queue_work(dev->mt76.wq, &dev->pm.wake_work); 99 return 0; 100 } 101 done = mt76_dma_rx_poll(napi, budget); 102 mt76_connac_pm_unref(&dev->pm); 103 104 return done; 105 } 106 107 int mt7615_wait_pdma_busy(struct mt7615_dev *dev) 108 { 109 struct mt76_dev *mdev = &dev->mt76; 110 111 if (!is_mt7663(mdev)) { 112 u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY; 113 u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY); 114 115 if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) { 116 dev_err(mdev->dev, "PDMA engine busy\n"); 117 return -EIO; 118 } 119 120 return 0; 121 } 122 123 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 124 MT_PDMA_TX_IDX_BUSY, 0, 1000)) { 125 dev_err(mdev->dev, "PDMA engine tx busy\n"); 126 return -EIO; 127 } 128 129 if (!mt76_poll_msec(dev, MT_PSE_PG_INFO, 130 MT_PSE_SRC_CNT, 0, 1000)) { 131 dev_err(mdev->dev, "PSE engine busy\n"); 132 return -EIO; 133 } 134 135 if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS, 136 MT_PDMA_BUSY_IDX, 0, 1000)) { 137 dev_err(mdev->dev, "PDMA engine busy\n"); 138 return -EIO; 139 } 140 141 return 0; 142 } 143 144 static void mt7622_dma_sched_init(struct mt7615_dev *dev) 145 { 146 u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE); 147 int i; 148 149 mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE, 150 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 151 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 152 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 153 154 for (i = 0; i <= 5; i++) 155 mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i), 156 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) | 157 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 158 159 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210); 160 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210); 161 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5); 162 mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0); 163 164 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f); 165 mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987); 166 } 167 168 static void mt7663_dma_sched_init(struct mt7615_dev *dev) 169 { 170 int i; 171 172 mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE), 173 MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE, 174 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | 175 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); 176 177 /* enable refill control group 0, 1, 2, 4, 5 */ 178 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000); 179 /* enable group 0, 1, 2, 4, 5, 15 */ 180 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037); 181 182 /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */ 183 for (i = 0; i < 5; i++) 184 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)), 185 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 186 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800)); 187 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)), 188 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) | 189 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40)); 190 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)), 191 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) | 192 FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20)); 193 194 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210); 195 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210); 196 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005); 197 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0); 198 /* ALTX0 and ALTX1 QID mapping to group 5 */ 199 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f); 200 mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987); 201 } 202 203 void mt7615_dma_start(struct mt7615_dev *dev) 204 { 205 /* start dma engine */ 206 mt76_set(dev, MT_WPDMA_GLO_CFG, 207 MT_WPDMA_GLO_CFG_TX_DMA_EN | 208 MT_WPDMA_GLO_CFG_RX_DMA_EN | 209 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 210 211 if (is_mt7622(&dev->mt76)) 212 mt7622_dma_sched_init(dev); 213 214 if (is_mt7663(&dev->mt76)) { 215 mt7663_dma_sched_init(dev); 216 217 mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK); 218 } 219 220 } 221 222 int mt7615_dma_init(struct mt7615_dev *dev) 223 { 224 int rx_ring_size = MT7615_RX_RING_SIZE; 225 int rx_buf_size = MT_RX_BUF_SIZE; 226 u32 mask; 227 int ret; 228 229 /* Increase buffer size to receive large VHT MPDUs */ 230 if (dev->mphy.cap.has_5ghz) 231 rx_buf_size *= 2; 232 233 mt76_dma_attach(&dev->mt76); 234 235 mt76_wr(dev, MT_WPDMA_GLO_CFG, 236 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE | 237 MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN | 238 MT_WPDMA_GLO_CFG_OMIT_TX_INFO); 239 240 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 241 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1); 242 243 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 244 MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1); 245 246 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 247 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3); 248 249 mt76_rmw_field(dev, MT_WPDMA_GLO_CFG, 250 MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3); 251 252 if (is_mt7615(&dev->mt76)) { 253 mt76_set(dev, MT_WPDMA_GLO_CFG, 254 MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY); 255 256 mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1); 257 mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000); 258 mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000); 259 mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026); 260 mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881); 261 mt76_set(dev, 0x7158, BIT(16)); 262 mt76_clear(dev, 0x7000, BIT(23)); 263 } 264 265 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0); 266 267 ret = mt7615_init_tx_queues(dev); 268 if (ret) 269 return ret; 270 271 /* init rx queues */ 272 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1, 273 MT7615_RX_MCU_RING_SIZE, rx_buf_size, 274 MT_RX_RING_BASE); 275 if (ret) 276 return ret; 277 278 if (!is_mt7615(&dev->mt76)) 279 rx_ring_size /= 2; 280 281 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0, 282 rx_ring_size, rx_buf_size, MT_RX_RING_BASE); 283 if (ret) 284 return ret; 285 286 mt76_wr(dev, MT_DELAY_INT_CFG, 0); 287 288 ret = mt76_init_queues(dev, mt7615_poll_rx); 289 if (ret < 0) 290 return ret; 291 292 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 293 mt7615_poll_tx, NAPI_POLL_WEIGHT); 294 napi_enable(&dev->mt76.tx_napi); 295 296 mt76_poll(dev, MT_WPDMA_GLO_CFG, 297 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 298 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000); 299 300 /* enable interrupts for TX/RX rings */ 301 302 mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev); 303 if (is_mt7663(&dev->mt76)) 304 mask |= MT7663_INT_MCU_CMD; 305 else 306 mask |= MT_INT_MCU_CMD; 307 308 mt7615_irq_enable(dev, mask); 309 310 mt7615_dma_start(dev); 311 312 return 0; 313 } 314 315 void mt7615_dma_cleanup(struct mt7615_dev *dev) 316 { 317 mt76_clear(dev, MT_WPDMA_GLO_CFG, 318 MT_WPDMA_GLO_CFG_TX_DMA_EN | 319 MT_WPDMA_GLO_CFG_RX_DMA_EN); 320 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 321 322 mt76_dma_cleanup(&dev->mt76); 323 } 324