17f17b86aSRyder Lee // SPDX-License-Identifier: ISC 2c8846e10SFelix Fietkau 3c8846e10SFelix Fietkau #include <linux/etherdevice.h> 4c8846e10SFelix Fietkau #include <linux/platform_device.h> 5c8846e10SFelix Fietkau #include <linux/pci.h> 6c8846e10SFelix Fietkau #include <linux/module.h> 7c8846e10SFelix Fietkau #include "mt7603.h" 8b126c889SFelix Fietkau #include "mac.h" 9c8846e10SFelix Fietkau #include "eeprom.h" 10c8846e10SFelix Fietkau 11c8846e10SFelix Fietkau static int 12c8846e10SFelix Fietkau mt7603_start(struct ieee80211_hw *hw) 13c8846e10SFelix Fietkau { 14c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 15c8846e10SFelix Fietkau 165a8d4678SLorenzo Bianconi mt7603_mac_reset_counters(dev); 17c8846e10SFelix Fietkau mt7603_mac_start(dev); 1896747a51SFelix Fietkau dev->mphy.survey_time = ktime_get_boottime(); 19011849e0SFelix Fietkau set_bit(MT76_STATE_RUNNING, &dev->mphy.state); 20a782f8bfSLorenzo Bianconi mt7603_mac_work(&dev->mphy.mac_work.work); 21c8846e10SFelix Fietkau 22c8846e10SFelix Fietkau return 0; 23c8846e10SFelix Fietkau } 24c8846e10SFelix Fietkau 25c8846e10SFelix Fietkau static void 26c8846e10SFelix Fietkau mt7603_stop(struct ieee80211_hw *hw) 27c8846e10SFelix Fietkau { 28c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 29c8846e10SFelix Fietkau 30011849e0SFelix Fietkau clear_bit(MT76_STATE_RUNNING, &dev->mphy.state); 31a782f8bfSLorenzo Bianconi cancel_delayed_work_sync(&dev->mphy.mac_work); 32c8846e10SFelix Fietkau mt7603_mac_stop(dev); 33c8846e10SFelix Fietkau } 34c8846e10SFelix Fietkau 35c8846e10SFelix Fietkau static int 36c8846e10SFelix Fietkau mt7603_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 37c8846e10SFelix Fietkau { 38c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 39c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 40c8846e10SFelix Fietkau struct mt76_txq *mtxq; 41c8846e10SFelix Fietkau u8 bc_addr[ETH_ALEN]; 42c8846e10SFelix Fietkau int idx; 43c8846e10SFelix Fietkau int ret = 0; 44c8846e10SFelix Fietkau 45c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 46c8846e10SFelix Fietkau 47b619e013SEvelyn Tsai mvif->idx = __ffs64(~dev->mt76.vif_mask); 48c8846e10SFelix Fietkau if (mvif->idx >= MT7603_MAX_INTERFACES) { 49c8846e10SFelix Fietkau ret = -ENOSPC; 50c8846e10SFelix Fietkau goto out; 51c8846e10SFelix Fietkau } 52c8846e10SFelix Fietkau 53c8846e10SFelix Fietkau mt76_wr(dev, MT_MAC_ADDR0(mvif->idx), 54c8846e10SFelix Fietkau get_unaligned_le32(vif->addr)); 55c8846e10SFelix Fietkau mt76_wr(dev, MT_MAC_ADDR1(mvif->idx), 56c8846e10SFelix Fietkau (get_unaligned_le16(vif->addr + 4) | 57c8846e10SFelix Fietkau MT_MAC_ADDR1_VALID)); 58c8846e10SFelix Fietkau 59c8846e10SFelix Fietkau if (vif->type == NL80211_IFTYPE_AP) { 60c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID0(mvif->idx), 61c8846e10SFelix Fietkau get_unaligned_le32(vif->addr)); 62c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID1(mvif->idx), 63c8846e10SFelix Fietkau (get_unaligned_le16(vif->addr + 4) | 64c8846e10SFelix Fietkau MT_BSSID1_VALID)); 65c8846e10SFelix Fietkau } 66c8846e10SFelix Fietkau 67c8846e10SFelix Fietkau idx = MT7603_WTBL_RESERVED - 1 - mvif->idx; 68b619e013SEvelyn Tsai dev->mt76.vif_mask |= BIT_ULL(mvif->idx); 69ea565833SFelix Fietkau INIT_LIST_HEAD(&mvif->sta.poll_list); 70c8846e10SFelix Fietkau mvif->sta.wcid.idx = idx; 71c8846e10SFelix Fietkau mvif->sta.wcid.hw_key_idx = -1; 72bd1e3e7bSLorenzo Bianconi mt76_packet_id_init(&mvif->sta.wcid); 73c8846e10SFelix Fietkau 74c8846e10SFelix Fietkau eth_broadcast_addr(bc_addr); 75c8846e10SFelix Fietkau mt7603_wtbl_init(dev, idx, mvif->idx, bc_addr); 76c8846e10SFelix Fietkau 77c8846e10SFelix Fietkau mtxq = (struct mt76_txq *)vif->txq->drv_priv; 7851fb1278SFelix Fietkau mtxq->wcid = idx; 79c8846e10SFelix Fietkau rcu_assign_pointer(dev->mt76.wcid[idx], &mvif->sta.wcid); 80c8846e10SFelix Fietkau 81c8846e10SFelix Fietkau out: 82c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 83c8846e10SFelix Fietkau 84c8846e10SFelix Fietkau return ret; 85c8846e10SFelix Fietkau } 86c8846e10SFelix Fietkau 87c8846e10SFelix Fietkau static void 88c8846e10SFelix Fietkau mt7603_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 89c8846e10SFelix Fietkau { 90c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 91ea565833SFelix Fietkau struct mt7603_sta *msta = &mvif->sta; 92c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 93ea565833SFelix Fietkau int idx = msta->wcid.idx; 94c8846e10SFelix Fietkau 95c8846e10SFelix Fietkau mt76_wr(dev, MT_MAC_ADDR0(mvif->idx), 0); 96c8846e10SFelix Fietkau mt76_wr(dev, MT_MAC_ADDR1(mvif->idx), 0); 97c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID0(mvif->idx), 0); 98c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID1(mvif->idx), 0); 99c8846e10SFelix Fietkau mt7603_beacon_set_timer(dev, mvif->idx, 0); 100c8846e10SFelix Fietkau 101c8846e10SFelix Fietkau rcu_assign_pointer(dev->mt76.wcid[idx], NULL); 102c8846e10SFelix Fietkau 103ea565833SFelix Fietkau spin_lock_bh(&dev->sta_poll_lock); 104ea565833SFelix Fietkau if (!list_empty(&msta->poll_list)) 105ea565833SFelix Fietkau list_del_init(&msta->poll_list); 106ea565833SFelix Fietkau spin_unlock_bh(&dev->sta_poll_lock); 107ea565833SFelix Fietkau 108c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 109b619e013SEvelyn Tsai dev->mt76.vif_mask &= ~BIT_ULL(mvif->idx); 110c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 111bd1e3e7bSLorenzo Bianconi 112bd1e3e7bSLorenzo Bianconi mt76_packet_id_flush(&dev->mt76, &mvif->sta.wcid); 113c8846e10SFelix Fietkau } 114c8846e10SFelix Fietkau 115984d8854SLorenzo Bianconi void mt7603_init_edcca(struct mt7603_dev *dev) 116c8846e10SFelix Fietkau { 117c8846e10SFelix Fietkau /* Set lower signal level to -65dBm */ 118c8846e10SFelix Fietkau mt76_rmw_field(dev, MT_RXTD(8), MT_RXTD_8_LOWER_SIGNAL, 0x23); 119c8846e10SFelix Fietkau 120c8846e10SFelix Fietkau /* clear previous energy detect monitor results */ 121c8846e10SFelix Fietkau mt76_rr(dev, MT_MIB_STAT_ED); 122c8846e10SFelix Fietkau 123c8846e10SFelix Fietkau if (dev->ed_monitor) 124c8846e10SFelix Fietkau mt76_set(dev, MT_MIB_CTL, MT_MIB_CTL_ED_TIME); 125c8846e10SFelix Fietkau else 126c8846e10SFelix Fietkau mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_ED_TIME); 127c8846e10SFelix Fietkau 128c8846e10SFelix Fietkau dev->ed_strict_mode = 0xff; 129c8846e10SFelix Fietkau dev->ed_strong_signal = 0; 130c8846e10SFelix Fietkau dev->ed_time = ktime_get_boottime(); 131c8846e10SFelix Fietkau 132c8846e10SFelix Fietkau mt7603_edcca_set_strict(dev, false); 133c8846e10SFelix Fietkau } 134c8846e10SFelix Fietkau 135c8846e10SFelix Fietkau static int 1364bbd6d83SLorenzo Bianconi mt7603_set_channel(struct ieee80211_hw *hw, struct cfg80211_chan_def *def) 137c8846e10SFelix Fietkau { 1384bbd6d83SLorenzo Bianconi struct mt7603_dev *dev = hw->priv; 139c8846e10SFelix Fietkau u8 *rssi_data = (u8 *)dev->mt76.eeprom.data; 140c8846e10SFelix Fietkau int idx, ret; 141c8846e10SFelix Fietkau u8 bw = MT_BW_20; 142c8846e10SFelix Fietkau bool failed = false; 143c8846e10SFelix Fietkau 1444bbd6d83SLorenzo Bianconi ieee80211_stop_queues(hw); 145a782f8bfSLorenzo Bianconi cancel_delayed_work_sync(&dev->mphy.mac_work); 146bd115805SLorenzo Bianconi tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 147c8846e10SFelix Fietkau 148c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 149011849e0SFelix Fietkau set_bit(MT76_RESET, &dev->mphy.state); 150c8846e10SFelix Fietkau 151bd115805SLorenzo Bianconi mt7603_beacon_set_timer(dev, -1, 0); 15296747a51SFelix Fietkau mt76_set_channel(&dev->mphy); 153c8846e10SFelix Fietkau mt7603_mac_stop(dev); 154c8846e10SFelix Fietkau 155c8846e10SFelix Fietkau if (def->width == NL80211_CHAN_WIDTH_40) 156c8846e10SFelix Fietkau bw = MT_BW_40; 157c8846e10SFelix Fietkau 15896747a51SFelix Fietkau dev->mphy.chandef = *def; 159c8846e10SFelix Fietkau mt76_rmw_field(dev, MT_AGG_BWCR, MT_AGG_BWCR_BW, bw); 160c8846e10SFelix Fietkau ret = mt7603_mcu_set_channel(dev); 161c8846e10SFelix Fietkau if (ret) { 162c8846e10SFelix Fietkau failed = true; 163c8846e10SFelix Fietkau goto out; 164c8846e10SFelix Fietkau } 165c8846e10SFelix Fietkau 166c8846e10SFelix Fietkau if (def->chan->band == NL80211_BAND_5GHZ) { 167c8846e10SFelix Fietkau idx = 1; 168c8846e10SFelix Fietkau rssi_data += MT_EE_RSSI_OFFSET_5G; 169c8846e10SFelix Fietkau } else { 170c8846e10SFelix Fietkau idx = 0; 171c8846e10SFelix Fietkau rssi_data += MT_EE_RSSI_OFFSET_2G; 172c8846e10SFelix Fietkau } 173c8846e10SFelix Fietkau 174c8846e10SFelix Fietkau memcpy(dev->rssi_offset, rssi_data, sizeof(dev->rssi_offset)); 175c8846e10SFelix Fietkau 176c8846e10SFelix Fietkau idx |= (def->chan - 177c8846e10SFelix Fietkau mt76_hw(dev)->wiphy->bands[def->chan->band]->channels) << 1; 178c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_RMAC_CH_FREQ, idx); 179c8846e10SFelix Fietkau mt7603_mac_set_timing(dev); 180c8846e10SFelix Fietkau mt7603_mac_start(dev); 181c8846e10SFelix Fietkau 182011849e0SFelix Fietkau clear_bit(MT76_RESET, &dev->mphy.state); 183c8846e10SFelix Fietkau 1849fba6d07SFelix Fietkau mt76_txq_schedule_all(&dev->mphy); 185c8846e10SFelix Fietkau 186a782f8bfSLorenzo Bianconi ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1875e814e71SLorenzo Bianconi msecs_to_jiffies(MT7603_WATCHDOG_TIME)); 188c8846e10SFelix Fietkau 189c8846e10SFelix Fietkau /* reset channel stats */ 190c8846e10SFelix Fietkau mt76_clear(dev, MT_MIB_CTL, MT_MIB_CTL_READ_CLR_DIS); 191c8846e10SFelix Fietkau mt76_set(dev, MT_MIB_CTL, 192c8846e10SFelix Fietkau MT_MIB_CTL_CCA_NAV_TX | MT_MIB_CTL_PSCCA_TIME); 19300c29ab2SLorenzo Bianconi mt76_rr(dev, MT_MIB_STAT_CCA); 194c8846e10SFelix Fietkau mt7603_cca_stats_reset(dev); 195c8846e10SFelix Fietkau 19696747a51SFelix Fietkau dev->mphy.survey_time = ktime_get_boottime(); 197c8846e10SFelix Fietkau 198c8846e10SFelix Fietkau mt7603_init_edcca(dev); 199c8846e10SFelix Fietkau 200c8846e10SFelix Fietkau out: 201bd115805SLorenzo Bianconi if (!(mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 202bd115805SLorenzo Bianconi mt7603_beacon_set_timer(dev, -1, dev->mt76.beacon_int); 203c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 204c8846e10SFelix Fietkau 205bd115805SLorenzo Bianconi tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 206bd115805SLorenzo Bianconi 207c8846e10SFelix Fietkau if (failed) 208a782f8bfSLorenzo Bianconi mt7603_mac_work(&dev->mphy.mac_work.work); 209c8846e10SFelix Fietkau 2104bbd6d83SLorenzo Bianconi ieee80211_wake_queues(hw); 2114bbd6d83SLorenzo Bianconi 212c8846e10SFelix Fietkau return ret; 213c8846e10SFelix Fietkau } 214c8846e10SFelix Fietkau 2154bbd6d83SLorenzo Bianconi static int mt7603_set_sar_specs(struct ieee80211_hw *hw, 2164bbd6d83SLorenzo Bianconi const struct cfg80211_sar_specs *sar) 2174bbd6d83SLorenzo Bianconi { 2184bbd6d83SLorenzo Bianconi struct mt7603_dev *dev = hw->priv; 2194bbd6d83SLorenzo Bianconi struct mt76_phy *mphy = &dev->mphy; 2204bbd6d83SLorenzo Bianconi int err; 2214bbd6d83SLorenzo Bianconi 2224bbd6d83SLorenzo Bianconi if (!cfg80211_chandef_valid(&mphy->chandef)) 2234bbd6d83SLorenzo Bianconi return -EINVAL; 2244bbd6d83SLorenzo Bianconi 2254bbd6d83SLorenzo Bianconi err = mt76_init_sar_power(hw, sar); 2264bbd6d83SLorenzo Bianconi if (err) 2274bbd6d83SLorenzo Bianconi return err; 2284bbd6d83SLorenzo Bianconi 2294bbd6d83SLorenzo Bianconi return mt7603_set_channel(hw, &mphy->chandef); 2304bbd6d83SLorenzo Bianconi } 2314bbd6d83SLorenzo Bianconi 232c8846e10SFelix Fietkau static int 233c8846e10SFelix Fietkau mt7603_config(struct ieee80211_hw *hw, u32 changed) 234c8846e10SFelix Fietkau { 235c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 236c8846e10SFelix Fietkau int ret = 0; 237c8846e10SFelix Fietkau 238c8846e10SFelix Fietkau if (changed & (IEEE80211_CONF_CHANGE_CHANNEL | 2394bbd6d83SLorenzo Bianconi IEEE80211_CONF_CHANGE_POWER)) 2404bbd6d83SLorenzo Bianconi ret = mt7603_set_channel(hw, &hw->conf.chandef); 241c8846e10SFelix Fietkau 242c8846e10SFelix Fietkau if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 243c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 244c8846e10SFelix Fietkau 245c8846e10SFelix Fietkau if (!(hw->conf.flags & IEEE80211_CONF_MONITOR)) 246c8846e10SFelix Fietkau dev->rxfilter |= MT_WF_RFCR_DROP_OTHER_UC; 247c8846e10SFelix Fietkau else 248c8846e10SFelix Fietkau dev->rxfilter &= ~MT_WF_RFCR_DROP_OTHER_UC; 249c8846e10SFelix Fietkau 250c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_RFCR, dev->rxfilter); 251c8846e10SFelix Fietkau 252c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 253c8846e10SFelix Fietkau } 254c8846e10SFelix Fietkau 255c8846e10SFelix Fietkau return ret; 256c8846e10SFelix Fietkau } 257c8846e10SFelix Fietkau 258c8846e10SFelix Fietkau static void 259c8846e10SFelix Fietkau mt7603_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, 260c8846e10SFelix Fietkau unsigned int *total_flags, u64 multicast) 261c8846e10SFelix Fietkau { 262c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 263c8846e10SFelix Fietkau u32 flags = 0; 264c8846e10SFelix Fietkau 265c8846e10SFelix Fietkau #define MT76_FILTER(_flag, _hw) do { \ 266c8846e10SFelix Fietkau flags |= *total_flags & FIF_##_flag; \ 267c8846e10SFelix Fietkau dev->rxfilter &= ~(_hw); \ 268c8846e10SFelix Fietkau dev->rxfilter |= !(flags & FIF_##_flag) * (_hw); \ 269c8846e10SFelix Fietkau } while (0) 270c8846e10SFelix Fietkau 271c8846e10SFelix Fietkau dev->rxfilter &= ~(MT_WF_RFCR_DROP_OTHER_BSS | 272c8846e10SFelix Fietkau MT_WF_RFCR_DROP_OTHER_BEACON | 273c8846e10SFelix Fietkau MT_WF_RFCR_DROP_FRAME_REPORT | 274c8846e10SFelix Fietkau MT_WF_RFCR_DROP_PROBEREQ | 275c8846e10SFelix Fietkau MT_WF_RFCR_DROP_MCAST_FILTERED | 276c8846e10SFelix Fietkau MT_WF_RFCR_DROP_MCAST | 277c8846e10SFelix Fietkau MT_WF_RFCR_DROP_BCAST | 278c8846e10SFelix Fietkau MT_WF_RFCR_DROP_DUPLICATE | 279c8846e10SFelix Fietkau MT_WF_RFCR_DROP_A2_BSSID | 280c8846e10SFelix Fietkau MT_WF_RFCR_DROP_UNWANTED_CTL | 281c8846e10SFelix Fietkau MT_WF_RFCR_DROP_STBC_MULTI); 282c8846e10SFelix Fietkau 283c8846e10SFelix Fietkau MT76_FILTER(OTHER_BSS, MT_WF_RFCR_DROP_OTHER_TIM | 284c8846e10SFelix Fietkau MT_WF_RFCR_DROP_A3_MAC | 285c8846e10SFelix Fietkau MT_WF_RFCR_DROP_A3_BSSID); 286c8846e10SFelix Fietkau 287c8846e10SFelix Fietkau MT76_FILTER(FCSFAIL, MT_WF_RFCR_DROP_FCSFAIL); 288c8846e10SFelix Fietkau 289c8846e10SFelix Fietkau MT76_FILTER(CONTROL, MT_WF_RFCR_DROP_CTS | 290c8846e10SFelix Fietkau MT_WF_RFCR_DROP_RTS | 291c8846e10SFelix Fietkau MT_WF_RFCR_DROP_CTL_RSV | 292c8846e10SFelix Fietkau MT_WF_RFCR_DROP_NDPA); 293c8846e10SFelix Fietkau 294c8846e10SFelix Fietkau *total_flags = flags; 295c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_RFCR, dev->rxfilter); 296c8846e10SFelix Fietkau } 297c8846e10SFelix Fietkau 298c8846e10SFelix Fietkau static void 299c8846e10SFelix Fietkau mt7603_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 3007b7090b4SJohannes Berg struct ieee80211_bss_conf *info, u64 changed) 301c8846e10SFelix Fietkau { 302c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 303c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 304c8846e10SFelix Fietkau 305c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 306c8846e10SFelix Fietkau 307c8846e10SFelix Fietkau if (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BSSID)) { 308f276e20bSJohannes Berg if (vif->cfg.assoc || vif->cfg.ibss_joined) { 309c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID0(mvif->idx), 310c8846e10SFelix Fietkau get_unaligned_le32(info->bssid)); 311c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID1(mvif->idx), 312c8846e10SFelix Fietkau (get_unaligned_le16(info->bssid + 4) | 313c8846e10SFelix Fietkau MT_BSSID1_VALID)); 314c8846e10SFelix Fietkau } else { 315c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID0(mvif->idx), 0); 316c8846e10SFelix Fietkau mt76_wr(dev, MT_BSSID1(mvif->idx), 0); 317c8846e10SFelix Fietkau } 318c8846e10SFelix Fietkau } 319c8846e10SFelix Fietkau 320c8846e10SFelix Fietkau if (changed & BSS_CHANGED_ERP_SLOT) { 321c8846e10SFelix Fietkau int slottime = info->use_short_slot ? 9 : 20; 322c8846e10SFelix Fietkau 323c8846e10SFelix Fietkau if (slottime != dev->slottime) { 324c8846e10SFelix Fietkau dev->slottime = slottime; 325c8846e10SFelix Fietkau mt7603_mac_set_timing(dev); 326c8846e10SFelix Fietkau } 327c8846e10SFelix Fietkau } 328c8846e10SFelix Fietkau 329c8846e10SFelix Fietkau if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON_INT)) { 330c8846e10SFelix Fietkau int beacon_int = !!info->enable_beacon * info->beacon_int; 331c8846e10SFelix Fietkau 332dc6057f4SLorenzo Bianconi tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 333c8846e10SFelix Fietkau mt7603_beacon_set_timer(dev, mvif->idx, beacon_int); 334dc6057f4SLorenzo Bianconi tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 335c8846e10SFelix Fietkau } 336c8846e10SFelix Fietkau 337c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 338c8846e10SFelix Fietkau } 339c8846e10SFelix Fietkau 340c8846e10SFelix Fietkau int 341c8846e10SFelix Fietkau mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 342c8846e10SFelix Fietkau struct ieee80211_sta *sta) 343c8846e10SFelix Fietkau { 344c8846e10SFelix Fietkau struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 345c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 346c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 347c8846e10SFelix Fietkau int idx; 348c8846e10SFelix Fietkau int ret = 0; 349c8846e10SFelix Fietkau 350c8846e10SFelix Fietkau idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7603_WTBL_STA - 1); 351c8846e10SFelix Fietkau if (idx < 0) 352c8846e10SFelix Fietkau return -ENOSPC; 353c8846e10SFelix Fietkau 354ea565833SFelix Fietkau INIT_LIST_HEAD(&msta->poll_list); 355c8846e10SFelix Fietkau __skb_queue_head_init(&msta->psq); 356c8846e10SFelix Fietkau msta->ps = ~0; 357c8846e10SFelix Fietkau msta->smps = ~0; 358c8846e10SFelix Fietkau msta->wcid.sta = 1; 359c8846e10SFelix Fietkau msta->wcid.idx = idx; 360c8846e10SFelix Fietkau mt7603_wtbl_init(dev, idx, mvif->idx, sta->addr); 361c8846e10SFelix Fietkau mt7603_wtbl_set_ps(dev, msta, false); 362c8846e10SFelix Fietkau 363c8846e10SFelix Fietkau if (vif->type == NL80211_IFTYPE_AP) 364c8846e10SFelix Fietkau set_bit(MT_WCID_FLAG_CHECK_PS, &msta->wcid.flags); 365c8846e10SFelix Fietkau 366c8846e10SFelix Fietkau return ret; 367c8846e10SFelix Fietkau } 368c8846e10SFelix Fietkau 369c8846e10SFelix Fietkau void 370c8846e10SFelix Fietkau mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif, 371c8846e10SFelix Fietkau struct ieee80211_sta *sta) 372c8846e10SFelix Fietkau { 373c8846e10SFelix Fietkau struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 374c8846e10SFelix Fietkau 375c8846e10SFelix Fietkau mt7603_wtbl_update_cap(dev, sta); 376c8846e10SFelix Fietkau } 377c8846e10SFelix Fietkau 378c8846e10SFelix Fietkau void 379c8846e10SFelix Fietkau mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 380c8846e10SFelix Fietkau struct ieee80211_sta *sta) 381c8846e10SFelix Fietkau { 382c8846e10SFelix Fietkau struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 383c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 384c8846e10SFelix Fietkau struct mt76_wcid *wcid = (struct mt76_wcid *)sta->drv_priv; 385c8846e10SFelix Fietkau 386c8846e10SFelix Fietkau spin_lock_bh(&dev->ps_lock); 387c8846e10SFelix Fietkau __skb_queue_purge(&msta->psq); 388c8846e10SFelix Fietkau mt7603_filter_tx(dev, wcid->idx, true); 389c8846e10SFelix Fietkau spin_unlock_bh(&dev->ps_lock); 390c8846e10SFelix Fietkau 391ea565833SFelix Fietkau spin_lock_bh(&dev->sta_poll_lock); 392ea565833SFelix Fietkau if (!list_empty(&msta->poll_list)) 393ea565833SFelix Fietkau list_del_init(&msta->poll_list); 394ea565833SFelix Fietkau spin_unlock_bh(&dev->sta_poll_lock); 395ea565833SFelix Fietkau 396c8846e10SFelix Fietkau mt7603_wtbl_clear(dev, wcid->idx); 397c8846e10SFelix Fietkau } 398c8846e10SFelix Fietkau 399c8846e10SFelix Fietkau static void 400c8846e10SFelix Fietkau mt7603_ps_tx_list(struct mt7603_dev *dev, struct sk_buff_head *list) 401c8846e10SFelix Fietkau { 402c8846e10SFelix Fietkau struct sk_buff *skb; 403c8846e10SFelix Fietkau 404d95093a1SLorenzo Bianconi while ((skb = __skb_dequeue(list)) != NULL) { 405d95093a1SLorenzo Bianconi int qid = skb_get_queue_mapping(skb); 406d95093a1SLorenzo Bianconi 40791990519SLorenzo Bianconi mt76_tx_queue_skb_raw(dev, dev->mphy.q_tx[qid], skb, 0); 408d95093a1SLorenzo Bianconi } 409c8846e10SFelix Fietkau } 410c8846e10SFelix Fietkau 411c8846e10SFelix Fietkau void 412c8846e10SFelix Fietkau mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps) 413c8846e10SFelix Fietkau { 414c8846e10SFelix Fietkau struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 415c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 416c8846e10SFelix Fietkau struct sk_buff_head list; 417c8846e10SFelix Fietkau 41891990519SLorenzo Bianconi mt76_stop_tx_queues(&dev->mphy, sta, true); 419c8846e10SFelix Fietkau mt7603_wtbl_set_ps(dev, msta, ps); 420c8846e10SFelix Fietkau if (ps) 421c8846e10SFelix Fietkau return; 422c8846e10SFelix Fietkau 423c8846e10SFelix Fietkau __skb_queue_head_init(&list); 424c8846e10SFelix Fietkau 425c8846e10SFelix Fietkau spin_lock_bh(&dev->ps_lock); 426c8846e10SFelix Fietkau skb_queue_splice_tail_init(&msta->psq, &list); 427c8846e10SFelix Fietkau spin_unlock_bh(&dev->ps_lock); 428c8846e10SFelix Fietkau 429c8846e10SFelix Fietkau mt7603_ps_tx_list(dev, &list); 430c8846e10SFelix Fietkau } 431c8846e10SFelix Fietkau 432c8846e10SFelix Fietkau static void 433b126c889SFelix Fietkau mt7603_ps_set_more_data(struct sk_buff *skb) 434b126c889SFelix Fietkau { 435b126c889SFelix Fietkau struct ieee80211_hdr *hdr; 436b126c889SFelix Fietkau 437b126c889SFelix Fietkau hdr = (struct ieee80211_hdr *)&skb->data[MT_TXD_SIZE]; 438b126c889SFelix Fietkau hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); 439b126c889SFelix Fietkau } 440b126c889SFelix Fietkau 441b126c889SFelix Fietkau static void 442c8846e10SFelix Fietkau mt7603_release_buffered_frames(struct ieee80211_hw *hw, 443c8846e10SFelix Fietkau struct ieee80211_sta *sta, 444c8846e10SFelix Fietkau u16 tids, int nframes, 445c8846e10SFelix Fietkau enum ieee80211_frame_release_type reason, 446c8846e10SFelix Fietkau bool more_data) 447c8846e10SFelix Fietkau { 448c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 449c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 450c8846e10SFelix Fietkau struct sk_buff_head list; 451c8846e10SFelix Fietkau struct sk_buff *skb, *tmp; 452c8846e10SFelix Fietkau 453c8846e10SFelix Fietkau __skb_queue_head_init(&list); 454c8846e10SFelix Fietkau 455f25e813bSFelix Fietkau mt7603_wtbl_set_ps(dev, msta, false); 456f25e813bSFelix Fietkau 457c8846e10SFelix Fietkau spin_lock_bh(&dev->ps_lock); 458c8846e10SFelix Fietkau skb_queue_walk_safe(&msta->psq, skb, tmp) { 459c8846e10SFelix Fietkau if (!nframes) 460c8846e10SFelix Fietkau break; 461c8846e10SFelix Fietkau 462c8846e10SFelix Fietkau if (!(tids & BIT(skb->priority))) 463c8846e10SFelix Fietkau continue; 464c8846e10SFelix Fietkau 465c8846e10SFelix Fietkau skb_set_queue_mapping(skb, MT_TXQ_PSD); 466c8846e10SFelix Fietkau __skb_unlink(skb, &msta->psq); 467b126c889SFelix Fietkau mt7603_ps_set_more_data(skb); 468c8846e10SFelix Fietkau __skb_queue_tail(&list, skb); 469c8846e10SFelix Fietkau nframes--; 470c8846e10SFelix Fietkau } 471c8846e10SFelix Fietkau spin_unlock_bh(&dev->ps_lock); 472c8846e10SFelix Fietkau 473b7001f46SFelix Fietkau if (!skb_queue_empty(&list)) 474b7001f46SFelix Fietkau ieee80211_sta_eosp(sta); 475b7001f46SFelix Fietkau 476c8846e10SFelix Fietkau mt7603_ps_tx_list(dev, &list); 477c8846e10SFelix Fietkau 478c8846e10SFelix Fietkau if (nframes) 479c8846e10SFelix Fietkau mt76_release_buffered_frames(hw, sta, tids, nframes, reason, 480c8846e10SFelix Fietkau more_data); 481c8846e10SFelix Fietkau } 482c8846e10SFelix Fietkau 483c8846e10SFelix Fietkau static int 484c8846e10SFelix Fietkau mt7603_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 485c8846e10SFelix Fietkau struct ieee80211_vif *vif, struct ieee80211_sta *sta, 486c8846e10SFelix Fietkau struct ieee80211_key_conf *key) 487c8846e10SFelix Fietkau { 488c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 489c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 490c8846e10SFelix Fietkau struct mt7603_sta *msta = sta ? (struct mt7603_sta *)sta->drv_priv : 491c8846e10SFelix Fietkau &mvif->sta; 492c8846e10SFelix Fietkau struct mt76_wcid *wcid = &msta->wcid; 493c8846e10SFelix Fietkau int idx = key->keyidx; 494c8846e10SFelix Fietkau 495c8846e10SFelix Fietkau /* fall back to sw encryption for unsupported ciphers */ 496c8846e10SFelix Fietkau switch (key->cipher) { 497c8846e10SFelix Fietkau case WLAN_CIPHER_SUITE_TKIP: 498c8846e10SFelix Fietkau case WLAN_CIPHER_SUITE_CCMP: 499c8846e10SFelix Fietkau break; 500c8846e10SFelix Fietkau default: 501c8846e10SFelix Fietkau return -EOPNOTSUPP; 502c8846e10SFelix Fietkau } 503c8846e10SFelix Fietkau 504c8846e10SFelix Fietkau /* 505c8846e10SFelix Fietkau * The hardware does not support per-STA RX GTK, fall back 506c8846e10SFelix Fietkau * to software mode for these. 507c8846e10SFelix Fietkau */ 508c8846e10SFelix Fietkau if ((vif->type == NL80211_IFTYPE_ADHOC || 509c8846e10SFelix Fietkau vif->type == NL80211_IFTYPE_MESH_POINT) && 510c8846e10SFelix Fietkau (key->cipher == WLAN_CIPHER_SUITE_TKIP || 511c8846e10SFelix Fietkau key->cipher == WLAN_CIPHER_SUITE_CCMP) && 512c8846e10SFelix Fietkau !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 513c8846e10SFelix Fietkau return -EOPNOTSUPP; 514c8846e10SFelix Fietkau 515*e6db67faSFelix Fietkau if (cmd != SET_KEY) { 516c8846e10SFelix Fietkau if (idx == wcid->hw_key_idx) 517c8846e10SFelix Fietkau wcid->hw_key_idx = -1; 518c8846e10SFelix Fietkau 519*e6db67faSFelix Fietkau return 0; 520c8846e10SFelix Fietkau } 521*e6db67faSFelix Fietkau 522*e6db67faSFelix Fietkau key->hw_key_idx = wcid->idx; 523*e6db67faSFelix Fietkau wcid->hw_key_idx = idx; 524c8846e10SFelix Fietkau mt76_wcid_key_setup(&dev->mt76, wcid, key); 525c8846e10SFelix Fietkau 526c8846e10SFelix Fietkau return mt7603_wtbl_set_key(dev, wcid->idx, key); 527c8846e10SFelix Fietkau } 528c8846e10SFelix Fietkau 529c8846e10SFelix Fietkau static int 530b3e2130bSJohannes Berg mt7603_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 531b3e2130bSJohannes Berg unsigned int link_id, u16 queue, 532c8846e10SFelix Fietkau const struct ieee80211_tx_queue_params *params) 533c8846e10SFelix Fietkau { 534c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 535c8846e10SFelix Fietkau u16 cw_min = (1 << 5) - 1; 536c8846e10SFelix Fietkau u16 cw_max = (1 << 10) - 1; 537c8846e10SFelix Fietkau u32 val; 538c8846e10SFelix Fietkau 53991990519SLorenzo Bianconi queue = dev->mphy.q_tx[queue]->hw_idx; 540c8846e10SFelix Fietkau 541c8846e10SFelix Fietkau if (params->cw_min) 542c8846e10SFelix Fietkau cw_min = params->cw_min; 543c8846e10SFelix Fietkau if (params->cw_max) 544c8846e10SFelix Fietkau cw_max = params->cw_max; 545c8846e10SFelix Fietkau 546c8846e10SFelix Fietkau mutex_lock(&dev->mt76.mutex); 547c8846e10SFelix Fietkau mt7603_mac_stop(dev); 548c8846e10SFelix Fietkau 549c8846e10SFelix Fietkau val = mt76_rr(dev, MT_WMM_TXOP(queue)); 550c8846e10SFelix Fietkau val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(queue)); 551c8846e10SFelix Fietkau val |= params->txop << MT_WMM_TXOP_SHIFT(queue); 552c8846e10SFelix Fietkau mt76_wr(dev, MT_WMM_TXOP(queue), val); 553c8846e10SFelix Fietkau 554c8846e10SFelix Fietkau val = mt76_rr(dev, MT_WMM_AIFSN); 555c8846e10SFelix Fietkau val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(queue)); 556c8846e10SFelix Fietkau val |= params->aifs << MT_WMM_AIFSN_SHIFT(queue); 557c8846e10SFelix Fietkau mt76_wr(dev, MT_WMM_AIFSN, val); 558c8846e10SFelix Fietkau 559c8846e10SFelix Fietkau val = mt76_rr(dev, MT_WMM_CWMIN); 560c8846e10SFelix Fietkau val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(queue)); 561c8846e10SFelix Fietkau val |= cw_min << MT_WMM_CWMIN_SHIFT(queue); 562c8846e10SFelix Fietkau mt76_wr(dev, MT_WMM_CWMIN, val); 563c8846e10SFelix Fietkau 564c8846e10SFelix Fietkau val = mt76_rr(dev, MT_WMM_CWMAX(queue)); 565c8846e10SFelix Fietkau val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(queue)); 566c8846e10SFelix Fietkau val |= cw_max << MT_WMM_CWMAX_SHIFT(queue); 567c8846e10SFelix Fietkau mt76_wr(dev, MT_WMM_CWMAX(queue), val); 568c8846e10SFelix Fietkau 569c8846e10SFelix Fietkau mt7603_mac_start(dev); 570c8846e10SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 571c8846e10SFelix Fietkau 572c8846e10SFelix Fietkau return 0; 573c8846e10SFelix Fietkau } 574c8846e10SFelix Fietkau 575c8846e10SFelix Fietkau static void 576c8846e10SFelix Fietkau mt7603_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 577c8846e10SFelix Fietkau u32 queues, bool drop) 578c8846e10SFelix Fietkau { 579c8846e10SFelix Fietkau } 580c8846e10SFelix Fietkau 581c8846e10SFelix Fietkau static int 582c8846e10SFelix Fietkau mt7603_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 583c8846e10SFelix Fietkau struct ieee80211_ampdu_params *params) 584c8846e10SFelix Fietkau { 585c8846e10SFelix Fietkau enum ieee80211_ampdu_mlme_action action = params->action; 586c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 587c8846e10SFelix Fietkau struct ieee80211_sta *sta = params->sta; 588c8846e10SFelix Fietkau struct ieee80211_txq *txq = sta->txq[params->tid]; 589c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 590c8846e10SFelix Fietkau u16 tid = params->tid; 591f8f3b20aSStanislaw Gruszka u16 ssn = params->ssn; 592c8846e10SFelix Fietkau u8 ba_size = params->buf_size; 593c8846e10SFelix Fietkau struct mt76_txq *mtxq; 59405d6c8cfSMarkus Theil int ret = 0; 595c8846e10SFelix Fietkau 596c8846e10SFelix Fietkau if (!txq) 597c8846e10SFelix Fietkau return -EINVAL; 598c8846e10SFelix Fietkau 599c8846e10SFelix Fietkau mtxq = (struct mt76_txq *)txq->drv_priv; 600c8846e10SFelix Fietkau 6011a817fa7SFelix Fietkau mutex_lock(&dev->mt76.mutex); 602c8846e10SFelix Fietkau switch (action) { 603c8846e10SFelix Fietkau case IEEE80211_AMPDU_RX_START: 604f8f3b20aSStanislaw Gruszka mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid, ssn, 605c8846e10SFelix Fietkau params->buf_size); 606c8846e10SFelix Fietkau mt7603_mac_rx_ba_reset(dev, sta->addr, tid); 607c8846e10SFelix Fietkau break; 608c8846e10SFelix Fietkau case IEEE80211_AMPDU_RX_STOP: 609c8846e10SFelix Fietkau mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid); 610c8846e10SFelix Fietkau break; 611c8846e10SFelix Fietkau case IEEE80211_AMPDU_TX_OPERATIONAL: 612c8846e10SFelix Fietkau mtxq->aggr = true; 613c8846e10SFelix Fietkau mtxq->send_bar = false; 614aa3cb24bSFelix Fietkau mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, ba_size); 615c8846e10SFelix Fietkau break; 616c8846e10SFelix Fietkau case IEEE80211_AMPDU_TX_STOP_FLUSH: 617c8846e10SFelix Fietkau case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 618c8846e10SFelix Fietkau mtxq->aggr = false; 619aa3cb24bSFelix Fietkau mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, -1); 620c8846e10SFelix Fietkau break; 621c8846e10SFelix Fietkau case IEEE80211_AMPDU_TX_START: 622f8f3b20aSStanislaw Gruszka mtxq->agg_ssn = IEEE80211_SN_TO_SEQ(ssn); 62305d6c8cfSMarkus Theil ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 62405d6c8cfSMarkus Theil break; 625c8846e10SFelix Fietkau case IEEE80211_AMPDU_TX_STOP_CONT: 626c8846e10SFelix Fietkau mtxq->aggr = false; 627aa3cb24bSFelix Fietkau mt7603_mac_tx_ba_reset(dev, msta->wcid.idx, tid, -1); 628c8846e10SFelix Fietkau ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 629c8846e10SFelix Fietkau break; 630c8846e10SFelix Fietkau } 6311a817fa7SFelix Fietkau mutex_unlock(&dev->mt76.mutex); 632c8846e10SFelix Fietkau 63305d6c8cfSMarkus Theil return ret; 634c8846e10SFelix Fietkau } 635c8846e10SFelix Fietkau 636c8846e10SFelix Fietkau static void 637c8846e10SFelix Fietkau mt7603_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 638c8846e10SFelix Fietkau struct ieee80211_sta *sta) 639c8846e10SFelix Fietkau { 640c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 641c8846e10SFelix Fietkau struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 642c8846e10SFelix Fietkau struct ieee80211_sta_rates *sta_rates = rcu_dereference(sta->rates); 643c8846e10SFelix Fietkau int i; 644c8846e10SFelix Fietkau 645fc8e2c70SLorenzo Bianconi if (!sta_rates) 646fc8e2c70SLorenzo Bianconi return; 647fc8e2c70SLorenzo Bianconi 648c8846e10SFelix Fietkau spin_lock_bh(&dev->mt76.lock); 649c8846e10SFelix Fietkau for (i = 0; i < ARRAY_SIZE(msta->rates); i++) { 650c8846e10SFelix Fietkau msta->rates[i].idx = sta_rates->rate[i].idx; 651c8846e10SFelix Fietkau msta->rates[i].count = sta_rates->rate[i].count; 652c8846e10SFelix Fietkau msta->rates[i].flags = sta_rates->rate[i].flags; 653c8846e10SFelix Fietkau 654c8846e10SFelix Fietkau if (msta->rates[i].idx < 0 || !msta->rates[i].count) 655c8846e10SFelix Fietkau break; 656c8846e10SFelix Fietkau } 657c8846e10SFelix Fietkau msta->n_rates = i; 658c8846e10SFelix Fietkau mt7603_wtbl_set_rates(dev, msta, NULL, msta->rates); 659c8846e10SFelix Fietkau msta->rate_probe = false; 660c8846e10SFelix Fietkau mt7603_wtbl_set_smps(dev, msta, 661261ce887SBenjamin Berg sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC); 662c8846e10SFelix Fietkau spin_unlock_bh(&dev->mt76.lock); 663c8846e10SFelix Fietkau } 664c8846e10SFelix Fietkau 665c8846e10SFelix Fietkau static void 666c8846e10SFelix Fietkau mt7603_set_coverage_class(struct ieee80211_hw *hw, s16 coverage_class) 667c8846e10SFelix Fietkau { 668c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 669c8846e10SFelix Fietkau 6702cb002e3SLorenzo Bianconi mutex_lock(&dev->mt76.mutex); 6716a792b1aSLorenzo Bianconi dev->coverage_class = max_t(s16, coverage_class, 0); 672c8846e10SFelix Fietkau mt7603_mac_set_timing(dev); 6732cb002e3SLorenzo Bianconi mutex_unlock(&dev->mt76.mutex); 674c8846e10SFelix Fietkau } 675c8846e10SFelix Fietkau 6767f17b86aSRyder Lee static void mt7603_tx(struct ieee80211_hw *hw, 6777f17b86aSRyder Lee struct ieee80211_tx_control *control, 678c8846e10SFelix Fietkau struct sk_buff *skb) 679c8846e10SFelix Fietkau { 680c8846e10SFelix Fietkau struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 681c8846e10SFelix Fietkau struct ieee80211_vif *vif = info->control.vif; 682c8846e10SFelix Fietkau struct mt7603_dev *dev = hw->priv; 683c8846e10SFelix Fietkau struct mt76_wcid *wcid = &dev->global_sta.wcid; 684c8846e10SFelix Fietkau 685c8846e10SFelix Fietkau if (control->sta) { 686c8846e10SFelix Fietkau struct mt7603_sta *msta; 687c8846e10SFelix Fietkau 688c8846e10SFelix Fietkau msta = (struct mt7603_sta *)control->sta->drv_priv; 689c8846e10SFelix Fietkau wcid = &msta->wcid; 690c8846e10SFelix Fietkau } else if (vif) { 691c8846e10SFelix Fietkau struct mt7603_vif *mvif; 692c8846e10SFelix Fietkau 693c8846e10SFelix Fietkau mvif = (struct mt7603_vif *)vif->drv_priv; 694c8846e10SFelix Fietkau wcid = &mvif->sta.wcid; 695c8846e10SFelix Fietkau } 696c8846e10SFelix Fietkau 6979fba6d07SFelix Fietkau mt76_tx(&dev->mphy, control->sta, wcid, skb); 698c8846e10SFelix Fietkau } 699c8846e10SFelix Fietkau 700c8846e10SFelix Fietkau const struct ieee80211_ops mt7603_ops = { 701c8846e10SFelix Fietkau .tx = mt7603_tx, 702c8846e10SFelix Fietkau .start = mt7603_start, 703c8846e10SFelix Fietkau .stop = mt7603_stop, 704c8846e10SFelix Fietkau .add_interface = mt7603_add_interface, 705c8846e10SFelix Fietkau .remove_interface = mt7603_remove_interface, 706c8846e10SFelix Fietkau .config = mt7603_config, 707c8846e10SFelix Fietkau .configure_filter = mt7603_configure_filter, 708c8846e10SFelix Fietkau .bss_info_changed = mt7603_bss_info_changed, 709c8846e10SFelix Fietkau .sta_state = mt76_sta_state, 71043ba1922SFelix Fietkau .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove, 711c8846e10SFelix Fietkau .set_key = mt7603_set_key, 712c8846e10SFelix Fietkau .conf_tx = mt7603_conf_tx, 7138b8ab5c2SLorenzo Bianconi .sw_scan_start = mt76_sw_scan, 7148b8ab5c2SLorenzo Bianconi .sw_scan_complete = mt76_sw_scan_complete, 715c8846e10SFelix Fietkau .flush = mt7603_flush, 716c8846e10SFelix Fietkau .ampdu_action = mt7603_ampdu_action, 717c8846e10SFelix Fietkau .get_txpower = mt76_get_txpower, 718c8846e10SFelix Fietkau .wake_tx_queue = mt76_wake_tx_queue, 719c8846e10SFelix Fietkau .sta_rate_tbl_update = mt7603_sta_rate_tbl_update, 720c8846e10SFelix Fietkau .release_buffered_frames = mt7603_release_buffered_frames, 721c8846e10SFelix Fietkau .set_coverage_class = mt7603_set_coverage_class, 72287d53103SStanislaw Gruszka .set_tim = mt76_set_tim, 723c8846e10SFelix Fietkau .get_survey = mt76_get_survey, 724e49c76d4SLorenzo Bianconi .get_antenna = mt76_get_antenna, 7254bbd6d83SLorenzo Bianconi .set_sar_specs = mt7603_set_sar_specs, 726c8846e10SFelix Fietkau }; 727c8846e10SFelix Fietkau 728c8846e10SFelix Fietkau MODULE_LICENSE("Dual BSD/GPL"); 729c8846e10SFelix Fietkau 730c8846e10SFelix Fietkau static int __init mt7603_init(void) 731c8846e10SFelix Fietkau { 732c8846e10SFelix Fietkau int ret; 733c8846e10SFelix Fietkau 734c8846e10SFelix Fietkau ret = platform_driver_register(&mt76_wmac_driver); 735c8846e10SFelix Fietkau if (ret) 736c8846e10SFelix Fietkau return ret; 737c8846e10SFelix Fietkau 738c8846e10SFelix Fietkau #ifdef CONFIG_PCI 739c8846e10SFelix Fietkau ret = pci_register_driver(&mt7603_pci_driver); 740c8846e10SFelix Fietkau if (ret) 741c8846e10SFelix Fietkau platform_driver_unregister(&mt76_wmac_driver); 742c8846e10SFelix Fietkau #endif 743c8846e10SFelix Fietkau return ret; 744c8846e10SFelix Fietkau } 745c8846e10SFelix Fietkau 746c8846e10SFelix Fietkau static void __exit mt7603_exit(void) 747c8846e10SFelix Fietkau { 748c8846e10SFelix Fietkau #ifdef CONFIG_PCI 749c8846e10SFelix Fietkau pci_unregister_driver(&mt7603_pci_driver); 750c8846e10SFelix Fietkau #endif 751c8846e10SFelix Fietkau platform_driver_unregister(&mt76_wmac_driver); 752c8846e10SFelix Fietkau } 753c8846e10SFelix Fietkau 754c8846e10SFelix Fietkau module_init(mt7603_init); 755c8846e10SFelix Fietkau module_exit(mt7603_exit); 756