1 // SPDX-License-Identifier: ISC 2 3 #include <linux/etherdevice.h> 4 #include <linux/timekeeping.h> 5 #include "mt7603.h" 6 #include "mac.h" 7 #include "../trace.h" 8 9 #define MT_PSE_PAGE_SIZE 128 10 11 static u32 12 mt7603_ac_queue_mask0(u32 mask) 13 { 14 u32 ret = 0; 15 16 ret |= GENMASK(3, 0) * !!(mask & BIT(0)); 17 ret |= GENMASK(8, 5) * !!(mask & BIT(1)); 18 ret |= GENMASK(13, 10) * !!(mask & BIT(2)); 19 ret |= GENMASK(19, 16) * !!(mask & BIT(3)); 20 return ret; 21 } 22 23 static void 24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) 25 { 26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); 27 } 28 29 static void 30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) 31 { 32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); 33 } 34 35 void mt7603_mac_reset_counters(struct mt7603_dev *dev) 36 { 37 int i; 38 39 for (i = 0; i < 2; i++) 40 mt76_rr(dev, MT_TX_AGG_CNT(i)); 41 42 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats)); 43 } 44 45 void mt7603_mac_set_timing(struct mt7603_dev *dev) 46 { 47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 48 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 49 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 50 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); 51 int offset = 3 * dev->coverage_class; 52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 53 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; 55 int sifs; 56 u32 val; 57 58 if (is_5ghz) 59 sifs = 16; 60 else 61 sifs = 10; 62 63 mt76_set(dev, MT_ARB_SCR, 64 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 65 udelay(1); 66 67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); 68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); 69 mt76_wr(dev, MT_IFS, 70 FIELD_PREP(MT_IFS_EIFS, 360) | 71 FIELD_PREP(MT_IFS_RIFS, 2) | 72 FIELD_PREP(MT_IFS_SIFS, sifs) | 73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); 74 75 if (dev->slottime < 20 || is_5ghz) 76 val = MT7603_CFEND_RATE_DEFAULT; 77 else 78 val = MT7603_CFEND_RATE_11B; 79 80 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); 81 82 mt76_clear(dev, MT_ARB_SCR, 83 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 84 } 85 86 static void 87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) 88 { 89 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 90 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 91 92 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 93 } 94 95 static u32 96 mt7603_wtbl1_addr(int idx) 97 { 98 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 99 } 100 101 static u32 102 mt7603_wtbl2_addr(int idx) 103 { 104 /* Mapped to WTBL2 */ 105 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE; 106 } 107 108 static u32 109 mt7603_wtbl3_addr(int idx) 110 { 111 u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE); 112 113 return base + idx * MT_WTBL3_SIZE; 114 } 115 116 static u32 117 mt7603_wtbl4_addr(int idx) 118 { 119 u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE); 120 121 return base + idx * MT_WTBL4_SIZE; 122 } 123 124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, 125 const u8 *mac_addr) 126 { 127 const void *_mac = mac_addr; 128 u32 addr = mt7603_wtbl1_addr(idx); 129 u32 w0 = 0, w1 = 0; 130 int i; 131 132 if (_mac) { 133 w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI, 134 get_unaligned_le16(_mac + 4)); 135 w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO, 136 get_unaligned_le32(_mac)); 137 } 138 139 if (vif < 0) 140 vif = 0; 141 else 142 w0 |= MT_WTBL1_W0_RX_CHECK_A1; 143 w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif); 144 145 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 146 147 mt76_set(dev, addr + 0 * 4, w0); 148 mt76_set(dev, addr + 1 * 4, w1); 149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); 150 151 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 152 addr = mt7603_wtbl2_addr(idx); 153 for (i = 0; i < MT_WTBL2_SIZE; i += 4) 154 mt76_wr(dev, addr + i, 0); 155 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 156 mt76_start_tx_ac(dev, GENMASK(3, 0)); 157 158 addr = mt7603_wtbl3_addr(idx); 159 for (i = 0; i < MT_WTBL3_SIZE; i += 4) 160 mt76_wr(dev, addr + i, 0); 161 162 addr = mt7603_wtbl4_addr(idx); 163 for (i = 0; i < MT_WTBL4_SIZE; i += 4) 164 mt76_wr(dev, addr + i, 0); 165 166 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 167 } 168 169 static void 170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) 171 { 172 u32 addr = mt7603_wtbl1_addr(idx); 173 u32 val = mt76_rr(dev, addr + 3 * 4); 174 175 val &= ~MT_WTBL1_W3_SKIP_TX; 176 val |= enabled * MT_WTBL1_W3_SKIP_TX; 177 178 mt76_wr(dev, addr + 3 * 4, val); 179 } 180 181 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort) 182 { 183 int i, port, queue; 184 185 if (abort) { 186 port = 3; /* PSE */ 187 queue = 8; /* free queue */ 188 } else { 189 port = 0; /* HIF */ 190 queue = 1; /* MCU queue */ 191 } 192 193 mt7603_wtbl_set_skip_tx(dev, idx, true); 194 195 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | 196 FIELD_PREP(MT_TX_ABORT_WCID, idx)); 197 198 for (i = 0; i < 4; i++) { 199 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | 200 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) | 201 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) | 202 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) | 203 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue)); 204 205 mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 15000); 206 } 207 208 WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY); 209 210 mt76_wr(dev, MT_TX_ABORT, 0); 211 212 mt7603_wtbl_set_skip_tx(dev, idx, false); 213 } 214 215 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, 216 bool enabled) 217 { 218 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); 219 220 if (sta->smps == enabled) 221 return; 222 223 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled); 224 sta->smps = enabled; 225 } 226 227 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, 228 bool enabled) 229 { 230 int idx = sta->wcid.idx; 231 u32 addr; 232 233 spin_lock_bh(&dev->ps_lock); 234 235 if (sta->ps == enabled) 236 goto out; 237 238 mt76_wr(dev, MT_PSE_RTA, 239 FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) | 240 FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) | 241 FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) | 242 FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) | 243 MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY); 244 245 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 246 247 if (enabled) 248 mt7603_filter_tx(dev, idx, false); 249 250 addr = mt7603_wtbl1_addr(idx); 251 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 252 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE, 253 enabled * MT_WTBL1_W3_POWER_SAVE); 254 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 255 sta->ps = enabled; 256 257 out: 258 spin_unlock_bh(&dev->ps_lock); 259 } 260 261 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) 262 { 263 int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE; 264 int wtbl2_frame = idx / wtbl2_frame_size; 265 int wtbl2_entry = idx % wtbl2_frame_size; 266 267 int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE; 268 int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE; 269 int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size; 270 int wtbl3_entry = (idx % wtbl3_frame_size) * 2; 271 272 int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE; 273 int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE; 274 int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size; 275 int wtbl4_entry = idx % wtbl4_frame_size; 276 277 u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 278 int i; 279 280 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 281 282 mt76_wr(dev, addr + 0 * 4, 283 MT_WTBL1_W0_RX_CHECK_A1 | 284 MT_WTBL1_W0_RX_CHECK_A2 | 285 MT_WTBL1_W0_RX_VALID); 286 mt76_wr(dev, addr + 1 * 4, 0); 287 mt76_wr(dev, addr + 2 * 4, 0); 288 289 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 290 291 mt76_wr(dev, addr + 3 * 4, 292 FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) | 293 FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) | 294 FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) | 295 MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM); 296 mt76_wr(dev, addr + 4 * 4, 297 FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) | 298 FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) | 299 FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry)); 300 301 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 302 303 addr = mt7603_wtbl2_addr(idx); 304 305 /* Clear BA information */ 306 mt76_wr(dev, addr + (15 * 4), 0); 307 308 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 309 for (i = 2; i <= 4; i++) 310 mt76_wr(dev, addr + (i * 4), 0); 311 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 312 mt76_start_tx_ac(dev, GENMASK(3, 0)); 313 314 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR); 315 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR); 316 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 317 } 318 319 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta) 320 { 321 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 322 int idx = msta->wcid.idx; 323 u8 ampdu_density; 324 u32 addr; 325 u32 val; 326 327 addr = mt7603_wtbl1_addr(idx); 328 329 ampdu_density = sta->ht_cap.ampdu_density; 330 if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4) 331 ampdu_density = IEEE80211_HT_MPDU_DENSITY_4; 332 333 val = mt76_rr(dev, addr + 2 * 4); 334 val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL; 335 val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) | 336 FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) | 337 MT_WTBL1_W2_TXS_BAF_REPORT; 338 339 if (sta->ht_cap.cap) 340 val |= MT_WTBL1_W2_HT; 341 if (sta->vht_cap.cap) 342 val |= MT_WTBL1_W2_VHT; 343 344 mt76_wr(dev, addr + 2 * 4, val); 345 346 addr = mt7603_wtbl2_addr(idx); 347 val = mt76_rr(dev, addr + 9 * 4); 348 val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 349 MT_WTBL2_W9_SHORT_GI_80); 350 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 351 val |= MT_WTBL2_W9_SHORT_GI_20; 352 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 353 val |= MT_WTBL2_W9_SHORT_GI_40; 354 mt76_wr(dev, addr + 9 * 4, val); 355 } 356 357 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid) 358 { 359 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr)); 360 mt76_wr(dev, MT_BA_CONTROL_1, 361 (get_unaligned_le16(addr + 4) | 362 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) | 363 MT_BA_CONTROL_1_RESET)); 364 } 365 366 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, 367 int ba_size) 368 { 369 u32 addr = mt7603_wtbl2_addr(wcid); 370 u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 371 (MT_WTBL2_W15_BA_WIN_SIZE << 372 (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT)); 373 u32 tid_val; 374 int i; 375 376 if (ba_size < 0) { 377 /* disable */ 378 mt76_clear(dev, addr + (15 * 4), tid_mask); 379 return; 380 } 381 382 for (i = 7; i > 0; i--) { 383 if (ba_size >= MT_AGG_SIZE_LIMIT(i)) 384 break; 385 } 386 387 tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 388 i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT); 389 390 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val); 391 } 392 393 void mt7603_mac_sta_poll(struct mt7603_dev *dev) 394 { 395 static const u8 ac_to_tid[4] = { 396 [IEEE80211_AC_BE] = 0, 397 [IEEE80211_AC_BK] = 1, 398 [IEEE80211_AC_VI] = 4, 399 [IEEE80211_AC_VO] = 6 400 }; 401 struct ieee80211_sta *sta; 402 struct mt7603_sta *msta; 403 u32 total_airtime = 0; 404 u32 airtime[4]; 405 u32 addr; 406 int i; 407 408 rcu_read_lock(); 409 410 while (1) { 411 bool clear = false; 412 413 spin_lock_bh(&dev->sta_poll_lock); 414 if (list_empty(&dev->sta_poll_list)) { 415 spin_unlock_bh(&dev->sta_poll_lock); 416 break; 417 } 418 419 msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta, 420 poll_list); 421 list_del_init(&msta->poll_list); 422 spin_unlock_bh(&dev->sta_poll_lock); 423 424 addr = mt7603_wtbl4_addr(msta->wcid.idx); 425 for (i = 0; i < 4; i++) { 426 u32 airtime_last = msta->tx_airtime_ac[i]; 427 428 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); 429 airtime[i] = msta->tx_airtime_ac[i] - airtime_last; 430 airtime[i] *= 32; 431 total_airtime += airtime[i]; 432 433 if (msta->tx_airtime_ac[i] & BIT(22)) 434 clear = true; 435 } 436 437 if (clear) { 438 mt7603_wtbl_update(dev, msta->wcid.idx, 439 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 440 memset(msta->tx_airtime_ac, 0, 441 sizeof(msta->tx_airtime_ac)); 442 } 443 444 if (!msta->wcid.sta) 445 continue; 446 447 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 448 for (i = 0; i < 4; i++) { 449 struct mt76_queue *q = dev->mphy.q_tx[i]; 450 u8 qidx = q->hw_idx; 451 u8 tid = ac_to_tid[i]; 452 u32 txtime = airtime[qidx]; 453 454 if (!txtime) 455 continue; 456 457 ieee80211_sta_register_airtime(sta, tid, txtime, 0); 458 } 459 } 460 461 rcu_read_unlock(); 462 463 if (!total_airtime) 464 return; 465 466 spin_lock_bh(&dev->mt76.cc_lock); 467 dev->mphy.chan_state->cc_tx += total_airtime; 468 spin_unlock_bh(&dev->mt76.cc_lock); 469 } 470 471 static struct mt76_wcid * 472 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) 473 { 474 struct mt7603_sta *sta; 475 struct mt76_wcid *wcid; 476 477 if (idx >= MT7603_WTBL_SIZE) 478 return NULL; 479 480 wcid = rcu_dereference(dev->mt76.wcid[idx]); 481 if (unicast || !wcid) 482 return wcid; 483 484 if (!wcid->sta) 485 return NULL; 486 487 sta = container_of(wcid, struct mt7603_sta, wcid); 488 if (!sta->vif) 489 return NULL; 490 491 return &sta->vif->sta.wcid; 492 } 493 494 int 495 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb) 496 { 497 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 498 struct ieee80211_supported_band *sband; 499 struct ieee80211_hdr *hdr; 500 __le32 *rxd = (__le32 *)skb->data; 501 u32 rxd0 = le32_to_cpu(rxd[0]); 502 u32 rxd1 = le32_to_cpu(rxd[1]); 503 u32 rxd2 = le32_to_cpu(rxd[2]); 504 bool unicast = rxd1 & MT_RXD1_NORMAL_U2M; 505 bool insert_ccmp_hdr = false; 506 bool remove_pad; 507 int idx; 508 int i; 509 510 memset(status, 0, sizeof(*status)); 511 512 i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 513 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; 514 i >>= 1; 515 516 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 517 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); 518 519 status->band = sband->band; 520 if (i < sband->n_channels) 521 status->freq = sband->channels[i].center_freq; 522 523 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 524 status->flag |= RX_FLAG_FAILED_FCS_CRC; 525 526 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 527 status->flag |= RX_FLAG_MMIC_ERROR; 528 529 /* ICV error or CCMP/BIP/WPI MIC error */ 530 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR) 531 status->flag |= RX_FLAG_ONLY_MONITOR; 532 533 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 534 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 535 status->flag |= RX_FLAG_DECRYPTED; 536 status->flag |= RX_FLAG_IV_STRIPPED; 537 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 538 } 539 540 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 541 542 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 543 return -EINVAL; 544 545 if (!sband->channels) 546 return -EINVAL; 547 548 rxd += 4; 549 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 550 rxd += 4; 551 if ((u8 *)rxd - skb->data >= skb->len) 552 return -EINVAL; 553 } 554 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 555 u8 *data = (u8 *)rxd; 556 557 if (status->flag & RX_FLAG_DECRYPTED) { 558 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) { 559 case MT_CIPHER_AES_CCMP: 560 case MT_CIPHER_CCMP_CCX: 561 case MT_CIPHER_CCMP_256: 562 insert_ccmp_hdr = 563 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 564 fallthrough; 565 case MT_CIPHER_TKIP: 566 case MT_CIPHER_TKIP_NO_MIC: 567 case MT_CIPHER_GCMP: 568 case MT_CIPHER_GCMP_256: 569 status->iv[0] = data[5]; 570 status->iv[1] = data[4]; 571 status->iv[2] = data[3]; 572 status->iv[3] = data[2]; 573 status->iv[4] = data[1]; 574 status->iv[5] = data[0]; 575 break; 576 default: 577 break; 578 } 579 } 580 581 rxd += 4; 582 if ((u8 *)rxd - skb->data >= skb->len) 583 return -EINVAL; 584 } 585 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 586 status->timestamp = le32_to_cpu(rxd[0]); 587 status->flag |= RX_FLAG_MACTIME_START; 588 589 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB | 590 MT_RXD2_NORMAL_NON_AMPDU))) { 591 status->flag |= RX_FLAG_AMPDU_DETAILS; 592 593 /* all subframes of an A-MPDU have the same timestamp */ 594 if (dev->rx_ampdu_ts != status->timestamp) { 595 if (!++dev->ampdu_ref) 596 dev->ampdu_ref++; 597 } 598 dev->rx_ampdu_ts = status->timestamp; 599 600 status->ampdu_ref = dev->ampdu_ref; 601 } 602 603 rxd += 2; 604 if ((u8 *)rxd - skb->data >= skb->len) 605 return -EINVAL; 606 } 607 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 608 u32 rxdg0 = le32_to_cpu(rxd[0]); 609 u32 rxdg3 = le32_to_cpu(rxd[3]); 610 bool cck = false; 611 612 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 613 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 614 case MT_PHY_TYPE_CCK: 615 cck = true; 616 fallthrough; 617 case MT_PHY_TYPE_OFDM: 618 i = mt76_get_rate(&dev->mt76, sband, i, cck); 619 break; 620 case MT_PHY_TYPE_HT_GF: 621 case MT_PHY_TYPE_HT: 622 status->encoding = RX_ENC_HT; 623 if (i > 15) 624 return -EINVAL; 625 break; 626 default: 627 return -EINVAL; 628 } 629 630 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 631 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 632 if (rxdg0 & MT_RXV1_HT_AD_CODE) 633 status->enc_flags |= RX_ENC_FLAG_LDPC; 634 635 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * 636 FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 637 638 status->rate_idx = i; 639 640 status->chains = dev->mphy.antenna_mask; 641 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + 642 dev->rssi_offset[0]; 643 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + 644 dev->rssi_offset[1]; 645 646 status->signal = status->chain_signal[0]; 647 if (status->chains & BIT(1)) 648 status->signal = max(status->signal, 649 status->chain_signal[1]); 650 651 if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1) 652 status->bw = RATE_INFO_BW_40; 653 654 rxd += 6; 655 if ((u8 *)rxd - skb->data >= skb->len) 656 return -EINVAL; 657 } else { 658 return -EINVAL; 659 } 660 661 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 662 663 if (insert_ccmp_hdr) { 664 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 665 666 mt76_insert_ccmp_hdr(skb, key_id); 667 } 668 669 hdr = (struct ieee80211_hdr *)skb->data; 670 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) 671 return 0; 672 673 status->aggr = unicast && 674 !ieee80211_is_qos_nullfunc(hdr->frame_control); 675 status->qos_ctl = *ieee80211_get_qos_ctl(hdr); 676 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 677 678 return 0; 679 } 680 681 static u16 682 mt7603_mac_tx_rate_val(struct mt7603_dev *dev, 683 const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw) 684 { 685 u8 phy, nss, rate_idx; 686 u16 rateval; 687 688 *bw = 0; 689 if (rate->flags & IEEE80211_TX_RC_MCS) { 690 rate_idx = rate->idx; 691 nss = 1 + (rate->idx >> 3); 692 phy = MT_PHY_TYPE_HT; 693 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 694 phy = MT_PHY_TYPE_HT_GF; 695 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 696 *bw = 1; 697 } else { 698 const struct ieee80211_rate *r; 699 int band = dev->mphy.chandef.chan->band; 700 u16 val; 701 702 nss = 1; 703 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; 704 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 705 val = r->hw_value_short; 706 else 707 val = r->hw_value; 708 709 phy = val >> 8; 710 rate_idx = val & 0xff; 711 } 712 713 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 714 FIELD_PREP(MT_TX_RATE_MODE, phy)); 715 716 if (stbc && nss == 1) 717 rateval |= MT_TX_RATE_STBC; 718 719 return rateval; 720 } 721 722 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, 723 struct ieee80211_tx_rate *probe_rate, 724 struct ieee80211_tx_rate *rates) 725 { 726 struct ieee80211_tx_rate *ref; 727 int wcid = sta->wcid.idx; 728 u32 addr = mt7603_wtbl2_addr(wcid); 729 bool stbc = false; 730 int n_rates = sta->n_rates; 731 u8 bw, bw_prev, bw_idx = 0; 732 u16 val[4]; 733 u16 probe_val; 734 u32 w9 = mt76_rr(dev, addr + 9 * 4); 735 bool rateset; 736 int i, k; 737 738 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 739 return; 740 741 for (i = n_rates; i < 4; i++) 742 rates[i] = rates[n_rates - 1]; 743 744 rateset = !(sta->rate_set_tsf & BIT(0)); 745 memcpy(sta->rateset[rateset].rates, rates, 746 sizeof(sta->rateset[rateset].rates)); 747 if (probe_rate) { 748 sta->rateset[rateset].probe_rate = *probe_rate; 749 ref = &sta->rateset[rateset].probe_rate; 750 } else { 751 sta->rateset[rateset].probe_rate.idx = -1; 752 ref = &sta->rateset[rateset].rates[0]; 753 } 754 755 rates = sta->rateset[rateset].rates; 756 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 757 /* 758 * We don't support switching between short and long GI 759 * within the rate set. For accurate tx status reporting, we 760 * need to make sure that flags match. 761 * For improved performance, avoid duplicate entries by 762 * decrementing the MCS index if necessary 763 */ 764 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 765 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 766 767 for (k = 0; k < i; k++) { 768 if (rates[i].idx != rates[k].idx) 769 continue; 770 if ((rates[i].flags ^ rates[k].flags) & 771 IEEE80211_TX_RC_40_MHZ_WIDTH) 772 continue; 773 774 if (!rates[i].idx) 775 continue; 776 777 rates[i].idx--; 778 } 779 } 780 781 w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 782 MT_WTBL2_W9_SHORT_GI_80; 783 784 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); 785 bw_prev = bw; 786 787 if (probe_rate) { 788 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw); 789 if (bw) 790 bw_idx = 1; 791 else 792 bw_prev = 0; 793 } else { 794 probe_val = val[0]; 795 } 796 797 w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw); 798 w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw); 799 800 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); 801 if (bw_prev) { 802 bw_idx = 3; 803 bw_prev = bw; 804 } 805 806 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); 807 if (bw_prev) { 808 bw_idx = 5; 809 bw_prev = bw; 810 } 811 812 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); 813 if (bw_prev) 814 bw_idx = 7; 815 816 w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE, 817 bw_idx ? bw_idx - 1 : 7); 818 819 mt76_wr(dev, MT_WTBL_RIUCR0, w9); 820 821 mt76_wr(dev, MT_WTBL_RIUCR1, 822 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) | 823 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | 824 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); 825 826 mt76_wr(dev, MT_WTBL_RIUCR2, 827 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | 828 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | 829 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | 830 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); 831 832 mt76_wr(dev, MT_WTBL_RIUCR3, 833 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | 834 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | 835 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); 836 837 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ 838 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; 839 840 mt76_wr(dev, MT_WTBL_UPDATE, 841 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 842 MT_WTBL_UPDATE_RATE_UPDATE | 843 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 844 845 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 846 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 847 848 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; 849 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 850 } 851 852 static enum mt76_cipher_type 853 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 854 { 855 memset(key_data, 0, 32); 856 if (!key) 857 return MT_CIPHER_NONE; 858 859 if (key->keylen > 32) 860 return MT_CIPHER_NONE; 861 862 memcpy(key_data, key->key, key->keylen); 863 864 switch (key->cipher) { 865 case WLAN_CIPHER_SUITE_WEP40: 866 return MT_CIPHER_WEP40; 867 case WLAN_CIPHER_SUITE_WEP104: 868 return MT_CIPHER_WEP104; 869 case WLAN_CIPHER_SUITE_TKIP: 870 /* Rx/Tx MIC keys are swapped */ 871 memcpy(key_data + 16, key->key + 24, 8); 872 memcpy(key_data + 24, key->key + 16, 8); 873 return MT_CIPHER_TKIP; 874 case WLAN_CIPHER_SUITE_CCMP: 875 return MT_CIPHER_AES_CCMP; 876 default: 877 return MT_CIPHER_NONE; 878 } 879 } 880 881 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, 882 struct ieee80211_key_conf *key) 883 { 884 enum mt76_cipher_type cipher; 885 u32 addr = mt7603_wtbl3_addr(wcid); 886 u8 key_data[32]; 887 int key_len = sizeof(key_data); 888 889 cipher = mt7603_mac_get_key_info(key, key_data); 890 if (cipher == MT_CIPHER_NONE && key) 891 return -EOPNOTSUPP; 892 893 if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) { 894 addr += key->keyidx * 16; 895 key_len = 16; 896 } 897 898 mt76_wr_copy(dev, addr, key_data, key_len); 899 900 addr = mt7603_wtbl1_addr(wcid); 901 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher); 902 if (key) 903 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); 904 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key); 905 906 return 0; 907 } 908 909 static int 910 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi, 911 struct sk_buff *skb, enum mt76_txq_id qid, 912 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 913 int pid, struct ieee80211_key_conf *key) 914 { 915 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 916 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 917 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 918 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; 919 struct ieee80211_vif *vif = info->control.vif; 920 struct mt76_queue *q = dev->mphy.q_tx[qid]; 921 struct mt7603_vif *mvif; 922 int wlan_idx; 923 int hdr_len = ieee80211_get_hdrlen_from_skb(skb); 924 int tx_count = 8; 925 u8 frame_type, frame_subtype; 926 u16 fc = le16_to_cpu(hdr->frame_control); 927 u16 seqno = 0; 928 u8 vif_idx = 0; 929 u32 val; 930 u8 bw; 931 932 if (vif) { 933 mvif = (struct mt7603_vif *)vif->drv_priv; 934 vif_idx = mvif->idx; 935 if (vif_idx && qid >= MT_TXQ_BEACON) 936 vif_idx += 0x10; 937 } 938 939 if (sta) { 940 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 941 942 tx_count = msta->rate_count; 943 } 944 945 if (wcid) 946 wlan_idx = wcid->idx; 947 else 948 wlan_idx = MT7603_WTBL_RESERVED; 949 950 frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2; 951 frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4; 952 953 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 954 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); 955 txwi[0] = cpu_to_le32(val); 956 957 val = MT_TXD1_LONG_FORMAT | 958 FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) | 959 FIELD_PREP(MT_TXD1_TID, 960 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 961 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 962 FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) | 963 FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) | 964 FIELD_PREP(MT_TXD1_PROTECTED, !!key); 965 txwi[1] = cpu_to_le32(val); 966 967 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 968 txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK); 969 970 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) | 971 FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) | 972 FIELD_PREP(MT_TXD2_MULTICAST, 973 is_multicast_ether_addr(hdr->addr1)); 974 txwi[2] = cpu_to_le32(val); 975 976 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 977 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 978 979 txwi[4] = 0; 980 981 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | 982 FIELD_PREP(MT_TXD5_PID, pid); 983 txwi[5] = cpu_to_le32(val); 984 985 txwi[6] = 0; 986 987 if (rate->idx >= 0 && rate->count && 988 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 989 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 990 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw); 991 992 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 993 994 val = MT_TXD6_FIXED_BW | 995 FIELD_PREP(MT_TXD6_BW, bw) | 996 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 997 txwi[6] |= cpu_to_le32(val); 998 999 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 1000 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 1001 1002 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 1003 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 1004 1005 tx_count = rate->count; 1006 } 1007 1008 /* use maximum tx count for beacons and buffered multicast */ 1009 if (qid >= MT_TXQ_BEACON) 1010 tx_count = 0x1f; 1011 1012 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) | 1013 MT_TXD3_SN_VALID; 1014 1015 if (ieee80211_is_data_qos(hdr->frame_control)) 1016 seqno = le16_to_cpu(hdr->seq_ctrl); 1017 else if (ieee80211_is_back_req(hdr->frame_control)) 1018 seqno = le16_to_cpu(bar->start_seq_num); 1019 else 1020 val &= ~MT_TXD3_SN_VALID; 1021 1022 val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4); 1023 1024 txwi[3] = cpu_to_le32(val); 1025 1026 if (key) { 1027 u64 pn = atomic64_inc_return(&key->tx_pn); 1028 1029 txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID); 1030 txwi[4] = cpu_to_le32(pn & GENMASK(31, 0)); 1031 txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32)); 1032 } 1033 1034 txwi[7] = 0; 1035 1036 return 0; 1037 } 1038 1039 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 1040 enum mt76_txq_id qid, struct mt76_wcid *wcid, 1041 struct ieee80211_sta *sta, 1042 struct mt76_tx_info *tx_info) 1043 { 1044 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1045 struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid); 1046 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 1047 struct ieee80211_key_conf *key = info->control.hw_key; 1048 int pid; 1049 1050 if (!wcid) 1051 wcid = &dev->global_sta.wcid; 1052 1053 if (sta) { 1054 msta = (struct mt7603_sta *)sta->drv_priv; 1055 1056 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | 1057 IEEE80211_TX_CTL_CLEAR_PS_FILT)) || 1058 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) 1059 mt7603_wtbl_set_ps(dev, msta, false); 1060 1061 mt76_tx_check_agg_ssn(sta, tx_info->skb); 1062 } 1063 1064 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 1065 1066 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { 1067 spin_lock_bh(&dev->mt76.lock); 1068 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], 1069 msta->rates); 1070 msta->rate_probe = true; 1071 spin_unlock_bh(&dev->mt76.lock); 1072 } 1073 1074 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, 1075 sta, pid, key); 1076 1077 return 0; 1078 } 1079 1080 static bool 1081 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta, 1082 struct ieee80211_tx_info *info, __le32 *txs_data) 1083 { 1084 struct ieee80211_supported_band *sband; 1085 struct mt7603_rate_set *rs; 1086 int first_idx = 0, last_idx; 1087 u32 rate_set_tsf; 1088 u32 final_rate; 1089 u32 final_rate_flags; 1090 bool rs_idx; 1091 bool ack_timeout; 1092 bool fixed_rate; 1093 bool probe; 1094 bool ampdu; 1095 bool cck = false; 1096 int count; 1097 u32 txs; 1098 int idx; 1099 int i; 1100 1101 fixed_rate = info->status.rates[0].count; 1102 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1103 1104 txs = le32_to_cpu(txs_data[4]); 1105 ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU); 1106 count = FIELD_GET(MT_TXS4_TX_COUNT, txs); 1107 last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs); 1108 1109 txs = le32_to_cpu(txs_data[0]); 1110 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 1111 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 1112 1113 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 1114 return false; 1115 1116 if (txs & MT_TXS0_QUEUE_TIMEOUT) 1117 return false; 1118 1119 if (!ack_timeout) 1120 info->flags |= IEEE80211_TX_STAT_ACK; 1121 1122 info->status.ampdu_len = 1; 1123 info->status.ampdu_ack_len = !!(info->flags & 1124 IEEE80211_TX_STAT_ACK); 1125 1126 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 1127 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 1128 1129 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY); 1130 1131 if (fixed_rate && !probe) { 1132 info->status.rates[0].count = count; 1133 i = 0; 1134 goto out; 1135 } 1136 1137 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1138 rs_idx = !((u32)(FIELD_GET(MT_TXS1_F0_TIMESTAMP, le32_to_cpu(txs_data[1])) - 1139 rate_set_tsf) < 1000000); 1140 rs_idx ^= rate_set_tsf & BIT(0); 1141 rs = &sta->rateset[rs_idx]; 1142 1143 if (!first_idx && rs->probe_rate.idx >= 0) { 1144 info->status.rates[0] = rs->probe_rate; 1145 1146 spin_lock_bh(&dev->mt76.lock); 1147 if (sta->rate_probe) { 1148 mt7603_wtbl_set_rates(dev, sta, NULL, 1149 sta->rates); 1150 sta->rate_probe = false; 1151 } 1152 spin_unlock_bh(&dev->mt76.lock); 1153 } else { 1154 info->status.rates[0] = rs->rates[first_idx / 2]; 1155 } 1156 info->status.rates[0].count = 0; 1157 1158 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1159 struct ieee80211_tx_rate *cur_rate; 1160 int cur_count; 1161 1162 cur_rate = &rs->rates[idx / 2]; 1163 cur_count = min_t(int, MT7603_RATE_RETRY, count); 1164 count -= cur_count; 1165 1166 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1167 cur_rate->flags != info->status.rates[i].flags)) { 1168 i++; 1169 if (i == ARRAY_SIZE(info->status.rates)) { 1170 i--; 1171 break; 1172 } 1173 1174 info->status.rates[i] = *cur_rate; 1175 info->status.rates[i].count = 0; 1176 } 1177 1178 info->status.rates[i].count += cur_count; 1179 } 1180 1181 out: 1182 final_rate_flags = info->status.rates[i].flags; 1183 1184 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1185 case MT_PHY_TYPE_CCK: 1186 cck = true; 1187 fallthrough; 1188 case MT_PHY_TYPE_OFDM: 1189 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) 1190 sband = &dev->mphy.sband_5g.sband; 1191 else 1192 sband = &dev->mphy.sband_2g.sband; 1193 final_rate &= GENMASK(5, 0); 1194 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1195 cck); 1196 final_rate_flags = 0; 1197 break; 1198 case MT_PHY_TYPE_HT_GF: 1199 case MT_PHY_TYPE_HT: 1200 final_rate_flags |= IEEE80211_TX_RC_MCS; 1201 final_rate &= GENMASK(5, 0); 1202 if (final_rate > 15) 1203 return false; 1204 break; 1205 default: 1206 return false; 1207 } 1208 1209 info->status.rates[i].idx = final_rate; 1210 info->status.rates[i].flags = final_rate_flags; 1211 1212 return true; 1213 } 1214 1215 static bool 1216 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid, 1217 __le32 *txs_data) 1218 { 1219 struct mt76_dev *mdev = &dev->mt76; 1220 struct sk_buff_head list; 1221 struct sk_buff *skb; 1222 1223 if (pid < MT_PACKET_ID_FIRST) 1224 return false; 1225 1226 trace_mac_txdone(mdev, sta->wcid.idx, pid); 1227 1228 mt76_tx_status_lock(mdev, &list); 1229 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1230 if (skb) { 1231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1232 1233 if (!mt7603_fill_txs(dev, sta, info, txs_data)) { 1234 info->status.rates[0].count = 0; 1235 info->status.rates[0].idx = -1; 1236 } 1237 1238 mt76_tx_status_skb_done(mdev, skb, &list); 1239 } 1240 mt76_tx_status_unlock(mdev, &list); 1241 1242 return !!skb; 1243 } 1244 1245 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data) 1246 { 1247 struct ieee80211_tx_info info = {}; 1248 struct ieee80211_sta *sta = NULL; 1249 struct mt7603_sta *msta = NULL; 1250 struct mt76_wcid *wcid; 1251 __le32 *txs_data = data; 1252 u32 txs; 1253 u8 wcidx; 1254 u8 pid; 1255 1256 txs = le32_to_cpu(txs_data[4]); 1257 pid = FIELD_GET(MT_TXS4_PID, txs); 1258 txs = le32_to_cpu(txs_data[3]); 1259 wcidx = FIELD_GET(MT_TXS3_WCID, txs); 1260 1261 if (pid == MT_PACKET_ID_NO_ACK) 1262 return; 1263 1264 if (wcidx >= MT7603_WTBL_SIZE) 1265 return; 1266 1267 rcu_read_lock(); 1268 1269 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1270 if (!wcid) 1271 goto out; 1272 1273 msta = container_of(wcid, struct mt7603_sta, wcid); 1274 sta = wcid_to_sta(wcid); 1275 1276 if (list_empty(&msta->poll_list)) { 1277 spin_lock_bh(&dev->sta_poll_lock); 1278 list_add_tail(&msta->poll_list, &dev->sta_poll_list); 1279 spin_unlock_bh(&dev->sta_poll_lock); 1280 } 1281 1282 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data)) 1283 goto out; 1284 1285 if (wcidx >= MT7603_WTBL_STA || !sta) 1286 goto out; 1287 1288 if (mt7603_fill_txs(dev, msta, &info, txs_data)) 1289 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info); 1290 1291 out: 1292 rcu_read_unlock(); 1293 } 1294 1295 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e) 1296 { 1297 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1298 struct sk_buff *skb = e->skb; 1299 1300 if (!e->txwi) { 1301 dev_kfree_skb_any(skb); 1302 return; 1303 } 1304 1305 dev->tx_hang_check = 0; 1306 mt76_tx_complete_skb(mdev, e->wcid, skb); 1307 } 1308 1309 static bool 1310 wait_for_wpdma(struct mt7603_dev *dev) 1311 { 1312 return mt76_poll(dev, MT_WPDMA_GLO_CFG, 1313 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 1314 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 1315 0, 1000); 1316 } 1317 1318 static void mt7603_pse_reset(struct mt7603_dev *dev) 1319 { 1320 /* Clear previous reset result */ 1321 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1322 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); 1323 1324 /* Reset PSE */ 1325 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1326 1327 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, 1328 MT_MCU_DEBUG_RESET_PSE_S, 1329 MT_MCU_DEBUG_RESET_PSE_S, 500)) { 1330 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; 1331 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1332 } else { 1333 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1334 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); 1335 } 1336 1337 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) 1338 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1339 } 1340 1341 void mt7603_mac_dma_start(struct mt7603_dev *dev) 1342 { 1343 mt7603_mac_start(dev); 1344 1345 wait_for_wpdma(dev); 1346 usleep_range(50, 100); 1347 1348 mt76_set(dev, MT_WPDMA_GLO_CFG, 1349 (MT_WPDMA_GLO_CFG_TX_DMA_EN | 1350 MT_WPDMA_GLO_CFG_RX_DMA_EN | 1351 FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | 1352 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE)); 1353 1354 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL); 1355 } 1356 1357 void mt7603_mac_start(struct mt7603_dev *dev) 1358 { 1359 mt76_clear(dev, MT_ARB_SCR, 1360 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1361 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); 1362 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1363 } 1364 1365 void mt7603_mac_stop(struct mt7603_dev *dev) 1366 { 1367 mt76_set(dev, MT_ARB_SCR, 1368 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1369 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); 1370 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1371 } 1372 1373 void mt7603_pse_client_reset(struct mt7603_dev *dev) 1374 { 1375 u32 addr; 1376 1377 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + 1378 MT_CLIENT_RESET_TX); 1379 1380 /* Clear previous reset state */ 1381 mt76_clear(dev, addr, 1382 MT_CLIENT_RESET_TX_R_E_1 | 1383 MT_CLIENT_RESET_TX_R_E_2 | 1384 MT_CLIENT_RESET_TX_R_E_1_S | 1385 MT_CLIENT_RESET_TX_R_E_2_S); 1386 1387 /* Start PSE client TX abort */ 1388 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); 1389 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S, 1390 MT_CLIENT_RESET_TX_R_E_1_S, 500); 1391 1392 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); 1393 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 1394 1395 /* Wait for PSE client to clear TX FIFO */ 1396 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S, 1397 MT_CLIENT_RESET_TX_R_E_2_S, 500); 1398 1399 /* Clear PSE client TX abort state */ 1400 mt76_clear(dev, addr, 1401 MT_CLIENT_RESET_TX_R_E_1 | 1402 MT_CLIENT_RESET_TX_R_E_2); 1403 } 1404 1405 static void mt7603_dma_sched_reset(struct mt7603_dev *dev) 1406 { 1407 if (!is_mt7628(dev)) 1408 return; 1409 1410 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); 1411 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); 1412 } 1413 1414 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) 1415 { 1416 int beacon_int = dev->mt76.beacon_int; 1417 u32 mask = dev->mt76.mmio.irqmask; 1418 int i; 1419 1420 ieee80211_stop_queues(dev->mt76.hw); 1421 set_bit(MT76_RESET, &dev->mphy.state); 1422 1423 /* lock/unlock all queues to ensure that no tx is pending */ 1424 mt76_txq_schedule_all(&dev->mphy); 1425 1426 mt76_worker_disable(&dev->mt76.tx_worker); 1427 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 1428 napi_disable(&dev->mt76.napi[0]); 1429 napi_disable(&dev->mt76.napi[1]); 1430 napi_disable(&dev->mt76.tx_napi); 1431 1432 mutex_lock(&dev->mt76.mutex); 1433 1434 mt7603_beacon_set_timer(dev, -1, 0); 1435 1436 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || 1437 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY || 1438 dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK || 1439 dev->cur_reset_cause == RESET_CAUSE_TX_HANG) 1440 mt7603_pse_reset(dev); 1441 1442 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1443 goto skip_dma_reset; 1444 1445 mt7603_mac_stop(dev); 1446 1447 mt76_clear(dev, MT_WPDMA_GLO_CFG, 1448 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN | 1449 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 1450 usleep_range(1000, 2000); 1451 1452 mt7603_irq_disable(dev, mask); 1453 1454 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF); 1455 1456 mt7603_pse_client_reset(dev); 1457 1458 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); 1459 for (i = 0; i < __MT_TXQ_MAX; i++) 1460 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); 1461 1462 mt76_for_each_q_rx(&dev->mt76, i) { 1463 mt76_queue_rx_reset(dev, i); 1464 } 1465 1466 mt76_tx_status_check(&dev->mt76, true); 1467 1468 mt7603_dma_sched_reset(dev); 1469 1470 mt7603_mac_dma_start(dev); 1471 1472 mt7603_irq_enable(dev, mask); 1473 1474 skip_dma_reset: 1475 clear_bit(MT76_RESET, &dev->mphy.state); 1476 mutex_unlock(&dev->mt76.mutex); 1477 1478 mt76_worker_enable(&dev->mt76.tx_worker); 1479 1480 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 1481 mt7603_beacon_set_timer(dev, -1, beacon_int); 1482 1483 local_bh_disable(); 1484 napi_enable(&dev->mt76.tx_napi); 1485 napi_schedule(&dev->mt76.tx_napi); 1486 1487 napi_enable(&dev->mt76.napi[0]); 1488 napi_schedule(&dev->mt76.napi[0]); 1489 1490 napi_enable(&dev->mt76.napi[1]); 1491 napi_schedule(&dev->mt76.napi[1]); 1492 local_bh_enable(); 1493 1494 ieee80211_wake_queues(dev->mt76.hw); 1495 mt76_txq_schedule_all(&dev->mphy); 1496 } 1497 1498 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index) 1499 { 1500 u32 val; 1501 1502 mt76_wr(dev, MT_WPDMA_DEBUG, 1503 FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) | 1504 MT_WPDMA_DEBUG_SEL); 1505 1506 val = mt76_rr(dev, MT_WPDMA_DEBUG); 1507 return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val); 1508 } 1509 1510 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev) 1511 { 1512 if (is_mt7628(dev)) 1513 return mt7603_dma_debug(dev, 9) & BIT(9); 1514 1515 return mt7603_dma_debug(dev, 2) & BIT(8); 1516 } 1517 1518 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev) 1519 { 1520 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) 1521 return false; 1522 1523 return mt7603_rx_fifo_busy(dev); 1524 } 1525 1526 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev) 1527 { 1528 u32 val; 1529 1530 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY)) 1531 return false; 1532 1533 val = mt7603_dma_debug(dev, 9); 1534 return (val & BIT(8)) && (val & 0xf) != 0xf; 1535 } 1536 1537 static bool mt7603_tx_hang(struct mt7603_dev *dev) 1538 { 1539 struct mt76_queue *q; 1540 u32 dma_idx, prev_dma_idx; 1541 int i; 1542 1543 for (i = 0; i < 4; i++) { 1544 q = dev->mphy.q_tx[i]; 1545 1546 if (!q->queued) 1547 continue; 1548 1549 prev_dma_idx = dev->tx_dma_idx[i]; 1550 dma_idx = readl(&q->regs->dma_idx); 1551 dev->tx_dma_idx[i] = dma_idx; 1552 1553 if (dma_idx == prev_dma_idx && 1554 dma_idx != readl(&q->regs->cpu_idx)) 1555 break; 1556 } 1557 1558 return i < 4; 1559 } 1560 1561 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) 1562 { 1563 u32 addr, val; 1564 1565 if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES) 1566 return true; 1567 1568 if (mt7603_rx_fifo_busy(dev)) 1569 return false; 1570 1571 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); 1572 mt76_wr(dev, addr, 3); 1573 val = mt76_rr(dev, addr) >> 16; 1574 1575 if (is_mt7628(dev) && (val & 0x4001) == 0x4001) 1576 return true; 1577 1578 return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001; 1579 } 1580 1581 static bool 1582 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter, 1583 enum mt7603_reset_cause cause, 1584 bool (*check)(struct mt7603_dev *dev)) 1585 { 1586 if (dev->reset_test == cause + 1) { 1587 dev->reset_test = 0; 1588 goto trigger; 1589 } 1590 1591 if (check) { 1592 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) { 1593 *counter = 0; 1594 return false; 1595 } 1596 1597 (*counter)++; 1598 } 1599 1600 if (*counter < MT7603_WATCHDOG_TIMEOUT) 1601 return false; 1602 trigger: 1603 dev->cur_reset_cause = cause; 1604 dev->reset_cause[cause]++; 1605 return true; 1606 } 1607 1608 void mt7603_update_channel(struct mt76_phy *mphy) 1609 { 1610 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76); 1611 struct mt76_channel_state *state; 1612 1613 state = mphy->chan_state; 1614 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); 1615 } 1616 1617 void 1618 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) 1619 { 1620 u32 rxtd_6 = 0xd7c80000; 1621 1622 if (val == dev->ed_strict_mode) 1623 return; 1624 1625 dev->ed_strict_mode = val; 1626 1627 /* Ensure that ED/CCA does not trigger if disabled */ 1628 if (!dev->ed_monitor) 1629 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34); 1630 else 1631 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d); 1632 1633 if (dev->ed_monitor && !dev->ed_strict_mode) 1634 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f); 1635 else 1636 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10); 1637 1638 mt76_wr(dev, MT_RXTD(6), rxtd_6); 1639 1640 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN, 1641 dev->ed_monitor && !dev->ed_strict_mode); 1642 } 1643 1644 static void 1645 mt7603_edcca_check(struct mt7603_dev *dev) 1646 { 1647 u32 val = mt76_rr(dev, MT_AGC(41)); 1648 ktime_t cur_time; 1649 int rssi0, rssi1; 1650 u32 active; 1651 u32 ed_busy; 1652 1653 if (!dev->ed_monitor) 1654 return; 1655 1656 rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val); 1657 if (rssi0 > 128) 1658 rssi0 -= 256; 1659 1660 if (dev->mphy.antenna_mask & BIT(1)) { 1661 rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val); 1662 if (rssi1 > 128) 1663 rssi1 -= 256; 1664 } else { 1665 rssi1 = rssi0; 1666 } 1667 1668 if (max(rssi0, rssi1) >= -40 && 1669 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) 1670 dev->ed_strong_signal++; 1671 else if (dev->ed_strong_signal > 0) 1672 dev->ed_strong_signal--; 1673 1674 cur_time = ktime_get_boottime(); 1675 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK; 1676 1677 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 1678 dev->ed_time = cur_time; 1679 1680 if (!active) 1681 return; 1682 1683 if (100 * ed_busy / active > 90) { 1684 if (dev->ed_trigger < 0) 1685 dev->ed_trigger = 0; 1686 dev->ed_trigger++; 1687 } else { 1688 if (dev->ed_trigger > 0) 1689 dev->ed_trigger = 0; 1690 dev->ed_trigger--; 1691 } 1692 1693 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || 1694 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { 1695 mt7603_edcca_set_strict(dev, true); 1696 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { 1697 mt7603_edcca_set_strict(dev, false); 1698 } 1699 1700 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) 1701 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; 1702 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) 1703 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; 1704 } 1705 1706 void mt7603_cca_stats_reset(struct mt7603_dev *dev) 1707 { 1708 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1709 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1710 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN); 1711 } 1712 1713 static void 1714 mt7603_adjust_sensitivity(struct mt7603_dev *dev) 1715 { 1716 u32 agc0 = dev->agc0, agc3 = dev->agc3; 1717 u32 adj; 1718 1719 if (!dev->sensitivity || dev->sensitivity < -100) { 1720 dev->sensitivity = 0; 1721 } else if (dev->sensitivity <= -84) { 1722 adj = 7 + (dev->sensitivity + 92) / 2; 1723 1724 agc0 = 0x56f0076f; 1725 agc0 |= adj << 12; 1726 agc0 |= adj << 16; 1727 agc3 = 0x81d0d5e3; 1728 } else if (dev->sensitivity <= -72) { 1729 adj = 7 + (dev->sensitivity + 80) / 2; 1730 1731 agc0 = 0x6af0006f; 1732 agc0 |= adj << 8; 1733 agc0 |= adj << 12; 1734 agc0 |= adj << 16; 1735 1736 agc3 = 0x8181d5e3; 1737 } else { 1738 if (dev->sensitivity > -54) 1739 dev->sensitivity = -54; 1740 1741 adj = 7 + (dev->sensitivity + 80) / 2; 1742 1743 agc0 = 0x7ff0000f; 1744 agc0 |= adj << 4; 1745 agc0 |= adj << 8; 1746 agc0 |= adj << 12; 1747 agc0 |= adj << 16; 1748 1749 agc3 = 0x818181e3; 1750 } 1751 1752 mt76_wr(dev, MT_AGC(0), agc0); 1753 mt76_wr(dev, MT_AGC1(0), agc0); 1754 1755 mt76_wr(dev, MT_AGC(3), agc3); 1756 mt76_wr(dev, MT_AGC1(3), agc3); 1757 } 1758 1759 static void 1760 mt7603_false_cca_check(struct mt7603_dev *dev) 1761 { 1762 int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm; 1763 int false_cca; 1764 int min_signal; 1765 u32 val; 1766 1767 if (!dev->dynamic_sensitivity) 1768 return; 1769 1770 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); 1771 pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val); 1772 pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val); 1773 1774 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); 1775 mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val); 1776 mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val); 1777 1778 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1779 dev->false_cca_cck = pd_cck - mdrdy_cck; 1780 1781 mt7603_cca_stats_reset(dev); 1782 1783 min_signal = mt76_get_min_avg_rssi(&dev->mt76, false); 1784 if (!min_signal) { 1785 dev->sensitivity = 0; 1786 dev->last_cca_adj = jiffies; 1787 goto out; 1788 } 1789 1790 min_signal -= 15; 1791 1792 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; 1793 if (false_cca > 600 && 1794 dev->sensitivity < -100 + dev->sensitivity_limit) { 1795 if (!dev->sensitivity) 1796 dev->sensitivity = -92; 1797 else 1798 dev->sensitivity += 2; 1799 dev->last_cca_adj = jiffies; 1800 } else if (false_cca < 100 || 1801 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { 1802 dev->last_cca_adj = jiffies; 1803 if (!dev->sensitivity) 1804 goto out; 1805 1806 dev->sensitivity -= 2; 1807 } 1808 1809 if (dev->sensitivity && dev->sensitivity > min_signal) { 1810 dev->sensitivity = min_signal; 1811 dev->last_cca_adj = jiffies; 1812 } 1813 1814 out: 1815 mt7603_adjust_sensitivity(dev); 1816 } 1817 1818 void mt7603_mac_work(struct work_struct *work) 1819 { 1820 struct mt7603_dev *dev = container_of(work, struct mt7603_dev, 1821 mphy.mac_work.work); 1822 bool reset = false; 1823 int i, idx; 1824 1825 mt76_tx_status_check(&dev->mt76, false); 1826 1827 mutex_lock(&dev->mt76.mutex); 1828 1829 dev->mphy.mac_work_count++; 1830 mt76_update_survey(&dev->mphy); 1831 mt7603_edcca_check(dev); 1832 1833 for (i = 0, idx = 0; i < 2; i++) { 1834 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i)); 1835 1836 dev->mt76.aggr_stats[idx++] += val & 0xffff; 1837 dev->mt76.aggr_stats[idx++] += val >> 16; 1838 } 1839 1840 if (dev->mphy.mac_work_count == 10) 1841 mt7603_false_cca_check(dev); 1842 1843 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, 1844 RESET_CAUSE_RX_PSE_BUSY, 1845 mt7603_rx_pse_busy) || 1846 mt7603_watchdog_check(dev, &dev->beacon_check, 1847 RESET_CAUSE_BEACON_STUCK, 1848 NULL) || 1849 mt7603_watchdog_check(dev, &dev->tx_hang_check, 1850 RESET_CAUSE_TX_HANG, 1851 mt7603_tx_hang) || 1852 mt7603_watchdog_check(dev, &dev->tx_dma_check, 1853 RESET_CAUSE_TX_BUSY, 1854 mt7603_tx_dma_busy) || 1855 mt7603_watchdog_check(dev, &dev->rx_dma_check, 1856 RESET_CAUSE_RX_BUSY, 1857 mt7603_rx_dma_busy) || 1858 mt7603_watchdog_check(dev, &dev->mcu_hang, 1859 RESET_CAUSE_MCU_HANG, 1860 NULL) || 1861 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { 1862 dev->beacon_check = 0; 1863 dev->tx_dma_check = 0; 1864 dev->tx_hang_check = 0; 1865 dev->rx_dma_check = 0; 1866 dev->rx_pse_check = 0; 1867 dev->mcu_hang = 0; 1868 dev->rx_dma_idx = ~0; 1869 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); 1870 reset = true; 1871 dev->mphy.mac_work_count = 0; 1872 } 1873 1874 if (dev->mphy.mac_work_count >= 10) 1875 dev->mphy.mac_work_count = 0; 1876 1877 mutex_unlock(&dev->mt76.mutex); 1878 1879 if (reset) 1880 mt7603_mac_watchdog_reset(dev); 1881 1882 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1883 msecs_to_jiffies(MT7603_WATCHDOG_TIME)); 1884 } 1885