1 // SPDX-License-Identifier: ISC
2 
3 #include <linux/etherdevice.h>
4 #include <linux/timekeeping.h>
5 #include "mt7603.h"
6 #include "mac.h"
7 #include "../trace.h"
8 
9 #define MT_PSE_PAGE_SIZE	128
10 
11 static u32
12 mt7603_ac_queue_mask0(u32 mask)
13 {
14 	u32 ret = 0;
15 
16 	ret |= GENMASK(3, 0) * !!(mask & BIT(0));
17 	ret |= GENMASK(8, 5) * !!(mask & BIT(1));
18 	ret |= GENMASK(13, 10) * !!(mask & BIT(2));
19 	ret |= GENMASK(19, 16) * !!(mask & BIT(3));
20 	return ret;
21 }
22 
23 static void
24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
25 {
26 	mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
27 }
28 
29 static void
30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
31 {
32 	mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
33 }
34 
35 void mt7603_mac_reset_counters(struct mt7603_dev *dev)
36 {
37 	int i;
38 
39 	for (i = 0; i < 2; i++)
40 		mt76_rr(dev, MT_TX_AGG_CNT(i));
41 
42 	memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
43 }
44 
45 void mt7603_mac_set_timing(struct mt7603_dev *dev)
46 {
47 	u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
48 		  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
49 	u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
50 		   FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24);
51 	int offset = 3 * dev->coverage_class;
52 	u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
53 			 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
54 	bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ;
55 	int sifs;
56 	u32 val;
57 
58 	if (is_5ghz)
59 		sifs = 16;
60 	else
61 		sifs = 10;
62 
63 	mt76_set(dev, MT_ARB_SCR,
64 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
65 	udelay(1);
66 
67 	mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
68 	mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
69 	mt76_wr(dev, MT_IFS,
70 		FIELD_PREP(MT_IFS_EIFS, 360) |
71 		FIELD_PREP(MT_IFS_RIFS, 2) |
72 		FIELD_PREP(MT_IFS_SIFS, sifs) |
73 		FIELD_PREP(MT_IFS_SLOT, dev->slottime));
74 
75 	if (dev->slottime < 20 || is_5ghz)
76 		val = MT7603_CFEND_RATE_DEFAULT;
77 	else
78 		val = MT7603_CFEND_RATE_11B;
79 
80 	mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
81 
82 	mt76_clear(dev, MT_ARB_SCR,
83 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
84 }
85 
86 static void
87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
88 {
89 	mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
90 		 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
91 
92 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
93 }
94 
95 static u32
96 mt7603_wtbl1_addr(int idx)
97 {
98 	return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
99 }
100 
101 static u32
102 mt7603_wtbl2_addr(int idx)
103 {
104 	/* Mapped to WTBL2 */
105 	return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
106 }
107 
108 static u32
109 mt7603_wtbl3_addr(int idx)
110 {
111 	u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
112 
113 	return base + idx * MT_WTBL3_SIZE;
114 }
115 
116 static u32
117 mt7603_wtbl4_addr(int idx)
118 {
119 	u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
120 
121 	return base + idx * MT_WTBL4_SIZE;
122 }
123 
124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
125 		      const u8 *mac_addr)
126 {
127 	const void *_mac = mac_addr;
128 	u32 addr = mt7603_wtbl1_addr(idx);
129 	u32 w0 = 0, w1 = 0;
130 	int i;
131 
132 	if (_mac) {
133 		w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI,
134 				get_unaligned_le16(_mac + 4));
135 		w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO,
136 				get_unaligned_le32(_mac));
137 	}
138 
139 	if (vif < 0)
140 		vif = 0;
141 	else
142 		w0 |= MT_WTBL1_W0_RX_CHECK_A1;
143 	w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif);
144 
145 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
146 
147 	mt76_set(dev, addr + 0 * 4, w0);
148 	mt76_set(dev, addr + 1 * 4, w1);
149 	mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
150 
151 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
152 	addr = mt7603_wtbl2_addr(idx);
153 	for (i = 0; i < MT_WTBL2_SIZE; i += 4)
154 		mt76_wr(dev, addr + i, 0);
155 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
156 	mt76_start_tx_ac(dev, GENMASK(3, 0));
157 
158 	addr = mt7603_wtbl3_addr(idx);
159 	for (i = 0; i < MT_WTBL3_SIZE; i += 4)
160 		mt76_wr(dev, addr + i, 0);
161 
162 	addr = mt7603_wtbl4_addr(idx);
163 	for (i = 0; i < MT_WTBL4_SIZE; i += 4)
164 		mt76_wr(dev, addr + i, 0);
165 
166 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
167 }
168 
169 static void
170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
171 {
172 	u32 addr = mt7603_wtbl1_addr(idx);
173 	u32 val = mt76_rr(dev, addr + 3 * 4);
174 
175 	val &= ~MT_WTBL1_W3_SKIP_TX;
176 	val |= enabled * MT_WTBL1_W3_SKIP_TX;
177 
178 	mt76_wr(dev, addr + 3 * 4, val);
179 }
180 
181 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
182 {
183 	int i, port, queue;
184 
185 	if (abort) {
186 		port = 3; /* PSE */
187 		queue = 8; /* free queue */
188 	} else {
189 		port = 0; /* HIF */
190 		queue = 1; /* MCU queue */
191 	}
192 
193 	mt7603_wtbl_set_skip_tx(dev, idx, true);
194 
195 	mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
196 			FIELD_PREP(MT_TX_ABORT_WCID, idx));
197 
198 	for (i = 0; i < 4; i++) {
199 		mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
200 			FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
201 			FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) |
202 			FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
203 			FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
204 
205 		mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 15000);
206 	}
207 
208 	WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY);
209 
210 	mt76_wr(dev, MT_TX_ABORT, 0);
211 
212 	mt7603_wtbl_set_skip_tx(dev, idx, false);
213 }
214 
215 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
216 			  bool enabled)
217 {
218 	u32 addr = mt7603_wtbl1_addr(sta->wcid.idx);
219 
220 	if (sta->smps == enabled)
221 		return;
222 
223 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
224 	sta->smps = enabled;
225 }
226 
227 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
228 			bool enabled)
229 {
230 	int idx = sta->wcid.idx;
231 	u32 addr;
232 
233 	spin_lock_bh(&dev->ps_lock);
234 
235 	if (sta->ps == enabled)
236 		goto out;
237 
238 	mt76_wr(dev, MT_PSE_RTA,
239 		FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) |
240 		FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |
241 		FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) |
242 		FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) |
243 		MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY);
244 
245 	mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
246 
247 	if (enabled)
248 		mt7603_filter_tx(dev, idx, false);
249 
250 	addr = mt7603_wtbl1_addr(idx);
251 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
252 	mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
253 		 enabled * MT_WTBL1_W3_POWER_SAVE);
254 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
255 	sta->ps = enabled;
256 
257 out:
258 	spin_unlock_bh(&dev->ps_lock);
259 }
260 
261 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
262 {
263 	int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE;
264 	int wtbl2_frame = idx / wtbl2_frame_size;
265 	int wtbl2_entry = idx % wtbl2_frame_size;
266 
267 	int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE;
268 	int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE;
269 	int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size;
270 	int wtbl3_entry = (idx % wtbl3_frame_size) * 2;
271 
272 	int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE;
273 	int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE;
274 	int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size;
275 	int wtbl4_entry = idx % wtbl4_frame_size;
276 
277 	u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
278 	int i;
279 
280 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
281 
282 	mt76_wr(dev, addr + 0 * 4,
283 		MT_WTBL1_W0_RX_CHECK_A1 |
284 		MT_WTBL1_W0_RX_CHECK_A2 |
285 		MT_WTBL1_W0_RX_VALID);
286 	mt76_wr(dev, addr + 1 * 4, 0);
287 	mt76_wr(dev, addr + 2 * 4, 0);
288 
289 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
290 
291 	mt76_wr(dev, addr + 3 * 4,
292 		FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
293 		FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
294 		FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
295 		MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
296 	mt76_wr(dev, addr + 4 * 4,
297 		FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
298 		FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
299 		FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
300 
301 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
302 
303 	addr = mt7603_wtbl2_addr(idx);
304 
305 	/* Clear BA information */
306 	mt76_wr(dev, addr + (15 * 4), 0);
307 
308 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
309 	for (i = 2; i <= 4; i++)
310 		mt76_wr(dev, addr + (i * 4), 0);
311 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
312 	mt76_start_tx_ac(dev, GENMASK(3, 0));
313 
314 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
315 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
316 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
317 }
318 
319 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
320 {
321 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
322 	int idx = msta->wcid.idx;
323 	u8 ampdu_density;
324 	u32 addr;
325 	u32 val;
326 
327 	addr = mt7603_wtbl1_addr(idx);
328 
329 	ampdu_density = sta->deflink.ht_cap.ampdu_density;
330 	if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
331 		ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
332 
333 	val = mt76_rr(dev, addr + 2 * 4);
334 	val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
335 	val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR,
336 			  sta->deflink.ht_cap.ampdu_factor) |
337 	       FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY,
338 			  sta->deflink.ht_cap.ampdu_density) |
339 	       MT_WTBL1_W2_TXS_BAF_REPORT;
340 
341 	if (sta->deflink.ht_cap.cap)
342 		val |= MT_WTBL1_W2_HT;
343 	if (sta->deflink.vht_cap.cap)
344 		val |= MT_WTBL1_W2_VHT;
345 
346 	mt76_wr(dev, addr + 2 * 4, val);
347 
348 	addr = mt7603_wtbl2_addr(idx);
349 	val = mt76_rr(dev, addr + 9 * 4);
350 	val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
351 		 MT_WTBL2_W9_SHORT_GI_80);
352 	if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
353 		val |= MT_WTBL2_W9_SHORT_GI_20;
354 	if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
355 		val |= MT_WTBL2_W9_SHORT_GI_40;
356 	mt76_wr(dev, addr + 9 * 4, val);
357 }
358 
359 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
360 {
361 	mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
362 	mt76_wr(dev, MT_BA_CONTROL_1,
363 		(get_unaligned_le16(addr + 4) |
364 		 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
365 		 MT_BA_CONTROL_1_RESET));
366 }
367 
368 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
369 			    int ba_size)
370 {
371 	u32 addr = mt7603_wtbl2_addr(wcid);
372 	u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
373 		       (MT_WTBL2_W15_BA_WIN_SIZE <<
374 			(tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
375 	u32 tid_val;
376 	int i;
377 
378 	if (ba_size < 0) {
379 		/* disable */
380 		mt76_clear(dev, addr + (15 * 4), tid_mask);
381 		return;
382 	}
383 
384 	for (i = 7; i > 0; i--) {
385 		if (ba_size >= MT_AGG_SIZE_LIMIT(i))
386 			break;
387 	}
388 
389 	tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
390 		  i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
391 
392 	mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
393 }
394 
395 void mt7603_mac_sta_poll(struct mt7603_dev *dev)
396 {
397 	static const u8 ac_to_tid[4] = {
398 		[IEEE80211_AC_BE] = 0,
399 		[IEEE80211_AC_BK] = 1,
400 		[IEEE80211_AC_VI] = 4,
401 		[IEEE80211_AC_VO] = 6
402 	};
403 	struct ieee80211_sta *sta;
404 	struct mt7603_sta *msta;
405 	u32 total_airtime = 0;
406 	u32 airtime[4];
407 	u32 addr;
408 	int i;
409 
410 	rcu_read_lock();
411 
412 	while (1) {
413 		bool clear = false;
414 
415 		spin_lock_bh(&dev->sta_poll_lock);
416 		if (list_empty(&dev->sta_poll_list)) {
417 			spin_unlock_bh(&dev->sta_poll_lock);
418 			break;
419 		}
420 
421 		msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta,
422 					poll_list);
423 		list_del_init(&msta->poll_list);
424 		spin_unlock_bh(&dev->sta_poll_lock);
425 
426 		addr = mt7603_wtbl4_addr(msta->wcid.idx);
427 		for (i = 0; i < 4; i++) {
428 			u32 airtime_last = msta->tx_airtime_ac[i];
429 
430 			msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8);
431 			airtime[i] = msta->tx_airtime_ac[i] - airtime_last;
432 			airtime[i] *= 32;
433 			total_airtime += airtime[i];
434 
435 			if (msta->tx_airtime_ac[i] & BIT(22))
436 				clear = true;
437 		}
438 
439 		if (clear) {
440 			mt7603_wtbl_update(dev, msta->wcid.idx,
441 					   MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
442 			memset(msta->tx_airtime_ac, 0,
443 			       sizeof(msta->tx_airtime_ac));
444 		}
445 
446 		if (!msta->wcid.sta)
447 			continue;
448 
449 		sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
450 		for (i = 0; i < 4; i++) {
451 			struct mt76_queue *q = dev->mphy.q_tx[i];
452 			u8 qidx = q->hw_idx;
453 			u8 tid = ac_to_tid[i];
454 			u32 txtime = airtime[qidx];
455 
456 			if (!txtime)
457 				continue;
458 
459 			ieee80211_sta_register_airtime(sta, tid, txtime, 0);
460 		}
461 	}
462 
463 	rcu_read_unlock();
464 
465 	if (!total_airtime)
466 		return;
467 
468 	spin_lock_bh(&dev->mt76.cc_lock);
469 	dev->mphy.chan_state->cc_tx += total_airtime;
470 	spin_unlock_bh(&dev->mt76.cc_lock);
471 }
472 
473 static struct mt76_wcid *
474 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
475 {
476 	struct mt7603_sta *sta;
477 	struct mt76_wcid *wcid;
478 
479 	if (idx >= MT7603_WTBL_SIZE)
480 		return NULL;
481 
482 	wcid = rcu_dereference(dev->mt76.wcid[idx]);
483 	if (unicast || !wcid)
484 		return wcid;
485 
486 	if (!wcid->sta)
487 		return NULL;
488 
489 	sta = container_of(wcid, struct mt7603_sta, wcid);
490 	if (!sta->vif)
491 		return NULL;
492 
493 	return &sta->vif->sta.wcid;
494 }
495 
496 int
497 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
498 {
499 	struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
500 	struct ieee80211_supported_band *sband;
501 	struct ieee80211_hdr *hdr;
502 	__le32 *rxd = (__le32 *)skb->data;
503 	u32 rxd0 = le32_to_cpu(rxd[0]);
504 	u32 rxd1 = le32_to_cpu(rxd[1]);
505 	u32 rxd2 = le32_to_cpu(rxd[2]);
506 	bool unicast = rxd1 & MT_RXD1_NORMAL_U2M;
507 	bool insert_ccmp_hdr = false;
508 	bool remove_pad;
509 	int idx;
510 	int i;
511 
512 	memset(status, 0, sizeof(*status));
513 
514 	i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
515 	sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband;
516 	i >>= 1;
517 
518 	idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
519 	status->wcid = mt7603_rx_get_wcid(dev, idx, unicast);
520 
521 	status->band = sband->band;
522 	if (i < sband->n_channels)
523 		status->freq = sband->channels[i].center_freq;
524 
525 	if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
526 		status->flag |= RX_FLAG_FAILED_FCS_CRC;
527 
528 	if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
529 		status->flag |= RX_FLAG_MMIC_ERROR;
530 
531 	/* ICV error or CCMP/BIP/WPI MIC error */
532 	if (rxd2 & MT_RXD2_NORMAL_ICV_ERR)
533 		status->flag |= RX_FLAG_ONLY_MONITOR;
534 
535 	if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
536 	    !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
537 		status->flag |= RX_FLAG_DECRYPTED;
538 		status->flag |= RX_FLAG_IV_STRIPPED;
539 		status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
540 	}
541 
542 	remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
543 
544 	if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
545 		return -EINVAL;
546 
547 	if (!sband->channels)
548 		return -EINVAL;
549 
550 	rxd += 4;
551 	if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
552 		rxd += 4;
553 		if ((u8 *)rxd - skb->data >= skb->len)
554 			return -EINVAL;
555 	}
556 	if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
557 		u8 *data = (u8 *)rxd;
558 
559 		if (status->flag & RX_FLAG_DECRYPTED) {
560 			switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
561 			case MT_CIPHER_AES_CCMP:
562 			case MT_CIPHER_CCMP_CCX:
563 			case MT_CIPHER_CCMP_256:
564 				insert_ccmp_hdr =
565 					FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
566 				fallthrough;
567 			case MT_CIPHER_TKIP:
568 			case MT_CIPHER_TKIP_NO_MIC:
569 			case MT_CIPHER_GCMP:
570 			case MT_CIPHER_GCMP_256:
571 				status->iv[0] = data[5];
572 				status->iv[1] = data[4];
573 				status->iv[2] = data[3];
574 				status->iv[3] = data[2];
575 				status->iv[4] = data[1];
576 				status->iv[5] = data[0];
577 				break;
578 			default:
579 				break;
580 			}
581 		}
582 
583 		rxd += 4;
584 		if ((u8 *)rxd - skb->data >= skb->len)
585 			return -EINVAL;
586 	}
587 	if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
588 		status->timestamp = le32_to_cpu(rxd[0]);
589 		status->flag |= RX_FLAG_MACTIME_START;
590 
591 		if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
592 			      MT_RXD2_NORMAL_NON_AMPDU))) {
593 			status->flag |= RX_FLAG_AMPDU_DETAILS;
594 
595 			/* all subframes of an A-MPDU have the same timestamp */
596 			if (dev->rx_ampdu_ts != status->timestamp) {
597 				if (!++dev->ampdu_ref)
598 					dev->ampdu_ref++;
599 			}
600 			dev->rx_ampdu_ts = status->timestamp;
601 
602 			status->ampdu_ref = dev->ampdu_ref;
603 		}
604 
605 		rxd += 2;
606 		if ((u8 *)rxd - skb->data >= skb->len)
607 			return -EINVAL;
608 	}
609 	if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
610 		u32 rxdg0 = le32_to_cpu(rxd[0]);
611 		u32 rxdg3 = le32_to_cpu(rxd[3]);
612 		bool cck = false;
613 
614 		i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
615 		switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
616 		case MT_PHY_TYPE_CCK:
617 			cck = true;
618 			fallthrough;
619 		case MT_PHY_TYPE_OFDM:
620 			i = mt76_get_rate(&dev->mt76, sband, i, cck);
621 			break;
622 		case MT_PHY_TYPE_HT_GF:
623 		case MT_PHY_TYPE_HT:
624 			status->encoding = RX_ENC_HT;
625 			if (i > 15)
626 				return -EINVAL;
627 			break;
628 		default:
629 			return -EINVAL;
630 		}
631 
632 		if (rxdg0 & MT_RXV1_HT_SHORT_GI)
633 			status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
634 		if (rxdg0 & MT_RXV1_HT_AD_CODE)
635 			status->enc_flags |= RX_ENC_FLAG_LDPC;
636 
637 		status->enc_flags |= RX_ENC_FLAG_STBC_MASK *
638 				    FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
639 
640 		status->rate_idx = i;
641 
642 		status->chains = dev->mphy.antenna_mask;
643 		status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +
644 					  dev->rssi_offset[0];
645 		status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) +
646 					  dev->rssi_offset[1];
647 
648 		if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1)
649 			status->bw = RATE_INFO_BW_40;
650 
651 		rxd += 6;
652 		if ((u8 *)rxd - skb->data >= skb->len)
653 			return -EINVAL;
654 	} else {
655 		return -EINVAL;
656 	}
657 
658 	skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
659 
660 	if (insert_ccmp_hdr) {
661 		u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
662 
663 		mt76_insert_ccmp_hdr(skb, key_id);
664 	}
665 
666 	hdr = (struct ieee80211_hdr *)skb->data;
667 	if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
668 		return 0;
669 
670 	status->aggr = unicast &&
671 		       !ieee80211_is_qos_nullfunc(hdr->frame_control);
672 	status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
673 	status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
674 
675 	return 0;
676 }
677 
678 static u16
679 mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
680 		       const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw)
681 {
682 	u8 phy, nss, rate_idx;
683 	u16 rateval;
684 
685 	*bw = 0;
686 	if (rate->flags & IEEE80211_TX_RC_MCS) {
687 		rate_idx = rate->idx;
688 		nss = 1 + (rate->idx >> 3);
689 		phy = MT_PHY_TYPE_HT;
690 		if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
691 			phy = MT_PHY_TYPE_HT_GF;
692 		if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
693 			*bw = 1;
694 	} else {
695 		const struct ieee80211_rate *r;
696 		int band = dev->mphy.chandef.chan->band;
697 		u16 val;
698 
699 		nss = 1;
700 		r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
701 		if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
702 			val = r->hw_value_short;
703 		else
704 			val = r->hw_value;
705 
706 		phy = val >> 8;
707 		rate_idx = val & 0xff;
708 	}
709 
710 	rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
711 		   FIELD_PREP(MT_TX_RATE_MODE, phy));
712 
713 	if (stbc && nss == 1)
714 		rateval |= MT_TX_RATE_STBC;
715 
716 	return rateval;
717 }
718 
719 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
720 			   struct ieee80211_tx_rate *probe_rate,
721 			   struct ieee80211_tx_rate *rates)
722 {
723 	struct ieee80211_tx_rate *ref;
724 	int wcid = sta->wcid.idx;
725 	u32 addr = mt7603_wtbl2_addr(wcid);
726 	bool stbc = false;
727 	int n_rates = sta->n_rates;
728 	u8 bw, bw_prev, bw_idx = 0;
729 	u16 val[4];
730 	u16 probe_val;
731 	u32 w9 = mt76_rr(dev, addr + 9 * 4);
732 	bool rateset;
733 	int i, k;
734 
735 	if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
736 		return;
737 
738 	for (i = n_rates; i < 4; i++)
739 		rates[i] = rates[n_rates - 1];
740 
741 	rateset = !(sta->rate_set_tsf & BIT(0));
742 	memcpy(sta->rateset[rateset].rates, rates,
743 	       sizeof(sta->rateset[rateset].rates));
744 	if (probe_rate) {
745 		sta->rateset[rateset].probe_rate = *probe_rate;
746 		ref = &sta->rateset[rateset].probe_rate;
747 	} else {
748 		sta->rateset[rateset].probe_rate.idx = -1;
749 		ref = &sta->rateset[rateset].rates[0];
750 	}
751 
752 	rates = sta->rateset[rateset].rates;
753 	for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
754 		/*
755 		 * We don't support switching between short and long GI
756 		 * within the rate set. For accurate tx status reporting, we
757 		 * need to make sure that flags match.
758 		 * For improved performance, avoid duplicate entries by
759 		 * decrementing the MCS index if necessary
760 		 */
761 		if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
762 			rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
763 
764 		for (k = 0; k < i; k++) {
765 			if (rates[i].idx != rates[k].idx)
766 				continue;
767 			if ((rates[i].flags ^ rates[k].flags) &
768 			    IEEE80211_TX_RC_40_MHZ_WIDTH)
769 				continue;
770 
771 			if (!rates[i].idx)
772 				continue;
773 
774 			rates[i].idx--;
775 		}
776 	}
777 
778 	w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
779 	      MT_WTBL2_W9_SHORT_GI_80;
780 
781 	val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
782 	bw_prev = bw;
783 
784 	if (probe_rate) {
785 		probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
786 		if (bw)
787 			bw_idx = 1;
788 		else
789 			bw_prev = 0;
790 	} else {
791 		probe_val = val[0];
792 	}
793 
794 	w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
795 	w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
796 
797 	val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
798 	if (bw_prev) {
799 		bw_idx = 3;
800 		bw_prev = bw;
801 	}
802 
803 	val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
804 	if (bw_prev) {
805 		bw_idx = 5;
806 		bw_prev = bw;
807 	}
808 
809 	val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
810 	if (bw_prev)
811 		bw_idx = 7;
812 
813 	w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
814 		       bw_idx ? bw_idx - 1 : 7);
815 
816 	mt76_wr(dev, MT_WTBL_RIUCR0, w9);
817 
818 	mt76_wr(dev, MT_WTBL_RIUCR1,
819 		FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
820 		FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
821 		FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
822 
823 	mt76_wr(dev, MT_WTBL_RIUCR2,
824 		FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
825 		FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
826 		FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
827 		FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
828 
829 	mt76_wr(dev, MT_WTBL_RIUCR3,
830 		FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
831 		FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
832 		FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
833 
834 	mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
835 	sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
836 
837 	mt76_wr(dev, MT_WTBL_UPDATE,
838 		FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
839 		MT_WTBL_UPDATE_RATE_UPDATE |
840 		MT_WTBL_UPDATE_TX_COUNT_CLEAR);
841 
842 	if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
843 		mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
844 
845 	sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates;
846 	sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
847 }
848 
849 static enum mt76_cipher_type
850 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
851 {
852 	memset(key_data, 0, 32);
853 	if (!key)
854 		return MT_CIPHER_NONE;
855 
856 	if (key->keylen > 32)
857 		return MT_CIPHER_NONE;
858 
859 	memcpy(key_data, key->key, key->keylen);
860 
861 	switch (key->cipher) {
862 	case WLAN_CIPHER_SUITE_WEP40:
863 		return MT_CIPHER_WEP40;
864 	case WLAN_CIPHER_SUITE_WEP104:
865 		return MT_CIPHER_WEP104;
866 	case WLAN_CIPHER_SUITE_TKIP:
867 		/* Rx/Tx MIC keys are swapped */
868 		memcpy(key_data + 16, key->key + 24, 8);
869 		memcpy(key_data + 24, key->key + 16, 8);
870 		return MT_CIPHER_TKIP;
871 	case WLAN_CIPHER_SUITE_CCMP:
872 		return MT_CIPHER_AES_CCMP;
873 	default:
874 		return MT_CIPHER_NONE;
875 	}
876 }
877 
878 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
879 			struct ieee80211_key_conf *key)
880 {
881 	enum mt76_cipher_type cipher;
882 	u32 addr = mt7603_wtbl3_addr(wcid);
883 	u8 key_data[32];
884 	int key_len = sizeof(key_data);
885 
886 	cipher = mt7603_mac_get_key_info(key, key_data);
887 	if (cipher == MT_CIPHER_NONE && key)
888 		return -EOPNOTSUPP;
889 
890 	if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) {
891 		addr += key->keyidx * 16;
892 		key_len = 16;
893 	}
894 
895 	mt76_wr_copy(dev, addr, key_data, key_len);
896 
897 	addr = mt7603_wtbl1_addr(wcid);
898 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
899 	if (key)
900 		mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
901 	mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
902 
903 	return 0;
904 }
905 
906 static int
907 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
908 		      struct sk_buff *skb, enum mt76_txq_id qid,
909 		      struct mt76_wcid *wcid, struct ieee80211_sta *sta,
910 		      int pid, struct ieee80211_key_conf *key)
911 {
912 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
913 	struct ieee80211_tx_rate *rate = &info->control.rates[0];
914 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
915 	struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
916 	struct ieee80211_vif *vif = info->control.vif;
917 	struct mt76_queue *q = dev->mphy.q_tx[qid];
918 	struct mt7603_vif *mvif;
919 	int wlan_idx;
920 	int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
921 	int tx_count = 8;
922 	u8 frame_type, frame_subtype;
923 	u16 fc = le16_to_cpu(hdr->frame_control);
924 	u16 seqno = 0;
925 	u8 vif_idx = 0;
926 	u32 val;
927 	u8 bw;
928 
929 	if (vif) {
930 		mvif = (struct mt7603_vif *)vif->drv_priv;
931 		vif_idx = mvif->idx;
932 		if (vif_idx && qid >= MT_TXQ_BEACON)
933 			vif_idx += 0x10;
934 	}
935 
936 	if (sta) {
937 		struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
938 
939 		tx_count = msta->rate_count;
940 	}
941 
942 	if (wcid)
943 		wlan_idx = wcid->idx;
944 	else
945 		wlan_idx = MT7603_WTBL_RESERVED;
946 
947 	frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
948 	frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
949 
950 	val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
951 	      FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
952 	txwi[0] = cpu_to_le32(val);
953 
954 	val = MT_TXD1_LONG_FORMAT |
955 	      FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
956 	      FIELD_PREP(MT_TXD1_TID,
957 			 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
958 	      FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
959 	      FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
960 	      FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
961 	      FIELD_PREP(MT_TXD1_PROTECTED, !!key);
962 	txwi[1] = cpu_to_le32(val);
963 
964 	if (info->flags & IEEE80211_TX_CTL_NO_ACK)
965 		txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
966 
967 	val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
968 	      FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
969 	      FIELD_PREP(MT_TXD2_MULTICAST,
970 			 is_multicast_ether_addr(hdr->addr1));
971 	txwi[2] = cpu_to_le32(val);
972 
973 	if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
974 		txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
975 
976 	txwi[4] = 0;
977 
978 	val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
979 	      FIELD_PREP(MT_TXD5_PID, pid);
980 	txwi[5] = cpu_to_le32(val);
981 
982 	txwi[6] = 0;
983 
984 	if (rate->idx >= 0 && rate->count &&
985 	    !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
986 		bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
987 		u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
988 
989 		txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
990 
991 		val = MT_TXD6_FIXED_BW |
992 		      FIELD_PREP(MT_TXD6_BW, bw) |
993 		      FIELD_PREP(MT_TXD6_TX_RATE, rateval);
994 		txwi[6] |= cpu_to_le32(val);
995 
996 		if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
997 			txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
998 
999 		if (!(rate->flags & IEEE80211_TX_RC_MCS))
1000 			txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
1001 
1002 		tx_count = rate->count;
1003 	}
1004 
1005 	/* use maximum tx count for beacons and buffered multicast */
1006 	if (qid >= MT_TXQ_BEACON)
1007 		tx_count = 0x1f;
1008 
1009 	val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
1010 		  MT_TXD3_SN_VALID;
1011 
1012 	if (ieee80211_is_data_qos(hdr->frame_control))
1013 		seqno = le16_to_cpu(hdr->seq_ctrl);
1014 	else if (ieee80211_is_back_req(hdr->frame_control))
1015 		seqno = le16_to_cpu(bar->start_seq_num);
1016 	else
1017 		val &= ~MT_TXD3_SN_VALID;
1018 
1019 	val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4);
1020 
1021 	txwi[3] = cpu_to_le32(val);
1022 
1023 	if (key) {
1024 		u64 pn = atomic64_inc_return(&key->tx_pn);
1025 
1026 		txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
1027 		txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
1028 		txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
1029 	}
1030 
1031 	txwi[7] = 0;
1032 
1033 	return 0;
1034 }
1035 
1036 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1037 			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
1038 			  struct ieee80211_sta *sta,
1039 			  struct mt76_tx_info *tx_info)
1040 {
1041 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1042 	struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid);
1043 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1044 	struct ieee80211_key_conf *key = info->control.hw_key;
1045 	int pid;
1046 
1047 	if (!wcid)
1048 		wcid = &dev->global_sta.wcid;
1049 
1050 	if (sta) {
1051 		msta = (struct mt7603_sta *)sta->drv_priv;
1052 
1053 		if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER |
1054 				    IEEE80211_TX_CTL_CLEAR_PS_FILT)) ||
1055 		    (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE))
1056 			mt7603_wtbl_set_ps(dev, msta, false);
1057 
1058 		mt76_tx_check_agg_ssn(sta, tx_info->skb);
1059 	}
1060 
1061 	pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1062 
1063 	if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
1064 		spin_lock_bh(&dev->mt76.lock);
1065 		mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],
1066 				      msta->rates);
1067 		msta->rate_probe = true;
1068 		spin_unlock_bh(&dev->mt76.lock);
1069 	}
1070 
1071 	mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid,
1072 			      sta, pid, key);
1073 
1074 	return 0;
1075 }
1076 
1077 static bool
1078 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
1079 		struct ieee80211_tx_info *info, __le32 *txs_data)
1080 {
1081 	struct ieee80211_supported_band *sband;
1082 	struct mt7603_rate_set *rs;
1083 	int first_idx = 0, last_idx;
1084 	u32 rate_set_tsf;
1085 	u32 final_rate;
1086 	u32 final_rate_flags;
1087 	bool rs_idx;
1088 	bool ack_timeout;
1089 	bool fixed_rate;
1090 	bool probe;
1091 	bool ampdu;
1092 	bool cck = false;
1093 	int count;
1094 	u32 txs;
1095 	int idx;
1096 	int i;
1097 
1098 	fixed_rate = info->status.rates[0].count;
1099 	probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1100 
1101 	txs = le32_to_cpu(txs_data[4]);
1102 	ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
1103 	count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
1104 	last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs);
1105 
1106 	txs = le32_to_cpu(txs_data[0]);
1107 	final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1108 	ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1109 
1110 	if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1111 		return false;
1112 
1113 	if (txs & MT_TXS0_QUEUE_TIMEOUT)
1114 		return false;
1115 
1116 	if (!ack_timeout)
1117 		info->flags |= IEEE80211_TX_STAT_ACK;
1118 
1119 	info->status.ampdu_len = 1;
1120 	info->status.ampdu_ack_len = !!(info->flags &
1121 					IEEE80211_TX_STAT_ACK);
1122 
1123 	if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1124 		info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1125 
1126 	first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY);
1127 
1128 	if (fixed_rate && !probe) {
1129 		info->status.rates[0].count = count;
1130 		i = 0;
1131 		goto out;
1132 	}
1133 
1134 	rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1135 	rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) -
1136 			 rate_set_tsf) < 1000000);
1137 	rs_idx ^= rate_set_tsf & BIT(0);
1138 	rs = &sta->rateset[rs_idx];
1139 
1140 	if (!first_idx && rs->probe_rate.idx >= 0) {
1141 		info->status.rates[0] = rs->probe_rate;
1142 
1143 		spin_lock_bh(&dev->mt76.lock);
1144 		if (sta->rate_probe) {
1145 			mt7603_wtbl_set_rates(dev, sta, NULL,
1146 					      sta->rates);
1147 			sta->rate_probe = false;
1148 		}
1149 		spin_unlock_bh(&dev->mt76.lock);
1150 	} else {
1151 		info->status.rates[0] = rs->rates[first_idx / 2];
1152 	}
1153 	info->status.rates[0].count = 0;
1154 
1155 	for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1156 		struct ieee80211_tx_rate *cur_rate;
1157 		int cur_count;
1158 
1159 		cur_rate = &rs->rates[idx / 2];
1160 		cur_count = min_t(int, MT7603_RATE_RETRY, count);
1161 		count -= cur_count;
1162 
1163 		if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1164 			    cur_rate->flags != info->status.rates[i].flags)) {
1165 			i++;
1166 			if (i == ARRAY_SIZE(info->status.rates)) {
1167 				i--;
1168 				break;
1169 			}
1170 
1171 			info->status.rates[i] = *cur_rate;
1172 			info->status.rates[i].count = 0;
1173 		}
1174 
1175 		info->status.rates[i].count += cur_count;
1176 	}
1177 
1178 out:
1179 	final_rate_flags = info->status.rates[i].flags;
1180 
1181 	switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1182 	case MT_PHY_TYPE_CCK:
1183 		cck = true;
1184 		fallthrough;
1185 	case MT_PHY_TYPE_OFDM:
1186 		if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ)
1187 			sband = &dev->mphy.sband_5g.sband;
1188 		else
1189 			sband = &dev->mphy.sband_2g.sband;
1190 		final_rate &= GENMASK(5, 0);
1191 		final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1192 					   cck);
1193 		final_rate_flags = 0;
1194 		break;
1195 	case MT_PHY_TYPE_HT_GF:
1196 	case MT_PHY_TYPE_HT:
1197 		final_rate_flags |= IEEE80211_TX_RC_MCS;
1198 		final_rate &= GENMASK(5, 0);
1199 		if (final_rate > 15)
1200 			return false;
1201 		break;
1202 	default:
1203 		return false;
1204 	}
1205 
1206 	info->status.rates[i].idx = final_rate;
1207 	info->status.rates[i].flags = final_rate_flags;
1208 
1209 	return true;
1210 }
1211 
1212 static bool
1213 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
1214 		       __le32 *txs_data)
1215 {
1216 	struct mt76_dev *mdev = &dev->mt76;
1217 	struct sk_buff_head list;
1218 	struct sk_buff *skb;
1219 
1220 	if (pid < MT_PACKET_ID_FIRST)
1221 		return false;
1222 
1223 	trace_mac_txdone(mdev, sta->wcid.idx, pid);
1224 
1225 	mt76_tx_status_lock(mdev, &list);
1226 	skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1227 	if (skb) {
1228 		struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1229 
1230 		if (!mt7603_fill_txs(dev, sta, info, txs_data)) {
1231 			info->status.rates[0].count = 0;
1232 			info->status.rates[0].idx = -1;
1233 		}
1234 
1235 		mt76_tx_status_skb_done(mdev, skb, &list);
1236 	}
1237 	mt76_tx_status_unlock(mdev, &list);
1238 
1239 	return !!skb;
1240 }
1241 
1242 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
1243 {
1244 	struct ieee80211_tx_info info = {};
1245 	struct ieee80211_sta *sta = NULL;
1246 	struct mt7603_sta *msta = NULL;
1247 	struct mt76_wcid *wcid;
1248 	__le32 *txs_data = data;
1249 	u8 wcidx;
1250 	u8 pid;
1251 
1252 	pid = le32_get_bits(txs_data[4], MT_TXS4_PID);
1253 	wcidx = le32_get_bits(txs_data[3], MT_TXS3_WCID);
1254 
1255 	if (pid == MT_PACKET_ID_NO_ACK)
1256 		return;
1257 
1258 	if (wcidx >= MT7603_WTBL_SIZE)
1259 		return;
1260 
1261 	rcu_read_lock();
1262 
1263 	wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1264 	if (!wcid)
1265 		goto out;
1266 
1267 	msta = container_of(wcid, struct mt7603_sta, wcid);
1268 	sta = wcid_to_sta(wcid);
1269 
1270 	if (list_empty(&msta->poll_list)) {
1271 		spin_lock_bh(&dev->sta_poll_lock);
1272 		list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1273 		spin_unlock_bh(&dev->sta_poll_lock);
1274 	}
1275 
1276 	if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data))
1277 		goto out;
1278 
1279 	if (wcidx >= MT7603_WTBL_STA || !sta)
1280 		goto out;
1281 
1282 	if (mt7603_fill_txs(dev, msta, &info, txs_data))
1283 		ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1284 
1285 out:
1286 	rcu_read_unlock();
1287 }
1288 
1289 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1290 {
1291 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1292 	struct sk_buff *skb = e->skb;
1293 
1294 	if (!e->txwi) {
1295 		dev_kfree_skb_any(skb);
1296 		return;
1297 	}
1298 
1299 	dev->tx_hang_check = 0;
1300 	mt76_tx_complete_skb(mdev, e->wcid, skb);
1301 }
1302 
1303 static bool
1304 wait_for_wpdma(struct mt7603_dev *dev)
1305 {
1306 	return mt76_poll(dev, MT_WPDMA_GLO_CFG,
1307 			 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
1308 			 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
1309 			 0, 1000);
1310 }
1311 
1312 static void mt7603_pse_reset(struct mt7603_dev *dev)
1313 {
1314 	/* Clear previous reset result */
1315 	if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1316 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
1317 
1318 	/* Reset PSE */
1319 	mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1320 
1321 	if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
1322 			    MT_MCU_DEBUG_RESET_PSE_S,
1323 			    MT_MCU_DEBUG_RESET_PSE_S, 500)) {
1324 		dev->reset_cause[RESET_CAUSE_RESET_FAILED]++;
1325 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1326 	} else {
1327 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1328 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
1329 	}
1330 
1331 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3)
1332 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1333 }
1334 
1335 void mt7603_mac_dma_start(struct mt7603_dev *dev)
1336 {
1337 	mt7603_mac_start(dev);
1338 
1339 	wait_for_wpdma(dev);
1340 	usleep_range(50, 100);
1341 
1342 	mt76_set(dev, MT_WPDMA_GLO_CFG,
1343 		 (MT_WPDMA_GLO_CFG_TX_DMA_EN |
1344 		  MT_WPDMA_GLO_CFG_RX_DMA_EN |
1345 		  FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
1346 		  MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
1347 
1348 	mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
1349 }
1350 
1351 void mt7603_mac_start(struct mt7603_dev *dev)
1352 {
1353 	mt76_clear(dev, MT_ARB_SCR,
1354 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1355 	mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
1356 	mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1357 }
1358 
1359 void mt7603_mac_stop(struct mt7603_dev *dev)
1360 {
1361 	mt76_set(dev, MT_ARB_SCR,
1362 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1363 	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
1364 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1365 }
1366 
1367 void mt7603_pse_client_reset(struct mt7603_dev *dev)
1368 {
1369 	u32 addr;
1370 
1371 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR +
1372 				   MT_CLIENT_RESET_TX);
1373 
1374 	/* Clear previous reset state */
1375 	mt76_clear(dev, addr,
1376 		   MT_CLIENT_RESET_TX_R_E_1 |
1377 		   MT_CLIENT_RESET_TX_R_E_2 |
1378 		   MT_CLIENT_RESET_TX_R_E_1_S |
1379 		   MT_CLIENT_RESET_TX_R_E_2_S);
1380 
1381 	/* Start PSE client TX abort */
1382 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);
1383 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
1384 		       MT_CLIENT_RESET_TX_R_E_1_S, 500);
1385 
1386 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);
1387 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
1388 
1389 	/* Wait for PSE client to clear TX FIFO */
1390 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
1391 		       MT_CLIENT_RESET_TX_R_E_2_S, 500);
1392 
1393 	/* Clear PSE client TX abort state */
1394 	mt76_clear(dev, addr,
1395 		   MT_CLIENT_RESET_TX_R_E_1 |
1396 		   MT_CLIENT_RESET_TX_R_E_2);
1397 }
1398 
1399 static void mt7603_dma_sched_reset(struct mt7603_dev *dev)
1400 {
1401 	if (!is_mt7628(dev))
1402 		return;
1403 
1404 	mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
1405 	mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
1406 }
1407 
1408 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
1409 {
1410 	int beacon_int = dev->mt76.beacon_int;
1411 	u32 mask = dev->mt76.mmio.irqmask;
1412 	int i;
1413 
1414 	ieee80211_stop_queues(dev->mt76.hw);
1415 	set_bit(MT76_RESET, &dev->mphy.state);
1416 
1417 	/* lock/unlock all queues to ensure that no tx is pending */
1418 	mt76_txq_schedule_all(&dev->mphy);
1419 
1420 	mt76_worker_disable(&dev->mt76.tx_worker);
1421 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
1422 	napi_disable(&dev->mt76.napi[0]);
1423 	napi_disable(&dev->mt76.napi[1]);
1424 	napi_disable(&dev->mt76.tx_napi);
1425 
1426 	mutex_lock(&dev->mt76.mutex);
1427 
1428 	mt7603_beacon_set_timer(dev, -1, 0);
1429 
1430 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] ||
1431 	    dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY ||
1432 	    dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK ||
1433 	    dev->cur_reset_cause == RESET_CAUSE_TX_HANG)
1434 		mt7603_pse_reset(dev);
1435 
1436 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1437 		goto skip_dma_reset;
1438 
1439 	mt7603_mac_stop(dev);
1440 
1441 	mt76_clear(dev, MT_WPDMA_GLO_CFG,
1442 		   MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1443 		   MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1444 	usleep_range(1000, 2000);
1445 
1446 	mt7603_irq_disable(dev, mask);
1447 
1448 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
1449 
1450 	mt7603_pse_client_reset(dev);
1451 
1452 	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
1453 	for (i = 0; i < __MT_TXQ_MAX; i++)
1454 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1455 
1456 	mt76_for_each_q_rx(&dev->mt76, i) {
1457 		mt76_queue_rx_reset(dev, i);
1458 	}
1459 
1460 	mt76_tx_status_check(&dev->mt76, true);
1461 
1462 	mt7603_dma_sched_reset(dev);
1463 
1464 	mt7603_mac_dma_start(dev);
1465 
1466 	mt7603_irq_enable(dev, mask);
1467 
1468 skip_dma_reset:
1469 	clear_bit(MT76_RESET, &dev->mphy.state);
1470 	mutex_unlock(&dev->mt76.mutex);
1471 
1472 	mt76_worker_enable(&dev->mt76.tx_worker);
1473 
1474 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
1475 	mt7603_beacon_set_timer(dev, -1, beacon_int);
1476 
1477 	local_bh_disable();
1478 	napi_enable(&dev->mt76.tx_napi);
1479 	napi_schedule(&dev->mt76.tx_napi);
1480 
1481 	napi_enable(&dev->mt76.napi[0]);
1482 	napi_schedule(&dev->mt76.napi[0]);
1483 
1484 	napi_enable(&dev->mt76.napi[1]);
1485 	napi_schedule(&dev->mt76.napi[1]);
1486 	local_bh_enable();
1487 
1488 	ieee80211_wake_queues(dev->mt76.hw);
1489 	mt76_txq_schedule_all(&dev->mphy);
1490 }
1491 
1492 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index)
1493 {
1494 	u32 val;
1495 
1496 	mt76_wr(dev, MT_WPDMA_DEBUG,
1497 		FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) |
1498 		MT_WPDMA_DEBUG_SEL);
1499 
1500 	val = mt76_rr(dev, MT_WPDMA_DEBUG);
1501 	return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val);
1502 }
1503 
1504 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev)
1505 {
1506 	if (is_mt7628(dev))
1507 		return mt7603_dma_debug(dev, 9) & BIT(9);
1508 
1509 	return mt7603_dma_debug(dev, 2) & BIT(8);
1510 }
1511 
1512 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev)
1513 {
1514 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY))
1515 		return false;
1516 
1517 	return mt7603_rx_fifo_busy(dev);
1518 }
1519 
1520 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
1521 {
1522 	u32 val;
1523 
1524 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY))
1525 		return false;
1526 
1527 	val = mt7603_dma_debug(dev, 9);
1528 	return (val & BIT(8)) && (val & 0xf) != 0xf;
1529 }
1530 
1531 static bool mt7603_tx_hang(struct mt7603_dev *dev)
1532 {
1533 	struct mt76_queue *q;
1534 	u32 dma_idx, prev_dma_idx;
1535 	int i;
1536 
1537 	for (i = 0; i < 4; i++) {
1538 		q = dev->mphy.q_tx[i];
1539 
1540 		if (!q->queued)
1541 			continue;
1542 
1543 		prev_dma_idx = dev->tx_dma_idx[i];
1544 		dma_idx = readl(&q->regs->dma_idx);
1545 		dev->tx_dma_idx[i] = dma_idx;
1546 
1547 		if (dma_idx == prev_dma_idx &&
1548 		    dma_idx != readl(&q->regs->cpu_idx))
1549 			break;
1550 	}
1551 
1552 	return i < 4;
1553 }
1554 
1555 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev)
1556 {
1557 	u32 addr, val;
1558 
1559 	if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES)
1560 		return true;
1561 
1562 	if (mt7603_rx_fifo_busy(dev))
1563 		return false;
1564 
1565 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS);
1566 	mt76_wr(dev, addr, 3);
1567 	val = mt76_rr(dev, addr) >> 16;
1568 
1569 	if (is_mt7628(dev) && (val & 0x4001) == 0x4001)
1570 		return true;
1571 
1572 	return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001;
1573 }
1574 
1575 static bool
1576 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter,
1577 		      enum mt7603_reset_cause cause,
1578 		      bool (*check)(struct mt7603_dev *dev))
1579 {
1580 	if (dev->reset_test == cause + 1) {
1581 		dev->reset_test = 0;
1582 		goto trigger;
1583 	}
1584 
1585 	if (check) {
1586 		if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) {
1587 			*counter = 0;
1588 			return false;
1589 		}
1590 
1591 		(*counter)++;
1592 	}
1593 
1594 	if (*counter < MT7603_WATCHDOG_TIMEOUT)
1595 		return false;
1596 trigger:
1597 	dev->cur_reset_cause = cause;
1598 	dev->reset_cause[cause]++;
1599 	return true;
1600 }
1601 
1602 void mt7603_update_channel(struct mt76_phy *mphy)
1603 {
1604 	struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76);
1605 	struct mt76_channel_state *state;
1606 
1607 	state = mphy->chan_state;
1608 	state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA);
1609 }
1610 
1611 void
1612 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val)
1613 {
1614 	u32 rxtd_6 = 0xd7c80000;
1615 
1616 	if (val == dev->ed_strict_mode)
1617 		return;
1618 
1619 	dev->ed_strict_mode = val;
1620 
1621 	/* Ensure that ED/CCA does not trigger if disabled */
1622 	if (!dev->ed_monitor)
1623 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);
1624 	else
1625 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);
1626 
1627 	if (dev->ed_monitor && !dev->ed_strict_mode)
1628 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);
1629 	else
1630 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);
1631 
1632 	mt76_wr(dev, MT_RXTD(6), rxtd_6);
1633 
1634 	mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
1635 		       dev->ed_monitor && !dev->ed_strict_mode);
1636 }
1637 
1638 static void
1639 mt7603_edcca_check(struct mt7603_dev *dev)
1640 {
1641 	u32 val = mt76_rr(dev, MT_AGC(41));
1642 	ktime_t cur_time;
1643 	int rssi0, rssi1;
1644 	u32 active;
1645 	u32 ed_busy;
1646 
1647 	if (!dev->ed_monitor)
1648 		return;
1649 
1650 	rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val);
1651 	if (rssi0 > 128)
1652 		rssi0 -= 256;
1653 
1654 	if (dev->mphy.antenna_mask & BIT(1)) {
1655 		rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val);
1656 		if (rssi1 > 128)
1657 			rssi1 -= 256;
1658 	} else {
1659 		rssi1 = rssi0;
1660 	}
1661 
1662 	if (max(rssi0, rssi1) >= -40 &&
1663 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH)
1664 		dev->ed_strong_signal++;
1665 	else if (dev->ed_strong_signal > 0)
1666 		dev->ed_strong_signal--;
1667 
1668 	cur_time = ktime_get_boottime();
1669 	ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK;
1670 
1671 	active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1672 	dev->ed_time = cur_time;
1673 
1674 	if (!active)
1675 		return;
1676 
1677 	if (100 * ed_busy / active > 90) {
1678 		if (dev->ed_trigger < 0)
1679 			dev->ed_trigger = 0;
1680 		dev->ed_trigger++;
1681 	} else {
1682 		if (dev->ed_trigger > 0)
1683 			dev->ed_trigger = 0;
1684 		dev->ed_trigger--;
1685 	}
1686 
1687 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH ||
1688 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) {
1689 		mt7603_edcca_set_strict(dev, true);
1690 	} else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) {
1691 		mt7603_edcca_set_strict(dev, false);
1692 	}
1693 
1694 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH)
1695 		dev->ed_trigger = MT7603_EDCCA_BLOCK_TH;
1696 	else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH)
1697 		dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH;
1698 }
1699 
1700 void mt7603_cca_stats_reset(struct mt7603_dev *dev)
1701 {
1702 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1703 	mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1704 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);
1705 }
1706 
1707 static void
1708 mt7603_adjust_sensitivity(struct mt7603_dev *dev)
1709 {
1710 	u32 agc0 = dev->agc0, agc3 = dev->agc3;
1711 	u32 adj;
1712 
1713 	if (!dev->sensitivity || dev->sensitivity < -100) {
1714 		dev->sensitivity = 0;
1715 	} else if (dev->sensitivity <= -84) {
1716 		adj = 7 + (dev->sensitivity + 92) / 2;
1717 
1718 		agc0 = 0x56f0076f;
1719 		agc0 |= adj << 12;
1720 		agc0 |= adj << 16;
1721 		agc3 = 0x81d0d5e3;
1722 	} else if (dev->sensitivity <= -72) {
1723 		adj = 7 + (dev->sensitivity + 80) / 2;
1724 
1725 		agc0 = 0x6af0006f;
1726 		agc0 |= adj << 8;
1727 		agc0 |= adj << 12;
1728 		agc0 |= adj << 16;
1729 
1730 		agc3 = 0x8181d5e3;
1731 	} else {
1732 		if (dev->sensitivity > -54)
1733 			dev->sensitivity = -54;
1734 
1735 		adj = 7 + (dev->sensitivity + 80) / 2;
1736 
1737 		agc0 = 0x7ff0000f;
1738 		agc0 |= adj << 4;
1739 		agc0 |= adj << 8;
1740 		agc0 |= adj << 12;
1741 		agc0 |= adj << 16;
1742 
1743 		agc3 = 0x818181e3;
1744 	}
1745 
1746 	mt76_wr(dev, MT_AGC(0), agc0);
1747 	mt76_wr(dev, MT_AGC1(0), agc0);
1748 
1749 	mt76_wr(dev, MT_AGC(3), agc3);
1750 	mt76_wr(dev, MT_AGC1(3), agc3);
1751 }
1752 
1753 static void
1754 mt7603_false_cca_check(struct mt7603_dev *dev)
1755 {
1756 	int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm;
1757 	int false_cca;
1758 	int min_signal;
1759 	u32 val;
1760 
1761 	if (!dev->dynamic_sensitivity)
1762 		return;
1763 
1764 	val = mt76_rr(dev, MT_PHYCTRL_STAT_PD);
1765 	pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val);
1766 	pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val);
1767 
1768 	val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY);
1769 	mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val);
1770 	mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val);
1771 
1772 	dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1773 	dev->false_cca_cck = pd_cck - mdrdy_cck;
1774 
1775 	mt7603_cca_stats_reset(dev);
1776 
1777 	min_signal = mt76_get_min_avg_rssi(&dev->mt76, false);
1778 	if (!min_signal) {
1779 		dev->sensitivity = 0;
1780 		dev->last_cca_adj = jiffies;
1781 		goto out;
1782 	}
1783 
1784 	min_signal -= 15;
1785 
1786 	false_cca = dev->false_cca_ofdm + dev->false_cca_cck;
1787 	if (false_cca > 600 &&
1788 	    dev->sensitivity < -100 + dev->sensitivity_limit) {
1789 		if (!dev->sensitivity)
1790 			dev->sensitivity = -92;
1791 		else
1792 			dev->sensitivity += 2;
1793 		dev->last_cca_adj = jiffies;
1794 	} else if (false_cca < 100 ||
1795 		   time_after(jiffies, dev->last_cca_adj + 10 * HZ)) {
1796 		dev->last_cca_adj = jiffies;
1797 		if (!dev->sensitivity)
1798 			goto out;
1799 
1800 		dev->sensitivity -= 2;
1801 	}
1802 
1803 	if (dev->sensitivity && dev->sensitivity > min_signal) {
1804 		dev->sensitivity = min_signal;
1805 		dev->last_cca_adj = jiffies;
1806 	}
1807 
1808 out:
1809 	mt7603_adjust_sensitivity(dev);
1810 }
1811 
1812 void mt7603_mac_work(struct work_struct *work)
1813 {
1814 	struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
1815 					      mphy.mac_work.work);
1816 	bool reset = false;
1817 	int i, idx;
1818 
1819 	mt76_tx_status_check(&dev->mt76, false);
1820 
1821 	mutex_lock(&dev->mt76.mutex);
1822 
1823 	dev->mphy.mac_work_count++;
1824 	mt76_update_survey(&dev->mphy);
1825 	mt7603_edcca_check(dev);
1826 
1827 	for (i = 0, idx = 0; i < 2; i++) {
1828 		u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1829 
1830 		dev->mt76.aggr_stats[idx++] += val & 0xffff;
1831 		dev->mt76.aggr_stats[idx++] += val >> 16;
1832 	}
1833 
1834 	if (dev->mphy.mac_work_count == 10)
1835 		mt7603_false_cca_check(dev);
1836 
1837 	if (mt7603_watchdog_check(dev, &dev->rx_pse_check,
1838 				  RESET_CAUSE_RX_PSE_BUSY,
1839 				  mt7603_rx_pse_busy) ||
1840 	    mt7603_watchdog_check(dev, &dev->beacon_check,
1841 				  RESET_CAUSE_BEACON_STUCK,
1842 				  NULL) ||
1843 	    mt7603_watchdog_check(dev, &dev->tx_hang_check,
1844 				  RESET_CAUSE_TX_HANG,
1845 				  mt7603_tx_hang) ||
1846 	    mt7603_watchdog_check(dev, &dev->tx_dma_check,
1847 				  RESET_CAUSE_TX_BUSY,
1848 				  mt7603_tx_dma_busy) ||
1849 	    mt7603_watchdog_check(dev, &dev->rx_dma_check,
1850 				  RESET_CAUSE_RX_BUSY,
1851 				  mt7603_rx_dma_busy) ||
1852 	    mt7603_watchdog_check(dev, &dev->mcu_hang,
1853 				  RESET_CAUSE_MCU_HANG,
1854 				  NULL) ||
1855 	    dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1856 		dev->beacon_check = 0;
1857 		dev->tx_dma_check = 0;
1858 		dev->tx_hang_check = 0;
1859 		dev->rx_dma_check = 0;
1860 		dev->rx_pse_check = 0;
1861 		dev->mcu_hang = 0;
1862 		dev->rx_dma_idx = ~0;
1863 		memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
1864 		reset = true;
1865 		dev->mphy.mac_work_count = 0;
1866 	}
1867 
1868 	if (dev->mphy.mac_work_count >= 10)
1869 		dev->mphy.mac_work_count = 0;
1870 
1871 	mutex_unlock(&dev->mt76.mutex);
1872 
1873 	if (reset)
1874 		mt7603_mac_watchdog_reset(dev);
1875 
1876 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1877 				     msecs_to_jiffies(MT7603_WATCHDOG_TIME));
1878 }
1879