1 // SPDX-License-Identifier: ISC
2 
3 #include <linux/etherdevice.h>
4 #include <linux/timekeeping.h>
5 #include "mt7603.h"
6 #include "mac.h"
7 #include "../trace.h"
8 
9 #define MT_PSE_PAGE_SIZE	128
10 
11 static u32
12 mt7603_ac_queue_mask0(u32 mask)
13 {
14 	u32 ret = 0;
15 
16 	ret |= GENMASK(3, 0) * !!(mask & BIT(0));
17 	ret |= GENMASK(8, 5) * !!(mask & BIT(1));
18 	ret |= GENMASK(13, 10) * !!(mask & BIT(2));
19 	ret |= GENMASK(19, 16) * !!(mask & BIT(3));
20 	return ret;
21 }
22 
23 static void
24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
25 {
26 	mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
27 }
28 
29 static void
30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
31 {
32 	mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
33 }
34 
35 void mt7603_mac_reset_counters(struct mt7603_dev *dev)
36 {
37 	int i;
38 
39 	for (i = 0; i < 2; i++)
40 		mt76_rr(dev, MT_TX_AGG_CNT(i));
41 
42 	memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
43 }
44 
45 void mt7603_mac_set_timing(struct mt7603_dev *dev)
46 {
47 	u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
48 		  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
49 	u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
50 		   FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24);
51 	int offset = 3 * dev->coverage_class;
52 	u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
53 			 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
54 	bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ;
55 	int sifs;
56 	u32 val;
57 
58 	if (is_5ghz)
59 		sifs = 16;
60 	else
61 		sifs = 10;
62 
63 	mt76_set(dev, MT_ARB_SCR,
64 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
65 	udelay(1);
66 
67 	mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
68 	mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
69 	mt76_wr(dev, MT_IFS,
70 		FIELD_PREP(MT_IFS_EIFS, 360) |
71 		FIELD_PREP(MT_IFS_RIFS, 2) |
72 		FIELD_PREP(MT_IFS_SIFS, sifs) |
73 		FIELD_PREP(MT_IFS_SLOT, dev->slottime));
74 
75 	if (dev->slottime < 20 || is_5ghz)
76 		val = MT7603_CFEND_RATE_DEFAULT;
77 	else
78 		val = MT7603_CFEND_RATE_11B;
79 
80 	mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
81 
82 	mt76_clear(dev, MT_ARB_SCR,
83 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
84 }
85 
86 static void
87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
88 {
89 	mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
90 		 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
91 
92 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
93 }
94 
95 static u32
96 mt7603_wtbl1_addr(int idx)
97 {
98 	return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
99 }
100 
101 static u32
102 mt7603_wtbl2_addr(int idx)
103 {
104 	/* Mapped to WTBL2 */
105 	return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
106 }
107 
108 static u32
109 mt7603_wtbl3_addr(int idx)
110 {
111 	u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
112 
113 	return base + idx * MT_WTBL3_SIZE;
114 }
115 
116 static u32
117 mt7603_wtbl4_addr(int idx)
118 {
119 	u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
120 
121 	return base + idx * MT_WTBL4_SIZE;
122 }
123 
124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
125 		      const u8 *mac_addr)
126 {
127 	const void *_mac = mac_addr;
128 	u32 addr = mt7603_wtbl1_addr(idx);
129 	u32 w0 = 0, w1 = 0;
130 	int i;
131 
132 	if (_mac) {
133 		w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI,
134 				get_unaligned_le16(_mac + 4));
135 		w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO,
136 				get_unaligned_le32(_mac));
137 	}
138 
139 	if (vif < 0)
140 		vif = 0;
141 	else
142 		w0 |= MT_WTBL1_W0_RX_CHECK_A1;
143 	w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif);
144 
145 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
146 
147 	mt76_set(dev, addr + 0 * 4, w0);
148 	mt76_set(dev, addr + 1 * 4, w1);
149 	mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
150 
151 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
152 	addr = mt7603_wtbl2_addr(idx);
153 	for (i = 0; i < MT_WTBL2_SIZE; i += 4)
154 		mt76_wr(dev, addr + i, 0);
155 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
156 	mt76_start_tx_ac(dev, GENMASK(3, 0));
157 
158 	addr = mt7603_wtbl3_addr(idx);
159 	for (i = 0; i < MT_WTBL3_SIZE; i += 4)
160 		mt76_wr(dev, addr + i, 0);
161 
162 	addr = mt7603_wtbl4_addr(idx);
163 	for (i = 0; i < MT_WTBL4_SIZE; i += 4)
164 		mt76_wr(dev, addr + i, 0);
165 
166 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
167 }
168 
169 static void
170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
171 {
172 	u32 addr = mt7603_wtbl1_addr(idx);
173 	u32 val = mt76_rr(dev, addr + 3 * 4);
174 
175 	val &= ~MT_WTBL1_W3_SKIP_TX;
176 	val |= enabled * MT_WTBL1_W3_SKIP_TX;
177 
178 	mt76_wr(dev, addr + 3 * 4, val);
179 }
180 
181 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
182 {
183 	int i, port, queue;
184 
185 	if (abort) {
186 		port = 3; /* PSE */
187 		queue = 8; /* free queue */
188 	} else {
189 		port = 0; /* HIF */
190 		queue = 1; /* MCU queue */
191 	}
192 
193 	mt7603_wtbl_set_skip_tx(dev, idx, true);
194 
195 	mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
196 			FIELD_PREP(MT_TX_ABORT_WCID, idx));
197 
198 	for (i = 0; i < 4; i++) {
199 		mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
200 			FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
201 			FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) |
202 			FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
203 			FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
204 
205 		mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 15000);
206 	}
207 
208 	WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY);
209 
210 	mt76_wr(dev, MT_TX_ABORT, 0);
211 
212 	mt7603_wtbl_set_skip_tx(dev, idx, false);
213 }
214 
215 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
216 			  bool enabled)
217 {
218 	u32 addr = mt7603_wtbl1_addr(sta->wcid.idx);
219 
220 	if (sta->smps == enabled)
221 		return;
222 
223 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
224 	sta->smps = enabled;
225 }
226 
227 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
228 			bool enabled)
229 {
230 	int idx = sta->wcid.idx;
231 	u32 addr;
232 
233 	spin_lock_bh(&dev->ps_lock);
234 
235 	if (sta->ps == enabled)
236 		goto out;
237 
238 	mt76_wr(dev, MT_PSE_RTA,
239 		FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) |
240 		FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |
241 		FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) |
242 		FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) |
243 		MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY);
244 
245 	mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
246 
247 	if (enabled)
248 		mt7603_filter_tx(dev, idx, false);
249 
250 	addr = mt7603_wtbl1_addr(idx);
251 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
252 	mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
253 		 enabled * MT_WTBL1_W3_POWER_SAVE);
254 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
255 	sta->ps = enabled;
256 
257 out:
258 	spin_unlock_bh(&dev->ps_lock);
259 }
260 
261 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
262 {
263 	int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE;
264 	int wtbl2_frame = idx / wtbl2_frame_size;
265 	int wtbl2_entry = idx % wtbl2_frame_size;
266 
267 	int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE;
268 	int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE;
269 	int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size;
270 	int wtbl3_entry = (idx % wtbl3_frame_size) * 2;
271 
272 	int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE;
273 	int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE;
274 	int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size;
275 	int wtbl4_entry = idx % wtbl4_frame_size;
276 
277 	u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
278 	int i;
279 
280 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
281 
282 	mt76_wr(dev, addr + 0 * 4,
283 		MT_WTBL1_W0_RX_CHECK_A1 |
284 		MT_WTBL1_W0_RX_CHECK_A2 |
285 		MT_WTBL1_W0_RX_VALID);
286 	mt76_wr(dev, addr + 1 * 4, 0);
287 	mt76_wr(dev, addr + 2 * 4, 0);
288 
289 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
290 
291 	mt76_wr(dev, addr + 3 * 4,
292 		FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
293 		FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
294 		FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
295 		MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
296 	mt76_wr(dev, addr + 4 * 4,
297 		FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
298 		FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
299 		FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
300 
301 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
302 
303 	addr = mt7603_wtbl2_addr(idx);
304 
305 	/* Clear BA information */
306 	mt76_wr(dev, addr + (15 * 4), 0);
307 
308 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
309 	for (i = 2; i <= 4; i++)
310 		mt76_wr(dev, addr + (i * 4), 0);
311 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
312 	mt76_start_tx_ac(dev, GENMASK(3, 0));
313 
314 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
315 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
316 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
317 }
318 
319 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
320 {
321 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
322 	int idx = msta->wcid.idx;
323 	u8 ampdu_density;
324 	u32 addr;
325 	u32 val;
326 
327 	addr = mt7603_wtbl1_addr(idx);
328 
329 	ampdu_density = sta->ht_cap.ampdu_density;
330 	if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
331 		ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
332 
333 	val = mt76_rr(dev, addr + 2 * 4);
334 	val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
335 	val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) |
336 	       FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) |
337 	       MT_WTBL1_W2_TXS_BAF_REPORT;
338 
339 	if (sta->ht_cap.cap)
340 		val |= MT_WTBL1_W2_HT;
341 	if (sta->vht_cap.cap)
342 		val |= MT_WTBL1_W2_VHT;
343 
344 	mt76_wr(dev, addr + 2 * 4, val);
345 
346 	addr = mt7603_wtbl2_addr(idx);
347 	val = mt76_rr(dev, addr + 9 * 4);
348 	val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
349 		 MT_WTBL2_W9_SHORT_GI_80);
350 	if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
351 		val |= MT_WTBL2_W9_SHORT_GI_20;
352 	if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
353 		val |= MT_WTBL2_W9_SHORT_GI_40;
354 	mt76_wr(dev, addr + 9 * 4, val);
355 }
356 
357 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
358 {
359 	mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
360 	mt76_wr(dev, MT_BA_CONTROL_1,
361 		(get_unaligned_le16(addr + 4) |
362 		 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
363 		 MT_BA_CONTROL_1_RESET));
364 }
365 
366 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
367 			    int ba_size)
368 {
369 	u32 addr = mt7603_wtbl2_addr(wcid);
370 	u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
371 		       (MT_WTBL2_W15_BA_WIN_SIZE <<
372 			(tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
373 	u32 tid_val;
374 	int i;
375 
376 	if (ba_size < 0) {
377 		/* disable */
378 		mt76_clear(dev, addr + (15 * 4), tid_mask);
379 		return;
380 	}
381 
382 	for (i = 7; i > 0; i--) {
383 		if (ba_size >= MT_AGG_SIZE_LIMIT(i))
384 			break;
385 	}
386 
387 	tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
388 		  i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
389 
390 	mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
391 }
392 
393 void mt7603_mac_sta_poll(struct mt7603_dev *dev)
394 {
395 	static const u8 ac_to_tid[4] = {
396 		[IEEE80211_AC_BE] = 0,
397 		[IEEE80211_AC_BK] = 1,
398 		[IEEE80211_AC_VI] = 4,
399 		[IEEE80211_AC_VO] = 6
400 	};
401 	struct ieee80211_sta *sta;
402 	struct mt7603_sta *msta;
403 	u32 total_airtime = 0;
404 	u32 airtime[4];
405 	u32 addr;
406 	int i;
407 
408 	rcu_read_lock();
409 
410 	while (1) {
411 		bool clear = false;
412 
413 		spin_lock_bh(&dev->sta_poll_lock);
414 		if (list_empty(&dev->sta_poll_list)) {
415 			spin_unlock_bh(&dev->sta_poll_lock);
416 			break;
417 		}
418 
419 		msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta,
420 					poll_list);
421 		list_del_init(&msta->poll_list);
422 		spin_unlock_bh(&dev->sta_poll_lock);
423 
424 		addr = mt7603_wtbl4_addr(msta->wcid.idx);
425 		for (i = 0; i < 4; i++) {
426 			u32 airtime_last = msta->tx_airtime_ac[i];
427 
428 			msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8);
429 			airtime[i] = msta->tx_airtime_ac[i] - airtime_last;
430 			airtime[i] *= 32;
431 			total_airtime += airtime[i];
432 
433 			if (msta->tx_airtime_ac[i] & BIT(22))
434 				clear = true;
435 		}
436 
437 		if (clear) {
438 			mt7603_wtbl_update(dev, msta->wcid.idx,
439 					   MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
440 			memset(msta->tx_airtime_ac, 0,
441 			       sizeof(msta->tx_airtime_ac));
442 		}
443 
444 		if (!msta->wcid.sta)
445 			continue;
446 
447 		sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
448 		for (i = 0; i < 4; i++) {
449 			struct mt76_queue *q = dev->mphy.q_tx[i];
450 			u8 qidx = q->hw_idx;
451 			u8 tid = ac_to_tid[i];
452 			u32 txtime = airtime[qidx];
453 
454 			if (!txtime)
455 				continue;
456 
457 			ieee80211_sta_register_airtime(sta, tid, txtime, 0);
458 		}
459 	}
460 
461 	rcu_read_unlock();
462 
463 	if (!total_airtime)
464 		return;
465 
466 	spin_lock_bh(&dev->mt76.cc_lock);
467 	dev->mphy.chan_state->cc_tx += total_airtime;
468 	spin_unlock_bh(&dev->mt76.cc_lock);
469 }
470 
471 static struct mt76_wcid *
472 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
473 {
474 	struct mt7603_sta *sta;
475 	struct mt76_wcid *wcid;
476 
477 	if (idx >= MT7603_WTBL_SIZE)
478 		return NULL;
479 
480 	wcid = rcu_dereference(dev->mt76.wcid[idx]);
481 	if (unicast || !wcid)
482 		return wcid;
483 
484 	if (!wcid->sta)
485 		return NULL;
486 
487 	sta = container_of(wcid, struct mt7603_sta, wcid);
488 	if (!sta->vif)
489 		return NULL;
490 
491 	return &sta->vif->sta.wcid;
492 }
493 
494 int
495 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
496 {
497 	struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
498 	struct ieee80211_supported_band *sband;
499 	struct ieee80211_hdr *hdr;
500 	__le32 *rxd = (__le32 *)skb->data;
501 	u32 rxd0 = le32_to_cpu(rxd[0]);
502 	u32 rxd1 = le32_to_cpu(rxd[1]);
503 	u32 rxd2 = le32_to_cpu(rxd[2]);
504 	bool unicast = rxd1 & MT_RXD1_NORMAL_U2M;
505 	bool insert_ccmp_hdr = false;
506 	bool remove_pad;
507 	int idx;
508 	int i;
509 
510 	memset(status, 0, sizeof(*status));
511 
512 	i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
513 	sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband;
514 	i >>= 1;
515 
516 	idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
517 	status->wcid = mt7603_rx_get_wcid(dev, idx, unicast);
518 
519 	status->band = sband->band;
520 	if (i < sband->n_channels)
521 		status->freq = sband->channels[i].center_freq;
522 
523 	if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
524 		status->flag |= RX_FLAG_FAILED_FCS_CRC;
525 
526 	if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
527 		status->flag |= RX_FLAG_MMIC_ERROR;
528 
529 	/* ICV error or CCMP/BIP/WPI MIC error */
530 	if (rxd2 & MT_RXD2_NORMAL_ICV_ERR)
531 		status->flag |= RX_FLAG_ONLY_MONITOR;
532 
533 	if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
534 	    !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
535 		status->flag |= RX_FLAG_DECRYPTED;
536 		status->flag |= RX_FLAG_IV_STRIPPED;
537 		status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
538 	}
539 
540 	remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
541 
542 	if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
543 		return -EINVAL;
544 
545 	if (!sband->channels)
546 		return -EINVAL;
547 
548 	rxd += 4;
549 	if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
550 		rxd += 4;
551 		if ((u8 *)rxd - skb->data >= skb->len)
552 			return -EINVAL;
553 	}
554 	if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
555 		u8 *data = (u8 *)rxd;
556 
557 		if (status->flag & RX_FLAG_DECRYPTED) {
558 			switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
559 			case MT_CIPHER_AES_CCMP:
560 			case MT_CIPHER_CCMP_CCX:
561 			case MT_CIPHER_CCMP_256:
562 				insert_ccmp_hdr =
563 					FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
564 				fallthrough;
565 			case MT_CIPHER_TKIP:
566 			case MT_CIPHER_TKIP_NO_MIC:
567 			case MT_CIPHER_GCMP:
568 			case MT_CIPHER_GCMP_256:
569 				status->iv[0] = data[5];
570 				status->iv[1] = data[4];
571 				status->iv[2] = data[3];
572 				status->iv[3] = data[2];
573 				status->iv[4] = data[1];
574 				status->iv[5] = data[0];
575 				break;
576 			default:
577 				break;
578 			}
579 		}
580 
581 		rxd += 4;
582 		if ((u8 *)rxd - skb->data >= skb->len)
583 			return -EINVAL;
584 	}
585 	if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
586 		status->timestamp = le32_to_cpu(rxd[0]);
587 		status->flag |= RX_FLAG_MACTIME_START;
588 
589 		if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
590 			      MT_RXD2_NORMAL_NON_AMPDU))) {
591 			status->flag |= RX_FLAG_AMPDU_DETAILS;
592 
593 			/* all subframes of an A-MPDU have the same timestamp */
594 			if (dev->rx_ampdu_ts != status->timestamp) {
595 				if (!++dev->ampdu_ref)
596 					dev->ampdu_ref++;
597 			}
598 			dev->rx_ampdu_ts = status->timestamp;
599 
600 			status->ampdu_ref = dev->ampdu_ref;
601 		}
602 
603 		rxd += 2;
604 		if ((u8 *)rxd - skb->data >= skb->len)
605 			return -EINVAL;
606 	}
607 	if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
608 		u32 rxdg0 = le32_to_cpu(rxd[0]);
609 		u32 rxdg3 = le32_to_cpu(rxd[3]);
610 		bool cck = false;
611 
612 		i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
613 		switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
614 		case MT_PHY_TYPE_CCK:
615 			cck = true;
616 			fallthrough;
617 		case MT_PHY_TYPE_OFDM:
618 			i = mt76_get_rate(&dev->mt76, sband, i, cck);
619 			break;
620 		case MT_PHY_TYPE_HT_GF:
621 		case MT_PHY_TYPE_HT:
622 			status->encoding = RX_ENC_HT;
623 			if (i > 15)
624 				return -EINVAL;
625 			break;
626 		default:
627 			return -EINVAL;
628 		}
629 
630 		if (rxdg0 & MT_RXV1_HT_SHORT_GI)
631 			status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
632 		if (rxdg0 & MT_RXV1_HT_AD_CODE)
633 			status->enc_flags |= RX_ENC_FLAG_LDPC;
634 
635 		status->enc_flags |= RX_ENC_FLAG_STBC_MASK *
636 				    FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
637 
638 		status->rate_idx = i;
639 
640 		status->chains = dev->mphy.antenna_mask;
641 		status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +
642 					  dev->rssi_offset[0];
643 		status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) +
644 					  dev->rssi_offset[1];
645 
646 		if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1)
647 			status->bw = RATE_INFO_BW_40;
648 
649 		rxd += 6;
650 		if ((u8 *)rxd - skb->data >= skb->len)
651 			return -EINVAL;
652 	} else {
653 		return -EINVAL;
654 	}
655 
656 	skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
657 
658 	if (insert_ccmp_hdr) {
659 		u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
660 
661 		mt76_insert_ccmp_hdr(skb, key_id);
662 	}
663 
664 	hdr = (struct ieee80211_hdr *)skb->data;
665 	if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
666 		return 0;
667 
668 	status->aggr = unicast &&
669 		       !ieee80211_is_qos_nullfunc(hdr->frame_control);
670 	status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
671 	status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
672 
673 	return 0;
674 }
675 
676 static u16
677 mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
678 		       const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw)
679 {
680 	u8 phy, nss, rate_idx;
681 	u16 rateval;
682 
683 	*bw = 0;
684 	if (rate->flags & IEEE80211_TX_RC_MCS) {
685 		rate_idx = rate->idx;
686 		nss = 1 + (rate->idx >> 3);
687 		phy = MT_PHY_TYPE_HT;
688 		if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
689 			phy = MT_PHY_TYPE_HT_GF;
690 		if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
691 			*bw = 1;
692 	} else {
693 		const struct ieee80211_rate *r;
694 		int band = dev->mphy.chandef.chan->band;
695 		u16 val;
696 
697 		nss = 1;
698 		r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
699 		if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
700 			val = r->hw_value_short;
701 		else
702 			val = r->hw_value;
703 
704 		phy = val >> 8;
705 		rate_idx = val & 0xff;
706 	}
707 
708 	rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
709 		   FIELD_PREP(MT_TX_RATE_MODE, phy));
710 
711 	if (stbc && nss == 1)
712 		rateval |= MT_TX_RATE_STBC;
713 
714 	return rateval;
715 }
716 
717 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
718 			   struct ieee80211_tx_rate *probe_rate,
719 			   struct ieee80211_tx_rate *rates)
720 {
721 	struct ieee80211_tx_rate *ref;
722 	int wcid = sta->wcid.idx;
723 	u32 addr = mt7603_wtbl2_addr(wcid);
724 	bool stbc = false;
725 	int n_rates = sta->n_rates;
726 	u8 bw, bw_prev, bw_idx = 0;
727 	u16 val[4];
728 	u16 probe_val;
729 	u32 w9 = mt76_rr(dev, addr + 9 * 4);
730 	bool rateset;
731 	int i, k;
732 
733 	if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
734 		return;
735 
736 	for (i = n_rates; i < 4; i++)
737 		rates[i] = rates[n_rates - 1];
738 
739 	rateset = !(sta->rate_set_tsf & BIT(0));
740 	memcpy(sta->rateset[rateset].rates, rates,
741 	       sizeof(sta->rateset[rateset].rates));
742 	if (probe_rate) {
743 		sta->rateset[rateset].probe_rate = *probe_rate;
744 		ref = &sta->rateset[rateset].probe_rate;
745 	} else {
746 		sta->rateset[rateset].probe_rate.idx = -1;
747 		ref = &sta->rateset[rateset].rates[0];
748 	}
749 
750 	rates = sta->rateset[rateset].rates;
751 	for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
752 		/*
753 		 * We don't support switching between short and long GI
754 		 * within the rate set. For accurate tx status reporting, we
755 		 * need to make sure that flags match.
756 		 * For improved performance, avoid duplicate entries by
757 		 * decrementing the MCS index if necessary
758 		 */
759 		if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
760 			rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
761 
762 		for (k = 0; k < i; k++) {
763 			if (rates[i].idx != rates[k].idx)
764 				continue;
765 			if ((rates[i].flags ^ rates[k].flags) &
766 			    IEEE80211_TX_RC_40_MHZ_WIDTH)
767 				continue;
768 
769 			if (!rates[i].idx)
770 				continue;
771 
772 			rates[i].idx--;
773 		}
774 	}
775 
776 	w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
777 	      MT_WTBL2_W9_SHORT_GI_80;
778 
779 	val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
780 	bw_prev = bw;
781 
782 	if (probe_rate) {
783 		probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
784 		if (bw)
785 			bw_idx = 1;
786 		else
787 			bw_prev = 0;
788 	} else {
789 		probe_val = val[0];
790 	}
791 
792 	w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
793 	w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
794 
795 	val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
796 	if (bw_prev) {
797 		bw_idx = 3;
798 		bw_prev = bw;
799 	}
800 
801 	val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
802 	if (bw_prev) {
803 		bw_idx = 5;
804 		bw_prev = bw;
805 	}
806 
807 	val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
808 	if (bw_prev)
809 		bw_idx = 7;
810 
811 	w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
812 		       bw_idx ? bw_idx - 1 : 7);
813 
814 	mt76_wr(dev, MT_WTBL_RIUCR0, w9);
815 
816 	mt76_wr(dev, MT_WTBL_RIUCR1,
817 		FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
818 		FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
819 		FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
820 
821 	mt76_wr(dev, MT_WTBL_RIUCR2,
822 		FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
823 		FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
824 		FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
825 		FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
826 
827 	mt76_wr(dev, MT_WTBL_RIUCR3,
828 		FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
829 		FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
830 		FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
831 
832 	mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
833 	sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
834 
835 	mt76_wr(dev, MT_WTBL_UPDATE,
836 		FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
837 		MT_WTBL_UPDATE_RATE_UPDATE |
838 		MT_WTBL_UPDATE_TX_COUNT_CLEAR);
839 
840 	if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
841 		mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
842 
843 	sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates;
844 	sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
845 }
846 
847 static enum mt76_cipher_type
848 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
849 {
850 	memset(key_data, 0, 32);
851 	if (!key)
852 		return MT_CIPHER_NONE;
853 
854 	if (key->keylen > 32)
855 		return MT_CIPHER_NONE;
856 
857 	memcpy(key_data, key->key, key->keylen);
858 
859 	switch (key->cipher) {
860 	case WLAN_CIPHER_SUITE_WEP40:
861 		return MT_CIPHER_WEP40;
862 	case WLAN_CIPHER_SUITE_WEP104:
863 		return MT_CIPHER_WEP104;
864 	case WLAN_CIPHER_SUITE_TKIP:
865 		/* Rx/Tx MIC keys are swapped */
866 		memcpy(key_data + 16, key->key + 24, 8);
867 		memcpy(key_data + 24, key->key + 16, 8);
868 		return MT_CIPHER_TKIP;
869 	case WLAN_CIPHER_SUITE_CCMP:
870 		return MT_CIPHER_AES_CCMP;
871 	default:
872 		return MT_CIPHER_NONE;
873 	}
874 }
875 
876 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
877 			struct ieee80211_key_conf *key)
878 {
879 	enum mt76_cipher_type cipher;
880 	u32 addr = mt7603_wtbl3_addr(wcid);
881 	u8 key_data[32];
882 	int key_len = sizeof(key_data);
883 
884 	cipher = mt7603_mac_get_key_info(key, key_data);
885 	if (cipher == MT_CIPHER_NONE && key)
886 		return -EOPNOTSUPP;
887 
888 	if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) {
889 		addr += key->keyidx * 16;
890 		key_len = 16;
891 	}
892 
893 	mt76_wr_copy(dev, addr, key_data, key_len);
894 
895 	addr = mt7603_wtbl1_addr(wcid);
896 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
897 	if (key)
898 		mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
899 	mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
900 
901 	return 0;
902 }
903 
904 static int
905 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
906 		      struct sk_buff *skb, enum mt76_txq_id qid,
907 		      struct mt76_wcid *wcid, struct ieee80211_sta *sta,
908 		      int pid, struct ieee80211_key_conf *key)
909 {
910 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
911 	struct ieee80211_tx_rate *rate = &info->control.rates[0];
912 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
913 	struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
914 	struct ieee80211_vif *vif = info->control.vif;
915 	struct mt76_queue *q = dev->mphy.q_tx[qid];
916 	struct mt7603_vif *mvif;
917 	int wlan_idx;
918 	int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
919 	int tx_count = 8;
920 	u8 frame_type, frame_subtype;
921 	u16 fc = le16_to_cpu(hdr->frame_control);
922 	u16 seqno = 0;
923 	u8 vif_idx = 0;
924 	u32 val;
925 	u8 bw;
926 
927 	if (vif) {
928 		mvif = (struct mt7603_vif *)vif->drv_priv;
929 		vif_idx = mvif->idx;
930 		if (vif_idx && qid >= MT_TXQ_BEACON)
931 			vif_idx += 0x10;
932 	}
933 
934 	if (sta) {
935 		struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
936 
937 		tx_count = msta->rate_count;
938 	}
939 
940 	if (wcid)
941 		wlan_idx = wcid->idx;
942 	else
943 		wlan_idx = MT7603_WTBL_RESERVED;
944 
945 	frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
946 	frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
947 
948 	val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
949 	      FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
950 	txwi[0] = cpu_to_le32(val);
951 
952 	val = MT_TXD1_LONG_FORMAT |
953 	      FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
954 	      FIELD_PREP(MT_TXD1_TID,
955 			 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
956 	      FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
957 	      FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
958 	      FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
959 	      FIELD_PREP(MT_TXD1_PROTECTED, !!key);
960 	txwi[1] = cpu_to_le32(val);
961 
962 	if (info->flags & IEEE80211_TX_CTL_NO_ACK)
963 		txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
964 
965 	val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
966 	      FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
967 	      FIELD_PREP(MT_TXD2_MULTICAST,
968 			 is_multicast_ether_addr(hdr->addr1));
969 	txwi[2] = cpu_to_le32(val);
970 
971 	if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
972 		txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
973 
974 	txwi[4] = 0;
975 
976 	val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
977 	      FIELD_PREP(MT_TXD5_PID, pid);
978 	txwi[5] = cpu_to_le32(val);
979 
980 	txwi[6] = 0;
981 
982 	if (rate->idx >= 0 && rate->count &&
983 	    !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
984 		bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
985 		u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
986 
987 		txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
988 
989 		val = MT_TXD6_FIXED_BW |
990 		      FIELD_PREP(MT_TXD6_BW, bw) |
991 		      FIELD_PREP(MT_TXD6_TX_RATE, rateval);
992 		txwi[6] |= cpu_to_le32(val);
993 
994 		if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
995 			txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
996 
997 		if (!(rate->flags & IEEE80211_TX_RC_MCS))
998 			txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
999 
1000 		tx_count = rate->count;
1001 	}
1002 
1003 	/* use maximum tx count for beacons and buffered multicast */
1004 	if (qid >= MT_TXQ_BEACON)
1005 		tx_count = 0x1f;
1006 
1007 	val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
1008 		  MT_TXD3_SN_VALID;
1009 
1010 	if (ieee80211_is_data_qos(hdr->frame_control))
1011 		seqno = le16_to_cpu(hdr->seq_ctrl);
1012 	else if (ieee80211_is_back_req(hdr->frame_control))
1013 		seqno = le16_to_cpu(bar->start_seq_num);
1014 	else
1015 		val &= ~MT_TXD3_SN_VALID;
1016 
1017 	val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4);
1018 
1019 	txwi[3] = cpu_to_le32(val);
1020 
1021 	if (key) {
1022 		u64 pn = atomic64_inc_return(&key->tx_pn);
1023 
1024 		txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
1025 		txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
1026 		txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
1027 	}
1028 
1029 	txwi[7] = 0;
1030 
1031 	return 0;
1032 }
1033 
1034 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1035 			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
1036 			  struct ieee80211_sta *sta,
1037 			  struct mt76_tx_info *tx_info)
1038 {
1039 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1040 	struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid);
1041 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1042 	struct ieee80211_key_conf *key = info->control.hw_key;
1043 	int pid;
1044 
1045 	if (!wcid)
1046 		wcid = &dev->global_sta.wcid;
1047 
1048 	if (sta) {
1049 		msta = (struct mt7603_sta *)sta->drv_priv;
1050 
1051 		if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER |
1052 				    IEEE80211_TX_CTL_CLEAR_PS_FILT)) ||
1053 		    (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE))
1054 			mt7603_wtbl_set_ps(dev, msta, false);
1055 
1056 		mt76_tx_check_agg_ssn(sta, tx_info->skb);
1057 	}
1058 
1059 	pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1060 
1061 	if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
1062 		spin_lock_bh(&dev->mt76.lock);
1063 		mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],
1064 				      msta->rates);
1065 		msta->rate_probe = true;
1066 		spin_unlock_bh(&dev->mt76.lock);
1067 	}
1068 
1069 	mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid,
1070 			      sta, pid, key);
1071 
1072 	return 0;
1073 }
1074 
1075 static bool
1076 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
1077 		struct ieee80211_tx_info *info, __le32 *txs_data)
1078 {
1079 	struct ieee80211_supported_band *sband;
1080 	struct mt7603_rate_set *rs;
1081 	int first_idx = 0, last_idx;
1082 	u32 rate_set_tsf;
1083 	u32 final_rate;
1084 	u32 final_rate_flags;
1085 	bool rs_idx;
1086 	bool ack_timeout;
1087 	bool fixed_rate;
1088 	bool probe;
1089 	bool ampdu;
1090 	bool cck = false;
1091 	int count;
1092 	u32 txs;
1093 	int idx;
1094 	int i;
1095 
1096 	fixed_rate = info->status.rates[0].count;
1097 	probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1098 
1099 	txs = le32_to_cpu(txs_data[4]);
1100 	ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
1101 	count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
1102 	last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs);
1103 
1104 	txs = le32_to_cpu(txs_data[0]);
1105 	final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1106 	ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1107 
1108 	if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1109 		return false;
1110 
1111 	if (txs & MT_TXS0_QUEUE_TIMEOUT)
1112 		return false;
1113 
1114 	if (!ack_timeout)
1115 		info->flags |= IEEE80211_TX_STAT_ACK;
1116 
1117 	info->status.ampdu_len = 1;
1118 	info->status.ampdu_ack_len = !!(info->flags &
1119 					IEEE80211_TX_STAT_ACK);
1120 
1121 	if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1122 		info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1123 
1124 	first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY);
1125 
1126 	if (fixed_rate && !probe) {
1127 		info->status.rates[0].count = count;
1128 		i = 0;
1129 		goto out;
1130 	}
1131 
1132 	rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1133 	rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) -
1134 			 rate_set_tsf) < 1000000);
1135 	rs_idx ^= rate_set_tsf & BIT(0);
1136 	rs = &sta->rateset[rs_idx];
1137 
1138 	if (!first_idx && rs->probe_rate.idx >= 0) {
1139 		info->status.rates[0] = rs->probe_rate;
1140 
1141 		spin_lock_bh(&dev->mt76.lock);
1142 		if (sta->rate_probe) {
1143 			mt7603_wtbl_set_rates(dev, sta, NULL,
1144 					      sta->rates);
1145 			sta->rate_probe = false;
1146 		}
1147 		spin_unlock_bh(&dev->mt76.lock);
1148 	} else {
1149 		info->status.rates[0] = rs->rates[first_idx / 2];
1150 	}
1151 	info->status.rates[0].count = 0;
1152 
1153 	for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1154 		struct ieee80211_tx_rate *cur_rate;
1155 		int cur_count;
1156 
1157 		cur_rate = &rs->rates[idx / 2];
1158 		cur_count = min_t(int, MT7603_RATE_RETRY, count);
1159 		count -= cur_count;
1160 
1161 		if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1162 			    cur_rate->flags != info->status.rates[i].flags)) {
1163 			i++;
1164 			if (i == ARRAY_SIZE(info->status.rates)) {
1165 				i--;
1166 				break;
1167 			}
1168 
1169 			info->status.rates[i] = *cur_rate;
1170 			info->status.rates[i].count = 0;
1171 		}
1172 
1173 		info->status.rates[i].count += cur_count;
1174 	}
1175 
1176 out:
1177 	final_rate_flags = info->status.rates[i].flags;
1178 
1179 	switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1180 	case MT_PHY_TYPE_CCK:
1181 		cck = true;
1182 		fallthrough;
1183 	case MT_PHY_TYPE_OFDM:
1184 		if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ)
1185 			sband = &dev->mphy.sband_5g.sband;
1186 		else
1187 			sband = &dev->mphy.sband_2g.sband;
1188 		final_rate &= GENMASK(5, 0);
1189 		final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1190 					   cck);
1191 		final_rate_flags = 0;
1192 		break;
1193 	case MT_PHY_TYPE_HT_GF:
1194 	case MT_PHY_TYPE_HT:
1195 		final_rate_flags |= IEEE80211_TX_RC_MCS;
1196 		final_rate &= GENMASK(5, 0);
1197 		if (final_rate > 15)
1198 			return false;
1199 		break;
1200 	default:
1201 		return false;
1202 	}
1203 
1204 	info->status.rates[i].idx = final_rate;
1205 	info->status.rates[i].flags = final_rate_flags;
1206 
1207 	return true;
1208 }
1209 
1210 static bool
1211 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
1212 		       __le32 *txs_data)
1213 {
1214 	struct mt76_dev *mdev = &dev->mt76;
1215 	struct sk_buff_head list;
1216 	struct sk_buff *skb;
1217 
1218 	if (pid < MT_PACKET_ID_FIRST)
1219 		return false;
1220 
1221 	trace_mac_txdone(mdev, sta->wcid.idx, pid);
1222 
1223 	mt76_tx_status_lock(mdev, &list);
1224 	skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1225 	if (skb) {
1226 		struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1227 
1228 		if (!mt7603_fill_txs(dev, sta, info, txs_data)) {
1229 			info->status.rates[0].count = 0;
1230 			info->status.rates[0].idx = -1;
1231 		}
1232 
1233 		mt76_tx_status_skb_done(mdev, skb, &list);
1234 	}
1235 	mt76_tx_status_unlock(mdev, &list);
1236 
1237 	return !!skb;
1238 }
1239 
1240 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
1241 {
1242 	struct ieee80211_tx_info info = {};
1243 	struct ieee80211_sta *sta = NULL;
1244 	struct mt7603_sta *msta = NULL;
1245 	struct mt76_wcid *wcid;
1246 	__le32 *txs_data = data;
1247 	u8 wcidx;
1248 	u8 pid;
1249 
1250 	pid = le32_get_bits(txs_data[4], MT_TXS4_PID);
1251 	wcidx = le32_get_bits(txs_data[3], MT_TXS3_WCID);
1252 
1253 	if (pid == MT_PACKET_ID_NO_ACK)
1254 		return;
1255 
1256 	if (wcidx >= MT7603_WTBL_SIZE)
1257 		return;
1258 
1259 	rcu_read_lock();
1260 
1261 	wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1262 	if (!wcid)
1263 		goto out;
1264 
1265 	msta = container_of(wcid, struct mt7603_sta, wcid);
1266 	sta = wcid_to_sta(wcid);
1267 
1268 	if (list_empty(&msta->poll_list)) {
1269 		spin_lock_bh(&dev->sta_poll_lock);
1270 		list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1271 		spin_unlock_bh(&dev->sta_poll_lock);
1272 	}
1273 
1274 	if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data))
1275 		goto out;
1276 
1277 	if (wcidx >= MT7603_WTBL_STA || !sta)
1278 		goto out;
1279 
1280 	if (mt7603_fill_txs(dev, msta, &info, txs_data))
1281 		ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1282 
1283 out:
1284 	rcu_read_unlock();
1285 }
1286 
1287 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1288 {
1289 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1290 	struct sk_buff *skb = e->skb;
1291 
1292 	if (!e->txwi) {
1293 		dev_kfree_skb_any(skb);
1294 		return;
1295 	}
1296 
1297 	dev->tx_hang_check = 0;
1298 	mt76_tx_complete_skb(mdev, e->wcid, skb);
1299 }
1300 
1301 static bool
1302 wait_for_wpdma(struct mt7603_dev *dev)
1303 {
1304 	return mt76_poll(dev, MT_WPDMA_GLO_CFG,
1305 			 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
1306 			 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
1307 			 0, 1000);
1308 }
1309 
1310 static void mt7603_pse_reset(struct mt7603_dev *dev)
1311 {
1312 	/* Clear previous reset result */
1313 	if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1314 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
1315 
1316 	/* Reset PSE */
1317 	mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1318 
1319 	if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
1320 			    MT_MCU_DEBUG_RESET_PSE_S,
1321 			    MT_MCU_DEBUG_RESET_PSE_S, 500)) {
1322 		dev->reset_cause[RESET_CAUSE_RESET_FAILED]++;
1323 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1324 	} else {
1325 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1326 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
1327 	}
1328 
1329 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3)
1330 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1331 }
1332 
1333 void mt7603_mac_dma_start(struct mt7603_dev *dev)
1334 {
1335 	mt7603_mac_start(dev);
1336 
1337 	wait_for_wpdma(dev);
1338 	usleep_range(50, 100);
1339 
1340 	mt76_set(dev, MT_WPDMA_GLO_CFG,
1341 		 (MT_WPDMA_GLO_CFG_TX_DMA_EN |
1342 		  MT_WPDMA_GLO_CFG_RX_DMA_EN |
1343 		  FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
1344 		  MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
1345 
1346 	mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
1347 }
1348 
1349 void mt7603_mac_start(struct mt7603_dev *dev)
1350 {
1351 	mt76_clear(dev, MT_ARB_SCR,
1352 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1353 	mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
1354 	mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1355 }
1356 
1357 void mt7603_mac_stop(struct mt7603_dev *dev)
1358 {
1359 	mt76_set(dev, MT_ARB_SCR,
1360 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1361 	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
1362 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1363 }
1364 
1365 void mt7603_pse_client_reset(struct mt7603_dev *dev)
1366 {
1367 	u32 addr;
1368 
1369 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR +
1370 				   MT_CLIENT_RESET_TX);
1371 
1372 	/* Clear previous reset state */
1373 	mt76_clear(dev, addr,
1374 		   MT_CLIENT_RESET_TX_R_E_1 |
1375 		   MT_CLIENT_RESET_TX_R_E_2 |
1376 		   MT_CLIENT_RESET_TX_R_E_1_S |
1377 		   MT_CLIENT_RESET_TX_R_E_2_S);
1378 
1379 	/* Start PSE client TX abort */
1380 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);
1381 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
1382 		       MT_CLIENT_RESET_TX_R_E_1_S, 500);
1383 
1384 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);
1385 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
1386 
1387 	/* Wait for PSE client to clear TX FIFO */
1388 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
1389 		       MT_CLIENT_RESET_TX_R_E_2_S, 500);
1390 
1391 	/* Clear PSE client TX abort state */
1392 	mt76_clear(dev, addr,
1393 		   MT_CLIENT_RESET_TX_R_E_1 |
1394 		   MT_CLIENT_RESET_TX_R_E_2);
1395 }
1396 
1397 static void mt7603_dma_sched_reset(struct mt7603_dev *dev)
1398 {
1399 	if (!is_mt7628(dev))
1400 		return;
1401 
1402 	mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
1403 	mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
1404 }
1405 
1406 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
1407 {
1408 	int beacon_int = dev->mt76.beacon_int;
1409 	u32 mask = dev->mt76.mmio.irqmask;
1410 	int i;
1411 
1412 	ieee80211_stop_queues(dev->mt76.hw);
1413 	set_bit(MT76_RESET, &dev->mphy.state);
1414 
1415 	/* lock/unlock all queues to ensure that no tx is pending */
1416 	mt76_txq_schedule_all(&dev->mphy);
1417 
1418 	mt76_worker_disable(&dev->mt76.tx_worker);
1419 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
1420 	napi_disable(&dev->mt76.napi[0]);
1421 	napi_disable(&dev->mt76.napi[1]);
1422 	napi_disable(&dev->mt76.tx_napi);
1423 
1424 	mutex_lock(&dev->mt76.mutex);
1425 
1426 	mt7603_beacon_set_timer(dev, -1, 0);
1427 
1428 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] ||
1429 	    dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY ||
1430 	    dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK ||
1431 	    dev->cur_reset_cause == RESET_CAUSE_TX_HANG)
1432 		mt7603_pse_reset(dev);
1433 
1434 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1435 		goto skip_dma_reset;
1436 
1437 	mt7603_mac_stop(dev);
1438 
1439 	mt76_clear(dev, MT_WPDMA_GLO_CFG,
1440 		   MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1441 		   MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1442 	usleep_range(1000, 2000);
1443 
1444 	mt7603_irq_disable(dev, mask);
1445 
1446 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
1447 
1448 	mt7603_pse_client_reset(dev);
1449 
1450 	mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
1451 	for (i = 0; i < __MT_TXQ_MAX; i++)
1452 		mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1453 
1454 	mt76_for_each_q_rx(&dev->mt76, i) {
1455 		mt76_queue_rx_reset(dev, i);
1456 	}
1457 
1458 	mt76_tx_status_check(&dev->mt76, true);
1459 
1460 	mt7603_dma_sched_reset(dev);
1461 
1462 	mt7603_mac_dma_start(dev);
1463 
1464 	mt7603_irq_enable(dev, mask);
1465 
1466 skip_dma_reset:
1467 	clear_bit(MT76_RESET, &dev->mphy.state);
1468 	mutex_unlock(&dev->mt76.mutex);
1469 
1470 	mt76_worker_enable(&dev->mt76.tx_worker);
1471 
1472 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
1473 	mt7603_beacon_set_timer(dev, -1, beacon_int);
1474 
1475 	local_bh_disable();
1476 	napi_enable(&dev->mt76.tx_napi);
1477 	napi_schedule(&dev->mt76.tx_napi);
1478 
1479 	napi_enable(&dev->mt76.napi[0]);
1480 	napi_schedule(&dev->mt76.napi[0]);
1481 
1482 	napi_enable(&dev->mt76.napi[1]);
1483 	napi_schedule(&dev->mt76.napi[1]);
1484 	local_bh_enable();
1485 
1486 	ieee80211_wake_queues(dev->mt76.hw);
1487 	mt76_txq_schedule_all(&dev->mphy);
1488 }
1489 
1490 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index)
1491 {
1492 	u32 val;
1493 
1494 	mt76_wr(dev, MT_WPDMA_DEBUG,
1495 		FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) |
1496 		MT_WPDMA_DEBUG_SEL);
1497 
1498 	val = mt76_rr(dev, MT_WPDMA_DEBUG);
1499 	return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val);
1500 }
1501 
1502 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev)
1503 {
1504 	if (is_mt7628(dev))
1505 		return mt7603_dma_debug(dev, 9) & BIT(9);
1506 
1507 	return mt7603_dma_debug(dev, 2) & BIT(8);
1508 }
1509 
1510 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev)
1511 {
1512 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY))
1513 		return false;
1514 
1515 	return mt7603_rx_fifo_busy(dev);
1516 }
1517 
1518 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
1519 {
1520 	u32 val;
1521 
1522 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY))
1523 		return false;
1524 
1525 	val = mt7603_dma_debug(dev, 9);
1526 	return (val & BIT(8)) && (val & 0xf) != 0xf;
1527 }
1528 
1529 static bool mt7603_tx_hang(struct mt7603_dev *dev)
1530 {
1531 	struct mt76_queue *q;
1532 	u32 dma_idx, prev_dma_idx;
1533 	int i;
1534 
1535 	for (i = 0; i < 4; i++) {
1536 		q = dev->mphy.q_tx[i];
1537 
1538 		if (!q->queued)
1539 			continue;
1540 
1541 		prev_dma_idx = dev->tx_dma_idx[i];
1542 		dma_idx = readl(&q->regs->dma_idx);
1543 		dev->tx_dma_idx[i] = dma_idx;
1544 
1545 		if (dma_idx == prev_dma_idx &&
1546 		    dma_idx != readl(&q->regs->cpu_idx))
1547 			break;
1548 	}
1549 
1550 	return i < 4;
1551 }
1552 
1553 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev)
1554 {
1555 	u32 addr, val;
1556 
1557 	if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES)
1558 		return true;
1559 
1560 	if (mt7603_rx_fifo_busy(dev))
1561 		return false;
1562 
1563 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS);
1564 	mt76_wr(dev, addr, 3);
1565 	val = mt76_rr(dev, addr) >> 16;
1566 
1567 	if (is_mt7628(dev) && (val & 0x4001) == 0x4001)
1568 		return true;
1569 
1570 	return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001;
1571 }
1572 
1573 static bool
1574 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter,
1575 		      enum mt7603_reset_cause cause,
1576 		      bool (*check)(struct mt7603_dev *dev))
1577 {
1578 	if (dev->reset_test == cause + 1) {
1579 		dev->reset_test = 0;
1580 		goto trigger;
1581 	}
1582 
1583 	if (check) {
1584 		if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) {
1585 			*counter = 0;
1586 			return false;
1587 		}
1588 
1589 		(*counter)++;
1590 	}
1591 
1592 	if (*counter < MT7603_WATCHDOG_TIMEOUT)
1593 		return false;
1594 trigger:
1595 	dev->cur_reset_cause = cause;
1596 	dev->reset_cause[cause]++;
1597 	return true;
1598 }
1599 
1600 void mt7603_update_channel(struct mt76_phy *mphy)
1601 {
1602 	struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76);
1603 	struct mt76_channel_state *state;
1604 
1605 	state = mphy->chan_state;
1606 	state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA);
1607 }
1608 
1609 void
1610 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val)
1611 {
1612 	u32 rxtd_6 = 0xd7c80000;
1613 
1614 	if (val == dev->ed_strict_mode)
1615 		return;
1616 
1617 	dev->ed_strict_mode = val;
1618 
1619 	/* Ensure that ED/CCA does not trigger if disabled */
1620 	if (!dev->ed_monitor)
1621 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);
1622 	else
1623 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);
1624 
1625 	if (dev->ed_monitor && !dev->ed_strict_mode)
1626 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);
1627 	else
1628 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);
1629 
1630 	mt76_wr(dev, MT_RXTD(6), rxtd_6);
1631 
1632 	mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
1633 		       dev->ed_monitor && !dev->ed_strict_mode);
1634 }
1635 
1636 static void
1637 mt7603_edcca_check(struct mt7603_dev *dev)
1638 {
1639 	u32 val = mt76_rr(dev, MT_AGC(41));
1640 	ktime_t cur_time;
1641 	int rssi0, rssi1;
1642 	u32 active;
1643 	u32 ed_busy;
1644 
1645 	if (!dev->ed_monitor)
1646 		return;
1647 
1648 	rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val);
1649 	if (rssi0 > 128)
1650 		rssi0 -= 256;
1651 
1652 	if (dev->mphy.antenna_mask & BIT(1)) {
1653 		rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val);
1654 		if (rssi1 > 128)
1655 			rssi1 -= 256;
1656 	} else {
1657 		rssi1 = rssi0;
1658 	}
1659 
1660 	if (max(rssi0, rssi1) >= -40 &&
1661 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH)
1662 		dev->ed_strong_signal++;
1663 	else if (dev->ed_strong_signal > 0)
1664 		dev->ed_strong_signal--;
1665 
1666 	cur_time = ktime_get_boottime();
1667 	ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK;
1668 
1669 	active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1670 	dev->ed_time = cur_time;
1671 
1672 	if (!active)
1673 		return;
1674 
1675 	if (100 * ed_busy / active > 90) {
1676 		if (dev->ed_trigger < 0)
1677 			dev->ed_trigger = 0;
1678 		dev->ed_trigger++;
1679 	} else {
1680 		if (dev->ed_trigger > 0)
1681 			dev->ed_trigger = 0;
1682 		dev->ed_trigger--;
1683 	}
1684 
1685 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH ||
1686 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) {
1687 		mt7603_edcca_set_strict(dev, true);
1688 	} else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) {
1689 		mt7603_edcca_set_strict(dev, false);
1690 	}
1691 
1692 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH)
1693 		dev->ed_trigger = MT7603_EDCCA_BLOCK_TH;
1694 	else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH)
1695 		dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH;
1696 }
1697 
1698 void mt7603_cca_stats_reset(struct mt7603_dev *dev)
1699 {
1700 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1701 	mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1702 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);
1703 }
1704 
1705 static void
1706 mt7603_adjust_sensitivity(struct mt7603_dev *dev)
1707 {
1708 	u32 agc0 = dev->agc0, agc3 = dev->agc3;
1709 	u32 adj;
1710 
1711 	if (!dev->sensitivity || dev->sensitivity < -100) {
1712 		dev->sensitivity = 0;
1713 	} else if (dev->sensitivity <= -84) {
1714 		adj = 7 + (dev->sensitivity + 92) / 2;
1715 
1716 		agc0 = 0x56f0076f;
1717 		agc0 |= adj << 12;
1718 		agc0 |= adj << 16;
1719 		agc3 = 0x81d0d5e3;
1720 	} else if (dev->sensitivity <= -72) {
1721 		adj = 7 + (dev->sensitivity + 80) / 2;
1722 
1723 		agc0 = 0x6af0006f;
1724 		agc0 |= adj << 8;
1725 		agc0 |= adj << 12;
1726 		agc0 |= adj << 16;
1727 
1728 		agc3 = 0x8181d5e3;
1729 	} else {
1730 		if (dev->sensitivity > -54)
1731 			dev->sensitivity = -54;
1732 
1733 		adj = 7 + (dev->sensitivity + 80) / 2;
1734 
1735 		agc0 = 0x7ff0000f;
1736 		agc0 |= adj << 4;
1737 		agc0 |= adj << 8;
1738 		agc0 |= adj << 12;
1739 		agc0 |= adj << 16;
1740 
1741 		agc3 = 0x818181e3;
1742 	}
1743 
1744 	mt76_wr(dev, MT_AGC(0), agc0);
1745 	mt76_wr(dev, MT_AGC1(0), agc0);
1746 
1747 	mt76_wr(dev, MT_AGC(3), agc3);
1748 	mt76_wr(dev, MT_AGC1(3), agc3);
1749 }
1750 
1751 static void
1752 mt7603_false_cca_check(struct mt7603_dev *dev)
1753 {
1754 	int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm;
1755 	int false_cca;
1756 	int min_signal;
1757 	u32 val;
1758 
1759 	if (!dev->dynamic_sensitivity)
1760 		return;
1761 
1762 	val = mt76_rr(dev, MT_PHYCTRL_STAT_PD);
1763 	pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val);
1764 	pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val);
1765 
1766 	val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY);
1767 	mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val);
1768 	mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val);
1769 
1770 	dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1771 	dev->false_cca_cck = pd_cck - mdrdy_cck;
1772 
1773 	mt7603_cca_stats_reset(dev);
1774 
1775 	min_signal = mt76_get_min_avg_rssi(&dev->mt76, false);
1776 	if (!min_signal) {
1777 		dev->sensitivity = 0;
1778 		dev->last_cca_adj = jiffies;
1779 		goto out;
1780 	}
1781 
1782 	min_signal -= 15;
1783 
1784 	false_cca = dev->false_cca_ofdm + dev->false_cca_cck;
1785 	if (false_cca > 600 &&
1786 	    dev->sensitivity < -100 + dev->sensitivity_limit) {
1787 		if (!dev->sensitivity)
1788 			dev->sensitivity = -92;
1789 		else
1790 			dev->sensitivity += 2;
1791 		dev->last_cca_adj = jiffies;
1792 	} else if (false_cca < 100 ||
1793 		   time_after(jiffies, dev->last_cca_adj + 10 * HZ)) {
1794 		dev->last_cca_adj = jiffies;
1795 		if (!dev->sensitivity)
1796 			goto out;
1797 
1798 		dev->sensitivity -= 2;
1799 	}
1800 
1801 	if (dev->sensitivity && dev->sensitivity > min_signal) {
1802 		dev->sensitivity = min_signal;
1803 		dev->last_cca_adj = jiffies;
1804 	}
1805 
1806 out:
1807 	mt7603_adjust_sensitivity(dev);
1808 }
1809 
1810 void mt7603_mac_work(struct work_struct *work)
1811 {
1812 	struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
1813 					      mphy.mac_work.work);
1814 	bool reset = false;
1815 	int i, idx;
1816 
1817 	mt76_tx_status_check(&dev->mt76, false);
1818 
1819 	mutex_lock(&dev->mt76.mutex);
1820 
1821 	dev->mphy.mac_work_count++;
1822 	mt76_update_survey(&dev->mphy);
1823 	mt7603_edcca_check(dev);
1824 
1825 	for (i = 0, idx = 0; i < 2; i++) {
1826 		u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1827 
1828 		dev->mt76.aggr_stats[idx++] += val & 0xffff;
1829 		dev->mt76.aggr_stats[idx++] += val >> 16;
1830 	}
1831 
1832 	if (dev->mphy.mac_work_count == 10)
1833 		mt7603_false_cca_check(dev);
1834 
1835 	if (mt7603_watchdog_check(dev, &dev->rx_pse_check,
1836 				  RESET_CAUSE_RX_PSE_BUSY,
1837 				  mt7603_rx_pse_busy) ||
1838 	    mt7603_watchdog_check(dev, &dev->beacon_check,
1839 				  RESET_CAUSE_BEACON_STUCK,
1840 				  NULL) ||
1841 	    mt7603_watchdog_check(dev, &dev->tx_hang_check,
1842 				  RESET_CAUSE_TX_HANG,
1843 				  mt7603_tx_hang) ||
1844 	    mt7603_watchdog_check(dev, &dev->tx_dma_check,
1845 				  RESET_CAUSE_TX_BUSY,
1846 				  mt7603_tx_dma_busy) ||
1847 	    mt7603_watchdog_check(dev, &dev->rx_dma_check,
1848 				  RESET_CAUSE_RX_BUSY,
1849 				  mt7603_rx_dma_busy) ||
1850 	    mt7603_watchdog_check(dev, &dev->mcu_hang,
1851 				  RESET_CAUSE_MCU_HANG,
1852 				  NULL) ||
1853 	    dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1854 		dev->beacon_check = 0;
1855 		dev->tx_dma_check = 0;
1856 		dev->tx_hang_check = 0;
1857 		dev->rx_dma_check = 0;
1858 		dev->rx_pse_check = 0;
1859 		dev->mcu_hang = 0;
1860 		dev->rx_dma_idx = ~0;
1861 		memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
1862 		reset = true;
1863 		dev->mphy.mac_work_count = 0;
1864 	}
1865 
1866 	if (dev->mphy.mac_work_count >= 10)
1867 		dev->mphy.mac_work_count = 0;
1868 
1869 	mutex_unlock(&dev->mt76.mutex);
1870 
1871 	if (reset)
1872 		mt7603_mac_watchdog_reset(dev);
1873 
1874 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1875 				     msecs_to_jiffies(MT7603_WATCHDOG_TIME));
1876 }
1877