1 // SPDX-License-Identifier: ISC 2 3 #include <linux/etherdevice.h> 4 #include <linux/timekeeping.h> 5 #include "mt7603.h" 6 #include "mac.h" 7 8 #define MT_PSE_PAGE_SIZE 128 9 10 static u32 11 mt7603_ac_queue_mask0(u32 mask) 12 { 13 u32 ret = 0; 14 15 ret |= GENMASK(3, 0) * !!(mask & BIT(0)); 16 ret |= GENMASK(8, 5) * !!(mask & BIT(1)); 17 ret |= GENMASK(13, 10) * !!(mask & BIT(2)); 18 ret |= GENMASK(19, 16) * !!(mask & BIT(3)); 19 return ret; 20 } 21 22 static void 23 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) 24 { 25 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); 26 } 27 28 static void 29 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) 30 { 31 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); 32 } 33 34 void mt7603_mac_set_timing(struct mt7603_dev *dev) 35 { 36 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 37 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 38 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 39 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); 40 int offset = 3 * dev->coverage_class; 41 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 42 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 43 int sifs; 44 u32 val; 45 46 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) 47 sifs = 16; 48 else 49 sifs = 10; 50 51 mt76_set(dev, MT_ARB_SCR, 52 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 53 udelay(1); 54 55 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset); 56 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset); 57 mt76_wr(dev, MT_IFS, 58 FIELD_PREP(MT_IFS_EIFS, 360) | 59 FIELD_PREP(MT_IFS_RIFS, 2) | 60 FIELD_PREP(MT_IFS_SIFS, sifs) | 61 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); 62 63 if (dev->slottime < 20) 64 val = MT7603_CFEND_RATE_DEFAULT; 65 else 66 val = MT7603_CFEND_RATE_11B; 67 68 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val); 69 70 mt76_clear(dev, MT_ARB_SCR, 71 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 72 } 73 74 static void 75 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) 76 { 77 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 78 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 79 80 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 81 } 82 83 static u32 84 mt7603_wtbl1_addr(int idx) 85 { 86 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 87 } 88 89 static u32 90 mt7603_wtbl2_addr(int idx) 91 { 92 /* Mapped to WTBL2 */ 93 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE; 94 } 95 96 static u32 97 mt7603_wtbl3_addr(int idx) 98 { 99 u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE); 100 101 return base + idx * MT_WTBL3_SIZE; 102 } 103 104 static u32 105 mt7603_wtbl4_addr(int idx) 106 { 107 u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE); 108 109 return base + idx * MT_WTBL4_SIZE; 110 } 111 112 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif, 113 const u8 *mac_addr) 114 { 115 const void *_mac = mac_addr; 116 u32 addr = mt7603_wtbl1_addr(idx); 117 u32 w0 = 0, w1 = 0; 118 int i; 119 120 if (_mac) { 121 w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI, 122 get_unaligned_le16(_mac + 4)); 123 w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO, 124 get_unaligned_le32(_mac)); 125 } 126 127 if (vif < 0) 128 vif = 0; 129 else 130 w0 |= MT_WTBL1_W0_RX_CHECK_A1; 131 w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif); 132 133 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 134 135 mt76_set(dev, addr + 0 * 4, w0); 136 mt76_set(dev, addr + 1 * 4, w1); 137 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL); 138 139 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 140 addr = mt7603_wtbl2_addr(idx); 141 for (i = 0; i < MT_WTBL2_SIZE; i += 4) 142 mt76_wr(dev, addr + i, 0); 143 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 144 mt76_start_tx_ac(dev, GENMASK(3, 0)); 145 146 addr = mt7603_wtbl3_addr(idx); 147 for (i = 0; i < MT_WTBL3_SIZE; i += 4) 148 mt76_wr(dev, addr + i, 0); 149 150 addr = mt7603_wtbl4_addr(idx); 151 for (i = 0; i < MT_WTBL4_SIZE; i += 4) 152 mt76_wr(dev, addr + i, 0); 153 } 154 155 static void 156 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled) 157 { 158 u32 addr = mt7603_wtbl1_addr(idx); 159 u32 val = mt76_rr(dev, addr + 3 * 4); 160 161 val &= ~MT_WTBL1_W3_SKIP_TX; 162 val |= enabled * MT_WTBL1_W3_SKIP_TX; 163 164 mt76_wr(dev, addr + 3 * 4, val); 165 } 166 167 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort) 168 { 169 int i, port, queue; 170 171 if (abort) { 172 port = 3; /* PSE */ 173 queue = 8; /* free queue */ 174 } else { 175 port = 0; /* HIF */ 176 queue = 1; /* MCU queue */ 177 } 178 179 mt7603_wtbl_set_skip_tx(dev, idx, true); 180 181 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN | 182 FIELD_PREP(MT_TX_ABORT_WCID, idx)); 183 184 for (i = 0; i < 4; i++) { 185 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | 186 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) | 187 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) | 188 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) | 189 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue)); 190 191 WARN_ON_ONCE(!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 192 0, 5000)); 193 } 194 195 mt76_wr(dev, MT_TX_ABORT, 0); 196 197 mt7603_wtbl_set_skip_tx(dev, idx, false); 198 } 199 200 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta, 201 bool enabled) 202 { 203 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); 204 205 if (sta->smps == enabled) 206 return; 207 208 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled); 209 sta->smps = enabled; 210 } 211 212 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, 213 bool enabled) 214 { 215 int idx = sta->wcid.idx; 216 u32 addr; 217 218 spin_lock_bh(&dev->ps_lock); 219 220 if (sta->ps == enabled) 221 goto out; 222 223 mt76_wr(dev, MT_PSE_RTA, 224 FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) | 225 FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) | 226 FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) | 227 FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) | 228 MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY); 229 230 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 231 232 if (enabled) 233 mt7603_filter_tx(dev, idx, false); 234 235 addr = mt7603_wtbl1_addr(idx); 236 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 237 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE, 238 enabled * MT_WTBL1_W3_POWER_SAVE); 239 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 240 sta->ps = enabled; 241 242 out: 243 spin_unlock_bh(&dev->ps_lock); 244 } 245 246 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx) 247 { 248 int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE; 249 int wtbl2_frame = idx / wtbl2_frame_size; 250 int wtbl2_entry = idx % wtbl2_frame_size; 251 252 int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE; 253 int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE; 254 int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size; 255 int wtbl3_entry = (idx % wtbl3_frame_size) * 2; 256 257 int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE; 258 int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE; 259 int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size; 260 int wtbl4_entry = idx % wtbl4_frame_size; 261 262 u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE; 263 int i; 264 265 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 266 267 mt76_wr(dev, addr + 0 * 4, 268 MT_WTBL1_W0_RX_CHECK_A1 | 269 MT_WTBL1_W0_RX_CHECK_A2 | 270 MT_WTBL1_W0_RX_VALID); 271 mt76_wr(dev, addr + 1 * 4, 0); 272 mt76_wr(dev, addr + 2 * 4, 0); 273 274 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 275 276 mt76_wr(dev, addr + 3 * 4, 277 FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) | 278 FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) | 279 FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) | 280 MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM); 281 mt76_wr(dev, addr + 4 * 4, 282 FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) | 283 FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) | 284 FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry)); 285 286 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE); 287 288 addr = mt7603_wtbl2_addr(idx); 289 290 /* Clear BA information */ 291 mt76_wr(dev, addr + (15 * 4), 0); 292 293 mt76_stop_tx_ac(dev, GENMASK(3, 0)); 294 for (i = 2; i <= 4; i++) 295 mt76_wr(dev, addr + (i * 4), 0); 296 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2); 297 mt76_start_tx_ac(dev, GENMASK(3, 0)); 298 299 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR); 300 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR); 301 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 302 } 303 304 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta) 305 { 306 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 307 int idx = msta->wcid.idx; 308 u32 addr; 309 u32 val; 310 311 addr = mt7603_wtbl1_addr(idx); 312 313 val = mt76_rr(dev, addr + 2 * 4); 314 val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL; 315 val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) | 316 FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) | 317 MT_WTBL1_W2_TXS_BAF_REPORT; 318 319 if (sta->ht_cap.cap) 320 val |= MT_WTBL1_W2_HT; 321 if (sta->vht_cap.cap) 322 val |= MT_WTBL1_W2_VHT; 323 324 mt76_wr(dev, addr + 2 * 4, val); 325 326 addr = mt7603_wtbl2_addr(idx); 327 val = mt76_rr(dev, addr + 9 * 4); 328 val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 329 MT_WTBL2_W9_SHORT_GI_80); 330 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) 331 val |= MT_WTBL2_W9_SHORT_GI_20; 332 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 333 val |= MT_WTBL2_W9_SHORT_GI_40; 334 mt76_wr(dev, addr + 9 * 4, val); 335 } 336 337 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid) 338 { 339 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr)); 340 mt76_wr(dev, MT_BA_CONTROL_1, 341 (get_unaligned_le16(addr + 4) | 342 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) | 343 MT_BA_CONTROL_1_RESET)); 344 } 345 346 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid, 347 int ba_size) 348 { 349 u32 addr = mt7603_wtbl2_addr(wcid); 350 u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 351 (MT_WTBL2_W15_BA_WIN_SIZE << 352 (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT)); 353 u32 tid_val; 354 int i; 355 356 if (ba_size < 0) { 357 /* disable */ 358 mt76_clear(dev, addr + (15 * 4), tid_mask); 359 return; 360 } 361 362 for (i = 7; i > 0; i--) { 363 if (ba_size >= MT_AGG_SIZE_LIMIT(i)) 364 break; 365 } 366 367 tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) | 368 i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT); 369 370 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val); 371 } 372 373 static struct mt76_wcid * 374 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast) 375 { 376 struct mt7603_sta *sta; 377 struct mt76_wcid *wcid; 378 379 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 380 return NULL; 381 382 wcid = rcu_dereference(dev->mt76.wcid[idx]); 383 if (unicast || !wcid) 384 return wcid; 385 386 if (!wcid->sta) 387 return NULL; 388 389 sta = container_of(wcid, struct mt7603_sta, wcid); 390 if (!sta->vif) 391 return NULL; 392 393 return &sta->vif->sta.wcid; 394 } 395 396 int 397 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb) 398 { 399 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 400 struct ieee80211_supported_band *sband; 401 struct ieee80211_hdr *hdr; 402 __le32 *rxd = (__le32 *)skb->data; 403 u32 rxd0 = le32_to_cpu(rxd[0]); 404 u32 rxd1 = le32_to_cpu(rxd[1]); 405 u32 rxd2 = le32_to_cpu(rxd[2]); 406 bool unicast = rxd1 & MT_RXD1_NORMAL_U2M; 407 bool insert_ccmp_hdr = false; 408 bool remove_pad; 409 int idx; 410 int i; 411 412 memset(status, 0, sizeof(*status)); 413 414 i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1); 415 sband = (i & 1) ? &dev->mt76.sband_5g.sband : &dev->mt76.sband_2g.sband; 416 i >>= 1; 417 418 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2); 419 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); 420 421 status->band = sband->band; 422 if (i < sband->n_channels) 423 status->freq = sband->channels[i].center_freq; 424 425 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR) 426 status->flag |= RX_FLAG_FAILED_FCS_CRC; 427 428 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR) 429 status->flag |= RX_FLAG_MMIC_ERROR; 430 431 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 && 432 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) { 433 status->flag |= RX_FLAG_DECRYPTED; 434 status->flag |= RX_FLAG_IV_STRIPPED; 435 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 436 } 437 438 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET; 439 440 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 441 return -EINVAL; 442 443 if (!sband->channels) 444 return -EINVAL; 445 446 rxd += 4; 447 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) { 448 rxd += 4; 449 if ((u8 *)rxd - skb->data >= skb->len) 450 return -EINVAL; 451 } 452 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) { 453 u8 *data = (u8 *)rxd; 454 455 if (status->flag & RX_FLAG_DECRYPTED) { 456 status->iv[0] = data[5]; 457 status->iv[1] = data[4]; 458 status->iv[2] = data[3]; 459 status->iv[3] = data[2]; 460 status->iv[4] = data[1]; 461 status->iv[5] = data[0]; 462 463 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 464 } 465 466 rxd += 4; 467 if ((u8 *)rxd - skb->data >= skb->len) 468 return -EINVAL; 469 } 470 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) { 471 rxd += 2; 472 if ((u8 *)rxd - skb->data >= skb->len) 473 return -EINVAL; 474 } 475 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) { 476 u32 rxdg0 = le32_to_cpu(rxd[0]); 477 u32 rxdg3 = le32_to_cpu(rxd[3]); 478 bool cck = false; 479 480 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0); 481 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) { 482 case MT_PHY_TYPE_CCK: 483 cck = true; 484 /* fall through */ 485 case MT_PHY_TYPE_OFDM: 486 i = mt76_get_rate(&dev->mt76, sband, i, cck); 487 break; 488 case MT_PHY_TYPE_HT_GF: 489 case MT_PHY_TYPE_HT: 490 status->encoding = RX_ENC_HT; 491 if (i > 15) 492 return -EINVAL; 493 break; 494 default: 495 return -EINVAL; 496 } 497 498 if (rxdg0 & MT_RXV1_HT_SHORT_GI) 499 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 500 if (rxdg0 & MT_RXV1_HT_AD_CODE) 501 status->enc_flags |= RX_ENC_FLAG_LDPC; 502 503 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * 504 FIELD_GET(MT_RXV1_HT_STBC, rxdg0); 505 506 status->rate_idx = i; 507 508 status->chains = dev->mt76.antenna_mask; 509 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + 510 dev->rssi_offset[0]; 511 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + 512 dev->rssi_offset[1]; 513 514 status->signal = status->chain_signal[0]; 515 if (status->chains & BIT(1)) 516 status->signal = max(status->signal, 517 status->chain_signal[1]); 518 519 if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1) 520 status->bw = RATE_INFO_BW_40; 521 522 rxd += 6; 523 if ((u8 *)rxd - skb->data >= skb->len) 524 return -EINVAL; 525 } else { 526 return -EINVAL; 527 } 528 529 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); 530 531 if (insert_ccmp_hdr) { 532 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 533 534 mt76_insert_ccmp_hdr(skb, key_id); 535 } 536 537 hdr = (struct ieee80211_hdr *)skb->data; 538 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) 539 return 0; 540 541 status->aggr = unicast && 542 !ieee80211_is_qos_nullfunc(hdr->frame_control); 543 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK; 544 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 545 546 return 0; 547 } 548 549 static u16 550 mt7603_mac_tx_rate_val(struct mt7603_dev *dev, 551 const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw) 552 { 553 u8 phy, nss, rate_idx; 554 u16 rateval; 555 556 *bw = 0; 557 if (rate->flags & IEEE80211_TX_RC_MCS) { 558 rate_idx = rate->idx; 559 nss = 1 + (rate->idx >> 3); 560 phy = MT_PHY_TYPE_HT; 561 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) 562 phy = MT_PHY_TYPE_HT_GF; 563 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 564 *bw = 1; 565 } else { 566 const struct ieee80211_rate *r; 567 int band = dev->mt76.chandef.chan->band; 568 u16 val; 569 570 nss = 1; 571 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; 572 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 573 val = r->hw_value_short; 574 else 575 val = r->hw_value; 576 577 phy = val >> 8; 578 rate_idx = val & 0xff; 579 } 580 581 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 582 FIELD_PREP(MT_TX_RATE_MODE, phy)); 583 584 if (stbc && nss == 1) 585 rateval |= MT_TX_RATE_STBC; 586 587 return rateval; 588 } 589 590 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta, 591 struct ieee80211_tx_rate *probe_rate, 592 struct ieee80211_tx_rate *rates) 593 { 594 struct ieee80211_tx_rate *ref; 595 int wcid = sta->wcid.idx; 596 u32 addr = mt7603_wtbl2_addr(wcid); 597 bool stbc = false; 598 int n_rates = sta->n_rates; 599 u8 bw, bw_prev, bw_idx = 0; 600 u16 val[4]; 601 u16 probe_val; 602 u32 w9 = mt76_rr(dev, addr + 9 * 4); 603 bool rateset; 604 int i, k; 605 606 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000)) 607 return; 608 609 for (i = n_rates; i < 4; i++) 610 rates[i] = rates[n_rates - 1]; 611 612 rateset = !(sta->rate_set_tsf & BIT(0)); 613 memcpy(sta->rateset[rateset].rates, rates, 614 sizeof(sta->rateset[rateset].rates)); 615 if (probe_rate) { 616 sta->rateset[rateset].probe_rate = *probe_rate; 617 ref = &sta->rateset[rateset].probe_rate; 618 } else { 619 sta->rateset[rateset].probe_rate.idx = -1; 620 ref = &sta->rateset[rateset].rates[0]; 621 } 622 623 rates = sta->rateset[rateset].rates; 624 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { 625 /* 626 * We don't support switching between short and long GI 627 * within the rate set. For accurate tx status reporting, we 628 * need to make sure that flags match. 629 * For improved performance, avoid duplicate entries by 630 * decrementing the MCS index if necessary 631 */ 632 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) 633 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI; 634 635 for (k = 0; k < i; k++) { 636 if (rates[i].idx != rates[k].idx) 637 continue; 638 if ((rates[i].flags ^ rates[k].flags) & 639 IEEE80211_TX_RC_40_MHZ_WIDTH) 640 continue; 641 642 if (!rates[i].idx) 643 continue; 644 645 rates[i].idx--; 646 } 647 } 648 649 w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 | 650 MT_WTBL2_W9_SHORT_GI_80; 651 652 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw); 653 bw_prev = bw; 654 655 if (probe_rate) { 656 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw); 657 if (bw) 658 bw_idx = 1; 659 else 660 bw_prev = 0; 661 } else { 662 probe_val = val[0]; 663 } 664 665 w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw); 666 w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw); 667 668 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw); 669 if (bw_prev) { 670 bw_idx = 3; 671 bw_prev = bw; 672 } 673 674 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw); 675 if (bw_prev) { 676 bw_idx = 5; 677 bw_prev = bw; 678 } 679 680 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw); 681 if (bw_prev) 682 bw_idx = 7; 683 684 w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE, 685 bw_idx ? bw_idx - 1 : 7); 686 687 mt76_wr(dev, MT_WTBL_RIUCR0, w9); 688 689 mt76_wr(dev, MT_WTBL_RIUCR1, 690 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) | 691 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) | 692 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1])); 693 694 mt76_wr(dev, MT_WTBL_RIUCR2, 695 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) | 696 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) | 697 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) | 698 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2])); 699 700 mt76_wr(dev, MT_WTBL_RIUCR3, 701 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) | 702 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) | 703 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3])); 704 705 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */ 706 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; 707 708 mt76_wr(dev, MT_WTBL_UPDATE, 709 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) | 710 MT_WTBL_UPDATE_RATE_UPDATE | 711 MT_WTBL_UPDATE_TX_COUNT_CLEAR); 712 713 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) 714 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000); 715 716 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; 717 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; 718 } 719 720 static enum mt7603_cipher_type 721 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) 722 { 723 memset(key_data, 0, 32); 724 if (!key) 725 return MT_CIPHER_NONE; 726 727 if (key->keylen > 32) 728 return MT_CIPHER_NONE; 729 730 memcpy(key_data, key->key, key->keylen); 731 732 switch (key->cipher) { 733 case WLAN_CIPHER_SUITE_WEP40: 734 return MT_CIPHER_WEP40; 735 case WLAN_CIPHER_SUITE_WEP104: 736 return MT_CIPHER_WEP104; 737 case WLAN_CIPHER_SUITE_TKIP: 738 /* Rx/Tx MIC keys are swapped */ 739 memcpy(key_data + 16, key->key + 24, 8); 740 memcpy(key_data + 24, key->key + 16, 8); 741 return MT_CIPHER_TKIP; 742 case WLAN_CIPHER_SUITE_CCMP: 743 return MT_CIPHER_AES_CCMP; 744 default: 745 return MT_CIPHER_NONE; 746 } 747 } 748 749 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid, 750 struct ieee80211_key_conf *key) 751 { 752 enum mt7603_cipher_type cipher; 753 u32 addr = mt7603_wtbl3_addr(wcid); 754 u8 key_data[32]; 755 int key_len = sizeof(key_data); 756 757 cipher = mt7603_mac_get_key_info(key, key_data); 758 if (cipher == MT_CIPHER_NONE && key) 759 return -EOPNOTSUPP; 760 761 if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) { 762 addr += key->keyidx * 16; 763 key_len = 16; 764 } 765 766 mt76_wr_copy(dev, addr, key_data, key_len); 767 768 addr = mt7603_wtbl1_addr(wcid); 769 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher); 770 if (key) 771 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); 772 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key); 773 774 return 0; 775 } 776 777 static int 778 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi, 779 struct sk_buff *skb, enum mt76_txq_id qid, 780 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 781 int pid, struct ieee80211_key_conf *key) 782 { 783 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 784 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 785 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 786 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; 787 struct ieee80211_vif *vif = info->control.vif; 788 struct mt76_queue *q = dev->mt76.q_tx[qid].q; 789 struct mt7603_vif *mvif; 790 int wlan_idx; 791 int hdr_len = ieee80211_get_hdrlen_from_skb(skb); 792 int tx_count = 8; 793 u8 frame_type, frame_subtype; 794 u16 fc = le16_to_cpu(hdr->frame_control); 795 u16 seqno = 0; 796 u8 vif_idx = 0; 797 u32 val; 798 u8 bw; 799 800 if (vif) { 801 mvif = (struct mt7603_vif *)vif->drv_priv; 802 vif_idx = mvif->idx; 803 if (vif_idx && qid >= MT_TXQ_BEACON) 804 vif_idx += 0x10; 805 } 806 807 if (sta) { 808 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; 809 810 tx_count = msta->rate_count; 811 } 812 813 if (wcid) 814 wlan_idx = wcid->idx; 815 else 816 wlan_idx = MT7603_WTBL_RESERVED; 817 818 frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2; 819 frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4; 820 821 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | 822 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); 823 txwi[0] = cpu_to_le32(val); 824 825 val = MT_TXD1_LONG_FORMAT | 826 FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) | 827 FIELD_PREP(MT_TXD1_TID, 828 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | 829 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | 830 FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) | 831 FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) | 832 FIELD_PREP(MT_TXD1_PROTECTED, !!key); 833 txwi[1] = cpu_to_le32(val); 834 835 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 836 txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK); 837 838 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) | 839 FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) | 840 FIELD_PREP(MT_TXD2_MULTICAST, 841 is_multicast_ether_addr(hdr->addr1)); 842 txwi[2] = cpu_to_le32(val); 843 844 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) 845 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 846 847 txwi[4] = 0; 848 849 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT | 850 FIELD_PREP(MT_TXD5_PID, pid); 851 txwi[5] = cpu_to_le32(val); 852 853 txwi[6] = 0; 854 855 if (rate->idx >= 0 && rate->count && 856 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { 857 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; 858 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw); 859 860 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 861 862 val = MT_TXD6_FIXED_BW | 863 FIELD_PREP(MT_TXD6_BW, bw) | 864 FIELD_PREP(MT_TXD6_TX_RATE, rateval); 865 txwi[6] |= cpu_to_le32(val); 866 867 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) 868 txwi[6] |= cpu_to_le32(MT_TXD6_SGI); 869 870 if (!(rate->flags & IEEE80211_TX_RC_MCS)) 871 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE); 872 873 tx_count = rate->count; 874 } 875 876 /* use maximum tx count for beacons and buffered multicast */ 877 if (qid >= MT_TXQ_BEACON) 878 tx_count = 0x1f; 879 880 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) | 881 MT_TXD3_SN_VALID; 882 883 if (ieee80211_is_data_qos(hdr->frame_control)) 884 seqno = le16_to_cpu(hdr->seq_ctrl); 885 else if (ieee80211_is_back_req(hdr->frame_control)) 886 seqno = le16_to_cpu(bar->start_seq_num); 887 else 888 val &= ~MT_TXD3_SN_VALID; 889 890 val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4); 891 892 txwi[3] = cpu_to_le32(val); 893 894 if (key) { 895 u64 pn = atomic64_inc_return(&key->tx_pn); 896 897 txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID); 898 txwi[4] = cpu_to_le32(pn & GENMASK(31, 0)); 899 txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32)); 900 } 901 902 txwi[7] = 0; 903 904 return 0; 905 } 906 907 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 908 enum mt76_txq_id qid, struct mt76_wcid *wcid, 909 struct ieee80211_sta *sta, 910 struct mt76_tx_info *tx_info) 911 { 912 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 913 struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid); 914 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 915 struct ieee80211_key_conf *key = info->control.hw_key; 916 int pid; 917 918 if (!wcid) 919 wcid = &dev->global_sta.wcid; 920 921 if (sta) { 922 msta = (struct mt7603_sta *)sta->drv_priv; 923 924 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | 925 IEEE80211_TX_CTL_CLEAR_PS_FILT)) || 926 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) 927 mt7603_wtbl_set_ps(dev, msta, false); 928 } 929 930 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 931 932 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { 933 spin_lock_bh(&dev->mt76.lock); 934 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], 935 msta->rates); 936 msta->rate_probe = true; 937 spin_unlock_bh(&dev->mt76.lock); 938 } 939 940 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, 941 sta, pid, key); 942 943 return 0; 944 } 945 946 static bool 947 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta, 948 struct ieee80211_tx_info *info, __le32 *txs_data) 949 { 950 struct ieee80211_supported_band *sband; 951 struct mt7603_rate_set *rs; 952 int first_idx = 0, last_idx; 953 u32 rate_set_tsf; 954 u32 final_rate; 955 u32 final_rate_flags; 956 bool rs_idx; 957 bool ack_timeout; 958 bool fixed_rate; 959 bool probe; 960 bool ampdu; 961 bool cck = false; 962 int count; 963 u32 txs; 964 int idx; 965 int i; 966 967 fixed_rate = info->status.rates[0].count; 968 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 969 970 txs = le32_to_cpu(txs_data[4]); 971 ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU); 972 count = FIELD_GET(MT_TXS4_TX_COUNT, txs); 973 last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs); 974 975 txs = le32_to_cpu(txs_data[0]); 976 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs); 977 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT; 978 979 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT)) 980 return false; 981 982 if (txs & MT_TXS0_QUEUE_TIMEOUT) 983 return false; 984 985 if (!ack_timeout) 986 info->flags |= IEEE80211_TX_STAT_ACK; 987 988 info->status.ampdu_len = 1; 989 info->status.ampdu_ack_len = !!(info->flags & 990 IEEE80211_TX_STAT_ACK); 991 992 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) 993 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; 994 995 first_idx = max_t(int, 0, last_idx - (count + 1) / MT7603_RATE_RETRY); 996 997 if (fixed_rate && !probe) { 998 info->status.rates[0].count = count; 999 i = 0; 1000 goto out; 1001 } 1002 1003 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); 1004 rs_idx = !((u32)(FIELD_GET(MT_TXS1_F0_TIMESTAMP, le32_to_cpu(txs_data[1])) - 1005 rate_set_tsf) < 1000000); 1006 rs_idx ^= rate_set_tsf & BIT(0); 1007 rs = &sta->rateset[rs_idx]; 1008 1009 if (!first_idx && rs->probe_rate.idx >= 0) { 1010 info->status.rates[0] = rs->probe_rate; 1011 1012 spin_lock_bh(&dev->mt76.lock); 1013 if (sta->rate_probe) { 1014 mt7603_wtbl_set_rates(dev, sta, NULL, 1015 sta->rates); 1016 sta->rate_probe = false; 1017 } 1018 spin_unlock_bh(&dev->mt76.lock); 1019 } else { 1020 info->status.rates[0] = rs->rates[first_idx / 2]; 1021 } 1022 info->status.rates[0].count = 0; 1023 1024 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) { 1025 struct ieee80211_tx_rate *cur_rate; 1026 int cur_count; 1027 1028 cur_rate = &rs->rates[idx / 2]; 1029 cur_count = min_t(int, MT7603_RATE_RETRY, count); 1030 count -= cur_count; 1031 1032 if (idx && (cur_rate->idx != info->status.rates[i].idx || 1033 cur_rate->flags != info->status.rates[i].flags)) { 1034 i++; 1035 if (i == ARRAY_SIZE(info->status.rates)) 1036 break; 1037 1038 info->status.rates[i] = *cur_rate; 1039 info->status.rates[i].count = 0; 1040 } 1041 1042 info->status.rates[i].count += cur_count; 1043 } 1044 1045 out: 1046 final_rate_flags = info->status.rates[i].flags; 1047 1048 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) { 1049 case MT_PHY_TYPE_CCK: 1050 cck = true; 1051 /* fall through */ 1052 case MT_PHY_TYPE_OFDM: 1053 if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) 1054 sband = &dev->mt76.sband_5g.sband; 1055 else 1056 sband = &dev->mt76.sband_2g.sband; 1057 final_rate &= GENMASK(5, 0); 1058 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, 1059 cck); 1060 final_rate_flags = 0; 1061 break; 1062 case MT_PHY_TYPE_HT_GF: 1063 case MT_PHY_TYPE_HT: 1064 final_rate_flags |= IEEE80211_TX_RC_MCS; 1065 final_rate &= GENMASK(5, 0); 1066 if (final_rate > 15) 1067 return false; 1068 break; 1069 default: 1070 return false; 1071 } 1072 1073 info->status.rates[i].idx = final_rate; 1074 info->status.rates[i].flags = final_rate_flags; 1075 1076 return true; 1077 } 1078 1079 static bool 1080 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid, 1081 __le32 *txs_data) 1082 { 1083 struct mt76_dev *mdev = &dev->mt76; 1084 struct sk_buff_head list; 1085 struct sk_buff *skb; 1086 1087 if (pid < MT_PACKET_ID_FIRST) 1088 return false; 1089 1090 mt76_tx_status_lock(mdev, &list); 1091 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); 1092 if (skb) { 1093 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1094 1095 if (!mt7603_fill_txs(dev, sta, info, txs_data)) { 1096 ieee80211_tx_info_clear_status(info); 1097 info->status.rates[0].idx = -1; 1098 } 1099 1100 mt76_tx_status_skb_done(mdev, skb, &list); 1101 } 1102 mt76_tx_status_unlock(mdev, &list); 1103 1104 return !!skb; 1105 } 1106 1107 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data) 1108 { 1109 struct ieee80211_tx_info info = {}; 1110 struct ieee80211_sta *sta = NULL; 1111 struct mt7603_sta *msta = NULL; 1112 struct mt76_wcid *wcid; 1113 __le32 *txs_data = data; 1114 u32 txs; 1115 u8 wcidx; 1116 u8 pid; 1117 1118 txs = le32_to_cpu(txs_data[4]); 1119 pid = FIELD_GET(MT_TXS4_PID, txs); 1120 txs = le32_to_cpu(txs_data[3]); 1121 wcidx = FIELD_GET(MT_TXS3_WCID, txs); 1122 1123 if (pid == MT_PACKET_ID_NO_ACK) 1124 return; 1125 1126 if (wcidx >= ARRAY_SIZE(dev->mt76.wcid)) 1127 return; 1128 1129 rcu_read_lock(); 1130 1131 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1132 if (!wcid) 1133 goto out; 1134 1135 msta = container_of(wcid, struct mt7603_sta, wcid); 1136 sta = wcid_to_sta(wcid); 1137 1138 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data)) 1139 goto out; 1140 1141 if (wcidx >= MT7603_WTBL_STA || !sta) 1142 goto out; 1143 1144 if (mt7603_fill_txs(dev, msta, &info, txs_data)) 1145 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info); 1146 1147 out: 1148 rcu_read_unlock(); 1149 } 1150 1151 void mt7603_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid, 1152 struct mt76_queue_entry *e) 1153 { 1154 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1155 struct sk_buff *skb = e->skb; 1156 1157 if (!e->txwi) { 1158 dev_kfree_skb_any(skb); 1159 return; 1160 } 1161 1162 if (qid < 4) 1163 dev->tx_hang_check = 0; 1164 1165 mt76_tx_complete_skb(mdev, skb); 1166 } 1167 1168 static bool 1169 wait_for_wpdma(struct mt7603_dev *dev) 1170 { 1171 return mt76_poll(dev, MT_WPDMA_GLO_CFG, 1172 MT_WPDMA_GLO_CFG_TX_DMA_BUSY | 1173 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 1174 0, 1000); 1175 } 1176 1177 static void mt7603_pse_reset(struct mt7603_dev *dev) 1178 { 1179 /* Clear previous reset result */ 1180 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1181 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S); 1182 1183 /* Reset PSE */ 1184 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1185 1186 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET, 1187 MT_MCU_DEBUG_RESET_PSE_S, 1188 MT_MCU_DEBUG_RESET_PSE_S, 500)) { 1189 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; 1190 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE); 1191 } else { 1192 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1193 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES); 1194 } 1195 1196 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) 1197 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; 1198 } 1199 1200 void mt7603_mac_dma_start(struct mt7603_dev *dev) 1201 { 1202 mt7603_mac_start(dev); 1203 1204 wait_for_wpdma(dev); 1205 usleep_range(50, 100); 1206 1207 mt76_set(dev, MT_WPDMA_GLO_CFG, 1208 (MT_WPDMA_GLO_CFG_TX_DMA_EN | 1209 MT_WPDMA_GLO_CFG_RX_DMA_EN | 1210 FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) | 1211 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE)); 1212 1213 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL); 1214 } 1215 1216 void mt7603_mac_start(struct mt7603_dev *dev) 1217 { 1218 mt76_clear(dev, MT_ARB_SCR, 1219 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1220 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0); 1221 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1222 } 1223 1224 void mt7603_mac_stop(struct mt7603_dev *dev) 1225 { 1226 mt76_set(dev, MT_ARB_SCR, 1227 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1228 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0); 1229 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START); 1230 } 1231 1232 void mt7603_pse_client_reset(struct mt7603_dev *dev) 1233 { 1234 u32 addr; 1235 1236 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + 1237 MT_CLIENT_RESET_TX); 1238 1239 /* Clear previous reset state */ 1240 mt76_clear(dev, addr, 1241 MT_CLIENT_RESET_TX_R_E_1 | 1242 MT_CLIENT_RESET_TX_R_E_2 | 1243 MT_CLIENT_RESET_TX_R_E_1_S | 1244 MT_CLIENT_RESET_TX_R_E_2_S); 1245 1246 /* Start PSE client TX abort */ 1247 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1); 1248 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S, 1249 MT_CLIENT_RESET_TX_R_E_1_S, 500); 1250 1251 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2); 1252 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET); 1253 1254 /* Wait for PSE client to clear TX FIFO */ 1255 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S, 1256 MT_CLIENT_RESET_TX_R_E_2_S, 500); 1257 1258 /* Clear PSE client TX abort state */ 1259 mt76_clear(dev, addr, 1260 MT_CLIENT_RESET_TX_R_E_1 | 1261 MT_CLIENT_RESET_TX_R_E_2); 1262 } 1263 1264 static void mt7603_dma_sched_reset(struct mt7603_dev *dev) 1265 { 1266 if (!is_mt7628(dev)) 1267 return; 1268 1269 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET); 1270 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET); 1271 } 1272 1273 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev) 1274 { 1275 int beacon_int = dev->mt76.beacon_int; 1276 u32 mask = dev->mt76.mmio.irqmask; 1277 int i; 1278 1279 ieee80211_stop_queues(dev->mt76.hw); 1280 set_bit(MT76_RESET, &dev->mt76.state); 1281 1282 /* lock/unlock all queues to ensure that no tx is pending */ 1283 mt76_txq_schedule_all(&dev->mt76); 1284 1285 tasklet_disable(&dev->mt76.tx_tasklet); 1286 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 1287 napi_disable(&dev->mt76.napi[0]); 1288 napi_disable(&dev->mt76.napi[1]); 1289 napi_disable(&dev->mt76.tx_napi); 1290 1291 mutex_lock(&dev->mt76.mutex); 1292 1293 mt7603_beacon_set_timer(dev, -1, 0); 1294 1295 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || 1296 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY || 1297 dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK || 1298 dev->cur_reset_cause == RESET_CAUSE_TX_HANG) 1299 mt7603_pse_reset(dev); 1300 1301 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED]) 1302 goto skip_dma_reset; 1303 1304 mt7603_mac_stop(dev); 1305 1306 mt76_clear(dev, MT_WPDMA_GLO_CFG, 1307 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN | 1308 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE); 1309 usleep_range(1000, 2000); 1310 1311 mt7603_irq_disable(dev, mask); 1312 1313 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF); 1314 1315 mt7603_pse_client_reset(dev); 1316 1317 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_tx); i++) 1318 mt76_queue_tx_cleanup(dev, i, true); 1319 1320 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_rx); i++) 1321 mt76_queue_rx_reset(dev, i); 1322 1323 mt7603_dma_sched_reset(dev); 1324 1325 mt7603_mac_dma_start(dev); 1326 1327 mt7603_irq_enable(dev, mask); 1328 1329 skip_dma_reset: 1330 clear_bit(MT76_RESET, &dev->mt76.state); 1331 mutex_unlock(&dev->mt76.mutex); 1332 1333 tasklet_enable(&dev->mt76.tx_tasklet); 1334 napi_enable(&dev->mt76.tx_napi); 1335 napi_schedule(&dev->mt76.tx_napi); 1336 1337 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); 1338 mt7603_beacon_set_timer(dev, -1, beacon_int); 1339 1340 napi_enable(&dev->mt76.napi[0]); 1341 napi_schedule(&dev->mt76.napi[0]); 1342 1343 napi_enable(&dev->mt76.napi[1]); 1344 napi_schedule(&dev->mt76.napi[1]); 1345 1346 ieee80211_wake_queues(dev->mt76.hw); 1347 mt76_txq_schedule_all(&dev->mt76); 1348 } 1349 1350 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index) 1351 { 1352 u32 val; 1353 1354 mt76_wr(dev, MT_WPDMA_DEBUG, 1355 FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) | 1356 MT_WPDMA_DEBUG_SEL); 1357 1358 val = mt76_rr(dev, MT_WPDMA_DEBUG); 1359 return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val); 1360 } 1361 1362 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev) 1363 { 1364 if (is_mt7628(dev)) 1365 return mt7603_dma_debug(dev, 9) & BIT(9); 1366 1367 return mt7603_dma_debug(dev, 2) & BIT(8); 1368 } 1369 1370 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev) 1371 { 1372 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY)) 1373 return false; 1374 1375 return mt7603_rx_fifo_busy(dev); 1376 } 1377 1378 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev) 1379 { 1380 u32 val; 1381 1382 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY)) 1383 return false; 1384 1385 val = mt7603_dma_debug(dev, 9); 1386 return (val & BIT(8)) && (val & 0xf) != 0xf; 1387 } 1388 1389 static bool mt7603_tx_hang(struct mt7603_dev *dev) 1390 { 1391 struct mt76_queue *q; 1392 u32 dma_idx, prev_dma_idx; 1393 int i; 1394 1395 for (i = 0; i < 4; i++) { 1396 q = dev->mt76.q_tx[i].q; 1397 1398 if (!q->queued) 1399 continue; 1400 1401 prev_dma_idx = dev->tx_dma_idx[i]; 1402 dma_idx = readl(&q->regs->dma_idx); 1403 dev->tx_dma_idx[i] = dma_idx; 1404 1405 if (dma_idx == prev_dma_idx && 1406 dma_idx != readl(&q->regs->cpu_idx)) 1407 break; 1408 } 1409 1410 return i < 4; 1411 } 1412 1413 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev) 1414 { 1415 u32 addr, val; 1416 1417 if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES) 1418 return true; 1419 1420 if (mt7603_rx_fifo_busy(dev)) 1421 return false; 1422 1423 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS); 1424 mt76_wr(dev, addr, 3); 1425 val = mt76_rr(dev, addr) >> 16; 1426 1427 if (is_mt7628(dev) && (val & 0x4001) == 0x4001) 1428 return true; 1429 1430 return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001; 1431 } 1432 1433 static bool 1434 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter, 1435 enum mt7603_reset_cause cause, 1436 bool (*check)(struct mt7603_dev *dev)) 1437 { 1438 if (dev->reset_test == cause + 1) { 1439 dev->reset_test = 0; 1440 goto trigger; 1441 } 1442 1443 if (check) { 1444 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) { 1445 *counter = 0; 1446 return false; 1447 } 1448 1449 (*counter)++; 1450 } 1451 1452 if (*counter < MT7603_WATCHDOG_TIMEOUT) 1453 return false; 1454 trigger: 1455 dev->cur_reset_cause = cause; 1456 dev->reset_cause[cause]++; 1457 return true; 1458 } 1459 1460 void mt7603_update_channel(struct mt76_dev *mdev) 1461 { 1462 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 1463 struct mt76_channel_state *state; 1464 ktime_t cur_time; 1465 u32 busy; 1466 1467 if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state)) 1468 return; 1469 1470 state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan); 1471 busy = mt76_rr(dev, MT_MIB_STAT_PSCCA); 1472 1473 spin_lock_bh(&dev->mt76.cc_lock); 1474 cur_time = ktime_get_boottime(); 1475 state->cc_busy += busy; 1476 state->cc_active += ktime_to_us(ktime_sub(cur_time, 1477 dev->mt76.survey_time)); 1478 dev->mt76.survey_time = cur_time; 1479 spin_unlock_bh(&dev->mt76.cc_lock); 1480 } 1481 1482 void 1483 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val) 1484 { 1485 u32 rxtd_6 = 0xd7c80000; 1486 1487 if (val == dev->ed_strict_mode) 1488 return; 1489 1490 dev->ed_strict_mode = val; 1491 1492 /* Ensure that ED/CCA does not trigger if disabled */ 1493 if (!dev->ed_monitor) 1494 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34); 1495 else 1496 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d); 1497 1498 if (dev->ed_monitor && !dev->ed_strict_mode) 1499 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f); 1500 else 1501 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10); 1502 1503 mt76_wr(dev, MT_RXTD(6), rxtd_6); 1504 1505 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN, 1506 dev->ed_monitor && !dev->ed_strict_mode); 1507 } 1508 1509 static void 1510 mt7603_edcca_check(struct mt7603_dev *dev) 1511 { 1512 u32 val = mt76_rr(dev, MT_AGC(41)); 1513 ktime_t cur_time; 1514 int rssi0, rssi1; 1515 u32 active; 1516 u32 ed_busy; 1517 1518 if (!dev->ed_monitor) 1519 return; 1520 1521 rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val); 1522 if (rssi0 > 128) 1523 rssi0 -= 256; 1524 1525 rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val); 1526 if (rssi1 > 128) 1527 rssi1 -= 256; 1528 1529 if (max(rssi0, rssi1) >= -40 && 1530 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) 1531 dev->ed_strong_signal++; 1532 else if (dev->ed_strong_signal > 0) 1533 dev->ed_strong_signal--; 1534 1535 cur_time = ktime_get_boottime(); 1536 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK; 1537 1538 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); 1539 dev->ed_time = cur_time; 1540 1541 if (!active) 1542 return; 1543 1544 if (100 * ed_busy / active > 90) { 1545 if (dev->ed_trigger < 0) 1546 dev->ed_trigger = 0; 1547 dev->ed_trigger++; 1548 } else { 1549 if (dev->ed_trigger > 0) 1550 dev->ed_trigger = 0; 1551 dev->ed_trigger--; 1552 } 1553 1554 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || 1555 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { 1556 mt7603_edcca_set_strict(dev, true); 1557 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { 1558 mt7603_edcca_set_strict(dev, false); 1559 } 1560 1561 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) 1562 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; 1563 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) 1564 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; 1565 } 1566 1567 void mt7603_cca_stats_reset(struct mt7603_dev *dev) 1568 { 1569 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1570 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET); 1571 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN); 1572 } 1573 1574 static void 1575 mt7603_adjust_sensitivity(struct mt7603_dev *dev) 1576 { 1577 u32 agc0 = dev->agc0, agc3 = dev->agc3; 1578 u32 adj; 1579 1580 if (!dev->sensitivity || dev->sensitivity < -100) { 1581 dev->sensitivity = 0; 1582 } else if (dev->sensitivity <= -84) { 1583 adj = 7 + (dev->sensitivity + 92) / 2; 1584 1585 agc0 = 0x56f0076f; 1586 agc0 |= adj << 12; 1587 agc0 |= adj << 16; 1588 agc3 = 0x81d0d5e3; 1589 } else if (dev->sensitivity <= -72) { 1590 adj = 7 + (dev->sensitivity + 80) / 2; 1591 1592 agc0 = 0x6af0006f; 1593 agc0 |= adj << 8; 1594 agc0 |= adj << 12; 1595 agc0 |= adj << 16; 1596 1597 agc3 = 0x8181d5e3; 1598 } else { 1599 if (dev->sensitivity > -54) 1600 dev->sensitivity = -54; 1601 1602 adj = 7 + (dev->sensitivity + 80) / 2; 1603 1604 agc0 = 0x7ff0000f; 1605 agc0 |= adj << 4; 1606 agc0 |= adj << 8; 1607 agc0 |= adj << 12; 1608 agc0 |= adj << 16; 1609 1610 agc3 = 0x818181e3; 1611 } 1612 1613 mt76_wr(dev, MT_AGC(0), agc0); 1614 mt76_wr(dev, MT_AGC1(0), agc0); 1615 1616 mt76_wr(dev, MT_AGC(3), agc3); 1617 mt76_wr(dev, MT_AGC1(3), agc3); 1618 } 1619 1620 static void 1621 mt7603_false_cca_check(struct mt7603_dev *dev) 1622 { 1623 int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm; 1624 int false_cca; 1625 int min_signal; 1626 u32 val; 1627 1628 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); 1629 pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val); 1630 pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val); 1631 1632 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); 1633 mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val); 1634 mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val); 1635 1636 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; 1637 dev->false_cca_cck = pd_cck - mdrdy_cck; 1638 1639 mt7603_cca_stats_reset(dev); 1640 1641 min_signal = mt76_get_min_avg_rssi(&dev->mt76); 1642 if (!min_signal) { 1643 dev->sensitivity = 0; 1644 dev->last_cca_adj = jiffies; 1645 goto out; 1646 } 1647 1648 min_signal -= 15; 1649 1650 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; 1651 if (false_cca > 600) { 1652 if (!dev->sensitivity) 1653 dev->sensitivity = -92; 1654 else 1655 dev->sensitivity += 2; 1656 dev->last_cca_adj = jiffies; 1657 } else if (false_cca < 100 || 1658 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { 1659 dev->last_cca_adj = jiffies; 1660 if (!dev->sensitivity) 1661 goto out; 1662 1663 dev->sensitivity -= 2; 1664 } 1665 1666 if (dev->sensitivity && dev->sensitivity > min_signal) { 1667 dev->sensitivity = min_signal; 1668 dev->last_cca_adj = jiffies; 1669 } 1670 1671 out: 1672 mt7603_adjust_sensitivity(dev); 1673 } 1674 1675 void mt7603_mac_work(struct work_struct *work) 1676 { 1677 struct mt7603_dev *dev = container_of(work, struct mt7603_dev, 1678 mt76.mac_work.work); 1679 bool reset = false; 1680 1681 mt76_tx_status_check(&dev->mt76, NULL, false); 1682 1683 mutex_lock(&dev->mt76.mutex); 1684 1685 dev->mac_work_count++; 1686 mt7603_update_channel(&dev->mt76); 1687 mt7603_edcca_check(dev); 1688 1689 if (dev->mac_work_count == 10) 1690 mt7603_false_cca_check(dev); 1691 1692 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, 1693 RESET_CAUSE_RX_PSE_BUSY, 1694 mt7603_rx_pse_busy) || 1695 mt7603_watchdog_check(dev, &dev->beacon_check, 1696 RESET_CAUSE_BEACON_STUCK, 1697 NULL) || 1698 mt7603_watchdog_check(dev, &dev->tx_hang_check, 1699 RESET_CAUSE_TX_HANG, 1700 mt7603_tx_hang) || 1701 mt7603_watchdog_check(dev, &dev->tx_dma_check, 1702 RESET_CAUSE_TX_BUSY, 1703 mt7603_tx_dma_busy) || 1704 mt7603_watchdog_check(dev, &dev->rx_dma_check, 1705 RESET_CAUSE_RX_BUSY, 1706 mt7603_rx_dma_busy) || 1707 mt7603_watchdog_check(dev, &dev->mcu_hang, 1708 RESET_CAUSE_MCU_HANG, 1709 NULL) || 1710 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { 1711 dev->beacon_check = 0; 1712 dev->tx_dma_check = 0; 1713 dev->tx_hang_check = 0; 1714 dev->rx_dma_check = 0; 1715 dev->rx_pse_check = 0; 1716 dev->mcu_hang = 0; 1717 dev->rx_dma_idx = ~0; 1718 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); 1719 reset = true; 1720 dev->mac_work_count = 0; 1721 } 1722 1723 if (dev->mac_work_count >= 10) 1724 dev->mac_work_count = 0; 1725 1726 mutex_unlock(&dev->mt76.mutex); 1727 1728 if (reset) 1729 mt7603_mac_watchdog_reset(dev); 1730 1731 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work, 1732 msecs_to_jiffies(MT7603_WATCHDOG_TIME)); 1733 } 1734