1 /* SPDX-License-Identifier: ISC */
2 
3 #include <linux/etherdevice.h>
4 #include <linux/timekeeping.h>
5 #include "mt7603.h"
6 #include "mac.h"
7 
8 #define MT_PSE_PAGE_SIZE	128
9 
10 static u32
11 mt7603_ac_queue_mask0(u32 mask)
12 {
13 	u32 ret = 0;
14 
15 	ret |= GENMASK(3, 0) * !!(mask & BIT(0));
16 	ret |= GENMASK(8, 5) * !!(mask & BIT(1));
17 	ret |= GENMASK(13, 10) * !!(mask & BIT(2));
18 	ret |= GENMASK(19, 16) * !!(mask & BIT(3));
19 	return ret;
20 }
21 
22 static void
23 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
24 {
25 	mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
26 }
27 
28 static void
29 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
30 {
31 	mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
32 }
33 
34 void mt7603_mac_set_timing(struct mt7603_dev *dev)
35 {
36 	u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
37 		  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
38 	u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
39 		   FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24);
40 	int offset = 3 * dev->coverage_class;
41 	u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
42 			 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
43 	int sifs;
44 	u32 val;
45 
46 	if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
47 		sifs = 16;
48 	else
49 		sifs = 10;
50 
51 	mt76_set(dev, MT_ARB_SCR,
52 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
53 	udelay(1);
54 
55 	mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
56 	mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
57 	mt76_wr(dev, MT_IFS,
58 		FIELD_PREP(MT_IFS_EIFS, 360) |
59 		FIELD_PREP(MT_IFS_RIFS, 2) |
60 		FIELD_PREP(MT_IFS_SIFS, sifs) |
61 		FIELD_PREP(MT_IFS_SLOT, dev->slottime));
62 
63 	if (dev->slottime < 20)
64 		val = MT7603_CFEND_RATE_DEFAULT;
65 	else
66 		val = MT7603_CFEND_RATE_11B;
67 
68 	mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
69 
70 	mt76_clear(dev, MT_ARB_SCR,
71 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
72 }
73 
74 static void
75 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
76 {
77 	mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
78 		 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
79 
80 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
81 }
82 
83 static u32
84 mt7603_wtbl1_addr(int idx)
85 {
86 	return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
87 }
88 
89 static u32
90 mt7603_wtbl2_addr(int idx)
91 {
92 	/* Mapped to WTBL2 */
93 	return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
94 }
95 
96 static u32
97 mt7603_wtbl3_addr(int idx)
98 {
99 	u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
100 
101 	return base + idx * MT_WTBL3_SIZE;
102 }
103 
104 static u32
105 mt7603_wtbl4_addr(int idx)
106 {
107 	u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
108 
109 	return base + idx * MT_WTBL4_SIZE;
110 }
111 
112 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
113 		      const u8 *mac_addr)
114 {
115 	const void *_mac = mac_addr;
116 	u32 addr = mt7603_wtbl1_addr(idx);
117 	u32 w0 = 0, w1 = 0;
118 	int i;
119 
120 	if (_mac) {
121 		w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI,
122 				get_unaligned_le16(_mac + 4));
123 		w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO,
124 				get_unaligned_le32(_mac));
125 	}
126 
127 	if (vif < 0)
128 		vif = 0;
129 	else
130 		w0 |= MT_WTBL1_W0_RX_CHECK_A1;
131 	w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif);
132 
133 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
134 
135 	mt76_set(dev, addr + 0 * 4, w0);
136 	mt76_set(dev, addr + 1 * 4, w1);
137 	mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
138 
139 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
140 	addr = mt7603_wtbl2_addr(idx);
141 	for (i = 0; i < MT_WTBL2_SIZE; i += 4)
142 		mt76_wr(dev, addr + i, 0);
143 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
144 	mt76_start_tx_ac(dev, GENMASK(3, 0));
145 
146 	addr = mt7603_wtbl3_addr(idx);
147 	for (i = 0; i < MT_WTBL3_SIZE; i += 4)
148 		mt76_wr(dev, addr + i, 0);
149 
150 	addr = mt7603_wtbl4_addr(idx);
151 	for (i = 0; i < MT_WTBL4_SIZE; i += 4)
152 		mt76_wr(dev, addr + i, 0);
153 }
154 
155 static void
156 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
157 {
158 	u32 addr = mt7603_wtbl1_addr(idx);
159 	u32 val = mt76_rr(dev, addr + 3 * 4);
160 
161 	val &= ~MT_WTBL1_W3_SKIP_TX;
162 	val |= enabled * MT_WTBL1_W3_SKIP_TX;
163 
164 	mt76_wr(dev, addr + 3 * 4, val);
165 }
166 
167 void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
168 {
169 	int i, port, queue;
170 
171 	if (abort) {
172 		port = 3; /* PSE */
173 		queue = 8; /* free queue */
174 	} else {
175 		port = 0; /* HIF */
176 		queue = 1; /* MCU queue */
177 	}
178 
179 	mt7603_wtbl_set_skip_tx(dev, idx, true);
180 
181 	mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
182 			FIELD_PREP(MT_TX_ABORT_WCID, idx));
183 
184 	for (i = 0; i < 4; i++) {
185 		mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
186 			FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
187 			FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) |
188 			FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
189 			FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
190 
191 		WARN_ON_ONCE(!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY,
192 					0, 5000));
193 	}
194 
195 	mt76_wr(dev, MT_TX_ABORT, 0);
196 
197 	mt7603_wtbl_set_skip_tx(dev, idx, false);
198 }
199 
200 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
201 			  bool enabled)
202 {
203 	u32 addr = mt7603_wtbl1_addr(sta->wcid.idx);
204 
205 	if (sta->smps == enabled)
206 		return;
207 
208 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
209 	sta->smps = enabled;
210 }
211 
212 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
213 			bool enabled)
214 {
215 	int idx = sta->wcid.idx;
216 	u32 addr;
217 
218 	spin_lock_bh(&dev->ps_lock);
219 
220 	if (sta->ps == enabled)
221 		goto out;
222 
223 	mt76_wr(dev, MT_PSE_RTA,
224 		FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) |
225 		FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |
226 		FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) |
227 		FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) |
228 		MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY);
229 
230 	mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
231 
232 	if (enabled)
233 		mt7603_filter_tx(dev, idx, false);
234 
235 	addr = mt7603_wtbl1_addr(idx);
236 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
237 	mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
238 		 enabled * MT_WTBL1_W3_POWER_SAVE);
239 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
240 	sta->ps = enabled;
241 
242 out:
243 	spin_unlock_bh(&dev->ps_lock);
244 }
245 
246 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
247 {
248 	int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE;
249 	int wtbl2_frame = idx / wtbl2_frame_size;
250 	int wtbl2_entry = idx % wtbl2_frame_size;
251 
252 	int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE;
253 	int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE;
254 	int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size;
255 	int wtbl3_entry = (idx % wtbl3_frame_size) * 2;
256 
257 	int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE;
258 	int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE;
259 	int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size;
260 	int wtbl4_entry = idx % wtbl4_frame_size;
261 
262 	u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
263 	int i;
264 
265 	mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
266 
267 	mt76_wr(dev, addr + 0 * 4,
268 		MT_WTBL1_W0_RX_CHECK_A1 |
269 		MT_WTBL1_W0_RX_CHECK_A2 |
270 		MT_WTBL1_W0_RX_VALID);
271 	mt76_wr(dev, addr + 1 * 4, 0);
272 	mt76_wr(dev, addr + 2 * 4, 0);
273 
274 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
275 
276 	mt76_wr(dev, addr + 3 * 4,
277 		FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
278 		FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
279 		FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
280 		MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
281 	mt76_wr(dev, addr + 4 * 4,
282 		FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
283 		FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
284 		FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
285 
286 	mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
287 
288 	addr = mt7603_wtbl2_addr(idx);
289 
290 	/* Clear BA information */
291 	mt76_wr(dev, addr + (15 * 4), 0);
292 
293 	mt76_stop_tx_ac(dev, GENMASK(3, 0));
294 	for (i = 2; i <= 4; i++)
295 		mt76_wr(dev, addr + (i * 4), 0);
296 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
297 	mt76_start_tx_ac(dev, GENMASK(3, 0));
298 
299 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
300 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
301 	mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
302 }
303 
304 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
305 {
306 	struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
307 	int idx = msta->wcid.idx;
308 	u32 addr;
309 	u32 val;
310 
311 	addr = mt7603_wtbl1_addr(idx);
312 
313 	val = mt76_rr(dev, addr + 2 * 4);
314 	val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
315 	val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) |
316 	       FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) |
317 	       MT_WTBL1_W2_TXS_BAF_REPORT;
318 
319 	if (sta->ht_cap.cap)
320 		val |= MT_WTBL1_W2_HT;
321 	if (sta->vht_cap.cap)
322 		val |= MT_WTBL1_W2_VHT;
323 
324 	mt76_wr(dev, addr + 2 * 4, val);
325 
326 	addr = mt7603_wtbl2_addr(idx);
327 	val = mt76_rr(dev, addr + 9 * 4);
328 	val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
329 		 MT_WTBL2_W9_SHORT_GI_80);
330 	if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
331 		val |= MT_WTBL2_W9_SHORT_GI_20;
332 	if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
333 		val |= MT_WTBL2_W9_SHORT_GI_40;
334 	mt76_wr(dev, addr + 9 * 4, val);
335 }
336 
337 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
338 {
339 	mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
340 	mt76_wr(dev, MT_BA_CONTROL_1,
341 		(get_unaligned_le16(addr + 4) |
342 		 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
343 		 MT_BA_CONTROL_1_RESET));
344 }
345 
346 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
347 			    int ba_size)
348 {
349 	u32 addr = mt7603_wtbl2_addr(wcid);
350 	u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
351 		       (MT_WTBL2_W15_BA_WIN_SIZE <<
352 			(tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
353 	u32 tid_val;
354 	int i;
355 
356 	if (ba_size < 0) {
357 		/* disable */
358 		mt76_clear(dev, addr + (15 * 4), tid_mask);
359 		return;
360 	}
361 
362 	for (i = 7; i > 0; i--) {
363 		if (ba_size >= MT_AGG_SIZE_LIMIT(i))
364 			break;
365 	}
366 
367 	tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
368 		  i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
369 
370 	mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
371 }
372 
373 static int
374 mt7603_get_rate(struct mt7603_dev *dev, struct ieee80211_supported_band *sband,
375 		int idx, bool cck)
376 {
377 	int offset = 0;
378 	int len = sband->n_bitrates;
379 	int i;
380 
381 	if (cck) {
382 		if (sband == &dev->mt76.sband_5g.sband)
383 			return 0;
384 
385 		idx &= ~BIT(2); /* short preamble */
386 	} else if (sband == &dev->mt76.sband_2g.sband) {
387 		offset = 4;
388 	}
389 
390 	for (i = offset; i < len; i++) {
391 		if ((sband->bitrates[i].hw_value & GENMASK(7, 0)) == idx)
392 			return i;
393 	}
394 
395 	return 0;
396 }
397 
398 static struct mt76_wcid *
399 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
400 {
401 	struct mt7603_sta *sta;
402 	struct mt76_wcid *wcid;
403 
404 	if (idx >= ARRAY_SIZE(dev->mt76.wcid))
405 		return NULL;
406 
407 	wcid = rcu_dereference(dev->mt76.wcid[idx]);
408 	if (unicast || !wcid)
409 		return wcid;
410 
411 	if (!wcid->sta)
412 		return NULL;
413 
414 	sta = container_of(wcid, struct mt7603_sta, wcid);
415 	if (!sta->vif)
416 		return NULL;
417 
418 	return &sta->vif->sta.wcid;
419 }
420 
421 static void
422 mt7603_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id)
423 {
424 	struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
425 	int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
426 	u8 *pn = status->iv;
427 	u8 *hdr;
428 
429 	__skb_push(skb, 8);
430 	memmove(skb->data, skb->data + 8, hdr_len);
431 	hdr = skb->data + hdr_len;
432 
433 	hdr[0] = pn[5];
434 	hdr[1] = pn[4];
435 	hdr[2] = 0;
436 	hdr[3] = 0x20 | (key_id << 6);
437 	hdr[4] = pn[3];
438 	hdr[5] = pn[2];
439 	hdr[6] = pn[1];
440 	hdr[7] = pn[0];
441 
442 	status->flag &= ~RX_FLAG_IV_STRIPPED;
443 }
444 
445 int
446 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
447 {
448 	struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
449 	struct ieee80211_supported_band *sband;
450 	struct ieee80211_hdr *hdr;
451 	__le32 *rxd = (__le32 *)skb->data;
452 	u32 rxd0 = le32_to_cpu(rxd[0]);
453 	u32 rxd1 = le32_to_cpu(rxd[1]);
454 	u32 rxd2 = le32_to_cpu(rxd[2]);
455 	bool unicast = rxd1 & MT_RXD1_NORMAL_U2M;
456 	bool insert_ccmp_hdr = false;
457 	bool remove_pad;
458 	int idx;
459 	int i;
460 
461 	memset(status, 0, sizeof(*status));
462 
463 	i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
464 	sband = (i & 1) ? &dev->mt76.sband_5g.sband : &dev->mt76.sband_2g.sband;
465 	i >>= 1;
466 
467 	idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
468 	status->wcid = mt7603_rx_get_wcid(dev, idx, unicast);
469 
470 	status->band = sband->band;
471 	if (i < sband->n_channels)
472 		status->freq = sband->channels[i].center_freq;
473 
474 	if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
475 		status->flag |= RX_FLAG_FAILED_FCS_CRC;
476 
477 	if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
478 		status->flag |= RX_FLAG_MMIC_ERROR;
479 
480 	if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
481 	    !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
482 		status->flag |= RX_FLAG_DECRYPTED;
483 		status->flag |= RX_FLAG_IV_STRIPPED;
484 		status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
485 	}
486 
487 	remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
488 
489 	if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
490 		return -EINVAL;
491 
492 	if (!sband->channels)
493 		return -EINVAL;
494 
495 	rxd += 4;
496 	if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
497 		rxd += 4;
498 		if ((u8 *)rxd - skb->data >= skb->len)
499 			return -EINVAL;
500 	}
501 	if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
502 		u8 *data = (u8 *)rxd;
503 
504 		if (status->flag & RX_FLAG_DECRYPTED) {
505 			status->iv[0] = data[5];
506 			status->iv[1] = data[4];
507 			status->iv[2] = data[3];
508 			status->iv[3] = data[2];
509 			status->iv[4] = data[1];
510 			status->iv[5] = data[0];
511 
512 			insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
513 		}
514 
515 		rxd += 4;
516 		if ((u8 *)rxd - skb->data >= skb->len)
517 			return -EINVAL;
518 	}
519 	if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
520 		rxd += 2;
521 		if ((u8 *)rxd - skb->data >= skb->len)
522 			return -EINVAL;
523 	}
524 	if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
525 		u32 rxdg0 = le32_to_cpu(rxd[0]);
526 		u32 rxdg3 = le32_to_cpu(rxd[3]);
527 		bool cck = false;
528 
529 		i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
530 		switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
531 		case MT_PHY_TYPE_CCK:
532 			cck = true;
533 			/* fall through */
534 		case MT_PHY_TYPE_OFDM:
535 			i = mt7603_get_rate(dev, sband, i, cck);
536 			break;
537 		case MT_PHY_TYPE_HT_GF:
538 		case MT_PHY_TYPE_HT:
539 			status->encoding = RX_ENC_HT;
540 			if (i > 15)
541 				return -EINVAL;
542 			break;
543 		default:
544 			return -EINVAL;
545 		}
546 
547 		if (rxdg0 & MT_RXV1_HT_SHORT_GI)
548 			status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
549 		if (rxdg0 & MT_RXV1_HT_AD_CODE)
550 			status->enc_flags |= RX_ENC_FLAG_LDPC;
551 
552 		status->enc_flags |= RX_ENC_FLAG_STBC_MASK *
553 				    FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
554 
555 		status->rate_idx = i;
556 
557 		status->chains = dev->mt76.antenna_mask;
558 		status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +
559 					  dev->rssi_offset[0];
560 		status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) +
561 					  dev->rssi_offset[1];
562 
563 		status->signal = status->chain_signal[0];
564 		if (status->chains & BIT(1))
565 			status->signal = max(status->signal,
566 					     status->chain_signal[1]);
567 
568 		if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1)
569 			status->bw = RATE_INFO_BW_40;
570 
571 		rxd += 6;
572 		if ((u8 *)rxd - skb->data >= skb->len)
573 			return -EINVAL;
574 	} else {
575 		return -EINVAL;
576 	}
577 
578 	skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
579 
580 	if (insert_ccmp_hdr) {
581 		u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
582 
583 		mt7603_insert_ccmp_hdr(skb, key_id);
584 	}
585 
586 	hdr = (struct ieee80211_hdr *)skb->data;
587 	if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
588 		return 0;
589 
590 	status->aggr = unicast &&
591 		       !ieee80211_is_qos_nullfunc(hdr->frame_control);
592 	status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
593 	status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
594 
595 	return 0;
596 }
597 
598 static u16
599 mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
600 		       const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw)
601 {
602 	u8 phy, nss, rate_idx;
603 	u16 rateval;
604 
605 	*bw = 0;
606 	if (rate->flags & IEEE80211_TX_RC_MCS) {
607 		rate_idx = rate->idx;
608 		nss = 1 + (rate->idx >> 3);
609 		phy = MT_PHY_TYPE_HT;
610 		if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
611 			phy = MT_PHY_TYPE_HT_GF;
612 		if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
613 			*bw = 1;
614 	} else {
615 		const struct ieee80211_rate *r;
616 		int band = dev->mt76.chandef.chan->band;
617 		u16 val;
618 
619 		nss = 1;
620 		r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
621 		if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
622 			val = r->hw_value_short;
623 		else
624 			val = r->hw_value;
625 
626 		phy = val >> 8;
627 		rate_idx = val & 0xff;
628 	}
629 
630 	rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
631 		   FIELD_PREP(MT_TX_RATE_MODE, phy));
632 
633 	if (stbc && nss == 1)
634 		rateval |= MT_TX_RATE_STBC;
635 
636 	return rateval;
637 }
638 
639 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
640 			   struct ieee80211_tx_rate *probe_rate,
641 			   struct ieee80211_tx_rate *rates)
642 {
643 	int wcid = sta->wcid.idx;
644 	u32 addr = mt7603_wtbl2_addr(wcid);
645 	bool stbc = false;
646 	int n_rates = sta->n_rates;
647 	u8 bw, bw_prev, bw_idx = 0;
648 	u16 val[4];
649 	u16 probe_val;
650 	u32 w9 = mt76_rr(dev, addr + 9 * 4);
651 	int i;
652 
653 	if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
654 		return;
655 
656 	for (i = n_rates; i < 4; i++)
657 		rates[i] = rates[n_rates - 1];
658 
659 	w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
660 	      MT_WTBL2_W9_SHORT_GI_80;
661 
662 	val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
663 	bw_prev = bw;
664 
665 	if (probe_rate) {
666 		probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
667 		if (bw)
668 			bw_idx = 1;
669 		else
670 			bw_prev = 0;
671 	} else {
672 		probe_val = val[0];
673 	}
674 
675 	w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
676 	w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
677 
678 	val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
679 	if (bw_prev) {
680 		bw_idx = 3;
681 		bw_prev = bw;
682 	}
683 
684 	val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
685 	if (bw_prev) {
686 		bw_idx = 5;
687 		bw_prev = bw;
688 	}
689 
690 	val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
691 	if (bw_prev)
692 		bw_idx = 7;
693 
694 	w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
695 		       bw_idx ? bw_idx - 1 : 7);
696 
697 	mt76_wr(dev, MT_WTBL_RIUCR0, w9);
698 
699 	mt76_wr(dev, MT_WTBL_RIUCR1,
700 		FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
701 		FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
702 		FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[0]));
703 
704 	mt76_wr(dev, MT_WTBL_RIUCR2,
705 		FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[0] >> 8) |
706 		FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
707 		FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[1]) |
708 		FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
709 
710 	mt76_wr(dev, MT_WTBL_RIUCR3,
711 		FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
712 		FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[2]) |
713 		FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
714 
715 	mt76_wr(dev, MT_WTBL_UPDATE,
716 		FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
717 		MT_WTBL_UPDATE_RATE_UPDATE |
718 		MT_WTBL_UPDATE_TX_COUNT_CLEAR);
719 
720 	if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
721 		mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
722 
723 	sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates;
724 	sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
725 }
726 
727 static enum mt7603_cipher_type
728 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
729 {
730 	memset(key_data, 0, 32);
731 	if (!key)
732 		return MT_CIPHER_NONE;
733 
734 	if (key->keylen > 32)
735 		return MT_CIPHER_NONE;
736 
737 	memcpy(key_data, key->key, key->keylen);
738 
739 	switch (key->cipher) {
740 	case WLAN_CIPHER_SUITE_WEP40:
741 		return MT_CIPHER_WEP40;
742 	case WLAN_CIPHER_SUITE_WEP104:
743 		return MT_CIPHER_WEP104;
744 	case WLAN_CIPHER_SUITE_TKIP:
745 		/* Rx/Tx MIC keys are swapped */
746 		memcpy(key_data + 16, key->key + 24, 8);
747 		memcpy(key_data + 24, key->key + 16, 8);
748 		return MT_CIPHER_TKIP;
749 	case WLAN_CIPHER_SUITE_CCMP:
750 		return MT_CIPHER_AES_CCMP;
751 	default:
752 		return MT_CIPHER_NONE;
753 	}
754 }
755 
756 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
757 			struct ieee80211_key_conf *key)
758 {
759 	enum mt7603_cipher_type cipher;
760 	u32 addr = mt7603_wtbl3_addr(wcid);
761 	u8 key_data[32];
762 	int key_len = sizeof(key_data);
763 
764 	cipher = mt7603_mac_get_key_info(key, key_data);
765 	if (cipher == MT_CIPHER_NONE && key)
766 		return -EOPNOTSUPP;
767 
768 	if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) {
769 		addr += key->keyidx * 16;
770 		key_len = 16;
771 	}
772 
773 	mt76_wr_copy(dev, addr, key_data, key_len);
774 
775 	addr = mt7603_wtbl1_addr(wcid);
776 	mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
777 	if (key)
778 		mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
779 	mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
780 
781 	return 0;
782 }
783 
784 static int
785 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
786 		      struct sk_buff *skb, enum mt76_txq_id qid,
787 		      struct mt76_wcid *wcid, struct ieee80211_sta *sta,
788 		      int pid, struct ieee80211_key_conf *key)
789 {
790 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
791 	struct ieee80211_tx_rate *rate = &info->control.rates[0];
792 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
793 	struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
794 	struct ieee80211_vif *vif = info->control.vif;
795 	struct mt76_queue *q = dev->mt76.q_tx[qid].q;
796 	struct mt7603_vif *mvif;
797 	int wlan_idx;
798 	int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
799 	int tx_count = 8;
800 	u8 frame_type, frame_subtype;
801 	u16 fc = le16_to_cpu(hdr->frame_control);
802 	u16 seqno = 0;
803 	u8 vif_idx = 0;
804 	u32 val;
805 	u8 bw;
806 
807 	if (vif) {
808 		mvif = (struct mt7603_vif *)vif->drv_priv;
809 		vif_idx = mvif->idx;
810 		if (vif_idx && qid >= MT_TXQ_BEACON)
811 			vif_idx += 0x10;
812 	}
813 
814 	if (sta) {
815 		struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
816 
817 		tx_count = msta->rate_count;
818 	}
819 
820 	if (wcid)
821 		wlan_idx = wcid->idx;
822 	else
823 		wlan_idx = MT7603_WTBL_RESERVED;
824 
825 	frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
826 	frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
827 
828 	val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
829 	      FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
830 	txwi[0] = cpu_to_le32(val);
831 
832 	val = MT_TXD1_LONG_FORMAT |
833 	      FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
834 	      FIELD_PREP(MT_TXD1_TID,
835 			 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
836 	      FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
837 	      FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
838 	      FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
839 	      FIELD_PREP(MT_TXD1_PROTECTED, !!key);
840 	txwi[1] = cpu_to_le32(val);
841 
842 	if (info->flags & IEEE80211_TX_CTL_NO_ACK)
843 		txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
844 
845 	val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
846 	      FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
847 	      FIELD_PREP(MT_TXD2_MULTICAST,
848 			 is_multicast_ether_addr(hdr->addr1));
849 	txwi[2] = cpu_to_le32(val);
850 
851 	if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
852 		txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
853 
854 	txwi[4] = 0;
855 
856 	val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
857 	      FIELD_PREP(MT_TXD5_PID, pid);
858 	txwi[5] = cpu_to_le32(val);
859 
860 	txwi[6] = 0;
861 
862 	if (rate->idx >= 0 && rate->count &&
863 	    !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
864 		bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
865 		u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
866 
867 		txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
868 
869 		val = MT_TXD6_FIXED_BW |
870 		      FIELD_PREP(MT_TXD6_BW, bw) |
871 		      FIELD_PREP(MT_TXD6_TX_RATE, rateval);
872 		txwi[6] |= cpu_to_le32(val);
873 
874 		if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
875 			txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
876 
877 		if (!(rate->flags & IEEE80211_TX_RC_MCS))
878 			txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
879 
880 		tx_count = rate->count;
881 	}
882 
883 	/* use maximum tx count for beacons and buffered multicast */
884 	if (qid >= MT_TXQ_BEACON)
885 		tx_count = 0x1f;
886 
887 	val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
888 		  MT_TXD3_SN_VALID;
889 
890 	if (ieee80211_is_data_qos(hdr->frame_control))
891 		seqno = le16_to_cpu(hdr->seq_ctrl);
892 	else if (ieee80211_is_back_req(hdr->frame_control))
893 		seqno = le16_to_cpu(bar->start_seq_num);
894 	else
895 		val &= ~MT_TXD3_SN_VALID;
896 
897 	val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4);
898 
899 	txwi[3] = cpu_to_le32(val);
900 
901 	if (key) {
902 		u64 pn = atomic64_inc_return(&key->tx_pn);
903 
904 		txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
905 		txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
906 		txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
907 	}
908 
909 	txwi[7] = 0;
910 
911 	return 0;
912 }
913 
914 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
915 			  enum mt76_txq_id qid, struct mt76_wcid *wcid,
916 			  struct ieee80211_sta *sta,
917 			  struct mt76_tx_info *tx_info)
918 {
919 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
920 	struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid);
921 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
922 	struct ieee80211_key_conf *key = info->control.hw_key;
923 	int pid;
924 
925 	if (!wcid)
926 		wcid = &dev->global_sta.wcid;
927 
928 	if (sta) {
929 		msta = (struct mt7603_sta *)sta->drv_priv;
930 
931 		if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER |
932 				    IEEE80211_TX_CTL_CLEAR_PS_FILT)) ||
933 		    (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE))
934 			mt7603_wtbl_set_ps(dev, msta, false);
935 	}
936 
937 	pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
938 
939 	if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
940 		spin_lock_bh(&dev->mt76.lock);
941 		msta->rate_probe = true;
942 		mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],
943 				      msta->rates);
944 		spin_unlock_bh(&dev->mt76.lock);
945 	}
946 
947 	mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid,
948 			      sta, pid, key);
949 
950 	return 0;
951 }
952 
953 static bool
954 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
955 		struct ieee80211_tx_info *info, __le32 *txs_data)
956 {
957 	struct ieee80211_supported_band *sband;
958 	int final_idx = 0;
959 	u32 final_rate;
960 	u32 final_rate_flags;
961 	bool final_mpdu;
962 	bool ack_timeout;
963 	bool fixed_rate;
964 	bool probe;
965 	bool ampdu;
966 	bool cck = false;
967 	int count;
968 	u32 txs;
969 	u8 pid;
970 	int idx;
971 	int i;
972 
973 	fixed_rate = info->status.rates[0].count;
974 	probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
975 
976 	txs = le32_to_cpu(txs_data[4]);
977 	final_mpdu = txs & MT_TXS4_ACKED_MPDU;
978 	ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
979 	pid = FIELD_GET(MT_TXS4_PID, txs);
980 	count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
981 
982 	txs = le32_to_cpu(txs_data[0]);
983 	final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
984 	ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
985 
986 	if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
987 		return false;
988 
989 	if (txs & MT_TXS0_QUEUE_TIMEOUT)
990 		return false;
991 
992 	if (!ack_timeout)
993 		info->flags |= IEEE80211_TX_STAT_ACK;
994 
995 	info->status.ampdu_len = 1;
996 	info->status.ampdu_ack_len = !!(info->flags &
997 					IEEE80211_TX_STAT_ACK);
998 
999 	if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1000 		info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1001 
1002 	if (fixed_rate && !probe) {
1003 		info->status.rates[0].count = count;
1004 		goto out;
1005 	}
1006 
1007 	for (i = 0, idx = 0; i < ARRAY_SIZE(info->status.rates); i++) {
1008 		int cur_count = min_t(int, count, 2 * MT7603_RATE_RETRY);
1009 
1010 		if (!i && probe) {
1011 			cur_count = 1;
1012 		} else {
1013 			info->status.rates[i] = sta->rates[idx];
1014 			idx++;
1015 		}
1016 
1017 		if (i && info->status.rates[i].idx < 0) {
1018 			info->status.rates[i - 1].count += count;
1019 			break;
1020 		}
1021 
1022 		if (!count) {
1023 			info->status.rates[i].idx = -1;
1024 			break;
1025 		}
1026 
1027 		info->status.rates[i].count = cur_count;
1028 		final_idx = i;
1029 		count -= cur_count;
1030 	}
1031 
1032 out:
1033 	final_rate_flags = info->status.rates[final_idx].flags;
1034 
1035 	switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1036 	case MT_PHY_TYPE_CCK:
1037 		cck = true;
1038 		/* fall through */
1039 	case MT_PHY_TYPE_OFDM:
1040 		if (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ)
1041 			sband = &dev->mt76.sband_5g.sband;
1042 		else
1043 			sband = &dev->mt76.sband_2g.sband;
1044 		final_rate &= GENMASK(5, 0);
1045 		final_rate = mt7603_get_rate(dev, sband, final_rate, cck);
1046 		final_rate_flags = 0;
1047 		break;
1048 	case MT_PHY_TYPE_HT_GF:
1049 	case MT_PHY_TYPE_HT:
1050 		final_rate_flags |= IEEE80211_TX_RC_MCS;
1051 		final_rate &= GENMASK(5, 0);
1052 		if (final_rate > 15)
1053 			return false;
1054 		break;
1055 	default:
1056 		return false;
1057 	}
1058 
1059 	info->status.rates[final_idx].idx = final_rate;
1060 	info->status.rates[final_idx].flags = final_rate_flags;
1061 
1062 	return true;
1063 }
1064 
1065 static bool
1066 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
1067 		       __le32 *txs_data)
1068 {
1069 	struct mt76_dev *mdev = &dev->mt76;
1070 	struct sk_buff_head list;
1071 	struct sk_buff *skb;
1072 
1073 	if (pid < MT_PACKET_ID_FIRST)
1074 		return false;
1075 
1076 	mt76_tx_status_lock(mdev, &list);
1077 	skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1078 	if (skb) {
1079 		struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1080 
1081 		if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
1082 			spin_lock_bh(&dev->mt76.lock);
1083 			if (sta->rate_probe) {
1084 				mt7603_wtbl_set_rates(dev, sta, NULL,
1085 						      sta->rates);
1086 				sta->rate_probe = false;
1087 			}
1088 			spin_unlock_bh(&dev->mt76.lock);
1089 		}
1090 
1091 		if (!mt7603_fill_txs(dev, sta, info, txs_data)) {
1092 			ieee80211_tx_info_clear_status(info);
1093 			info->status.rates[0].idx = -1;
1094 		}
1095 
1096 		mt76_tx_status_skb_done(mdev, skb, &list);
1097 	}
1098 	mt76_tx_status_unlock(mdev, &list);
1099 
1100 	return !!skb;
1101 }
1102 
1103 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
1104 {
1105 	struct ieee80211_tx_info info = {};
1106 	struct ieee80211_sta *sta = NULL;
1107 	struct mt7603_sta *msta = NULL;
1108 	struct mt76_wcid *wcid;
1109 	__le32 *txs_data = data;
1110 	u32 txs;
1111 	u8 wcidx;
1112 	u8 pid;
1113 
1114 	txs = le32_to_cpu(txs_data[4]);
1115 	pid = FIELD_GET(MT_TXS4_PID, txs);
1116 	txs = le32_to_cpu(txs_data[3]);
1117 	wcidx = FIELD_GET(MT_TXS3_WCID, txs);
1118 
1119 	if (pid == MT_PACKET_ID_NO_ACK)
1120 		return;
1121 
1122 	if (wcidx >= ARRAY_SIZE(dev->mt76.wcid))
1123 		return;
1124 
1125 	rcu_read_lock();
1126 
1127 	wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1128 	if (!wcid)
1129 		goto out;
1130 
1131 	msta = container_of(wcid, struct mt7603_sta, wcid);
1132 	sta = wcid_to_sta(wcid);
1133 
1134 	if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data))
1135 		goto out;
1136 
1137 	if (wcidx >= MT7603_WTBL_STA || !sta)
1138 		goto out;
1139 
1140 	if (mt7603_fill_txs(dev, msta, &info, txs_data))
1141 		ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1142 
1143 out:
1144 	rcu_read_unlock();
1145 }
1146 
1147 void mt7603_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
1148 			    struct mt76_queue_entry *e)
1149 {
1150 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1151 	struct sk_buff *skb = e->skb;
1152 
1153 	if (!e->txwi) {
1154 		dev_kfree_skb_any(skb);
1155 		return;
1156 	}
1157 
1158 	if (qid < 4)
1159 		dev->tx_hang_check = 0;
1160 
1161 	mt76_tx_complete_skb(mdev, skb);
1162 }
1163 
1164 static bool
1165 wait_for_wpdma(struct mt7603_dev *dev)
1166 {
1167 	return mt76_poll(dev, MT_WPDMA_GLO_CFG,
1168 			 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
1169 			 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
1170 			 0, 1000);
1171 }
1172 
1173 static void mt7603_pse_reset(struct mt7603_dev *dev)
1174 {
1175 	/* Clear previous reset result */
1176 	if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1177 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
1178 
1179 	/* Reset PSE */
1180 	mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1181 
1182 	if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
1183 			    MT_MCU_DEBUG_RESET_PSE_S,
1184 			    MT_MCU_DEBUG_RESET_PSE_S, 500)) {
1185 		dev->reset_cause[RESET_CAUSE_RESET_FAILED]++;
1186 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1187 	} else {
1188 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1189 		mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
1190 	}
1191 
1192 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3)
1193 		dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1194 }
1195 
1196 void mt7603_mac_dma_start(struct mt7603_dev *dev)
1197 {
1198 	mt7603_mac_start(dev);
1199 
1200 	wait_for_wpdma(dev);
1201 	usleep_range(50, 100);
1202 
1203 	mt76_set(dev, MT_WPDMA_GLO_CFG,
1204 		 (MT_WPDMA_GLO_CFG_TX_DMA_EN |
1205 		  MT_WPDMA_GLO_CFG_RX_DMA_EN |
1206 		  FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
1207 		  MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
1208 
1209 	mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
1210 }
1211 
1212 void mt7603_mac_start(struct mt7603_dev *dev)
1213 {
1214 	mt76_clear(dev, MT_ARB_SCR,
1215 		   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1216 	mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
1217 	mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1218 }
1219 
1220 void mt7603_mac_stop(struct mt7603_dev *dev)
1221 {
1222 	mt76_set(dev, MT_ARB_SCR,
1223 		 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1224 	mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
1225 	mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1226 }
1227 
1228 void mt7603_pse_client_reset(struct mt7603_dev *dev)
1229 {
1230 	u32 addr;
1231 
1232 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR +
1233 				   MT_CLIENT_RESET_TX);
1234 
1235 	/* Clear previous reset state */
1236 	mt76_clear(dev, addr,
1237 		   MT_CLIENT_RESET_TX_R_E_1 |
1238 		   MT_CLIENT_RESET_TX_R_E_2 |
1239 		   MT_CLIENT_RESET_TX_R_E_1_S |
1240 		   MT_CLIENT_RESET_TX_R_E_2_S);
1241 
1242 	/* Start PSE client TX abort */
1243 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);
1244 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
1245 		       MT_CLIENT_RESET_TX_R_E_1_S, 500);
1246 
1247 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);
1248 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
1249 
1250 	/* Wait for PSE client to clear TX FIFO */
1251 	mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
1252 		       MT_CLIENT_RESET_TX_R_E_2_S, 500);
1253 
1254 	/* Clear PSE client TX abort state */
1255 	mt76_clear(dev, addr,
1256 		   MT_CLIENT_RESET_TX_R_E_1 |
1257 		   MT_CLIENT_RESET_TX_R_E_2);
1258 }
1259 
1260 static void mt7603_dma_sched_reset(struct mt7603_dev *dev)
1261 {
1262 	if (!is_mt7628(dev))
1263 		return;
1264 
1265 	mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
1266 	mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
1267 }
1268 
1269 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
1270 {
1271 	int beacon_int = dev->mt76.beacon_int;
1272 	u32 mask = dev->mt76.mmio.irqmask;
1273 	int i;
1274 
1275 	ieee80211_stop_queues(dev->mt76.hw);
1276 	set_bit(MT76_RESET, &dev->mt76.state);
1277 
1278 	/* lock/unlock all queues to ensure that no tx is pending */
1279 	mt76_txq_schedule_all(&dev->mt76);
1280 
1281 	tasklet_disable(&dev->mt76.tx_tasklet);
1282 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
1283 	napi_disable(&dev->mt76.napi[0]);
1284 	napi_disable(&dev->mt76.napi[1]);
1285 
1286 	mutex_lock(&dev->mt76.mutex);
1287 
1288 	mt7603_beacon_set_timer(dev, -1, 0);
1289 
1290 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] ||
1291 	    dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY ||
1292 	    dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK ||
1293 	    dev->cur_reset_cause == RESET_CAUSE_TX_HANG)
1294 		mt7603_pse_reset(dev);
1295 
1296 	if (dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1297 		goto skip_dma_reset;
1298 
1299 	mt7603_mac_stop(dev);
1300 
1301 	mt76_clear(dev, MT_WPDMA_GLO_CFG,
1302 		   MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1303 		   MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1304 	usleep_range(1000, 2000);
1305 
1306 	mt7603_irq_disable(dev, mask);
1307 
1308 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
1309 
1310 	mt7603_pse_client_reset(dev);
1311 
1312 	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_tx); i++)
1313 		mt76_queue_tx_cleanup(dev, i, true);
1314 
1315 	for (i = 0; i < ARRAY_SIZE(dev->mt76.q_rx); i++)
1316 		mt76_queue_rx_reset(dev, i);
1317 
1318 	mt7603_dma_sched_reset(dev);
1319 
1320 	mt7603_mac_dma_start(dev);
1321 
1322 	mt7603_irq_enable(dev, mask);
1323 
1324 skip_dma_reset:
1325 	clear_bit(MT76_RESET, &dev->mt76.state);
1326 	mutex_unlock(&dev->mt76.mutex);
1327 
1328 	tasklet_enable(&dev->mt76.tx_tasklet);
1329 	tasklet_schedule(&dev->mt76.tx_tasklet);
1330 
1331 	tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
1332 	mt7603_beacon_set_timer(dev, -1, beacon_int);
1333 
1334 	napi_enable(&dev->mt76.napi[0]);
1335 	napi_schedule(&dev->mt76.napi[0]);
1336 
1337 	napi_enable(&dev->mt76.napi[1]);
1338 	napi_schedule(&dev->mt76.napi[1]);
1339 
1340 	ieee80211_wake_queues(dev->mt76.hw);
1341 	mt76_txq_schedule_all(&dev->mt76);
1342 }
1343 
1344 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index)
1345 {
1346 	u32 val;
1347 
1348 	mt76_wr(dev, MT_WPDMA_DEBUG,
1349 		FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) |
1350 		MT_WPDMA_DEBUG_SEL);
1351 
1352 	val = mt76_rr(dev, MT_WPDMA_DEBUG);
1353 	return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val);
1354 }
1355 
1356 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev)
1357 {
1358 	if (is_mt7628(dev))
1359 		return mt7603_dma_debug(dev, 9) & BIT(9);
1360 
1361 	return mt7603_dma_debug(dev, 2) & BIT(8);
1362 }
1363 
1364 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev)
1365 {
1366 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY))
1367 		return false;
1368 
1369 	return mt7603_rx_fifo_busy(dev);
1370 }
1371 
1372 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
1373 {
1374 	u32 val;
1375 
1376 	if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY))
1377 		return false;
1378 
1379 	val = mt7603_dma_debug(dev, 9);
1380 	return (val & BIT(8)) && (val & 0xf) != 0xf;
1381 }
1382 
1383 static bool mt7603_tx_hang(struct mt7603_dev *dev)
1384 {
1385 	struct mt76_queue *q;
1386 	u32 dma_idx, prev_dma_idx;
1387 	int i;
1388 
1389 	for (i = 0; i < 4; i++) {
1390 		q = dev->mt76.q_tx[i].q;
1391 
1392 		if (!q->queued)
1393 			continue;
1394 
1395 		prev_dma_idx = dev->tx_dma_idx[i];
1396 		dma_idx = readl(&q->regs->dma_idx);
1397 		dev->tx_dma_idx[i] = dma_idx;
1398 
1399 		if (dma_idx == prev_dma_idx &&
1400 		    dma_idx != readl(&q->regs->cpu_idx))
1401 			break;
1402 	}
1403 
1404 	return i < 4;
1405 }
1406 
1407 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev)
1408 {
1409 	u32 addr, val;
1410 
1411 	if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES)
1412 		return true;
1413 
1414 	if (mt7603_rx_fifo_busy(dev))
1415 		return false;
1416 
1417 	addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS);
1418 	mt76_wr(dev, addr, 3);
1419 	val = mt76_rr(dev, addr) >> 16;
1420 
1421 	if (is_mt7628(dev) && (val & 0x4001) == 0x4001)
1422 		return true;
1423 
1424 	return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001;
1425 }
1426 
1427 static bool
1428 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter,
1429 		      enum mt7603_reset_cause cause,
1430 		      bool (*check)(struct mt7603_dev *dev))
1431 {
1432 	if (dev->reset_test == cause + 1) {
1433 		dev->reset_test = 0;
1434 		goto trigger;
1435 	}
1436 
1437 	if (check) {
1438 		if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) {
1439 			*counter = 0;
1440 			return false;
1441 		}
1442 
1443 		(*counter)++;
1444 	}
1445 
1446 	if (*counter < MT7603_WATCHDOG_TIMEOUT)
1447 		return false;
1448 trigger:
1449 	dev->cur_reset_cause = cause;
1450 	dev->reset_cause[cause]++;
1451 	return true;
1452 }
1453 
1454 void mt7603_update_channel(struct mt76_dev *mdev)
1455 {
1456 	struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1457 	struct mt76_channel_state *state;
1458 	ktime_t cur_time;
1459 	u32 busy;
1460 
1461 	if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
1462 		return;
1463 
1464 	state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan);
1465 	busy = mt76_rr(dev, MT_MIB_STAT_PSCCA);
1466 
1467 	spin_lock_bh(&dev->mt76.cc_lock);
1468 	cur_time = ktime_get_boottime();
1469 	state->cc_busy += busy;
1470 	state->cc_active += ktime_to_us(ktime_sub(cur_time, dev->survey_time));
1471 	dev->survey_time = cur_time;
1472 	spin_unlock_bh(&dev->mt76.cc_lock);
1473 }
1474 
1475 void
1476 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val)
1477 {
1478 	u32 rxtd_6 = 0xd7c80000;
1479 
1480 	if (val == dev->ed_strict_mode)
1481 		return;
1482 
1483 	dev->ed_strict_mode = val;
1484 
1485 	/* Ensure that ED/CCA does not trigger if disabled */
1486 	if (!dev->ed_monitor)
1487 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);
1488 	else
1489 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);
1490 
1491 	if (dev->ed_monitor && !dev->ed_strict_mode)
1492 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);
1493 	else
1494 		rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);
1495 
1496 	mt76_wr(dev, MT_RXTD(6), rxtd_6);
1497 
1498 	mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
1499 		       dev->ed_monitor && !dev->ed_strict_mode);
1500 }
1501 
1502 static void
1503 mt7603_edcca_check(struct mt7603_dev *dev)
1504 {
1505 	u32 val = mt76_rr(dev, MT_AGC(41));
1506 	ktime_t cur_time;
1507 	int rssi0, rssi1;
1508 	u32 active;
1509 	u32 ed_busy;
1510 
1511 	if (!dev->ed_monitor)
1512 		return;
1513 
1514 	rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val);
1515 	if (rssi0 > 128)
1516 		rssi0 -= 256;
1517 
1518 	rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val);
1519 	if (rssi1 > 128)
1520 		rssi1 -= 256;
1521 
1522 	if (max(rssi0, rssi1) >= -40 &&
1523 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH)
1524 		dev->ed_strong_signal++;
1525 	else if (dev->ed_strong_signal > 0)
1526 		dev->ed_strong_signal--;
1527 
1528 	cur_time = ktime_get_boottime();
1529 	ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK;
1530 
1531 	active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1532 	dev->ed_time = cur_time;
1533 
1534 	if (!active)
1535 		return;
1536 
1537 	if (100 * ed_busy / active > 90) {
1538 		if (dev->ed_trigger < 0)
1539 			dev->ed_trigger = 0;
1540 		dev->ed_trigger++;
1541 	} else {
1542 		if (dev->ed_trigger > 0)
1543 			dev->ed_trigger = 0;
1544 		dev->ed_trigger--;
1545 	}
1546 
1547 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH ||
1548 	    dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) {
1549 		mt7603_edcca_set_strict(dev, true);
1550 	} else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) {
1551 		mt7603_edcca_set_strict(dev, false);
1552 	}
1553 
1554 	if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH)
1555 		dev->ed_trigger = MT7603_EDCCA_BLOCK_TH;
1556 	else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH)
1557 		dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH;
1558 }
1559 
1560 void mt7603_cca_stats_reset(struct mt7603_dev *dev)
1561 {
1562 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1563 	mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1564 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);
1565 }
1566 
1567 static void
1568 mt7603_adjust_sensitivity(struct mt7603_dev *dev)
1569 {
1570 	u32 agc0 = dev->agc0, agc3 = dev->agc3;
1571 	u32 adj;
1572 
1573 	if (!dev->sensitivity || dev->sensitivity < -100) {
1574 		dev->sensitivity = 0;
1575 	} else if (dev->sensitivity <= -84) {
1576 		adj = 7 + (dev->sensitivity + 92) / 2;
1577 
1578 		agc0 = 0x56f0076f;
1579 		agc0 |= adj << 12;
1580 		agc0 |= adj << 16;
1581 		agc3 = 0x81d0d5e3;
1582 	} else if (dev->sensitivity <= -72) {
1583 		adj = 7 + (dev->sensitivity + 80) / 2;
1584 
1585 		agc0 = 0x6af0006f;
1586 		agc0 |= adj << 8;
1587 		agc0 |= adj << 12;
1588 		agc0 |= adj << 16;
1589 
1590 		agc3 = 0x8181d5e3;
1591 	} else {
1592 		if (dev->sensitivity > -54)
1593 			dev->sensitivity = -54;
1594 
1595 		adj = 7 + (dev->sensitivity + 80) / 2;
1596 
1597 		agc0 = 0x7ff0000f;
1598 		agc0 |= adj << 4;
1599 		agc0 |= adj << 8;
1600 		agc0 |= adj << 12;
1601 		agc0 |= adj << 16;
1602 
1603 		agc3 = 0x818181e3;
1604 	}
1605 
1606 	mt76_wr(dev, MT_AGC(0), agc0);
1607 	mt76_wr(dev, MT_AGC1(0), agc0);
1608 
1609 	mt76_wr(dev, MT_AGC(3), agc3);
1610 	mt76_wr(dev, MT_AGC1(3), agc3);
1611 }
1612 
1613 static void
1614 mt7603_false_cca_check(struct mt7603_dev *dev)
1615 {
1616 	int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm;
1617 	int false_cca;
1618 	int min_signal;
1619 	u32 val;
1620 
1621 	val = mt76_rr(dev, MT_PHYCTRL_STAT_PD);
1622 	pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val);
1623 	pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val);
1624 
1625 	val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY);
1626 	mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val);
1627 	mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val);
1628 
1629 	dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1630 	dev->false_cca_cck = pd_cck - mdrdy_cck;
1631 
1632 	mt7603_cca_stats_reset(dev);
1633 
1634 	min_signal = mt76_get_min_avg_rssi(&dev->mt76);
1635 	if (!min_signal) {
1636 		dev->sensitivity = 0;
1637 		dev->last_cca_adj = jiffies;
1638 		goto out;
1639 	}
1640 
1641 	min_signal -= 15;
1642 
1643 	false_cca = dev->false_cca_ofdm + dev->false_cca_cck;
1644 	if (false_cca > 600) {
1645 		if (!dev->sensitivity)
1646 			dev->sensitivity = -92;
1647 		else
1648 			dev->sensitivity += 2;
1649 		dev->last_cca_adj = jiffies;
1650 	} else if (false_cca < 100 ||
1651 		   time_after(jiffies, dev->last_cca_adj + 10 * HZ)) {
1652 		dev->last_cca_adj = jiffies;
1653 		if (!dev->sensitivity)
1654 			goto out;
1655 
1656 		dev->sensitivity -= 2;
1657 	}
1658 
1659 	if (dev->sensitivity && dev->sensitivity > min_signal) {
1660 		dev->sensitivity = min_signal;
1661 		dev->last_cca_adj = jiffies;
1662 	}
1663 
1664 out:
1665 	mt7603_adjust_sensitivity(dev);
1666 }
1667 
1668 void mt7603_mac_work(struct work_struct *work)
1669 {
1670 	struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
1671 					      mt76.mac_work.work);
1672 	bool reset = false;
1673 
1674 	mt76_tx_status_check(&dev->mt76, NULL, false);
1675 
1676 	mutex_lock(&dev->mt76.mutex);
1677 
1678 	dev->mac_work_count++;
1679 	mt7603_update_channel(&dev->mt76);
1680 	mt7603_edcca_check(dev);
1681 
1682 	if (dev->mac_work_count == 10)
1683 		mt7603_false_cca_check(dev);
1684 
1685 	if (mt7603_watchdog_check(dev, &dev->rx_pse_check,
1686 				  RESET_CAUSE_RX_PSE_BUSY,
1687 				  mt7603_rx_pse_busy) ||
1688 	    mt7603_watchdog_check(dev, &dev->beacon_check,
1689 				  RESET_CAUSE_BEACON_STUCK,
1690 				  NULL) ||
1691 	    mt7603_watchdog_check(dev, &dev->tx_hang_check,
1692 				  RESET_CAUSE_TX_HANG,
1693 				  mt7603_tx_hang) ||
1694 	    mt7603_watchdog_check(dev, &dev->tx_dma_check,
1695 				  RESET_CAUSE_TX_BUSY,
1696 				  mt7603_tx_dma_busy) ||
1697 	    mt7603_watchdog_check(dev, &dev->rx_dma_check,
1698 				  RESET_CAUSE_RX_BUSY,
1699 				  mt7603_rx_dma_busy) ||
1700 	    mt7603_watchdog_check(dev, &dev->mcu_hang,
1701 				  RESET_CAUSE_MCU_HANG,
1702 				  NULL) ||
1703 	    dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1704 		dev->beacon_check = 0;
1705 		dev->tx_dma_check = 0;
1706 		dev->tx_hang_check = 0;
1707 		dev->rx_dma_check = 0;
1708 		dev->rx_pse_check = 0;
1709 		dev->mcu_hang = 0;
1710 		dev->rx_dma_idx = ~0;
1711 		memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
1712 		reset = true;
1713 		dev->mac_work_count = 0;
1714 	}
1715 
1716 	if (dev->mac_work_count >= 10)
1717 		dev->mac_work_count = 0;
1718 
1719 	mutex_unlock(&dev->mt76.mutex);
1720 
1721 	if (reset)
1722 		mt7603_mac_watchdog_reset(dev);
1723 
1724 	ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mt76.mac_work,
1725 				     msecs_to_jiffies(MT7603_WATCHDOG_TIME));
1726 }
1727