1 /* SPDX-License-Identifier: ISC */ 2 3 #include <linux/etherdevice.h> 4 #include "mt7603.h" 5 #include "mac.h" 6 #include "eeprom.h" 7 8 const struct mt76_driver_ops mt7603_drv_ops = { 9 .txwi_size = MT_TXD_SIZE, 10 .tx_prepare_skb = mt7603_tx_prepare_skb, 11 .tx_complete_skb = mt7603_tx_complete_skb, 12 .rx_skb = mt7603_queue_rx_skb, 13 .rx_poll_complete = mt7603_rx_poll_complete, 14 .sta_ps = mt7603_sta_ps, 15 .sta_add = mt7603_sta_add, 16 .sta_assoc = mt7603_sta_assoc, 17 .sta_remove = mt7603_sta_remove, 18 .update_survey = mt7603_update_channel, 19 }; 20 21 static void 22 mt7603_set_tmac_template(struct mt7603_dev *dev) 23 { 24 u32 desc[5] = { 25 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), 26 [3] = MT_TXD5_SW_POWER_MGMT 27 }; 28 u32 addr; 29 int i; 30 31 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); 32 addr += MT_CLIENT_TMAC_INFO_TEMPLATE; 33 for (i = 0; i < ARRAY_SIZE(desc); i++) 34 mt76_wr(dev, addr + 4 * i, desc[i]); 35 } 36 37 static void 38 mt7603_dma_sched_init(struct mt7603_dev *dev) 39 { 40 int page_size = 128; 41 int page_count; 42 int max_len = 1792; 43 int max_amsdu_pages = 4096 / page_size; 44 int max_mcu_len = 4096; 45 int max_beacon_len = 512 * 4 + max_len; 46 int max_mcast_pages = 4 * max_len / page_size; 47 int reserved_count = 0; 48 int beacon_pages; 49 int mcu_pages; 50 int i; 51 52 page_count = mt76_get_field(dev, MT_PSE_FC_P0, 53 MT_PSE_FC_P0_MAX_QUOTA); 54 beacon_pages = 4 * (max_beacon_len / page_size); 55 mcu_pages = max_mcu_len / page_size; 56 57 mt76_wr(dev, MT_PSE_FRP, 58 FIELD_PREP(MT_PSE_FRP_P0, 7) | 59 FIELD_PREP(MT_PSE_FRP_P1, 6) | 60 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); 61 62 mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553); 63 mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555); 64 65 mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e); 66 mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c); 67 68 mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff); 69 70 mt76_wr(dev, MT_SCH_1, page_count | (2 << 28)); 71 mt76_wr(dev, MT_SCH_2, max_amsdu_pages); 72 73 for (i = 0; i <= 4; i++) 74 mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages); 75 reserved_count += 5 * max_amsdu_pages; 76 77 mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages); 78 reserved_count += mcu_pages; 79 80 mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages); 81 reserved_count += beacon_pages; 82 83 mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages); 84 reserved_count += max_mcast_pages; 85 86 if (is_mt7603(dev)) 87 reserved_count = 0; 88 89 mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count); 90 91 if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) { 92 mt76_wr(dev, MT_GROUP_THRESH(0), 93 page_count - beacon_pages - mcu_pages); 94 mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages); 95 mt76_wr(dev, MT_BMAP_0, 0x0080ff5f); 96 mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages); 97 mt76_wr(dev, MT_BMAP_1, 0x00000020); 98 } else { 99 mt76_wr(dev, MT_GROUP_THRESH(0), page_count); 100 mt76_wr(dev, MT_BMAP_0, 0xffff); 101 } 102 103 mt76_wr(dev, MT_SCH_4, 0); 104 105 for (i = 0; i <= 15; i++) 106 mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff); 107 108 mt76_set(dev, MT_SCH_4, BIT(6)); 109 } 110 111 static void 112 mt7603_phy_init(struct mt7603_dev *dev) 113 { 114 int rx_chains = dev->mt76.antenna_mask; 115 int tx_chains = hweight8(rx_chains) - 1; 116 117 mt76_rmw(dev, MT_WF_RMAC_RMCR, 118 (MT_WF_RMAC_RMCR_SMPS_MODE | 119 MT_WF_RMAC_RMCR_RX_STREAMS), 120 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | 121 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); 122 123 mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS, 124 tx_chains); 125 126 dev->agc0 = mt76_rr(dev, MT_AGC(0)); 127 dev->agc3 = mt76_rr(dev, MT_AGC(3)); 128 } 129 130 static void 131 mt7603_mac_init(struct mt7603_dev *dev) 132 { 133 u8 bc_addr[ETH_ALEN]; 134 u32 addr; 135 int i; 136 137 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0, 138 (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 139 (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 140 (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 141 (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); 142 143 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1, 144 (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 145 (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 146 (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | 147 (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); 148 149 mt76_wr(dev, MT_AGG_LIMIT, 150 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | 151 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | 152 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | 153 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); 154 155 mt76_wr(dev, MT_AGG_LIMIT_1, 156 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | 157 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | 158 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | 159 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); 160 161 mt76_wr(dev, MT_AGG_CONTROL, 162 FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) | 163 FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) | 164 MT_AGG_CONTROL_NO_BA_AR_RULE); 165 166 mt76_wr(dev, MT_AGG_RETRY_CONTROL, 167 FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) | 168 FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15)); 169 170 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP | 171 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096)); 172 173 mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13)); 174 mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13)); 175 176 mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31)); 177 178 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT); 179 mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000); 180 181 mt76_wr(dev, MT_WF_RFCR1, 0); 182 183 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE); 184 185 mt7603_set_tmac_template(dev); 186 187 /* Enable RX group to HIF */ 188 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); 189 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS); 190 191 /* Enable RX group to MCU */ 192 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11)); 193 194 mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3); 195 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN); 196 197 /* include preamble detection in CCA trigger signal */ 198 mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2); 199 200 mt76_wr(dev, MT_RXREQ, 4); 201 202 /* Configure all rx packets to HIF */ 203 mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000); 204 205 /* Configure MCU txs selection with aggregation */ 206 mt76_wr(dev, MT_DMA_TCFR0, 207 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ 208 MT_DMA_TCFR_TXS_AGGR_COUNT); 209 210 /* Configure HIF txs selection with aggregation */ 211 mt76_wr(dev, MT_DMA_TCFR1, 212 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ 213 MT_DMA_TCFR_TXS_AGGR_COUNT | /* Maximum count */ 214 MT_DMA_TCFR_TXS_BIT_MAP); 215 216 mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR); 217 218 for (i = 0; i < MT7603_WTBL_SIZE; i++) 219 mt7603_wtbl_clear(dev, i); 220 221 eth_broadcast_addr(bc_addr); 222 mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr); 223 dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED; 224 rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED], 225 &dev->global_sta.wcid); 226 227 mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2); 228 mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2); 229 230 mt76_wr(dev, MT_AGG_ARUCR, 231 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | 232 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | 233 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | 234 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | 235 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | 236 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | 237 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) | 238 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1)); 239 240 mt76_wr(dev, MT_AGG_ARDCR, 241 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) | 242 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) | 243 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) | 244 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) | 245 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) | 246 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) | 247 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) | 248 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1)); 249 250 mt76_wr(dev, MT_AGG_ARCR, 251 (MT_AGG_ARCR_INIT_RATE1 | 252 FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) | 253 MT_AGG_ARCR_RATE_DOWN_RATIO_EN | 254 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) | 255 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4))); 256 257 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE); 258 259 mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER); 260 mt76_clear(dev, MT_SEC_SCR, BIT(18)); 261 262 /* Set secondary beacon time offsets */ 263 for (i = 0; i <= 4; i++) 264 mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET, 265 (i + 1) * (20 + 4096)); 266 } 267 268 static int 269 mt7603_init_hardware(struct mt7603_dev *dev) 270 { 271 int i, ret; 272 273 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 274 275 ret = mt7603_eeprom_init(dev); 276 if (ret < 0) 277 return ret; 278 279 ret = mt7603_dma_init(dev); 280 if (ret) 281 return ret; 282 283 mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850); 284 mt7603_mac_dma_start(dev); 285 dev->rxfilter = mt76_rr(dev, MT_WF_RFCR); 286 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); 287 288 for (i = 0; i < MT7603_WTBL_SIZE; i++) { 289 mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE | 290 FIELD_PREP(MT_PSE_RTA_TAG_ID, i)); 291 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); 292 } 293 294 ret = mt7603_mcu_init(dev); 295 if (ret) 296 return ret; 297 298 mt7603_dma_sched_init(dev); 299 mt7603_mcu_set_eeprom(dev); 300 mt7603_phy_init(dev); 301 mt7603_mac_init(dev); 302 303 return 0; 304 } 305 306 #define CCK_RATE(_idx, _rate) { \ 307 .bitrate = _rate, \ 308 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 309 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 310 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 311 } 312 313 #define OFDM_RATE(_idx, _rate) { \ 314 .bitrate = _rate, \ 315 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 316 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 317 } 318 319 static struct ieee80211_rate mt7603_rates[] = { 320 CCK_RATE(0, 10), 321 CCK_RATE(1, 20), 322 CCK_RATE(2, 55), 323 CCK_RATE(3, 110), 324 OFDM_RATE(11, 60), 325 OFDM_RATE(15, 90), 326 OFDM_RATE(10, 120), 327 OFDM_RATE(14, 180), 328 OFDM_RATE(9, 240), 329 OFDM_RATE(13, 360), 330 OFDM_RATE(8, 480), 331 OFDM_RATE(12, 540), 332 }; 333 334 static const struct ieee80211_iface_limit if_limits[] = { 335 { 336 .max = 1, 337 .types = BIT(NL80211_IFTYPE_ADHOC) 338 }, { 339 .max = MT7603_MAX_INTERFACES, 340 .types = BIT(NL80211_IFTYPE_STATION) | 341 #ifdef CONFIG_MAC80211_MESH 342 BIT(NL80211_IFTYPE_MESH_POINT) | 343 #endif 344 BIT(NL80211_IFTYPE_AP) 345 }, 346 }; 347 348 static const struct ieee80211_iface_combination if_comb[] = { 349 { 350 .limits = if_limits, 351 .n_limits = ARRAY_SIZE(if_limits), 352 .max_interfaces = 4, 353 .num_different_channels = 1, 354 .beacon_int_infra_match = true, 355 } 356 }; 357 358 static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on, 359 u8 delay_off) 360 { 361 struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev, 362 mt76); 363 u32 val, addr; 364 365 val = MT_LED_STATUS_DURATION(0xffff) | 366 MT_LED_STATUS_OFF(delay_off) | 367 MT_LED_STATUS_ON(delay_on); 368 369 addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin)); 370 mt76_wr(dev, addr, val); 371 addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin)); 372 mt76_wr(dev, addr, val); 373 374 val = MT_LED_CTRL_REPLAY(mt76->led_pin) | 375 MT_LED_CTRL_KICK(mt76->led_pin); 376 if (mt76->led_al) 377 val |= MT_LED_CTRL_POLARITY(mt76->led_pin); 378 addr = mt7603_reg_map(dev, MT_LED_CTRL); 379 mt76_wr(dev, addr, val); 380 } 381 382 static int mt7603_led_set_blink(struct led_classdev *led_cdev, 383 unsigned long *delay_on, 384 unsigned long *delay_off) 385 { 386 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 387 led_cdev); 388 u8 delta_on, delta_off; 389 390 delta_off = max_t(u8, *delay_off / 10, 1); 391 delta_on = max_t(u8, *delay_on / 10, 1); 392 393 mt7603_led_set_config(mt76, delta_on, delta_off); 394 return 0; 395 } 396 397 static void mt7603_led_set_brightness(struct led_classdev *led_cdev, 398 enum led_brightness brightness) 399 { 400 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, 401 led_cdev); 402 403 if (!brightness) 404 mt7603_led_set_config(mt76, 0, 0xff); 405 else 406 mt7603_led_set_config(mt76, 0xff, 0); 407 } 408 409 static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr) 410 { 411 if (addr < 0x100000) 412 return addr; 413 414 return mt7603_reg_map(dev, addr); 415 } 416 417 static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset) 418 { 419 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 420 u32 addr = __mt7603_reg_addr(dev, offset); 421 422 return dev->bus_ops->rr(mdev, addr); 423 } 424 425 static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val) 426 { 427 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 428 u32 addr = __mt7603_reg_addr(dev, offset); 429 430 dev->bus_ops->wr(mdev, addr, val); 431 } 432 433 static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 434 { 435 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 436 u32 addr = __mt7603_reg_addr(dev, offset); 437 438 return dev->bus_ops->rmw(mdev, addr, mask, val); 439 } 440 441 static void 442 mt7603_regd_notifier(struct wiphy *wiphy, 443 struct regulatory_request *request) 444 { 445 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 446 struct mt7603_dev *dev = hw->priv; 447 448 dev->mt76.region = request->dfs_region; 449 dev->ed_monitor = dev->ed_monitor_enabled && 450 dev->mt76.region == NL80211_DFS_ETSI; 451 } 452 453 static int 454 mt7603_txpower_signed(int val) 455 { 456 bool sign = val & BIT(6); 457 458 if (!(val & BIT(7))) 459 return 0; 460 461 val &= GENMASK(5, 0); 462 if (!sign) 463 val = -val; 464 465 return val; 466 } 467 468 static void 469 mt7603_init_txpower(struct mt7603_dev *dev, 470 struct ieee80211_supported_band *sband) 471 { 472 struct ieee80211_channel *chan; 473 u8 *eeprom = (u8 *)dev->mt76.eeprom.data; 474 int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7); 475 u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK]; 476 bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1); 477 int max_offset, cur_offset; 478 int i; 479 480 if (ext_pa && is_mt7603(dev)) 481 target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7); 482 483 if (target_power & BIT(6)) 484 target_power = -(target_power & GENMASK(5, 0)); 485 486 max_offset = 0; 487 for (i = 0; i < 14; i++) { 488 cur_offset = mt7603_txpower_signed(rate_power[i]); 489 max_offset = max(max_offset, cur_offset); 490 } 491 492 target_power += max_offset; 493 494 dev->tx_power_limit = target_power; 495 dev->mt76.txpower_cur = target_power; 496 497 target_power = DIV_ROUND_UP(target_power, 2); 498 499 /* add 3 dBm for 2SS devices (combined output) */ 500 if (dev->mt76.antenna_mask & BIT(1)) 501 target_power += 3; 502 503 for (i = 0; i < sband->n_channels; i++) { 504 chan = &sband->channels[i]; 505 chan->max_power = min_t(int, chan->max_reg_power, target_power); 506 chan->orig_mpwr = target_power; 507 } 508 } 509 510 511 int mt7603_register_device(struct mt7603_dev *dev) 512 { 513 struct mt76_bus_ops *bus_ops; 514 struct ieee80211_hw *hw = mt76_hw(dev); 515 struct wiphy *wiphy = hw->wiphy; 516 int ret; 517 518 dev->bus_ops = dev->mt76.bus; 519 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 520 GFP_KERNEL); 521 if (!bus_ops) 522 return -ENOMEM; 523 524 bus_ops->rr = mt7603_rr; 525 bus_ops->wr = mt7603_wr; 526 bus_ops->rmw = mt7603_rmw; 527 dev->mt76.bus = bus_ops; 528 529 spin_lock_init(&dev->ps_lock); 530 531 INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7603_mac_work); 532 tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet, 533 (unsigned long)dev); 534 535 /* Check for 7688, which only has 1SS */ 536 dev->mt76.antenna_mask = 3; 537 if (mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4)) 538 dev->mt76.antenna_mask = 1; 539 540 dev->slottime = 9; 541 542 ret = mt7603_init_hardware(dev); 543 if (ret) 544 return ret; 545 546 hw->queues = 4; 547 hw->max_rates = 3; 548 hw->max_report_rates = 7; 549 hw->max_rate_tries = 11; 550 551 hw->sta_data_size = sizeof(struct mt7603_sta); 552 hw->vif_data_size = sizeof(struct mt7603_vif); 553 554 wiphy->iface_combinations = if_comb; 555 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 556 557 ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER); 558 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN); 559 560 /* init led callbacks */ 561 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 562 dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness; 563 dev->mt76.led_cdev.blink_set = mt7603_led_set_blink; 564 } 565 566 wiphy->interface_modes = 567 BIT(NL80211_IFTYPE_STATION) | 568 BIT(NL80211_IFTYPE_AP) | 569 #ifdef CONFIG_MAC80211_MESH 570 BIT(NL80211_IFTYPE_MESH_POINT) | 571 #endif 572 BIT(NL80211_IFTYPE_ADHOC); 573 574 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 575 576 wiphy->reg_notifier = mt7603_regd_notifier; 577 578 ret = mt76_register_device(&dev->mt76, true, mt7603_rates, 579 ARRAY_SIZE(mt7603_rates)); 580 if (ret) 581 return ret; 582 583 mt7603_init_debugfs(dev); 584 mt7603_init_txpower(dev, &dev->mt76.sband_2g.sband); 585 586 return 0; 587 } 588 589 void mt7603_unregister_device(struct mt7603_dev *dev) 590 { 591 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); 592 mt76_unregister_device(&dev->mt76); 593 mt7603_mcu_exit(dev); 594 mt7603_dma_cleanup(dev); 595 mt76_free_device(&dev->mt76); 596 } 597