1 /* SPDX-License-Identifier: ISC */ 2 3 #include "mt7603.h" 4 5 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 6 { 7 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); 8 9 mt7603_irq_enable(dev, MT_INT_RX_DONE(q)); 10 } 11 12 irqreturn_t mt7603_irq_handler(int irq, void *dev_instance) 13 { 14 struct mt7603_dev *dev = dev_instance; 15 u32 intr; 16 17 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 18 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 19 20 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mt76.state)) 21 return IRQ_NONE; 22 23 intr &= dev->mt76.mmio.irqmask; 24 25 if (intr & MT_INT_MAC_IRQ3) { 26 u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3)); 27 28 mt76_wr(dev, MT_HW_INT_STATUS(3), hwintr); 29 if (hwintr & MT_HW_INT3_PRE_TBTT0) 30 tasklet_schedule(&dev->mt76.pre_tbtt_tasklet); 31 32 if ((hwintr & MT_HW_INT3_TBTT0) && dev->mt76.csa_complete) 33 mt76_csa_finish(&dev->mt76); 34 } 35 36 if (intr & MT_INT_TX_DONE_ALL) { 37 mt7603_irq_disable(dev, MT_INT_TX_DONE_ALL); 38 tasklet_schedule(&dev->mt76.tx_tasklet); 39 } 40 41 if (intr & MT_INT_RX_DONE(0)) { 42 mt7603_irq_disable(dev, MT_INT_RX_DONE(0)); 43 napi_schedule(&dev->mt76.napi[0]); 44 } 45 46 if (intr & MT_INT_RX_DONE(1)) { 47 mt7603_irq_disable(dev, MT_INT_RX_DONE(1)); 48 napi_schedule(&dev->mt76.napi[1]); 49 } 50 51 return IRQ_HANDLED; 52 } 53 54 u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr) 55 { 56 u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE; 57 u32 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET; 58 59 dev->bus_ops->wr(&dev->mt76, MT_MCU_PCIE_REMAP_2, base); 60 61 return MT_PCIE_REMAP_BASE_2 + offset; 62 } 63