1 // SPDX-License-Identifier: ISC
2 
3 #include "mt7603.h"
4 
5 struct beacon_bc_data {
6 	struct mt7603_dev *dev;
7 	struct sk_buff_head q;
8 	struct sk_buff *tail[MT7603_MAX_INTERFACES];
9 	int count[MT7603_MAX_INTERFACES];
10 };
11 
12 static void
13 mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
14 {
15 	struct mt7603_dev *dev = (struct mt7603_dev *)priv;
16 	struct mt76_dev *mdev = &dev->mt76;
17 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
18 	struct sk_buff *skb = NULL;
19 
20 	if (!(mdev->beacon_mask & BIT(mvif->idx)))
21 		return;
22 
23 	skb = ieee80211_beacon_get(mt76_hw(dev), vif);
24 	if (!skb)
25 		return;
26 
27 	mt76_tx_queue_skb(dev, dev->mphy.q_tx[MT_TXQ_BEACON], skb,
28 			  &mvif->sta.wcid, NULL);
29 
30 	spin_lock_bh(&dev->ps_lock);
31 	mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
32 		FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, mvif->sta.wcid.idx) |
33 		FIELD_PREP(MT_DMA_FQCR0_TARGET_QID,
34 			   dev->mphy.q_tx[MT_TXQ_CAB]->hw_idx) |
35 		FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, 3) |
36 		FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, 8));
37 
38 	if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000))
39 		dev->beacon_check = MT7603_WATCHDOG_TIMEOUT;
40 
41 	spin_unlock_bh(&dev->ps_lock);
42 }
43 
44 static void
45 mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
46 {
47 	struct beacon_bc_data *data = priv;
48 	struct mt7603_dev *dev = data->dev;
49 	struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
50 	struct ieee80211_tx_info *info;
51 	struct sk_buff *skb;
52 
53 	if (!(dev->mt76.beacon_mask & BIT(mvif->idx)))
54 		return;
55 
56 	skb = ieee80211_get_buffered_bc(mt76_hw(dev), vif);
57 	if (!skb)
58 		return;
59 
60 	info = IEEE80211_SKB_CB(skb);
61 	info->control.vif = vif;
62 	info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
63 	mt76_skb_set_moredata(skb, true);
64 	__skb_queue_tail(&data->q, skb);
65 	data->tail[mvif->idx] = skb;
66 	data->count[mvif->idx]++;
67 }
68 
69 void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
70 {
71 	struct mt7603_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
72 	struct mt76_dev *mdev = &dev->mt76;
73 	struct mt76_queue *q;
74 	struct beacon_bc_data data = {};
75 	struct sk_buff *skb;
76 	int i, nframes;
77 
78 	if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
79 		return;
80 
81 	data.dev = dev;
82 	__skb_queue_head_init(&data.q);
83 
84 	q = dev->mphy.q_tx[MT_TXQ_BEACON];
85 	spin_lock_bh(&q->lock);
86 	ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
87 		IEEE80211_IFACE_ITER_RESUME_ALL,
88 		mt7603_update_beacon_iter, dev);
89 	mt76_queue_kick(dev, q);
90 	spin_unlock_bh(&q->lock);
91 
92 	/* Flush all previous CAB queue packets */
93 	mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
94 
95 	mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_CAB], false);
96 
97 	mt76_csa_check(mdev);
98 	if (mdev->csa_complete)
99 		goto out;
100 
101 	q = dev->mphy.q_tx[MT_TXQ_CAB];
102 	do {
103 		nframes = skb_queue_len(&data.q);
104 		ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
105 			IEEE80211_IFACE_ITER_RESUME_ALL,
106 			mt7603_add_buffered_bc, &data);
107 	} while (nframes != skb_queue_len(&data.q) &&
108 		 skb_queue_len(&data.q) < 8);
109 
110 	if (skb_queue_empty(&data.q))
111 		goto out;
112 
113 	for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
114 		if (!data.tail[i])
115 			continue;
116 
117 		mt76_skb_set_moredata(data.tail[i], false);
118 	}
119 
120 	spin_lock_bh(&q->lock);
121 	while ((skb = __skb_dequeue(&data.q)) != NULL) {
122 		struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
123 		struct ieee80211_vif *vif = info->control.vif;
124 		struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
125 
126 		mt76_tx_queue_skb(dev, q, skb, &mvif->sta.wcid, NULL);
127 	}
128 	mt76_queue_kick(dev, q);
129 	spin_unlock_bh(&q->lock);
130 
131 	for (i = 0; i < ARRAY_SIZE(data.count); i++)
132 		mt76_wr(dev, MT_WF_ARB_CAB_COUNT_B0_REG(i),
133 			data.count[i] << MT_WF_ARB_CAB_COUNT_B0_SHIFT(i));
134 
135 	mt76_wr(dev, MT_WF_ARB_CAB_START,
136 		MT_WF_ARB_CAB_START_BSSn(0) |
137 		(MT_WF_ARB_CAB_START_BSS0n(1) *
138 		 ((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
139 
140 out:
141 	mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BEACON], false);
142 	if (dev->mphy.q_tx[MT_TXQ_BEACON]->queued > hweight8(mdev->beacon_mask))
143 		dev->beacon_check++;
144 }
145 
146 void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval)
147 {
148 	u32 pre_tbtt = MT7603_PRE_TBTT_TIME / 64;
149 
150 	if (idx >= 0) {
151 		if (intval)
152 			dev->mt76.beacon_mask |= BIT(idx);
153 		else
154 			dev->mt76.beacon_mask &= ~BIT(idx);
155 	}
156 
157 	if (!dev->mt76.beacon_mask || (!intval && idx < 0)) {
158 		mt7603_irq_disable(dev, MT_INT_MAC_IRQ3);
159 		mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK);
160 		mt76_wr(dev, MT_HW_INT_MASK(3), 0);
161 		return;
162 	}
163 
164 	dev->mt76.beacon_int = intval;
165 	mt76_wr(dev, MT_TBTT,
166 		FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
167 
168 	mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */
169 
170 	mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK,
171 		       MT_BCNQ_OPMODE_AP);
172 	mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO);
173 	mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO);
174 
175 	mt76_wr(dev, MT_PRE_TBTT, pre_tbtt);
176 
177 	mt76_set(dev, MT_HW_INT_MASK(3),
178 		 MT_HW_INT3_PRE_TBTT0 | MT_HW_INT3_TBTT0);
179 
180 	mt76_set(dev, MT_WF_ARB_BCN_START,
181 		 MT_WF_ARB_BCN_START_BSSn(0) |
182 		 ((dev->mt76.beacon_mask >> 1) *
183 		  MT_WF_ARB_BCN_START_BSS0n(1)));
184 	mt7603_irq_enable(dev, MT_INT_MAC_IRQ3);
185 
186 	if (dev->mt76.beacon_mask & ~BIT(0))
187 		mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
188 	else
189 		mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
190 }
191