1c8846e10SFelix Fietkau /* SPDX-License-Identifier: ISC */ 2c8846e10SFelix Fietkau 3c8846e10SFelix Fietkau #include "mt7603.h" 4c8846e10SFelix Fietkau 5c8846e10SFelix Fietkau struct beacon_bc_data { 6c8846e10SFelix Fietkau struct mt7603_dev *dev; 7c8846e10SFelix Fietkau struct sk_buff_head q; 8c8846e10SFelix Fietkau struct sk_buff *tail[MT7603_MAX_INTERFACES]; 9c8846e10SFelix Fietkau int count[MT7603_MAX_INTERFACES]; 10c8846e10SFelix Fietkau }; 11c8846e10SFelix Fietkau 12c8846e10SFelix Fietkau static void 13c8846e10SFelix Fietkau mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif) 14c8846e10SFelix Fietkau { 15c8846e10SFelix Fietkau struct mt7603_dev *dev = (struct mt7603_dev *)priv; 16c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 17c8846e10SFelix Fietkau struct sk_buff *skb = NULL; 18c8846e10SFelix Fietkau 19c8a04d98SLorenzo Bianconi if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) 20c8846e10SFelix Fietkau return; 21c8846e10SFelix Fietkau 22c8846e10SFelix Fietkau skb = ieee80211_beacon_get(mt76_hw(dev), vif); 23c8846e10SFelix Fietkau if (!skb) 24c8846e10SFelix Fietkau return; 25c8846e10SFelix Fietkau 26eb9ca7ecSLorenzo Bianconi mt76_tx_queue_skb(dev, MT_TXQ_BEACON, skb, &mvif->sta.wcid, NULL); 27c8846e10SFelix Fietkau 28c8846e10SFelix Fietkau spin_lock_bh(&dev->ps_lock); 29c8846e10SFelix Fietkau mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY | 30c8846e10SFelix Fietkau FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, mvif->sta.wcid.idx) | 31c8846e10SFelix Fietkau FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, 32af005f26SLorenzo Bianconi dev->mt76.q_tx[MT_TXQ_CAB].q->hw_idx) | 33c8846e10SFelix Fietkau FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, 3) | 34c8846e10SFelix Fietkau FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, 8)); 35c8846e10SFelix Fietkau 36c8846e10SFelix Fietkau if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000)) 37c8846e10SFelix Fietkau dev->beacon_check = MT7603_WATCHDOG_TIMEOUT; 38c8846e10SFelix Fietkau 39c8846e10SFelix Fietkau spin_unlock_bh(&dev->ps_lock); 40c8846e10SFelix Fietkau } 41c8846e10SFelix Fietkau 42c8846e10SFelix Fietkau static void 43c8846e10SFelix Fietkau mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif) 44c8846e10SFelix Fietkau { 45c8846e10SFelix Fietkau struct beacon_bc_data *data = priv; 46c8846e10SFelix Fietkau struct mt7603_dev *dev = data->dev; 47c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 48c8846e10SFelix Fietkau struct ieee80211_tx_info *info; 49c8846e10SFelix Fietkau struct sk_buff *skb; 50c8846e10SFelix Fietkau 51c8a04d98SLorenzo Bianconi if (!(dev->mt76.beacon_mask & BIT(mvif->idx))) 52c8846e10SFelix Fietkau return; 53c8846e10SFelix Fietkau 54c8846e10SFelix Fietkau skb = ieee80211_get_buffered_bc(mt76_hw(dev), vif); 55c8846e10SFelix Fietkau if (!skb) 56c8846e10SFelix Fietkau return; 57c8846e10SFelix Fietkau 58c8846e10SFelix Fietkau info = IEEE80211_SKB_CB(skb); 59c8846e10SFelix Fietkau info->control.vif = vif; 60c8846e10SFelix Fietkau info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ; 61c8846e10SFelix Fietkau mt76_skb_set_moredata(skb, true); 62c8846e10SFelix Fietkau __skb_queue_tail(&data->q, skb); 63c8846e10SFelix Fietkau data->tail[mvif->idx] = skb; 64c8846e10SFelix Fietkau data->count[mvif->idx]++; 65c8846e10SFelix Fietkau } 66c8846e10SFelix Fietkau 67c8846e10SFelix Fietkau void mt7603_pre_tbtt_tasklet(unsigned long arg) 68c8846e10SFelix Fietkau { 69c8846e10SFelix Fietkau struct mt7603_dev *dev = (struct mt7603_dev *)arg; 70c8846e10SFelix Fietkau struct mt76_queue *q; 71c8846e10SFelix Fietkau struct beacon_bc_data data = {}; 72c8846e10SFelix Fietkau struct sk_buff *skb; 73c8846e10SFelix Fietkau int i, nframes; 74c8846e10SFelix Fietkau 75c8846e10SFelix Fietkau data.dev = dev; 76c8846e10SFelix Fietkau __skb_queue_head_init(&data.q); 77c8846e10SFelix Fietkau 78af005f26SLorenzo Bianconi q = dev->mt76.q_tx[MT_TXQ_BEACON].q; 79c8846e10SFelix Fietkau spin_lock_bh(&q->lock); 80c8846e10SFelix Fietkau ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 81c8846e10SFelix Fietkau IEEE80211_IFACE_ITER_RESUME_ALL, 82c8846e10SFelix Fietkau mt7603_update_beacon_iter, dev); 83c8846e10SFelix Fietkau mt76_queue_kick(dev, q); 84c8846e10SFelix Fietkau spin_unlock_bh(&q->lock); 85c8846e10SFelix Fietkau 86c8846e10SFelix Fietkau /* Flush all previous CAB queue packets */ 87c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0)); 88c8846e10SFelix Fietkau 89c8846e10SFelix Fietkau mt76_queue_tx_cleanup(dev, MT_TXQ_CAB, false); 90c8846e10SFelix Fietkau 91c8846e10SFelix Fietkau mt76_csa_check(&dev->mt76); 92c8846e10SFelix Fietkau if (dev->mt76.csa_complete) 93c8846e10SFelix Fietkau goto out; 94c8846e10SFelix Fietkau 95af005f26SLorenzo Bianconi q = dev->mt76.q_tx[MT_TXQ_CAB].q; 96c8846e10SFelix Fietkau do { 97c8846e10SFelix Fietkau nframes = skb_queue_len(&data.q); 98c8846e10SFelix Fietkau ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev), 99c8846e10SFelix Fietkau IEEE80211_IFACE_ITER_RESUME_ALL, 100c8846e10SFelix Fietkau mt7603_add_buffered_bc, &data); 101c8846e10SFelix Fietkau } while (nframes != skb_queue_len(&data.q) && 102c8846e10SFelix Fietkau skb_queue_len(&data.q) < 8); 103c8846e10SFelix Fietkau 104c8846e10SFelix Fietkau if (skb_queue_empty(&data.q)) 105c8846e10SFelix Fietkau goto out; 106c8846e10SFelix Fietkau 107c8846e10SFelix Fietkau for (i = 0; i < ARRAY_SIZE(data.tail); i++) { 108c8846e10SFelix Fietkau if (!data.tail[i]) 109c8846e10SFelix Fietkau continue; 110c8846e10SFelix Fietkau 111c8846e10SFelix Fietkau mt76_skb_set_moredata(data.tail[i], false); 112c8846e10SFelix Fietkau } 113c8846e10SFelix Fietkau 114c8846e10SFelix Fietkau spin_lock_bh(&q->lock); 115c8846e10SFelix Fietkau while ((skb = __skb_dequeue(&data.q)) != NULL) { 116c8846e10SFelix Fietkau struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 117c8846e10SFelix Fietkau struct ieee80211_vif *vif = info->control.vif; 118c8846e10SFelix Fietkau struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv; 119c8846e10SFelix Fietkau 120eb9ca7ecSLorenzo Bianconi mt76_tx_queue_skb(dev, MT_TXQ_CAB, skb, &mvif->sta.wcid, NULL); 121c8846e10SFelix Fietkau } 122c8846e10SFelix Fietkau mt76_queue_kick(dev, q); 123c8846e10SFelix Fietkau spin_unlock_bh(&q->lock); 124c8846e10SFelix Fietkau 125c8846e10SFelix Fietkau for (i = 0; i < ARRAY_SIZE(data.count); i++) 126c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_ARB_CAB_COUNT_B0_REG(i), 127c8846e10SFelix Fietkau data.count[i] << MT_WF_ARB_CAB_COUNT_B0_SHIFT(i)); 128c8846e10SFelix Fietkau 129c8846e10SFelix Fietkau mt76_wr(dev, MT_WF_ARB_CAB_START, 130c8846e10SFelix Fietkau MT_WF_ARB_CAB_START_BSSn(0) | 131c8846e10SFelix Fietkau (MT_WF_ARB_CAB_START_BSS0n(1) * 132c8846e10SFelix Fietkau ((1 << (MT7603_MAX_INTERFACES - 1)) - 1))); 133c8846e10SFelix Fietkau 134c8846e10SFelix Fietkau out: 135c8846e10SFelix Fietkau mt76_queue_tx_cleanup(dev, MT_TXQ_BEACON, false); 136af005f26SLorenzo Bianconi if (dev->mt76.q_tx[MT_TXQ_BEACON].q->queued > 137c8a04d98SLorenzo Bianconi hweight8(dev->mt76.beacon_mask)) 138c8846e10SFelix Fietkau dev->beacon_check++; 139c8846e10SFelix Fietkau } 140c8846e10SFelix Fietkau 141c8846e10SFelix Fietkau void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval) 142c8846e10SFelix Fietkau { 143c8846e10SFelix Fietkau u32 pre_tbtt = MT7603_PRE_TBTT_TIME / 64; 144c8846e10SFelix Fietkau 145c8846e10SFelix Fietkau if (idx >= 0) { 146c8846e10SFelix Fietkau if (intval) 147c8a04d98SLorenzo Bianconi dev->mt76.beacon_mask |= BIT(idx); 148c8846e10SFelix Fietkau else 149c8a04d98SLorenzo Bianconi dev->mt76.beacon_mask &= ~BIT(idx); 150c8846e10SFelix Fietkau } 151c8846e10SFelix Fietkau 152c8a04d98SLorenzo Bianconi if (!dev->mt76.beacon_mask || (!intval && idx < 0)) { 153c8846e10SFelix Fietkau mt7603_irq_disable(dev, MT_INT_MAC_IRQ3); 154c8846e10SFelix Fietkau mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK); 155c8846e10SFelix Fietkau mt76_wr(dev, MT_HW_INT_MASK(3), 0); 156c8846e10SFelix Fietkau return; 157c8846e10SFelix Fietkau } 158c8846e10SFelix Fietkau 1593041c445SLorenzo Bianconi dev->mt76.beacon_int = intval; 160c8846e10SFelix Fietkau mt76_wr(dev, MT_TBTT, 161c8846e10SFelix Fietkau FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE); 162c8846e10SFelix Fietkau 163c8846e10SFelix Fietkau mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99); /* start timer */ 164c8846e10SFelix Fietkau 165c8846e10SFelix Fietkau mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK, 166c8846e10SFelix Fietkau MT_BCNQ_OPMODE_AP); 167c8846e10SFelix Fietkau mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO); 168c8846e10SFelix Fietkau mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO); 169c8846e10SFelix Fietkau 170c8846e10SFelix Fietkau mt76_wr(dev, MT_PRE_TBTT, pre_tbtt); 171c8846e10SFelix Fietkau 172c8846e10SFelix Fietkau mt76_set(dev, MT_HW_INT_MASK(3), 173c8846e10SFelix Fietkau MT_HW_INT3_PRE_TBTT0 | MT_HW_INT3_TBTT0); 174c8846e10SFelix Fietkau 175c8846e10SFelix Fietkau mt76_set(dev, MT_WF_ARB_BCN_START, 176c8846e10SFelix Fietkau MT_WF_ARB_BCN_START_BSSn(0) | 177c8a04d98SLorenzo Bianconi ((dev->mt76.beacon_mask >> 1) * 178c8a04d98SLorenzo Bianconi MT_WF_ARB_BCN_START_BSS0n(1))); 179c8846e10SFelix Fietkau mt7603_irq_enable(dev, MT_INT_MAC_IRQ3); 180c8846e10SFelix Fietkau 181c8a04d98SLorenzo Bianconi if (dev->mt76.beacon_mask & ~BIT(0)) 182c8846e10SFelix Fietkau mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); 183c8846e10SFelix Fietkau else 184c8846e10SFelix Fietkau mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN); 185c8846e10SFelix Fietkau } 186