1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 MT_PHY_TYPE_EHT_SU = 13, 268 MT_PHY_TYPE_EHT_TRIG, 269 MT_PHY_TYPE_EHT_MU, 270 __MT_PHY_TYPE_MAX, 271 }; 272 273 struct mt76_sta_stats { 274 u64 tx_mode[__MT_PHY_TYPE_MAX]; 275 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 276 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 277 u64 tx_mcs[16]; /* mcs idx */ 278 u64 tx_bytes; 279 /* WED TX */ 280 u32 tx_packets; 281 u32 tx_retries; 282 u32 tx_failed; 283 /* WED RX */ 284 u64 rx_bytes; 285 u32 rx_packets; 286 u32 rx_errors; 287 u32 rx_drops; 288 }; 289 290 enum mt76_wcid_flags { 291 MT_WCID_FLAG_CHECK_PS, 292 MT_WCID_FLAG_PS, 293 MT_WCID_FLAG_4ADDR, 294 MT_WCID_FLAG_HDR_TRANS, 295 }; 296 297 #define MT76_N_WCIDS 1088 298 299 /* stored in ieee80211_tx_info::hw_queue */ 300 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 301 302 DECLARE_EWMA(signal, 10, 8); 303 304 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 305 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 306 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 307 #define MT_WCID_TX_INFO_SET BIT(31) 308 309 struct mt76_wcid { 310 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 311 312 atomic_t non_aql_packets; 313 unsigned long flags; 314 315 struct ewma_signal rssi; 316 int inactive_count; 317 318 struct rate_info rate; 319 320 u16 idx; 321 u8 hw_key_idx; 322 u8 hw_key_idx2; 323 324 u8 sta:1; 325 u8 amsdu:1; 326 u8 phy_idx:2; 327 328 u8 rx_check_pn; 329 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 330 u16 cipher; 331 332 u32 tx_info; 333 bool sw_iv; 334 335 struct list_head list; 336 struct idr pktid; 337 338 struct mt76_sta_stats stats; 339 }; 340 341 struct mt76_txq { 342 u16 wcid; 343 344 u16 agg_ssn; 345 bool send_bar; 346 bool aggr; 347 }; 348 349 struct mt76_txwi_cache { 350 struct list_head list; 351 dma_addr_t dma_addr; 352 353 union { 354 struct sk_buff *skb; 355 void *ptr; 356 }; 357 }; 358 359 struct mt76_rx_tid { 360 struct rcu_head rcu_head; 361 362 struct mt76_dev *dev; 363 364 spinlock_t lock; 365 struct delayed_work reorder_work; 366 367 u16 head; 368 u16 size; 369 u16 nframes; 370 371 u8 num; 372 373 u8 started:1, stopped:1, timer_pending:1; 374 375 struct sk_buff *reorder_buf[]; 376 }; 377 378 #define MT_TX_CB_DMA_DONE BIT(0) 379 #define MT_TX_CB_TXS_DONE BIT(1) 380 #define MT_TX_CB_TXS_FAILED BIT(2) 381 382 #define MT_PACKET_ID_MASK GENMASK(6, 0) 383 #define MT_PACKET_ID_NO_ACK 0 384 #define MT_PACKET_ID_NO_SKB 1 385 #define MT_PACKET_ID_WED 2 386 #define MT_PACKET_ID_FIRST 3 387 #define MT_PACKET_ID_HAS_RATE BIT(7) 388 /* This is timer for when to give up when waiting for TXS callback, 389 * with starting time being the time at which the DMA_DONE callback 390 * was seen (so, we know packet was processed then, it should not take 391 * long after that for firmware to send the TXS callback if it is going 392 * to do so.) 393 */ 394 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 395 396 struct mt76_tx_cb { 397 unsigned long jiffies; 398 u16 wcid; 399 u8 pktid; 400 u8 flags; 401 }; 402 403 enum { 404 MT76_STATE_INITIALIZED, 405 MT76_STATE_REGISTERED, 406 MT76_STATE_RUNNING, 407 MT76_STATE_MCU_RUNNING, 408 MT76_SCANNING, 409 MT76_HW_SCANNING, 410 MT76_HW_SCHED_SCANNING, 411 MT76_RESTART, 412 MT76_RESET, 413 MT76_MCU_RESET, 414 MT76_REMOVED, 415 MT76_READING_STATS, 416 MT76_STATE_POWER_OFF, 417 MT76_STATE_SUSPEND, 418 MT76_STATE_ROC, 419 MT76_STATE_PM, 420 MT76_STATE_WED_RESET, 421 }; 422 423 struct mt76_hw_cap { 424 bool has_2ghz; 425 bool has_5ghz; 426 bool has_6ghz; 427 }; 428 429 #define MT_DRV_TXWI_NO_FREE BIT(0) 430 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 431 #define MT_DRV_SW_RX_AIRTIME BIT(2) 432 #define MT_DRV_RX_DMA_HDR BIT(3) 433 #define MT_DRV_HW_MGMT_TXQ BIT(4) 434 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 435 436 struct mt76_driver_ops { 437 u32 drv_flags; 438 u32 survey_flags; 439 u16 txwi_size; 440 u16 token_size; 441 u8 mcs_rates; 442 443 void (*update_survey)(struct mt76_phy *phy); 444 445 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 446 enum mt76_txq_id qid, struct mt76_wcid *wcid, 447 struct ieee80211_sta *sta, 448 struct mt76_tx_info *tx_info); 449 450 void (*tx_complete_skb)(struct mt76_dev *dev, 451 struct mt76_queue_entry *e); 452 453 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 454 455 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 456 457 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 458 struct sk_buff *skb, u32 *info); 459 460 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 461 462 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 463 bool ps); 464 465 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 466 struct ieee80211_sta *sta); 467 468 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 469 struct ieee80211_sta *sta); 470 471 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 472 struct ieee80211_sta *sta); 473 }; 474 475 struct mt76_channel_state { 476 u64 cc_active; 477 u64 cc_busy; 478 u64 cc_rx; 479 u64 cc_bss_rx; 480 u64 cc_tx; 481 482 s8 noise; 483 }; 484 485 struct mt76_sband { 486 struct ieee80211_supported_band sband; 487 struct mt76_channel_state *chan; 488 }; 489 490 /* addr req mask */ 491 #define MT_VEND_TYPE_EEPROM BIT(31) 492 #define MT_VEND_TYPE_CFG BIT(30) 493 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 494 495 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 496 enum mt_vendor_req { 497 MT_VEND_DEV_MODE = 0x1, 498 MT_VEND_WRITE = 0x2, 499 MT_VEND_POWER_ON = 0x4, 500 MT_VEND_MULTI_WRITE = 0x6, 501 MT_VEND_MULTI_READ = 0x7, 502 MT_VEND_READ_EEPROM = 0x9, 503 MT_VEND_WRITE_FCE = 0x42, 504 MT_VEND_WRITE_CFG = 0x46, 505 MT_VEND_READ_CFG = 0x47, 506 MT_VEND_READ_EXT = 0x63, 507 MT_VEND_WRITE_EXT = 0x66, 508 MT_VEND_FEATURE_SET = 0x91, 509 }; 510 511 enum mt76u_in_ep { 512 MT_EP_IN_PKT_RX, 513 MT_EP_IN_CMD_RESP, 514 __MT_EP_IN_MAX, 515 }; 516 517 enum mt76u_out_ep { 518 MT_EP_OUT_INBAND_CMD, 519 MT_EP_OUT_AC_BE, 520 MT_EP_OUT_AC_BK, 521 MT_EP_OUT_AC_VI, 522 MT_EP_OUT_AC_VO, 523 MT_EP_OUT_HCCA, 524 __MT_EP_OUT_MAX, 525 }; 526 527 struct mt76_mcu { 528 struct mutex mutex; 529 u32 msg_seq; 530 int timeout; 531 532 struct sk_buff_head res_q; 533 wait_queue_head_t wait; 534 }; 535 536 #define MT_TX_SG_MAX_SIZE 8 537 #define MT_RX_SG_MAX_SIZE 4 538 #define MT_NUM_TX_ENTRIES 256 539 #define MT_NUM_RX_ENTRIES 128 540 #define MCU_RESP_URB_SIZE 1024 541 struct mt76_usb { 542 struct mutex usb_ctrl_mtx; 543 u8 *data; 544 u16 data_len; 545 546 struct mt76_worker status_worker; 547 struct mt76_worker rx_worker; 548 549 struct work_struct stat_work; 550 551 u8 out_ep[__MT_EP_OUT_MAX]; 552 u8 in_ep[__MT_EP_IN_MAX]; 553 bool sg_en; 554 555 struct mt76u_mcu { 556 u8 *data; 557 /* multiple reads */ 558 struct mt76_reg_pair *rp; 559 int rp_len; 560 u32 base; 561 } mcu; 562 }; 563 564 #define MT76S_XMIT_BUF_SZ 0x3fe00 565 #define MT76S_NUM_TX_ENTRIES 256 566 #define MT76S_NUM_RX_ENTRIES 512 567 struct mt76_sdio { 568 struct mt76_worker txrx_worker; 569 struct mt76_worker status_worker; 570 struct mt76_worker net_worker; 571 572 struct work_struct stat_work; 573 574 u8 *xmit_buf; 575 u32 xmit_buf_sz; 576 577 struct sdio_func *func; 578 void *intr_data; 579 u8 hw_ver; 580 wait_queue_head_t wait; 581 582 struct { 583 int pse_data_quota; 584 int ple_data_quota; 585 int pse_mcu_quota; 586 int pse_page_size; 587 int deficit; 588 } sched; 589 590 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 591 }; 592 593 struct mt76_mmio { 594 void __iomem *regs; 595 spinlock_t irq_lock; 596 u32 irqmask; 597 598 struct mtk_wed_device wed; 599 struct completion wed_reset; 600 struct completion wed_reset_complete; 601 }; 602 603 struct mt76_rx_status { 604 union { 605 struct mt76_wcid *wcid; 606 u16 wcid_idx; 607 }; 608 609 u32 reorder_time; 610 611 u32 ampdu_ref; 612 u32 timestamp; 613 614 u8 iv[6]; 615 616 u8 phy_idx:2; 617 u8 aggr:1; 618 u8 qos_ctl; 619 u16 seqno; 620 621 u16 freq; 622 u32 flag; 623 u8 enc_flags; 624 u8 encoding:3, bw:4; 625 union { 626 struct { 627 u8 he_ru:3; 628 u8 he_gi:2; 629 u8 he_dcm:1; 630 }; 631 struct { 632 u8 ru:4; 633 u8 gi:2; 634 } eht; 635 }; 636 637 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 638 u8 rate_idx; 639 u8 nss:5, band:3; 640 s8 signal; 641 u8 chains; 642 s8 chain_signal[IEEE80211_MAX_CHAINS]; 643 }; 644 645 struct mt76_freq_range_power { 646 const struct cfg80211_sar_freq_ranges *range; 647 s8 power; 648 }; 649 650 struct mt76_testmode_ops { 651 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 652 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 653 enum mt76_testmode_state new_state); 654 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 655 }; 656 657 struct mt76_testmode_data { 658 enum mt76_testmode_state state; 659 660 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 661 struct sk_buff *tx_skb; 662 663 u32 tx_count; 664 u16 tx_mpdu_len; 665 666 u8 tx_rate_mode; 667 u8 tx_rate_idx; 668 u8 tx_rate_nss; 669 u8 tx_rate_sgi; 670 u8 tx_rate_ldpc; 671 u8 tx_rate_stbc; 672 u8 tx_ltf; 673 674 u8 tx_antenna_mask; 675 u8 tx_spe_idx; 676 677 u8 tx_duty_cycle; 678 u32 tx_time; 679 u32 tx_ipg; 680 681 u32 freq_offset; 682 683 u8 tx_power[4]; 684 u8 tx_power_control; 685 686 u8 addr[3][ETH_ALEN]; 687 688 u32 tx_pending; 689 u32 tx_queued; 690 u16 tx_queued_limit; 691 u32 tx_done; 692 struct { 693 u64 packets[__MT_RXQ_MAX]; 694 u64 fcs_error[__MT_RXQ_MAX]; 695 } rx_stats; 696 }; 697 698 struct mt76_vif { 699 u8 idx; 700 u8 omac_idx; 701 u8 band_idx; 702 u8 wmm_idx; 703 u8 scan_seq_num; 704 u8 cipher; 705 }; 706 707 struct mt76_phy { 708 struct ieee80211_hw *hw; 709 struct mt76_dev *dev; 710 void *priv; 711 712 unsigned long state; 713 u8 band_idx; 714 715 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 716 717 struct cfg80211_chan_def chandef; 718 struct ieee80211_channel *main_chan; 719 720 struct mt76_channel_state *chan_state; 721 enum mt76_dfs_state dfs_state; 722 ktime_t survey_time; 723 724 u32 aggr_stats[32]; 725 726 struct mt76_hw_cap cap; 727 struct mt76_sband sband_2g; 728 struct mt76_sband sband_5g; 729 struct mt76_sband sband_6g; 730 731 u8 macaddr[ETH_ALEN]; 732 733 int txpower_cur; 734 u8 antenna_mask; 735 u16 chainmask; 736 737 #ifdef CONFIG_NL80211_TESTMODE 738 struct mt76_testmode_data test; 739 #endif 740 741 struct delayed_work mac_work; 742 u8 mac_work_count; 743 744 struct { 745 struct sk_buff *head; 746 struct sk_buff **tail; 747 u16 seqno; 748 } rx_amsdu[__MT_RXQ_MAX]; 749 750 struct mt76_freq_range_power *frp; 751 752 struct { 753 struct led_classdev cdev; 754 char name[32]; 755 bool al; 756 u8 pin; 757 } leds; 758 }; 759 760 struct mt76_dev { 761 struct mt76_phy phy; /* must be first */ 762 struct mt76_phy *phys[__MT_MAX_BAND]; 763 764 struct ieee80211_hw *hw; 765 766 spinlock_t wed_lock; 767 spinlock_t lock; 768 spinlock_t cc_lock; 769 770 u32 cur_cc_bss_rx; 771 772 struct mt76_rx_status rx_ampdu_status; 773 u32 rx_ampdu_len; 774 u32 rx_ampdu_ref; 775 776 struct mutex mutex; 777 778 const struct mt76_bus_ops *bus; 779 const struct mt76_driver_ops *drv; 780 const struct mt76_mcu_ops *mcu_ops; 781 struct device *dev; 782 struct device *dma_dev; 783 784 struct mt76_mcu mcu; 785 786 struct net_device napi_dev; 787 struct net_device tx_napi_dev; 788 spinlock_t rx_lock; 789 struct napi_struct napi[__MT_RXQ_MAX]; 790 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 791 struct tasklet_struct irq_tasklet; 792 793 struct list_head txwi_cache; 794 struct list_head rxwi_cache; 795 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 796 struct mt76_queue q_rx[__MT_RXQ_MAX]; 797 const struct mt76_queue_ops *queue_ops; 798 int tx_dma_idx[4]; 799 800 struct mt76_worker tx_worker; 801 struct napi_struct tx_napi; 802 803 spinlock_t token_lock; 804 struct idr token; 805 u16 wed_token_count; 806 u16 token_count; 807 u16 token_size; 808 809 spinlock_t rx_token_lock; 810 struct idr rx_token; 811 u16 rx_token_size; 812 813 wait_queue_head_t tx_wait; 814 /* spinclock used to protect wcid pktid linked list */ 815 spinlock_t status_lock; 816 817 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 818 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 819 820 u64 vif_mask; 821 822 struct mt76_wcid global_wcid; 823 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 824 struct list_head wcid_list; 825 826 u32 rev; 827 828 struct tasklet_struct pre_tbtt_tasklet; 829 int beacon_int; 830 u8 beacon_mask; 831 832 struct debugfs_blob_wrapper eeprom; 833 struct debugfs_blob_wrapper otp; 834 835 char alpha2[3]; 836 enum nl80211_dfs_regions region; 837 838 u32 debugfs_reg; 839 840 u8 csa_complete; 841 842 u32 rxfilter; 843 844 #ifdef CONFIG_NL80211_TESTMODE 845 const struct mt76_testmode_ops *test_ops; 846 struct { 847 const char *name; 848 u32 offset; 849 } test_mtd; 850 #endif 851 struct workqueue_struct *wq; 852 853 union { 854 struct mt76_mmio mmio; 855 struct mt76_usb usb; 856 struct mt76_sdio sdio; 857 }; 858 }; 859 860 struct mt76_power_limits { 861 s8 cck[4]; 862 s8 ofdm[8]; 863 s8 mcs[4][10]; 864 s8 ru[7][12]; 865 }; 866 867 struct mt76_ethtool_worker_info { 868 u64 *data; 869 int idx; 870 int initial_stat_idx; 871 int worker_stat_count; 872 int sta_count; 873 }; 874 875 #define CCK_RATE(_idx, _rate) { \ 876 .bitrate = _rate, \ 877 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 878 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 879 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 880 } 881 882 #define OFDM_RATE(_idx, _rate) { \ 883 .bitrate = _rate, \ 884 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 885 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 886 } 887 888 extern struct ieee80211_rate mt76_rates[12]; 889 890 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 891 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 892 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 893 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 894 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 895 896 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 897 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 898 899 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 900 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 901 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 902 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 903 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 904 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 905 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 906 907 908 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 909 910 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 911 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 912 913 #define mt76_get_field(_dev, _reg, _field) \ 914 FIELD_GET(_field, mt76_rr(dev, _reg)) 915 916 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 917 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 918 919 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 920 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 921 922 #define mt76_hw(dev) (dev)->mphy.hw 923 924 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 925 int timeout); 926 927 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 928 929 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 930 int timeout, int kick); 931 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 932 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 933 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 934 935 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 936 void mt76_pci_disable_aspm(struct pci_dev *pdev); 937 938 static inline u16 mt76_chip(struct mt76_dev *dev) 939 { 940 return dev->rev >> 16; 941 } 942 943 static inline u16 mt76_rev(struct mt76_dev *dev) 944 { 945 return dev->rev & 0xffff; 946 } 947 948 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 949 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 950 951 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 952 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 953 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 954 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 955 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 956 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 957 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 958 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 959 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 960 961 #define mt76_for_each_q_rx(dev, i) \ 962 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 963 if ((dev)->q_rx[i].ndesc) 964 965 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 966 const struct ieee80211_ops *ops, 967 const struct mt76_driver_ops *drv_ops); 968 int mt76_register_device(struct mt76_dev *dev, bool vht, 969 struct ieee80211_rate *rates, int n_rates); 970 void mt76_unregister_device(struct mt76_dev *dev); 971 void mt76_free_device(struct mt76_dev *dev); 972 void mt76_unregister_phy(struct mt76_phy *phy); 973 974 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 975 const struct ieee80211_ops *ops, 976 u8 band_idx); 977 int mt76_register_phy(struct mt76_phy *phy, bool vht, 978 struct ieee80211_rate *rates, int n_rates); 979 980 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 981 const struct file_operations *ops); 982 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 983 { 984 return mt76_register_debugfs_fops(&dev->phy, NULL); 985 } 986 987 int mt76_queues_read(struct seq_file *s, void *data); 988 void mt76_seq_puts_array(struct seq_file *file, const char *str, 989 s8 *val, int len); 990 991 int mt76_eeprom_init(struct mt76_dev *dev, int len); 992 void mt76_eeprom_override(struct mt76_phy *phy); 993 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 994 995 struct mt76_queue * 996 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 997 int ring_base, u32 flags); 998 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 999 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1000 int n_desc, int ring_base, u32 flags) 1001 { 1002 struct mt76_queue *q; 1003 1004 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 1005 if (IS_ERR(q)) 1006 return PTR_ERR(q); 1007 1008 phy->q_tx[qid] = q; 1009 1010 return 0; 1011 } 1012 1013 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1014 int n_desc, int ring_base) 1015 { 1016 struct mt76_queue *q; 1017 1018 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1019 if (IS_ERR(q)) 1020 return PTR_ERR(q); 1021 1022 dev->q_mcu[qid] = q; 1023 1024 return 0; 1025 } 1026 1027 static inline struct mt76_phy * 1028 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1029 { 1030 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1031 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1032 return dev->phys[phy_idx]; 1033 1034 return &dev->phy; 1035 } 1036 1037 static inline struct ieee80211_hw * 1038 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1039 { 1040 return mt76_dev_phy(dev, phy_idx)->hw; 1041 } 1042 1043 static inline u8 * 1044 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1045 { 1046 return (u8 *)t - dev->drv->txwi_size; 1047 } 1048 1049 /* increment with wrap-around */ 1050 static inline int mt76_incr(int val, int size) 1051 { 1052 return (val + 1) & (size - 1); 1053 } 1054 1055 /* decrement with wrap-around */ 1056 static inline int mt76_decr(int val, int size) 1057 { 1058 return (val - 1) & (size - 1); 1059 } 1060 1061 u8 mt76_ac_to_hwq(u8 ac); 1062 1063 static inline struct ieee80211_txq * 1064 mtxq_to_txq(struct mt76_txq *mtxq) 1065 { 1066 void *ptr = mtxq; 1067 1068 return container_of(ptr, struct ieee80211_txq, drv_priv); 1069 } 1070 1071 static inline struct ieee80211_sta * 1072 wcid_to_sta(struct mt76_wcid *wcid) 1073 { 1074 void *ptr = wcid; 1075 1076 if (!wcid || !wcid->sta) 1077 return NULL; 1078 1079 return container_of(ptr, struct ieee80211_sta, drv_priv); 1080 } 1081 1082 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1083 { 1084 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1085 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1086 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1087 } 1088 1089 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1090 { 1091 struct mt76_rx_status mstat; 1092 u8 *data = skb->data; 1093 1094 /* Alignment concerns */ 1095 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1096 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1097 1098 mstat = *((struct mt76_rx_status *)skb->cb); 1099 1100 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1101 data += sizeof(struct ieee80211_radiotap_he); 1102 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1103 data += sizeof(struct ieee80211_radiotap_he_mu); 1104 1105 return data; 1106 } 1107 1108 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1109 { 1110 int len = ieee80211_get_hdrlen_from_skb(skb); 1111 1112 if (len % 4 == 0) 1113 return; 1114 1115 skb_push(skb, 2); 1116 memmove(skb->data, skb->data + 2, len); 1117 1118 skb->data[len] = 0; 1119 skb->data[len + 1] = 0; 1120 } 1121 1122 static inline bool mt76_is_skb_pktid(u8 pktid) 1123 { 1124 if (pktid & MT_PACKET_ID_HAS_RATE) 1125 return false; 1126 1127 return pktid >= MT_PACKET_ID_FIRST; 1128 } 1129 1130 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1131 { 1132 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1133 u8 idx = nss - 1; 1134 1135 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1136 } 1137 1138 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1139 { 1140 #ifdef CONFIG_NL80211_TESTMODE 1141 return phy->test.state != MT76_TM_STATE_OFF; 1142 #else 1143 return false; 1144 #endif 1145 } 1146 1147 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1148 struct sk_buff *skb, 1149 struct ieee80211_hw **hw) 1150 { 1151 #ifdef CONFIG_NL80211_TESTMODE 1152 int i; 1153 1154 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1155 struct mt76_phy *phy = dev->phys[i]; 1156 1157 if (phy && skb == phy->test.tx_skb) { 1158 *hw = dev->phys[i]->hw; 1159 return true; 1160 } 1161 } 1162 return false; 1163 #else 1164 return false; 1165 #endif 1166 } 1167 1168 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1169 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1170 struct mt76_wcid *wcid, struct sk_buff *skb); 1171 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1172 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1173 bool send_bar); 1174 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1175 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1176 void mt76_txq_schedule_all(struct mt76_phy *phy); 1177 void mt76_tx_worker_run(struct mt76_dev *dev); 1178 void mt76_tx_worker(struct mt76_worker *w); 1179 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1180 struct ieee80211_sta *sta, 1181 u16 tids, int nframes, 1182 enum ieee80211_frame_release_type reason, 1183 bool more_data); 1184 bool mt76_has_tx_pending(struct mt76_phy *phy); 1185 void mt76_set_channel(struct mt76_phy *phy); 1186 void mt76_update_survey(struct mt76_phy *phy); 1187 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1188 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1189 struct survey_info *survey); 1190 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1191 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1192 1193 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1194 u16 ssn, u16 size); 1195 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1196 1197 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1198 struct ieee80211_key_conf *key); 1199 1200 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1201 __acquires(&dev->status_lock); 1202 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1203 __releases(&dev->status_lock); 1204 1205 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1206 struct sk_buff *skb); 1207 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1208 struct mt76_wcid *wcid, int pktid, 1209 struct sk_buff_head *list); 1210 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1211 struct sk_buff_head *list); 1212 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1213 struct list_head *free_list); 1214 static inline void 1215 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1216 { 1217 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1218 } 1219 1220 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1221 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1222 struct ieee80211_sta *sta, 1223 enum ieee80211_sta_state old_state, 1224 enum ieee80211_sta_state new_state); 1225 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1226 struct ieee80211_sta *sta); 1227 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1228 struct ieee80211_sta *sta); 1229 1230 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1231 1232 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1233 int *dbm); 1234 int mt76_init_sar_power(struct ieee80211_hw *hw, 1235 const struct cfg80211_sar_specs *sar); 1236 int mt76_get_sar_power(struct mt76_phy *phy, 1237 struct ieee80211_channel *chan, 1238 int power); 1239 1240 void mt76_csa_check(struct mt76_dev *dev); 1241 void mt76_csa_finish(struct mt76_dev *dev); 1242 1243 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1244 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1245 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1246 int mt76_get_rate(struct mt76_dev *dev, 1247 struct ieee80211_supported_band *sband, 1248 int idx, bool cck); 1249 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1250 const u8 *mac); 1251 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1252 struct ieee80211_vif *vif); 1253 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1254 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1255 void *data, int len); 1256 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1257 struct netlink_callback *cb, void *data, int len); 1258 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1259 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1260 1261 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1262 { 1263 #ifdef CONFIG_NL80211_TESTMODE 1264 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1265 1266 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1267 state = MT76_TM_STATE_OFF; 1268 1269 mt76_testmode_set_state(phy, state); 1270 #endif 1271 } 1272 1273 1274 /* internal */ 1275 static inline struct ieee80211_hw * 1276 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1277 { 1278 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1279 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1280 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1281 1282 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1283 1284 return hw; 1285 } 1286 1287 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1288 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1289 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1290 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1291 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1292 struct napi_struct *napi); 1293 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1294 struct napi_struct *napi); 1295 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1296 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1297 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1298 struct mt76_queue_entry *e); 1299 1300 /* usb */ 1301 static inline bool mt76u_urb_error(struct urb *urb) 1302 { 1303 return urb->status && 1304 urb->status != -ECONNRESET && 1305 urb->status != -ESHUTDOWN && 1306 urb->status != -ENOENT; 1307 } 1308 1309 /* Map hardware queues to usb endpoints */ 1310 static inline u8 q2ep(u8 qid) 1311 { 1312 /* TODO: take management packets to queue 5 */ 1313 return qid + 1; 1314 } 1315 1316 static inline int 1317 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1318 int timeout, int ep) 1319 { 1320 struct usb_interface *uintf = to_usb_interface(dev->dev); 1321 struct usb_device *udev = interface_to_usbdev(uintf); 1322 struct mt76_usb *usb = &dev->usb; 1323 unsigned int pipe; 1324 1325 if (actual_len) 1326 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1327 else 1328 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1329 1330 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1331 } 1332 1333 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1334 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1335 struct mt76_sta_stats *stats, bool eht); 1336 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1337 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1338 u16 val, u16 offset, void *buf, size_t len); 1339 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1340 u8 req_type, u16 val, u16 offset, 1341 void *buf, size_t len); 1342 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1343 const u16 offset, const u32 val); 1344 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1345 void *data, int len); 1346 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1347 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1348 u32 addr, u32 val); 1349 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1350 struct mt76_bus_ops *ops); 1351 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1352 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1353 int mt76u_alloc_queues(struct mt76_dev *dev); 1354 void mt76u_stop_tx(struct mt76_dev *dev); 1355 void mt76u_stop_rx(struct mt76_dev *dev); 1356 int mt76u_resume_rx(struct mt76_dev *dev); 1357 void mt76u_queues_deinit(struct mt76_dev *dev); 1358 1359 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1360 const struct mt76_bus_ops *bus_ops); 1361 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1362 int mt76s_alloc_tx(struct mt76_dev *dev); 1363 void mt76s_deinit(struct mt76_dev *dev); 1364 void mt76s_sdio_irq(struct sdio_func *func); 1365 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1366 bool mt76s_txqs_empty(struct mt76_dev *dev); 1367 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1368 int hw_ver); 1369 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1370 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1371 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1372 u32 mt76s_read_pcr(struct mt76_dev *dev); 1373 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1374 const void *data, int len); 1375 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1376 void *data, int len); 1377 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1378 const struct mt76_reg_pair *data, 1379 int len); 1380 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1381 struct mt76_reg_pair *data, int len); 1382 1383 struct sk_buff * 1384 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1385 int len, int data_len, gfp_t gfp); 1386 static inline struct sk_buff * 1387 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1388 int data_len) 1389 { 1390 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1391 } 1392 1393 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1394 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1395 unsigned long expires); 1396 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1397 int len, bool wait_resp, struct sk_buff **ret); 1398 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1399 int cmd, bool wait_resp, struct sk_buff **ret); 1400 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1401 int len, int max_len); 1402 static inline int 1403 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1404 int len) 1405 { 1406 int max_len = 4096 - dev->mcu_ops->headroom; 1407 1408 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1409 } 1410 1411 static inline int 1412 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1413 bool wait_resp) 1414 { 1415 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1416 } 1417 1418 static inline int 1419 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1420 bool wait_resp) 1421 { 1422 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1423 } 1424 1425 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1426 1427 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1428 struct ieee80211_channel *chan, 1429 struct mt76_power_limits *dest, 1430 s8 target_power); 1431 1432 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1433 { 1434 return (q->flags & MT_QFLAG_WED) && 1435 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1436 } 1437 1438 struct mt76_txwi_cache * 1439 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1440 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1441 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1442 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1443 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1444 struct mt76_txwi_cache *r, dma_addr_t phys); 1445 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1446 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1447 { 1448 struct page *page = virt_to_head_page(buf); 1449 1450 page_pool_put_full_page(page->pp, page, allow_direct); 1451 } 1452 1453 static inline void * 1454 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1455 { 1456 struct page *page; 1457 1458 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1459 if (!page) 1460 return NULL; 1461 1462 return page_address(page) + *offset; 1463 } 1464 1465 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1466 { 1467 spin_lock_bh(&dev->token_lock); 1468 __mt76_set_tx_blocked(dev, blocked); 1469 spin_unlock_bh(&dev->token_lock); 1470 } 1471 1472 static inline int 1473 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1474 { 1475 int token; 1476 1477 spin_lock_bh(&dev->token_lock); 1478 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1479 spin_unlock_bh(&dev->token_lock); 1480 1481 return token; 1482 } 1483 1484 static inline struct mt76_txwi_cache * 1485 mt76_token_put(struct mt76_dev *dev, int token) 1486 { 1487 struct mt76_txwi_cache *txwi; 1488 1489 spin_lock_bh(&dev->token_lock); 1490 txwi = idr_remove(&dev->token, token); 1491 spin_unlock_bh(&dev->token_lock); 1492 1493 return txwi; 1494 } 1495 1496 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1497 { 1498 INIT_LIST_HEAD(&wcid->list); 1499 idr_init(&wcid->pktid); 1500 } 1501 1502 static inline void 1503 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1504 { 1505 struct sk_buff_head list; 1506 1507 mt76_tx_status_lock(dev, &list); 1508 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1509 mt76_tx_status_unlock(dev, &list); 1510 1511 idr_destroy(&wcid->pktid); 1512 } 1513 1514 #endif 1515