1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 MT_PHY_TYPE_EHT_SU = 13, 268 MT_PHY_TYPE_EHT_TRIG, 269 MT_PHY_TYPE_EHT_MU, 270 __MT_PHY_TYPE_MAX, 271 }; 272 273 struct mt76_sta_stats { 274 u64 tx_mode[__MT_PHY_TYPE_MAX]; 275 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 276 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 277 u64 tx_mcs[16]; /* mcs idx */ 278 u64 tx_bytes; 279 /* WED TX */ 280 u32 tx_packets; 281 u32 tx_retries; 282 u32 tx_failed; 283 /* WED RX */ 284 u64 rx_bytes; 285 u32 rx_packets; 286 u32 rx_errors; 287 u32 rx_drops; 288 }; 289 290 enum mt76_wcid_flags { 291 MT_WCID_FLAG_CHECK_PS, 292 MT_WCID_FLAG_PS, 293 MT_WCID_FLAG_4ADDR, 294 MT_WCID_FLAG_HDR_TRANS, 295 }; 296 297 #define MT76_N_WCIDS 1088 298 299 /* stored in ieee80211_tx_info::hw_queue */ 300 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 301 302 DECLARE_EWMA(signal, 10, 8); 303 304 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 305 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 306 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 307 #define MT_WCID_TX_INFO_SET BIT(31) 308 309 struct mt76_wcid { 310 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 311 312 atomic_t non_aql_packets; 313 unsigned long flags; 314 315 struct ewma_signal rssi; 316 int inactive_count; 317 318 struct rate_info rate; 319 320 u16 idx; 321 u8 hw_key_idx; 322 u8 hw_key_idx2; 323 324 u8 sta:1; 325 u8 amsdu:1; 326 u8 phy_idx:2; 327 328 u8 rx_check_pn; 329 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 330 u16 cipher; 331 332 u32 tx_info; 333 bool sw_iv; 334 335 struct list_head list; 336 struct idr pktid; 337 338 struct mt76_sta_stats stats; 339 }; 340 341 struct mt76_txq { 342 u16 wcid; 343 344 u16 agg_ssn; 345 bool send_bar; 346 bool aggr; 347 }; 348 349 struct mt76_txwi_cache { 350 struct list_head list; 351 dma_addr_t dma_addr; 352 353 union { 354 struct sk_buff *skb; 355 void *ptr; 356 }; 357 }; 358 359 struct mt76_rx_tid { 360 struct rcu_head rcu_head; 361 362 struct mt76_dev *dev; 363 364 spinlock_t lock; 365 struct delayed_work reorder_work; 366 367 u16 head; 368 u16 size; 369 u16 nframes; 370 371 u8 num; 372 373 u8 started:1, stopped:1, timer_pending:1; 374 375 struct sk_buff *reorder_buf[]; 376 }; 377 378 #define MT_TX_CB_DMA_DONE BIT(0) 379 #define MT_TX_CB_TXS_DONE BIT(1) 380 #define MT_TX_CB_TXS_FAILED BIT(2) 381 382 #define MT_PACKET_ID_MASK GENMASK(6, 0) 383 #define MT_PACKET_ID_NO_ACK 0 384 #define MT_PACKET_ID_NO_SKB 1 385 #define MT_PACKET_ID_WED 2 386 #define MT_PACKET_ID_FIRST 3 387 #define MT_PACKET_ID_HAS_RATE BIT(7) 388 /* This is timer for when to give up when waiting for TXS callback, 389 * with starting time being the time at which the DMA_DONE callback 390 * was seen (so, we know packet was processed then, it should not take 391 * long after that for firmware to send the TXS callback if it is going 392 * to do so.) 393 */ 394 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 395 396 struct mt76_tx_cb { 397 unsigned long jiffies; 398 u16 wcid; 399 u8 pktid; 400 u8 flags; 401 }; 402 403 enum { 404 MT76_STATE_INITIALIZED, 405 MT76_STATE_REGISTERED, 406 MT76_STATE_RUNNING, 407 MT76_STATE_MCU_RUNNING, 408 MT76_SCANNING, 409 MT76_HW_SCANNING, 410 MT76_HW_SCHED_SCANNING, 411 MT76_RESTART, 412 MT76_RESET, 413 MT76_MCU_RESET, 414 MT76_REMOVED, 415 MT76_READING_STATS, 416 MT76_STATE_POWER_OFF, 417 MT76_STATE_SUSPEND, 418 MT76_STATE_ROC, 419 MT76_STATE_PM, 420 MT76_STATE_WED_RESET, 421 }; 422 423 struct mt76_hw_cap { 424 bool has_2ghz; 425 bool has_5ghz; 426 bool has_6ghz; 427 }; 428 429 #define MT_DRV_TXWI_NO_FREE BIT(0) 430 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 431 #define MT_DRV_SW_RX_AIRTIME BIT(2) 432 #define MT_DRV_RX_DMA_HDR BIT(3) 433 #define MT_DRV_HW_MGMT_TXQ BIT(4) 434 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 435 436 struct mt76_driver_ops { 437 u32 drv_flags; 438 u32 survey_flags; 439 u16 txwi_size; 440 u16 token_size; 441 u8 mcs_rates; 442 443 void (*update_survey)(struct mt76_phy *phy); 444 445 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 446 enum mt76_txq_id qid, struct mt76_wcid *wcid, 447 struct ieee80211_sta *sta, 448 struct mt76_tx_info *tx_info); 449 450 void (*tx_complete_skb)(struct mt76_dev *dev, 451 struct mt76_queue_entry *e); 452 453 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 454 455 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 456 457 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 458 struct sk_buff *skb, u32 *info); 459 460 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 461 462 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 463 bool ps); 464 465 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 466 struct ieee80211_sta *sta); 467 468 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 469 struct ieee80211_sta *sta); 470 471 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 472 struct ieee80211_sta *sta); 473 }; 474 475 struct mt76_channel_state { 476 u64 cc_active; 477 u64 cc_busy; 478 u64 cc_rx; 479 u64 cc_bss_rx; 480 u64 cc_tx; 481 482 s8 noise; 483 }; 484 485 struct mt76_sband { 486 struct ieee80211_supported_band sband; 487 struct mt76_channel_state *chan; 488 }; 489 490 /* addr req mask */ 491 #define MT_VEND_TYPE_EEPROM BIT(31) 492 #define MT_VEND_TYPE_CFG BIT(30) 493 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 494 495 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 496 enum mt_vendor_req { 497 MT_VEND_DEV_MODE = 0x1, 498 MT_VEND_WRITE = 0x2, 499 MT_VEND_POWER_ON = 0x4, 500 MT_VEND_MULTI_WRITE = 0x6, 501 MT_VEND_MULTI_READ = 0x7, 502 MT_VEND_READ_EEPROM = 0x9, 503 MT_VEND_WRITE_FCE = 0x42, 504 MT_VEND_WRITE_CFG = 0x46, 505 MT_VEND_READ_CFG = 0x47, 506 MT_VEND_READ_EXT = 0x63, 507 MT_VEND_WRITE_EXT = 0x66, 508 MT_VEND_FEATURE_SET = 0x91, 509 }; 510 511 enum mt76u_in_ep { 512 MT_EP_IN_PKT_RX, 513 MT_EP_IN_CMD_RESP, 514 __MT_EP_IN_MAX, 515 }; 516 517 enum mt76u_out_ep { 518 MT_EP_OUT_INBAND_CMD, 519 MT_EP_OUT_AC_BE, 520 MT_EP_OUT_AC_BK, 521 MT_EP_OUT_AC_VI, 522 MT_EP_OUT_AC_VO, 523 MT_EP_OUT_HCCA, 524 __MT_EP_OUT_MAX, 525 }; 526 527 struct mt76_mcu { 528 struct mutex mutex; 529 u32 msg_seq; 530 int timeout; 531 532 struct sk_buff_head res_q; 533 wait_queue_head_t wait; 534 }; 535 536 #define MT_TX_SG_MAX_SIZE 8 537 #define MT_RX_SG_MAX_SIZE 4 538 #define MT_NUM_TX_ENTRIES 256 539 #define MT_NUM_RX_ENTRIES 128 540 #define MCU_RESP_URB_SIZE 1024 541 struct mt76_usb { 542 struct mutex usb_ctrl_mtx; 543 u8 *data; 544 u16 data_len; 545 546 struct mt76_worker status_worker; 547 struct mt76_worker rx_worker; 548 549 struct work_struct stat_work; 550 551 u8 out_ep[__MT_EP_OUT_MAX]; 552 u8 in_ep[__MT_EP_IN_MAX]; 553 bool sg_en; 554 555 struct mt76u_mcu { 556 u8 *data; 557 /* multiple reads */ 558 struct mt76_reg_pair *rp; 559 int rp_len; 560 u32 base; 561 } mcu; 562 }; 563 564 #define MT76S_XMIT_BUF_SZ 0x3fe00 565 #define MT76S_NUM_TX_ENTRIES 256 566 #define MT76S_NUM_RX_ENTRIES 512 567 struct mt76_sdio { 568 struct mt76_worker txrx_worker; 569 struct mt76_worker status_worker; 570 struct mt76_worker net_worker; 571 572 struct work_struct stat_work; 573 574 u8 *xmit_buf; 575 u32 xmit_buf_sz; 576 577 struct sdio_func *func; 578 void *intr_data; 579 u8 hw_ver; 580 wait_queue_head_t wait; 581 582 struct { 583 int pse_data_quota; 584 int ple_data_quota; 585 int pse_mcu_quota; 586 int pse_page_size; 587 int deficit; 588 } sched; 589 590 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 591 }; 592 593 struct mt76_mmio { 594 void __iomem *regs; 595 spinlock_t irq_lock; 596 u32 irqmask; 597 598 struct mtk_wed_device wed; 599 struct completion wed_reset; 600 struct completion wed_reset_complete; 601 }; 602 603 struct mt76_rx_status { 604 union { 605 struct mt76_wcid *wcid; 606 u16 wcid_idx; 607 }; 608 609 u32 reorder_time; 610 611 u32 ampdu_ref; 612 u32 timestamp; 613 614 u8 iv[6]; 615 616 u8 phy_idx:2; 617 u8 aggr:1; 618 u8 qos_ctl; 619 u16 seqno; 620 621 u16 freq; 622 u32 flag; 623 u8 enc_flags; 624 u8 encoding:2, bw:3, he_ru:3; 625 u8 he_gi:2, he_dcm:1; 626 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 627 u8 rate_idx; 628 u8 nss; 629 u8 band; 630 s8 signal; 631 u8 chains; 632 s8 chain_signal[IEEE80211_MAX_CHAINS]; 633 }; 634 635 struct mt76_freq_range_power { 636 const struct cfg80211_sar_freq_ranges *range; 637 s8 power; 638 }; 639 640 struct mt76_testmode_ops { 641 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 642 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 643 enum mt76_testmode_state new_state); 644 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 645 }; 646 647 struct mt76_testmode_data { 648 enum mt76_testmode_state state; 649 650 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 651 struct sk_buff *tx_skb; 652 653 u32 tx_count; 654 u16 tx_mpdu_len; 655 656 u8 tx_rate_mode; 657 u8 tx_rate_idx; 658 u8 tx_rate_nss; 659 u8 tx_rate_sgi; 660 u8 tx_rate_ldpc; 661 u8 tx_rate_stbc; 662 u8 tx_ltf; 663 664 u8 tx_antenna_mask; 665 u8 tx_spe_idx; 666 667 u8 tx_duty_cycle; 668 u32 tx_time; 669 u32 tx_ipg; 670 671 u32 freq_offset; 672 673 u8 tx_power[4]; 674 u8 tx_power_control; 675 676 u8 addr[3][ETH_ALEN]; 677 678 u32 tx_pending; 679 u32 tx_queued; 680 u16 tx_queued_limit; 681 u32 tx_done; 682 struct { 683 u64 packets[__MT_RXQ_MAX]; 684 u64 fcs_error[__MT_RXQ_MAX]; 685 } rx_stats; 686 }; 687 688 struct mt76_vif { 689 u8 idx; 690 u8 omac_idx; 691 u8 band_idx; 692 u8 wmm_idx; 693 u8 scan_seq_num; 694 u8 cipher; 695 }; 696 697 struct mt76_phy { 698 struct ieee80211_hw *hw; 699 struct mt76_dev *dev; 700 void *priv; 701 702 unsigned long state; 703 u8 band_idx; 704 705 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 706 707 struct cfg80211_chan_def chandef; 708 struct ieee80211_channel *main_chan; 709 710 struct mt76_channel_state *chan_state; 711 enum mt76_dfs_state dfs_state; 712 ktime_t survey_time; 713 714 u32 aggr_stats[32]; 715 716 struct mt76_hw_cap cap; 717 struct mt76_sband sband_2g; 718 struct mt76_sband sband_5g; 719 struct mt76_sband sband_6g; 720 721 u8 macaddr[ETH_ALEN]; 722 723 int txpower_cur; 724 u8 antenna_mask; 725 u16 chainmask; 726 727 #ifdef CONFIG_NL80211_TESTMODE 728 struct mt76_testmode_data test; 729 #endif 730 731 struct delayed_work mac_work; 732 u8 mac_work_count; 733 734 struct { 735 struct sk_buff *head; 736 struct sk_buff **tail; 737 u16 seqno; 738 } rx_amsdu[__MT_RXQ_MAX]; 739 740 struct mt76_freq_range_power *frp; 741 742 struct { 743 struct led_classdev cdev; 744 char name[32]; 745 bool al; 746 u8 pin; 747 } leds; 748 }; 749 750 struct mt76_dev { 751 struct mt76_phy phy; /* must be first */ 752 struct mt76_phy *phys[__MT_MAX_BAND]; 753 754 struct ieee80211_hw *hw; 755 756 spinlock_t wed_lock; 757 spinlock_t lock; 758 spinlock_t cc_lock; 759 760 u32 cur_cc_bss_rx; 761 762 struct mt76_rx_status rx_ampdu_status; 763 u32 rx_ampdu_len; 764 u32 rx_ampdu_ref; 765 766 struct mutex mutex; 767 768 const struct mt76_bus_ops *bus; 769 const struct mt76_driver_ops *drv; 770 const struct mt76_mcu_ops *mcu_ops; 771 struct device *dev; 772 struct device *dma_dev; 773 774 struct mt76_mcu mcu; 775 776 struct net_device napi_dev; 777 struct net_device tx_napi_dev; 778 spinlock_t rx_lock; 779 struct napi_struct napi[__MT_RXQ_MAX]; 780 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 781 782 struct list_head txwi_cache; 783 struct list_head rxwi_cache; 784 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 785 struct mt76_queue q_rx[__MT_RXQ_MAX]; 786 const struct mt76_queue_ops *queue_ops; 787 int tx_dma_idx[4]; 788 789 struct mt76_worker tx_worker; 790 struct napi_struct tx_napi; 791 792 spinlock_t token_lock; 793 struct idr token; 794 u16 wed_token_count; 795 u16 token_count; 796 u16 token_size; 797 798 spinlock_t rx_token_lock; 799 struct idr rx_token; 800 u16 rx_token_size; 801 802 wait_queue_head_t tx_wait; 803 /* spinclock used to protect wcid pktid linked list */ 804 spinlock_t status_lock; 805 806 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 807 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 808 809 u64 vif_mask; 810 811 struct mt76_wcid global_wcid; 812 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 813 struct list_head wcid_list; 814 815 u32 rev; 816 817 struct tasklet_struct pre_tbtt_tasklet; 818 int beacon_int; 819 u8 beacon_mask; 820 821 struct debugfs_blob_wrapper eeprom; 822 struct debugfs_blob_wrapper otp; 823 824 char alpha2[3]; 825 enum nl80211_dfs_regions region; 826 827 u32 debugfs_reg; 828 829 u8 csa_complete; 830 831 u32 rxfilter; 832 833 #ifdef CONFIG_NL80211_TESTMODE 834 const struct mt76_testmode_ops *test_ops; 835 struct { 836 const char *name; 837 u32 offset; 838 } test_mtd; 839 #endif 840 struct workqueue_struct *wq; 841 842 union { 843 struct mt76_mmio mmio; 844 struct mt76_usb usb; 845 struct mt76_sdio sdio; 846 }; 847 }; 848 849 struct mt76_power_limits { 850 s8 cck[4]; 851 s8 ofdm[8]; 852 s8 mcs[4][10]; 853 s8 ru[7][12]; 854 }; 855 856 struct mt76_ethtool_worker_info { 857 u64 *data; 858 int idx; 859 int initial_stat_idx; 860 int worker_stat_count; 861 int sta_count; 862 }; 863 864 #define CCK_RATE(_idx, _rate) { \ 865 .bitrate = _rate, \ 866 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 867 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 868 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 869 } 870 871 #define OFDM_RATE(_idx, _rate) { \ 872 .bitrate = _rate, \ 873 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 874 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 875 } 876 877 extern struct ieee80211_rate mt76_rates[12]; 878 879 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 880 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 881 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 882 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 883 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 884 885 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 886 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 887 888 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 889 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 890 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 891 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 892 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 893 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 894 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 895 896 897 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 898 899 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 900 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 901 902 #define mt76_get_field(_dev, _reg, _field) \ 903 FIELD_GET(_field, mt76_rr(dev, _reg)) 904 905 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 906 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 907 908 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 909 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 910 911 #define mt76_hw(dev) (dev)->mphy.hw 912 913 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 914 int timeout); 915 916 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 917 918 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 919 int timeout, int kick); 920 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 921 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 922 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 923 924 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 925 void mt76_pci_disable_aspm(struct pci_dev *pdev); 926 927 static inline u16 mt76_chip(struct mt76_dev *dev) 928 { 929 return dev->rev >> 16; 930 } 931 932 static inline u16 mt76_rev(struct mt76_dev *dev) 933 { 934 return dev->rev & 0xffff; 935 } 936 937 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 938 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 939 940 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 941 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 942 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 943 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 944 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 945 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 946 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 947 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 948 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 949 950 #define mt76_for_each_q_rx(dev, i) \ 951 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 952 if ((dev)->q_rx[i].ndesc) 953 954 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 955 const struct ieee80211_ops *ops, 956 const struct mt76_driver_ops *drv_ops); 957 int mt76_register_device(struct mt76_dev *dev, bool vht, 958 struct ieee80211_rate *rates, int n_rates); 959 void mt76_unregister_device(struct mt76_dev *dev); 960 void mt76_free_device(struct mt76_dev *dev); 961 void mt76_unregister_phy(struct mt76_phy *phy); 962 963 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 964 const struct ieee80211_ops *ops, 965 u8 band_idx); 966 int mt76_register_phy(struct mt76_phy *phy, bool vht, 967 struct ieee80211_rate *rates, int n_rates); 968 969 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 970 const struct file_operations *ops); 971 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 972 { 973 return mt76_register_debugfs_fops(&dev->phy, NULL); 974 } 975 976 int mt76_queues_read(struct seq_file *s, void *data); 977 void mt76_seq_puts_array(struct seq_file *file, const char *str, 978 s8 *val, int len); 979 980 int mt76_eeprom_init(struct mt76_dev *dev, int len); 981 void mt76_eeprom_override(struct mt76_phy *phy); 982 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 983 984 struct mt76_queue * 985 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 986 int ring_base, u32 flags); 987 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 988 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 989 int n_desc, int ring_base, u32 flags) 990 { 991 struct mt76_queue *q; 992 993 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 994 if (IS_ERR(q)) 995 return PTR_ERR(q); 996 997 phy->q_tx[qid] = q; 998 999 return 0; 1000 } 1001 1002 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1003 int n_desc, int ring_base) 1004 { 1005 struct mt76_queue *q; 1006 1007 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1008 if (IS_ERR(q)) 1009 return PTR_ERR(q); 1010 1011 dev->q_mcu[qid] = q; 1012 1013 return 0; 1014 } 1015 1016 static inline struct mt76_phy * 1017 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1018 { 1019 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1020 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1021 return dev->phys[phy_idx]; 1022 1023 return &dev->phy; 1024 } 1025 1026 static inline struct ieee80211_hw * 1027 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1028 { 1029 return mt76_dev_phy(dev, phy_idx)->hw; 1030 } 1031 1032 static inline u8 * 1033 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1034 { 1035 return (u8 *)t - dev->drv->txwi_size; 1036 } 1037 1038 /* increment with wrap-around */ 1039 static inline int mt76_incr(int val, int size) 1040 { 1041 return (val + 1) & (size - 1); 1042 } 1043 1044 /* decrement with wrap-around */ 1045 static inline int mt76_decr(int val, int size) 1046 { 1047 return (val - 1) & (size - 1); 1048 } 1049 1050 u8 mt76_ac_to_hwq(u8 ac); 1051 1052 static inline struct ieee80211_txq * 1053 mtxq_to_txq(struct mt76_txq *mtxq) 1054 { 1055 void *ptr = mtxq; 1056 1057 return container_of(ptr, struct ieee80211_txq, drv_priv); 1058 } 1059 1060 static inline struct ieee80211_sta * 1061 wcid_to_sta(struct mt76_wcid *wcid) 1062 { 1063 void *ptr = wcid; 1064 1065 if (!wcid || !wcid->sta) 1066 return NULL; 1067 1068 return container_of(ptr, struct ieee80211_sta, drv_priv); 1069 } 1070 1071 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1072 { 1073 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1074 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1075 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1076 } 1077 1078 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1079 { 1080 struct mt76_rx_status mstat; 1081 u8 *data = skb->data; 1082 1083 /* Alignment concerns */ 1084 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1085 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1086 1087 mstat = *((struct mt76_rx_status *)skb->cb); 1088 1089 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1090 data += sizeof(struct ieee80211_radiotap_he); 1091 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1092 data += sizeof(struct ieee80211_radiotap_he_mu); 1093 1094 return data; 1095 } 1096 1097 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1098 { 1099 int len = ieee80211_get_hdrlen_from_skb(skb); 1100 1101 if (len % 4 == 0) 1102 return; 1103 1104 skb_push(skb, 2); 1105 memmove(skb->data, skb->data + 2, len); 1106 1107 skb->data[len] = 0; 1108 skb->data[len + 1] = 0; 1109 } 1110 1111 static inline bool mt76_is_skb_pktid(u8 pktid) 1112 { 1113 if (pktid & MT_PACKET_ID_HAS_RATE) 1114 return false; 1115 1116 return pktid >= MT_PACKET_ID_FIRST; 1117 } 1118 1119 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1120 { 1121 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1122 u8 idx = nss - 1; 1123 1124 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1125 } 1126 1127 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1128 { 1129 #ifdef CONFIG_NL80211_TESTMODE 1130 return phy->test.state != MT76_TM_STATE_OFF; 1131 #else 1132 return false; 1133 #endif 1134 } 1135 1136 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1137 struct sk_buff *skb, 1138 struct ieee80211_hw **hw) 1139 { 1140 #ifdef CONFIG_NL80211_TESTMODE 1141 int i; 1142 1143 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1144 struct mt76_phy *phy = dev->phys[i]; 1145 1146 if (phy && skb == phy->test.tx_skb) { 1147 *hw = dev->phys[i]->hw; 1148 return true; 1149 } 1150 } 1151 return false; 1152 #else 1153 return false; 1154 #endif 1155 } 1156 1157 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1158 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1159 struct mt76_wcid *wcid, struct sk_buff *skb); 1160 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1161 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1162 bool send_bar); 1163 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1164 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1165 void mt76_txq_schedule_all(struct mt76_phy *phy); 1166 void mt76_tx_worker_run(struct mt76_dev *dev); 1167 void mt76_tx_worker(struct mt76_worker *w); 1168 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1169 struct ieee80211_sta *sta, 1170 u16 tids, int nframes, 1171 enum ieee80211_frame_release_type reason, 1172 bool more_data); 1173 bool mt76_has_tx_pending(struct mt76_phy *phy); 1174 void mt76_set_channel(struct mt76_phy *phy); 1175 void mt76_update_survey(struct mt76_phy *phy); 1176 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1177 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1178 struct survey_info *survey); 1179 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1180 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1181 1182 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1183 u16 ssn, u16 size); 1184 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1185 1186 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1187 struct ieee80211_key_conf *key); 1188 1189 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1190 __acquires(&dev->status_lock); 1191 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1192 __releases(&dev->status_lock); 1193 1194 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1195 struct sk_buff *skb); 1196 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1197 struct mt76_wcid *wcid, int pktid, 1198 struct sk_buff_head *list); 1199 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1200 struct sk_buff_head *list); 1201 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1202 struct list_head *free_list); 1203 static inline void 1204 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1205 { 1206 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1207 } 1208 1209 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1210 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1211 struct ieee80211_sta *sta, 1212 enum ieee80211_sta_state old_state, 1213 enum ieee80211_sta_state new_state); 1214 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1215 struct ieee80211_sta *sta); 1216 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1217 struct ieee80211_sta *sta); 1218 1219 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1220 1221 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1222 int *dbm); 1223 int mt76_init_sar_power(struct ieee80211_hw *hw, 1224 const struct cfg80211_sar_specs *sar); 1225 int mt76_get_sar_power(struct mt76_phy *phy, 1226 struct ieee80211_channel *chan, 1227 int power); 1228 1229 void mt76_csa_check(struct mt76_dev *dev); 1230 void mt76_csa_finish(struct mt76_dev *dev); 1231 1232 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1233 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1234 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1235 int mt76_get_rate(struct mt76_dev *dev, 1236 struct ieee80211_supported_band *sband, 1237 int idx, bool cck); 1238 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1239 const u8 *mac); 1240 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1241 struct ieee80211_vif *vif); 1242 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1243 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1244 void *data, int len); 1245 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1246 struct netlink_callback *cb, void *data, int len); 1247 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1248 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1249 1250 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1251 { 1252 #ifdef CONFIG_NL80211_TESTMODE 1253 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1254 1255 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1256 state = MT76_TM_STATE_OFF; 1257 1258 mt76_testmode_set_state(phy, state); 1259 #endif 1260 } 1261 1262 1263 /* internal */ 1264 static inline struct ieee80211_hw * 1265 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1266 { 1267 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1268 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1269 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1270 1271 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1272 1273 return hw; 1274 } 1275 1276 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1277 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1278 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1279 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1280 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1281 struct napi_struct *napi); 1282 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1283 struct napi_struct *napi); 1284 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1285 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1286 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1287 struct mt76_queue_entry *e); 1288 1289 /* usb */ 1290 static inline bool mt76u_urb_error(struct urb *urb) 1291 { 1292 return urb->status && 1293 urb->status != -ECONNRESET && 1294 urb->status != -ESHUTDOWN && 1295 urb->status != -ENOENT; 1296 } 1297 1298 /* Map hardware queues to usb endpoints */ 1299 static inline u8 q2ep(u8 qid) 1300 { 1301 /* TODO: take management packets to queue 5 */ 1302 return qid + 1; 1303 } 1304 1305 static inline int 1306 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1307 int timeout, int ep) 1308 { 1309 struct usb_interface *uintf = to_usb_interface(dev->dev); 1310 struct usb_device *udev = interface_to_usbdev(uintf); 1311 struct mt76_usb *usb = &dev->usb; 1312 unsigned int pipe; 1313 1314 if (actual_len) 1315 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1316 else 1317 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1318 1319 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1320 } 1321 1322 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1323 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1324 struct mt76_sta_stats *stats, bool eht); 1325 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1326 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1327 u16 val, u16 offset, void *buf, size_t len); 1328 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1329 u8 req_type, u16 val, u16 offset, 1330 void *buf, size_t len); 1331 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1332 const u16 offset, const u32 val); 1333 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1334 void *data, int len); 1335 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1336 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1337 u32 addr, u32 val); 1338 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1339 struct mt76_bus_ops *ops); 1340 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1341 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1342 int mt76u_alloc_queues(struct mt76_dev *dev); 1343 void mt76u_stop_tx(struct mt76_dev *dev); 1344 void mt76u_stop_rx(struct mt76_dev *dev); 1345 int mt76u_resume_rx(struct mt76_dev *dev); 1346 void mt76u_queues_deinit(struct mt76_dev *dev); 1347 1348 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1349 const struct mt76_bus_ops *bus_ops); 1350 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1351 int mt76s_alloc_tx(struct mt76_dev *dev); 1352 void mt76s_deinit(struct mt76_dev *dev); 1353 void mt76s_sdio_irq(struct sdio_func *func); 1354 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1355 bool mt76s_txqs_empty(struct mt76_dev *dev); 1356 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1357 int hw_ver); 1358 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1359 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1360 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1361 u32 mt76s_read_pcr(struct mt76_dev *dev); 1362 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1363 const void *data, int len); 1364 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1365 void *data, int len); 1366 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1367 const struct mt76_reg_pair *data, 1368 int len); 1369 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1370 struct mt76_reg_pair *data, int len); 1371 1372 struct sk_buff * 1373 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1374 int len, int data_len, gfp_t gfp); 1375 static inline struct sk_buff * 1376 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1377 int data_len) 1378 { 1379 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1380 } 1381 1382 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1383 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1384 unsigned long expires); 1385 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1386 int len, bool wait_resp, struct sk_buff **ret); 1387 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1388 int cmd, bool wait_resp, struct sk_buff **ret); 1389 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1390 int len, int max_len); 1391 static inline int 1392 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1393 int len) 1394 { 1395 int max_len = 4096 - dev->mcu_ops->headroom; 1396 1397 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1398 } 1399 1400 static inline int 1401 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1402 bool wait_resp) 1403 { 1404 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1405 } 1406 1407 static inline int 1408 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1409 bool wait_resp) 1410 { 1411 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1412 } 1413 1414 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1415 1416 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1417 struct ieee80211_channel *chan, 1418 struct mt76_power_limits *dest, 1419 s8 target_power); 1420 1421 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1422 { 1423 return (q->flags & MT_QFLAG_WED) && 1424 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1425 } 1426 1427 struct mt76_txwi_cache * 1428 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1429 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1430 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1431 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1432 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1433 struct mt76_txwi_cache *r, dma_addr_t phys); 1434 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1435 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1436 { 1437 struct page *page = virt_to_head_page(buf); 1438 1439 page_pool_put_full_page(page->pp, page, allow_direct); 1440 } 1441 1442 static inline void * 1443 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1444 { 1445 struct page *page; 1446 1447 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1448 if (!page) 1449 return NULL; 1450 1451 return page_address(page) + *offset; 1452 } 1453 1454 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1455 { 1456 spin_lock_bh(&dev->token_lock); 1457 __mt76_set_tx_blocked(dev, blocked); 1458 spin_unlock_bh(&dev->token_lock); 1459 } 1460 1461 static inline int 1462 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1463 { 1464 int token; 1465 1466 spin_lock_bh(&dev->token_lock); 1467 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1468 spin_unlock_bh(&dev->token_lock); 1469 1470 return token; 1471 } 1472 1473 static inline struct mt76_txwi_cache * 1474 mt76_token_put(struct mt76_dev *dev, int token) 1475 { 1476 struct mt76_txwi_cache *txwi; 1477 1478 spin_lock_bh(&dev->token_lock); 1479 txwi = idr_remove(&dev->token, token); 1480 spin_unlock_bh(&dev->token_lock); 1481 1482 return txwi; 1483 } 1484 1485 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1486 { 1487 INIT_LIST_HEAD(&wcid->list); 1488 idr_init(&wcid->pktid); 1489 } 1490 1491 static inline void 1492 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1493 { 1494 struct sk_buff_head list; 1495 1496 mt76_tx_status_lock(dev, &list); 1497 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1498 mt76_tx_status_unlock(dev, &list); 1499 1500 idr_destroy(&wcid->pktid); 1501 } 1502 1503 #endif 1504