1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 MT_PHY_TYPE_EHT_SU = 13, 268 MT_PHY_TYPE_EHT_TRIG, 269 MT_PHY_TYPE_EHT_MU, 270 __MT_PHY_TYPE_MAX, 271 }; 272 273 struct mt76_sta_stats { 274 u64 tx_mode[__MT_PHY_TYPE_MAX]; 275 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 276 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 277 u64 tx_mcs[16]; /* mcs idx */ 278 u64 tx_bytes; 279 /* WED TX */ 280 u32 tx_packets; 281 u32 tx_retries; 282 u32 tx_failed; 283 /* WED RX */ 284 u64 rx_bytes; 285 u32 rx_packets; 286 u32 rx_errors; 287 u32 rx_drops; 288 }; 289 290 enum mt76_wcid_flags { 291 MT_WCID_FLAG_CHECK_PS, 292 MT_WCID_FLAG_PS, 293 MT_WCID_FLAG_4ADDR, 294 MT_WCID_FLAG_HDR_TRANS, 295 }; 296 297 #define MT76_N_WCIDS 544 298 299 /* stored in ieee80211_tx_info::hw_queue */ 300 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 301 302 DECLARE_EWMA(signal, 10, 8); 303 304 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 305 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 306 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 307 #define MT_WCID_TX_INFO_SET BIT(31) 308 309 struct mt76_wcid { 310 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 311 312 atomic_t non_aql_packets; 313 unsigned long flags; 314 315 struct ewma_signal rssi; 316 int inactive_count; 317 318 struct rate_info rate; 319 320 u16 idx; 321 u8 hw_key_idx; 322 u8 hw_key_idx2; 323 324 u8 sta:1; 325 u8 amsdu:1; 326 u8 phy_idx:2; 327 328 u8 rx_check_pn; 329 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 330 u16 cipher; 331 332 u32 tx_info; 333 bool sw_iv; 334 335 struct list_head list; 336 struct idr pktid; 337 338 struct mt76_sta_stats stats; 339 }; 340 341 struct mt76_txq { 342 u16 wcid; 343 344 u16 agg_ssn; 345 bool send_bar; 346 bool aggr; 347 }; 348 349 struct mt76_txwi_cache { 350 struct list_head list; 351 dma_addr_t dma_addr; 352 353 union { 354 struct sk_buff *skb; 355 void *ptr; 356 }; 357 }; 358 359 struct mt76_rx_tid { 360 struct rcu_head rcu_head; 361 362 struct mt76_dev *dev; 363 364 spinlock_t lock; 365 struct delayed_work reorder_work; 366 367 u16 head; 368 u16 size; 369 u16 nframes; 370 371 u8 num; 372 373 u8 started:1, stopped:1, timer_pending:1; 374 375 struct sk_buff *reorder_buf[]; 376 }; 377 378 #define MT_TX_CB_DMA_DONE BIT(0) 379 #define MT_TX_CB_TXS_DONE BIT(1) 380 #define MT_TX_CB_TXS_FAILED BIT(2) 381 382 #define MT_PACKET_ID_MASK GENMASK(6, 0) 383 #define MT_PACKET_ID_NO_ACK 0 384 #define MT_PACKET_ID_NO_SKB 1 385 #define MT_PACKET_ID_WED 2 386 #define MT_PACKET_ID_FIRST 3 387 #define MT_PACKET_ID_HAS_RATE BIT(7) 388 /* This is timer for when to give up when waiting for TXS callback, 389 * with starting time being the time at which the DMA_DONE callback 390 * was seen (so, we know packet was processed then, it should not take 391 * long after that for firmware to send the TXS callback if it is going 392 * to do so.) 393 */ 394 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 395 396 struct mt76_tx_cb { 397 unsigned long jiffies; 398 u16 wcid; 399 u8 pktid; 400 u8 flags; 401 }; 402 403 enum { 404 MT76_STATE_INITIALIZED, 405 MT76_STATE_RUNNING, 406 MT76_STATE_MCU_RUNNING, 407 MT76_SCANNING, 408 MT76_HW_SCANNING, 409 MT76_HW_SCHED_SCANNING, 410 MT76_RESTART, 411 MT76_RESET, 412 MT76_MCU_RESET, 413 MT76_REMOVED, 414 MT76_READING_STATS, 415 MT76_STATE_POWER_OFF, 416 MT76_STATE_SUSPEND, 417 MT76_STATE_ROC, 418 MT76_STATE_PM, 419 }; 420 421 struct mt76_hw_cap { 422 bool has_2ghz; 423 bool has_5ghz; 424 bool has_6ghz; 425 }; 426 427 #define MT_DRV_TXWI_NO_FREE BIT(0) 428 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 429 #define MT_DRV_SW_RX_AIRTIME BIT(2) 430 #define MT_DRV_RX_DMA_HDR BIT(3) 431 #define MT_DRV_HW_MGMT_TXQ BIT(4) 432 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 433 434 struct mt76_driver_ops { 435 u32 drv_flags; 436 u32 survey_flags; 437 u16 txwi_size; 438 u16 token_size; 439 u8 mcs_rates; 440 441 void (*update_survey)(struct mt76_phy *phy); 442 443 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 444 enum mt76_txq_id qid, struct mt76_wcid *wcid, 445 struct ieee80211_sta *sta, 446 struct mt76_tx_info *tx_info); 447 448 void (*tx_complete_skb)(struct mt76_dev *dev, 449 struct mt76_queue_entry *e); 450 451 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 452 453 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 454 455 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 456 struct sk_buff *skb, u32 *info); 457 458 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 459 460 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 461 bool ps); 462 463 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 464 struct ieee80211_sta *sta); 465 466 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 467 struct ieee80211_sta *sta); 468 469 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 470 struct ieee80211_sta *sta); 471 }; 472 473 struct mt76_channel_state { 474 u64 cc_active; 475 u64 cc_busy; 476 u64 cc_rx; 477 u64 cc_bss_rx; 478 u64 cc_tx; 479 480 s8 noise; 481 }; 482 483 struct mt76_sband { 484 struct ieee80211_supported_band sband; 485 struct mt76_channel_state *chan; 486 }; 487 488 /* addr req mask */ 489 #define MT_VEND_TYPE_EEPROM BIT(31) 490 #define MT_VEND_TYPE_CFG BIT(30) 491 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 492 493 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 494 enum mt_vendor_req { 495 MT_VEND_DEV_MODE = 0x1, 496 MT_VEND_WRITE = 0x2, 497 MT_VEND_POWER_ON = 0x4, 498 MT_VEND_MULTI_WRITE = 0x6, 499 MT_VEND_MULTI_READ = 0x7, 500 MT_VEND_READ_EEPROM = 0x9, 501 MT_VEND_WRITE_FCE = 0x42, 502 MT_VEND_WRITE_CFG = 0x46, 503 MT_VEND_READ_CFG = 0x47, 504 MT_VEND_READ_EXT = 0x63, 505 MT_VEND_WRITE_EXT = 0x66, 506 MT_VEND_FEATURE_SET = 0x91, 507 }; 508 509 enum mt76u_in_ep { 510 MT_EP_IN_PKT_RX, 511 MT_EP_IN_CMD_RESP, 512 __MT_EP_IN_MAX, 513 }; 514 515 enum mt76u_out_ep { 516 MT_EP_OUT_INBAND_CMD, 517 MT_EP_OUT_AC_BE, 518 MT_EP_OUT_AC_BK, 519 MT_EP_OUT_AC_VI, 520 MT_EP_OUT_AC_VO, 521 MT_EP_OUT_HCCA, 522 __MT_EP_OUT_MAX, 523 }; 524 525 struct mt76_mcu { 526 struct mutex mutex; 527 u32 msg_seq; 528 int timeout; 529 530 struct sk_buff_head res_q; 531 wait_queue_head_t wait; 532 }; 533 534 #define MT_TX_SG_MAX_SIZE 8 535 #define MT_RX_SG_MAX_SIZE 4 536 #define MT_NUM_TX_ENTRIES 256 537 #define MT_NUM_RX_ENTRIES 128 538 #define MCU_RESP_URB_SIZE 1024 539 struct mt76_usb { 540 struct mutex usb_ctrl_mtx; 541 u8 *data; 542 u16 data_len; 543 544 struct mt76_worker status_worker; 545 struct mt76_worker rx_worker; 546 547 struct work_struct stat_work; 548 549 u8 out_ep[__MT_EP_OUT_MAX]; 550 u8 in_ep[__MT_EP_IN_MAX]; 551 bool sg_en; 552 553 struct mt76u_mcu { 554 u8 *data; 555 /* multiple reads */ 556 struct mt76_reg_pair *rp; 557 int rp_len; 558 u32 base; 559 } mcu; 560 }; 561 562 #define MT76S_XMIT_BUF_SZ 0x3fe00 563 #define MT76S_NUM_TX_ENTRIES 256 564 #define MT76S_NUM_RX_ENTRIES 512 565 struct mt76_sdio { 566 struct mt76_worker txrx_worker; 567 struct mt76_worker status_worker; 568 struct mt76_worker net_worker; 569 570 struct work_struct stat_work; 571 572 u8 *xmit_buf; 573 u32 xmit_buf_sz; 574 575 struct sdio_func *func; 576 void *intr_data; 577 u8 hw_ver; 578 wait_queue_head_t wait; 579 580 struct { 581 int pse_data_quota; 582 int ple_data_quota; 583 int pse_mcu_quota; 584 int pse_page_size; 585 int deficit; 586 } sched; 587 588 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 589 }; 590 591 struct mt76_mmio { 592 void __iomem *regs; 593 spinlock_t irq_lock; 594 u32 irqmask; 595 596 struct mtk_wed_device wed; 597 }; 598 599 struct mt76_rx_status { 600 union { 601 struct mt76_wcid *wcid; 602 u16 wcid_idx; 603 }; 604 605 u32 reorder_time; 606 607 u32 ampdu_ref; 608 u32 timestamp; 609 610 u8 iv[6]; 611 612 u8 phy_idx:2; 613 u8 aggr:1; 614 u8 qos_ctl; 615 u16 seqno; 616 617 u16 freq; 618 u32 flag; 619 u8 enc_flags; 620 u8 encoding:2, bw:3, he_ru:3; 621 u8 he_gi:2, he_dcm:1; 622 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 623 u8 rate_idx; 624 u8 nss; 625 u8 band; 626 s8 signal; 627 u8 chains; 628 s8 chain_signal[IEEE80211_MAX_CHAINS]; 629 }; 630 631 struct mt76_freq_range_power { 632 const struct cfg80211_sar_freq_ranges *range; 633 s8 power; 634 }; 635 636 struct mt76_testmode_ops { 637 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 638 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 639 enum mt76_testmode_state new_state); 640 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 641 }; 642 643 struct mt76_testmode_data { 644 enum mt76_testmode_state state; 645 646 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 647 struct sk_buff *tx_skb; 648 649 u32 tx_count; 650 u16 tx_mpdu_len; 651 652 u8 tx_rate_mode; 653 u8 tx_rate_idx; 654 u8 tx_rate_nss; 655 u8 tx_rate_sgi; 656 u8 tx_rate_ldpc; 657 u8 tx_rate_stbc; 658 u8 tx_ltf; 659 660 u8 tx_antenna_mask; 661 u8 tx_spe_idx; 662 663 u8 tx_duty_cycle; 664 u32 tx_time; 665 u32 tx_ipg; 666 667 u32 freq_offset; 668 669 u8 tx_power[4]; 670 u8 tx_power_control; 671 672 u8 addr[3][ETH_ALEN]; 673 674 u32 tx_pending; 675 u32 tx_queued; 676 u16 tx_queued_limit; 677 u32 tx_done; 678 struct { 679 u64 packets[__MT_RXQ_MAX]; 680 u64 fcs_error[__MT_RXQ_MAX]; 681 } rx_stats; 682 }; 683 684 struct mt76_vif { 685 u8 idx; 686 u8 omac_idx; 687 u8 band_idx; 688 u8 wmm_idx; 689 u8 scan_seq_num; 690 u8 cipher; 691 }; 692 693 struct mt76_phy { 694 struct ieee80211_hw *hw; 695 struct mt76_dev *dev; 696 void *priv; 697 698 unsigned long state; 699 u8 band_idx; 700 701 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 702 703 struct cfg80211_chan_def chandef; 704 struct ieee80211_channel *main_chan; 705 706 struct mt76_channel_state *chan_state; 707 enum mt76_dfs_state dfs_state; 708 ktime_t survey_time; 709 710 u32 aggr_stats[32]; 711 712 struct mt76_hw_cap cap; 713 struct mt76_sband sband_2g; 714 struct mt76_sband sband_5g; 715 struct mt76_sband sband_6g; 716 717 u8 macaddr[ETH_ALEN]; 718 719 int txpower_cur; 720 u8 antenna_mask; 721 u16 chainmask; 722 723 #ifdef CONFIG_NL80211_TESTMODE 724 struct mt76_testmode_data test; 725 #endif 726 727 struct delayed_work mac_work; 728 u8 mac_work_count; 729 730 struct { 731 struct sk_buff *head; 732 struct sk_buff **tail; 733 u16 seqno; 734 } rx_amsdu[__MT_RXQ_MAX]; 735 736 struct mt76_freq_range_power *frp; 737 738 struct { 739 struct led_classdev cdev; 740 char name[32]; 741 bool al; 742 u8 pin; 743 } leds; 744 }; 745 746 struct mt76_dev { 747 struct mt76_phy phy; /* must be first */ 748 struct mt76_phy *phys[__MT_MAX_BAND]; 749 750 struct ieee80211_hw *hw; 751 752 spinlock_t wed_lock; 753 spinlock_t lock; 754 spinlock_t cc_lock; 755 756 u32 cur_cc_bss_rx; 757 758 struct mt76_rx_status rx_ampdu_status; 759 u32 rx_ampdu_len; 760 u32 rx_ampdu_ref; 761 762 struct mutex mutex; 763 764 const struct mt76_bus_ops *bus; 765 const struct mt76_driver_ops *drv; 766 const struct mt76_mcu_ops *mcu_ops; 767 struct device *dev; 768 struct device *dma_dev; 769 770 struct mt76_mcu mcu; 771 772 struct net_device napi_dev; 773 struct net_device tx_napi_dev; 774 spinlock_t rx_lock; 775 struct napi_struct napi[__MT_RXQ_MAX]; 776 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 777 778 struct list_head txwi_cache; 779 struct list_head rxwi_cache; 780 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 781 struct mt76_queue q_rx[__MT_RXQ_MAX]; 782 const struct mt76_queue_ops *queue_ops; 783 int tx_dma_idx[4]; 784 785 struct mt76_worker tx_worker; 786 struct napi_struct tx_napi; 787 788 spinlock_t token_lock; 789 struct idr token; 790 u16 wed_token_count; 791 u16 token_count; 792 u16 token_size; 793 794 spinlock_t rx_token_lock; 795 struct idr rx_token; 796 u16 rx_token_size; 797 798 wait_queue_head_t tx_wait; 799 /* spinclock used to protect wcid pktid linked list */ 800 spinlock_t status_lock; 801 802 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 803 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 804 805 u64 vif_mask; 806 807 struct mt76_wcid global_wcid; 808 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 809 struct list_head wcid_list; 810 811 u32 rev; 812 813 struct tasklet_struct pre_tbtt_tasklet; 814 int beacon_int; 815 u8 beacon_mask; 816 817 struct debugfs_blob_wrapper eeprom; 818 struct debugfs_blob_wrapper otp; 819 820 char alpha2[3]; 821 enum nl80211_dfs_regions region; 822 823 u32 debugfs_reg; 824 825 u8 csa_complete; 826 827 u32 rxfilter; 828 829 #ifdef CONFIG_NL80211_TESTMODE 830 const struct mt76_testmode_ops *test_ops; 831 struct { 832 const char *name; 833 u32 offset; 834 } test_mtd; 835 #endif 836 struct workqueue_struct *wq; 837 838 union { 839 struct mt76_mmio mmio; 840 struct mt76_usb usb; 841 struct mt76_sdio sdio; 842 }; 843 }; 844 845 struct mt76_power_limits { 846 s8 cck[4]; 847 s8 ofdm[8]; 848 s8 mcs[4][10]; 849 s8 ru[7][12]; 850 }; 851 852 struct mt76_ethtool_worker_info { 853 u64 *data; 854 int idx; 855 int initial_stat_idx; 856 int worker_stat_count; 857 int sta_count; 858 }; 859 860 #define CCK_RATE(_idx, _rate) { \ 861 .bitrate = _rate, \ 862 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 863 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 864 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 865 } 866 867 #define OFDM_RATE(_idx, _rate) { \ 868 .bitrate = _rate, \ 869 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 870 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 871 } 872 873 extern struct ieee80211_rate mt76_rates[12]; 874 875 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 876 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 877 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 878 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 879 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 880 881 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 882 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 883 884 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 885 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 886 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 887 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 888 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 889 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 890 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 891 892 893 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 894 895 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 896 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 897 898 #define mt76_get_field(_dev, _reg, _field) \ 899 FIELD_GET(_field, mt76_rr(dev, _reg)) 900 901 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 902 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 903 904 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 905 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 906 907 #define mt76_hw(dev) (dev)->mphy.hw 908 909 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 910 int timeout); 911 912 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 913 914 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 915 int timeout, int kick); 916 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 917 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 918 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 919 920 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 921 void mt76_pci_disable_aspm(struct pci_dev *pdev); 922 923 static inline u16 mt76_chip(struct mt76_dev *dev) 924 { 925 return dev->rev >> 16; 926 } 927 928 static inline u16 mt76_rev(struct mt76_dev *dev) 929 { 930 return dev->rev & 0xffff; 931 } 932 933 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 934 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 935 936 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 937 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 938 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 939 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 940 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 941 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 942 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 943 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 944 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 945 946 #define mt76_for_each_q_rx(dev, i) \ 947 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 948 if ((dev)->q_rx[i].ndesc) 949 950 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 951 const struct ieee80211_ops *ops, 952 const struct mt76_driver_ops *drv_ops); 953 int mt76_register_device(struct mt76_dev *dev, bool vht, 954 struct ieee80211_rate *rates, int n_rates); 955 void mt76_unregister_device(struct mt76_dev *dev); 956 void mt76_free_device(struct mt76_dev *dev); 957 void mt76_unregister_phy(struct mt76_phy *phy); 958 959 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 960 const struct ieee80211_ops *ops, 961 u8 band_idx); 962 int mt76_register_phy(struct mt76_phy *phy, bool vht, 963 struct ieee80211_rate *rates, int n_rates); 964 965 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 966 const struct file_operations *ops); 967 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 968 { 969 return mt76_register_debugfs_fops(&dev->phy, NULL); 970 } 971 972 int mt76_queues_read(struct seq_file *s, void *data); 973 void mt76_seq_puts_array(struct seq_file *file, const char *str, 974 s8 *val, int len); 975 976 int mt76_eeprom_init(struct mt76_dev *dev, int len); 977 void mt76_eeprom_override(struct mt76_phy *phy); 978 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 979 980 struct mt76_queue * 981 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 982 int ring_base, u32 flags); 983 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 984 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 985 int n_desc, int ring_base, u32 flags) 986 { 987 struct mt76_queue *q; 988 989 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 990 if (IS_ERR(q)) 991 return PTR_ERR(q); 992 993 phy->q_tx[qid] = q; 994 995 return 0; 996 } 997 998 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 999 int n_desc, int ring_base) 1000 { 1001 struct mt76_queue *q; 1002 1003 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1004 if (IS_ERR(q)) 1005 return PTR_ERR(q); 1006 1007 dev->q_mcu[qid] = q; 1008 1009 return 0; 1010 } 1011 1012 static inline struct mt76_phy * 1013 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1014 { 1015 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1016 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1017 return dev->phys[phy_idx]; 1018 1019 return &dev->phy; 1020 } 1021 1022 static inline struct ieee80211_hw * 1023 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1024 { 1025 return mt76_dev_phy(dev, phy_idx)->hw; 1026 } 1027 1028 static inline u8 * 1029 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1030 { 1031 return (u8 *)t - dev->drv->txwi_size; 1032 } 1033 1034 /* increment with wrap-around */ 1035 static inline int mt76_incr(int val, int size) 1036 { 1037 return (val + 1) & (size - 1); 1038 } 1039 1040 /* decrement with wrap-around */ 1041 static inline int mt76_decr(int val, int size) 1042 { 1043 return (val - 1) & (size - 1); 1044 } 1045 1046 u8 mt76_ac_to_hwq(u8 ac); 1047 1048 static inline struct ieee80211_txq * 1049 mtxq_to_txq(struct mt76_txq *mtxq) 1050 { 1051 void *ptr = mtxq; 1052 1053 return container_of(ptr, struct ieee80211_txq, drv_priv); 1054 } 1055 1056 static inline struct ieee80211_sta * 1057 wcid_to_sta(struct mt76_wcid *wcid) 1058 { 1059 void *ptr = wcid; 1060 1061 if (!wcid || !wcid->sta) 1062 return NULL; 1063 1064 return container_of(ptr, struct ieee80211_sta, drv_priv); 1065 } 1066 1067 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1068 { 1069 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1070 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1071 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1072 } 1073 1074 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1075 { 1076 struct mt76_rx_status mstat; 1077 u8 *data = skb->data; 1078 1079 /* Alignment concerns */ 1080 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1081 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1082 1083 mstat = *((struct mt76_rx_status *)skb->cb); 1084 1085 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1086 data += sizeof(struct ieee80211_radiotap_he); 1087 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1088 data += sizeof(struct ieee80211_radiotap_he_mu); 1089 1090 return data; 1091 } 1092 1093 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1094 { 1095 int len = ieee80211_get_hdrlen_from_skb(skb); 1096 1097 if (len % 4 == 0) 1098 return; 1099 1100 skb_push(skb, 2); 1101 memmove(skb->data, skb->data + 2, len); 1102 1103 skb->data[len] = 0; 1104 skb->data[len + 1] = 0; 1105 } 1106 1107 static inline bool mt76_is_skb_pktid(u8 pktid) 1108 { 1109 if (pktid & MT_PACKET_ID_HAS_RATE) 1110 return false; 1111 1112 return pktid >= MT_PACKET_ID_FIRST; 1113 } 1114 1115 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1116 { 1117 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1118 u8 idx = nss - 1; 1119 1120 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1121 } 1122 1123 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1124 { 1125 #ifdef CONFIG_NL80211_TESTMODE 1126 return phy->test.state != MT76_TM_STATE_OFF; 1127 #else 1128 return false; 1129 #endif 1130 } 1131 1132 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1133 struct sk_buff *skb, 1134 struct ieee80211_hw **hw) 1135 { 1136 #ifdef CONFIG_NL80211_TESTMODE 1137 int i; 1138 1139 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1140 struct mt76_phy *phy = dev->phys[i]; 1141 1142 if (phy && skb == phy->test.tx_skb) { 1143 *hw = dev->phys[i]->hw; 1144 return true; 1145 } 1146 } 1147 return false; 1148 #else 1149 return false; 1150 #endif 1151 } 1152 1153 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1154 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1155 struct mt76_wcid *wcid, struct sk_buff *skb); 1156 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1157 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1158 bool send_bar); 1159 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1160 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1161 void mt76_txq_schedule_all(struct mt76_phy *phy); 1162 void mt76_tx_worker_run(struct mt76_dev *dev); 1163 void mt76_tx_worker(struct mt76_worker *w); 1164 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1165 struct ieee80211_sta *sta, 1166 u16 tids, int nframes, 1167 enum ieee80211_frame_release_type reason, 1168 bool more_data); 1169 bool mt76_has_tx_pending(struct mt76_phy *phy); 1170 void mt76_set_channel(struct mt76_phy *phy); 1171 void mt76_update_survey(struct mt76_phy *phy); 1172 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1173 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1174 struct survey_info *survey); 1175 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1176 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1177 1178 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1179 u16 ssn, u16 size); 1180 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1181 1182 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1183 struct ieee80211_key_conf *key); 1184 1185 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1186 __acquires(&dev->status_lock); 1187 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1188 __releases(&dev->status_lock); 1189 1190 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1191 struct sk_buff *skb); 1192 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1193 struct mt76_wcid *wcid, int pktid, 1194 struct sk_buff_head *list); 1195 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1196 struct sk_buff_head *list); 1197 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1198 struct list_head *free_list); 1199 static inline void 1200 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1201 { 1202 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1203 } 1204 1205 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1206 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1207 struct ieee80211_sta *sta, 1208 enum ieee80211_sta_state old_state, 1209 enum ieee80211_sta_state new_state); 1210 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1211 struct ieee80211_sta *sta); 1212 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1213 struct ieee80211_sta *sta); 1214 1215 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1216 1217 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1218 int *dbm); 1219 int mt76_init_sar_power(struct ieee80211_hw *hw, 1220 const struct cfg80211_sar_specs *sar); 1221 int mt76_get_sar_power(struct mt76_phy *phy, 1222 struct ieee80211_channel *chan, 1223 int power); 1224 1225 void mt76_csa_check(struct mt76_dev *dev); 1226 void mt76_csa_finish(struct mt76_dev *dev); 1227 1228 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1229 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1230 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1231 int mt76_get_rate(struct mt76_dev *dev, 1232 struct ieee80211_supported_band *sband, 1233 int idx, bool cck); 1234 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1235 const u8 *mac); 1236 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1237 struct ieee80211_vif *vif); 1238 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1239 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1240 void *data, int len); 1241 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1242 struct netlink_callback *cb, void *data, int len); 1243 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1244 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1245 1246 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1247 { 1248 #ifdef CONFIG_NL80211_TESTMODE 1249 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1250 1251 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1252 state = MT76_TM_STATE_OFF; 1253 1254 mt76_testmode_set_state(phy, state); 1255 #endif 1256 } 1257 1258 1259 /* internal */ 1260 static inline struct ieee80211_hw * 1261 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1262 { 1263 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1264 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1265 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1266 1267 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1268 1269 return hw; 1270 } 1271 1272 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1273 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1274 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1275 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1276 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1277 struct napi_struct *napi); 1278 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1279 struct napi_struct *napi); 1280 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1281 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1282 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1283 struct mt76_queue_entry *e); 1284 1285 /* usb */ 1286 static inline bool mt76u_urb_error(struct urb *urb) 1287 { 1288 return urb->status && 1289 urb->status != -ECONNRESET && 1290 urb->status != -ESHUTDOWN && 1291 urb->status != -ENOENT; 1292 } 1293 1294 /* Map hardware queues to usb endpoints */ 1295 static inline u8 q2ep(u8 qid) 1296 { 1297 /* TODO: take management packets to queue 5 */ 1298 return qid + 1; 1299 } 1300 1301 static inline int 1302 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1303 int timeout, int ep) 1304 { 1305 struct usb_interface *uintf = to_usb_interface(dev->dev); 1306 struct usb_device *udev = interface_to_usbdev(uintf); 1307 struct mt76_usb *usb = &dev->usb; 1308 unsigned int pipe; 1309 1310 if (actual_len) 1311 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1312 else 1313 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1314 1315 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1316 } 1317 1318 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1319 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1320 struct mt76_sta_stats *stats); 1321 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1322 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1323 u16 val, u16 offset, void *buf, size_t len); 1324 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1325 u8 req_type, u16 val, u16 offset, 1326 void *buf, size_t len); 1327 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1328 const u16 offset, const u32 val); 1329 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1330 void *data, int len); 1331 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1332 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1333 u32 addr, u32 val); 1334 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1335 struct mt76_bus_ops *ops); 1336 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1337 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1338 int mt76u_alloc_queues(struct mt76_dev *dev); 1339 void mt76u_stop_tx(struct mt76_dev *dev); 1340 void mt76u_stop_rx(struct mt76_dev *dev); 1341 int mt76u_resume_rx(struct mt76_dev *dev); 1342 void mt76u_queues_deinit(struct mt76_dev *dev); 1343 1344 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1345 const struct mt76_bus_ops *bus_ops); 1346 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1347 int mt76s_alloc_tx(struct mt76_dev *dev); 1348 void mt76s_deinit(struct mt76_dev *dev); 1349 void mt76s_sdio_irq(struct sdio_func *func); 1350 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1351 bool mt76s_txqs_empty(struct mt76_dev *dev); 1352 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1353 int hw_ver); 1354 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1355 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1356 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1357 u32 mt76s_read_pcr(struct mt76_dev *dev); 1358 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1359 const void *data, int len); 1360 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1361 void *data, int len); 1362 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1363 const struct mt76_reg_pair *data, 1364 int len); 1365 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1366 struct mt76_reg_pair *data, int len); 1367 1368 struct sk_buff * 1369 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1370 int len, int data_len, gfp_t gfp); 1371 static inline struct sk_buff * 1372 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1373 int data_len) 1374 { 1375 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1376 } 1377 1378 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1379 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1380 unsigned long expires); 1381 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1382 int len, bool wait_resp, struct sk_buff **ret); 1383 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1384 int cmd, bool wait_resp, struct sk_buff **ret); 1385 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1386 int len, int max_len); 1387 static inline int 1388 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1389 int len) 1390 { 1391 int max_len = 4096 - dev->mcu_ops->headroom; 1392 1393 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1394 } 1395 1396 static inline int 1397 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1398 bool wait_resp) 1399 { 1400 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1401 } 1402 1403 static inline int 1404 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1405 bool wait_resp) 1406 { 1407 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1408 } 1409 1410 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1411 1412 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1413 struct ieee80211_channel *chan, 1414 struct mt76_power_limits *dest, 1415 s8 target_power); 1416 1417 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1418 { 1419 return (q->flags & MT_QFLAG_WED) && 1420 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1421 } 1422 1423 struct mt76_txwi_cache * 1424 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1425 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1426 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1427 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1428 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1429 struct mt76_txwi_cache *r, dma_addr_t phys); 1430 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1431 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1432 { 1433 struct page *page = virt_to_head_page(buf); 1434 1435 page_pool_put_full_page(page->pp, page, allow_direct); 1436 } 1437 1438 static inline void * 1439 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1440 { 1441 struct page *page; 1442 1443 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1444 if (!page) 1445 return NULL; 1446 1447 return page_address(page) + *offset; 1448 } 1449 1450 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1451 { 1452 spin_lock_bh(&dev->token_lock); 1453 __mt76_set_tx_blocked(dev, blocked); 1454 spin_unlock_bh(&dev->token_lock); 1455 } 1456 1457 static inline int 1458 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1459 { 1460 int token; 1461 1462 spin_lock_bh(&dev->token_lock); 1463 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1464 spin_unlock_bh(&dev->token_lock); 1465 1466 return token; 1467 } 1468 1469 static inline struct mt76_txwi_cache * 1470 mt76_token_put(struct mt76_dev *dev, int token) 1471 { 1472 struct mt76_txwi_cache *txwi; 1473 1474 spin_lock_bh(&dev->token_lock); 1475 txwi = idr_remove(&dev->token, token); 1476 spin_unlock_bh(&dev->token_lock); 1477 1478 return txwi; 1479 } 1480 1481 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1482 { 1483 INIT_LIST_HEAD(&wcid->list); 1484 idr_init(&wcid->pktid); 1485 } 1486 1487 static inline void 1488 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1489 { 1490 struct sk_buff_head list; 1491 1492 mt76_tx_status_lock(dev, &list); 1493 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1494 mt76_tx_status_unlock(dev, &list); 1495 1496 idr_destroy(&wcid->pktid); 1497 } 1498 1499 #endif 1500