1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 #include "testmode.h" 19 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 #define MT_MAX_NON_AQL_PKT 16 25 #define MT_TXQ_FREE_THR 32 26 27 #define MT76_TOKEN_FREE_THR 64 28 29 struct mt76_dev; 30 struct mt76_phy; 31 struct mt76_wcid; 32 33 struct mt76_reg_pair { 34 u32 reg; 35 u32 value; 36 }; 37 38 enum mt76_bus_type { 39 MT76_BUS_MMIO, 40 MT76_BUS_USB, 41 MT76_BUS_SDIO, 42 }; 43 44 struct mt76_bus_ops { 45 u32 (*rr)(struct mt76_dev *dev, u32 offset); 46 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 47 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 48 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 49 int len); 50 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 51 int len); 52 int (*wr_rp)(struct mt76_dev *dev, u32 base, 53 const struct mt76_reg_pair *rp, int len); 54 int (*rd_rp)(struct mt76_dev *dev, u32 base, 55 struct mt76_reg_pair *rp, int len); 56 enum mt76_bus_type type; 57 }; 58 59 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 60 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 61 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 62 63 enum mt76_txq_id { 64 MT_TXQ_VO = IEEE80211_AC_VO, 65 MT_TXQ_VI = IEEE80211_AC_VI, 66 MT_TXQ_BE = IEEE80211_AC_BE, 67 MT_TXQ_BK = IEEE80211_AC_BK, 68 MT_TXQ_PSD, 69 MT_TXQ_BEACON, 70 MT_TXQ_CAB, 71 __MT_TXQ_MAX 72 }; 73 74 enum mt76_mcuq_id { 75 MT_MCUQ_WM, 76 MT_MCUQ_WA, 77 MT_MCUQ_FWDL, 78 __MT_MCUQ_MAX 79 }; 80 81 enum mt76_rxq_id { 82 MT_RXQ_MAIN, 83 MT_RXQ_MCU, 84 MT_RXQ_MCU_WA, 85 MT_RXQ_EXT, 86 MT_RXQ_EXT_WA, 87 __MT_RXQ_MAX 88 }; 89 90 struct mt76_queue_buf { 91 dma_addr_t addr; 92 u16 len; 93 bool skip_unmap; 94 }; 95 96 struct mt76_tx_info { 97 struct mt76_queue_buf buf[32]; 98 struct sk_buff *skb; 99 int nbuf; 100 u32 info; 101 }; 102 103 struct mt76_queue_entry { 104 union { 105 void *buf; 106 struct sk_buff *skb; 107 }; 108 union { 109 struct mt76_txwi_cache *txwi; 110 struct urb *urb; 111 int buf_sz; 112 }; 113 u32 dma_addr[2]; 114 u16 dma_len[2]; 115 u16 wcid; 116 bool skip_buf0:1; 117 bool skip_buf1:1; 118 bool done:1; 119 }; 120 121 struct mt76_queue_regs { 122 u32 desc_base; 123 u32 ring_size; 124 u32 cpu_idx; 125 u32 dma_idx; 126 } __packed __aligned(4); 127 128 struct mt76_queue { 129 struct mt76_queue_regs __iomem *regs; 130 131 spinlock_t lock; 132 spinlock_t cleanup_lock; 133 struct mt76_queue_entry *entry; 134 struct mt76_desc *desc; 135 136 u16 first; 137 u16 head; 138 u16 tail; 139 int ndesc; 140 int queued; 141 int buf_size; 142 bool stopped; 143 bool blocked; 144 145 u8 buf_offset; 146 u8 hw_idx; 147 u8 qid; 148 149 dma_addr_t desc_dma; 150 struct sk_buff *rx_head; 151 struct page_frag_cache rx_page; 152 }; 153 154 struct mt76_mcu_ops { 155 u32 headroom; 156 u32 tailroom; 157 158 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 159 int len, bool wait_resp); 160 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 161 int cmd, int *seq); 162 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 163 struct sk_buff *skb, int seq); 164 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 165 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 166 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 167 const struct mt76_reg_pair *rp, int len); 168 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 169 struct mt76_reg_pair *rp, int len); 170 int (*mcu_restart)(struct mt76_dev *dev); 171 }; 172 173 struct mt76_queue_ops { 174 int (*init)(struct mt76_dev *dev, 175 int (*poll)(struct napi_struct *napi, int budget)); 176 177 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 178 int idx, int n_desc, int bufsize, 179 u32 ring_base); 180 181 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 182 struct sk_buff *skb, struct mt76_wcid *wcid, 183 struct ieee80211_sta *sta); 184 185 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 186 struct sk_buff *skb, u32 tx_info); 187 188 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 189 int *len, u32 *info, bool *more); 190 191 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 192 193 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 194 bool flush); 195 196 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 197 198 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 199 200 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 201 }; 202 203 enum mt76_wcid_flags { 204 MT_WCID_FLAG_CHECK_PS, 205 MT_WCID_FLAG_PS, 206 MT_WCID_FLAG_4ADDR, 207 MT_WCID_FLAG_HDR_TRANS, 208 }; 209 210 #define MT76_N_WCIDS 288 211 212 /* stored in ieee80211_tx_info::hw_queue */ 213 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 214 215 DECLARE_EWMA(signal, 10, 8); 216 217 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 218 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 219 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 220 #define MT_WCID_TX_INFO_SET BIT(31) 221 222 struct mt76_wcid { 223 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 224 225 atomic_t non_aql_packets; 226 unsigned long flags; 227 228 struct ewma_signal rssi; 229 int inactive_count; 230 231 u16 idx; 232 u8 hw_key_idx; 233 u8 hw_key_idx2; 234 235 u8 sta:1; 236 u8 ext_phy:1; 237 u8 amsdu:1; 238 239 u8 rx_check_pn; 240 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 241 u16 cipher; 242 243 u32 tx_info; 244 bool sw_iv; 245 246 u8 packet_id; 247 }; 248 249 struct mt76_txq { 250 struct mt76_wcid *wcid; 251 252 u16 agg_ssn; 253 bool send_bar; 254 bool aggr; 255 }; 256 257 struct mt76_txwi_cache { 258 struct list_head list; 259 dma_addr_t dma_addr; 260 261 struct sk_buff *skb; 262 }; 263 264 struct mt76_rx_tid { 265 struct rcu_head rcu_head; 266 267 struct mt76_dev *dev; 268 269 spinlock_t lock; 270 struct delayed_work reorder_work; 271 272 u16 head; 273 u16 size; 274 u16 nframes; 275 276 u8 num; 277 278 u8 started:1, stopped:1, timer_pending:1; 279 280 struct sk_buff *reorder_buf[]; 281 }; 282 283 #define MT_TX_CB_DMA_DONE BIT(0) 284 #define MT_TX_CB_TXS_DONE BIT(1) 285 #define MT_TX_CB_TXS_FAILED BIT(2) 286 287 #define MT_PACKET_ID_MASK GENMASK(6, 0) 288 #define MT_PACKET_ID_NO_ACK 0 289 #define MT_PACKET_ID_NO_SKB 1 290 #define MT_PACKET_ID_FIRST 2 291 #define MT_PACKET_ID_HAS_RATE BIT(7) 292 293 #define MT_TX_STATUS_SKB_TIMEOUT HZ 294 295 struct mt76_tx_cb { 296 unsigned long jiffies; 297 u16 wcid; 298 u8 pktid; 299 u8 flags; 300 }; 301 302 enum { 303 MT76_STATE_INITIALIZED, 304 MT76_STATE_RUNNING, 305 MT76_STATE_MCU_RUNNING, 306 MT76_SCANNING, 307 MT76_HW_SCANNING, 308 MT76_HW_SCHED_SCANNING, 309 MT76_RESTART, 310 MT76_RESET, 311 MT76_MCU_RESET, 312 MT76_REMOVED, 313 MT76_READING_STATS, 314 MT76_STATE_POWER_OFF, 315 MT76_STATE_SUSPEND, 316 MT76_STATE_ROC, 317 MT76_STATE_PM, 318 }; 319 320 struct mt76_hw_cap { 321 bool has_2ghz; 322 bool has_5ghz; 323 }; 324 325 #define MT_DRV_TXWI_NO_FREE BIT(0) 326 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 327 #define MT_DRV_SW_RX_AIRTIME BIT(2) 328 #define MT_DRV_RX_DMA_HDR BIT(3) 329 #define MT_DRV_HW_MGMT_TXQ BIT(4) 330 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 331 332 struct mt76_driver_ops { 333 u32 drv_flags; 334 u32 survey_flags; 335 u16 txwi_size; 336 u16 token_size; 337 u8 mcs_rates; 338 339 void (*update_survey)(struct mt76_dev *dev); 340 341 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 342 enum mt76_txq_id qid, struct mt76_wcid *wcid, 343 struct ieee80211_sta *sta, 344 struct mt76_tx_info *tx_info); 345 346 void (*tx_complete_skb)(struct mt76_dev *dev, 347 struct mt76_queue_entry *e); 348 349 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 350 351 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 352 struct sk_buff *skb); 353 354 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 355 356 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 357 bool ps); 358 359 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 360 struct ieee80211_sta *sta); 361 362 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 363 struct ieee80211_sta *sta); 364 365 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 366 struct ieee80211_sta *sta); 367 }; 368 369 struct mt76_channel_state { 370 u64 cc_active; 371 u64 cc_busy; 372 u64 cc_rx; 373 u64 cc_bss_rx; 374 u64 cc_tx; 375 376 s8 noise; 377 }; 378 379 struct mt76_sband { 380 struct ieee80211_supported_band sband; 381 struct mt76_channel_state *chan; 382 }; 383 384 struct mt76_rate_power { 385 union { 386 struct { 387 s8 cck[4]; 388 s8 ofdm[8]; 389 s8 stbc[10]; 390 s8 ht[16]; 391 s8 vht[10]; 392 }; 393 s8 all[48]; 394 }; 395 }; 396 397 /* addr req mask */ 398 #define MT_VEND_TYPE_EEPROM BIT(31) 399 #define MT_VEND_TYPE_CFG BIT(30) 400 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 401 402 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 403 enum mt_vendor_req { 404 MT_VEND_DEV_MODE = 0x1, 405 MT_VEND_WRITE = 0x2, 406 MT_VEND_POWER_ON = 0x4, 407 MT_VEND_MULTI_WRITE = 0x6, 408 MT_VEND_MULTI_READ = 0x7, 409 MT_VEND_READ_EEPROM = 0x9, 410 MT_VEND_WRITE_FCE = 0x42, 411 MT_VEND_WRITE_CFG = 0x46, 412 MT_VEND_READ_CFG = 0x47, 413 MT_VEND_READ_EXT = 0x63, 414 MT_VEND_WRITE_EXT = 0x66, 415 MT_VEND_FEATURE_SET = 0x91, 416 }; 417 418 enum mt76u_in_ep { 419 MT_EP_IN_PKT_RX, 420 MT_EP_IN_CMD_RESP, 421 __MT_EP_IN_MAX, 422 }; 423 424 enum mt76u_out_ep { 425 MT_EP_OUT_INBAND_CMD, 426 MT_EP_OUT_AC_BE, 427 MT_EP_OUT_AC_BK, 428 MT_EP_OUT_AC_VI, 429 MT_EP_OUT_AC_VO, 430 MT_EP_OUT_HCCA, 431 __MT_EP_OUT_MAX, 432 }; 433 434 struct mt76_mcu { 435 struct mutex mutex; 436 u32 msg_seq; 437 int timeout; 438 439 struct sk_buff_head res_q; 440 wait_queue_head_t wait; 441 }; 442 443 #define MT_TX_SG_MAX_SIZE 8 444 #define MT_RX_SG_MAX_SIZE 4 445 #define MT_NUM_TX_ENTRIES 256 446 #define MT_NUM_RX_ENTRIES 128 447 #define MCU_RESP_URB_SIZE 1024 448 struct mt76_usb { 449 struct mutex usb_ctrl_mtx; 450 u8 *data; 451 u16 data_len; 452 453 struct mt76_worker status_worker; 454 struct mt76_worker rx_worker; 455 456 struct work_struct stat_work; 457 458 u8 out_ep[__MT_EP_OUT_MAX]; 459 u8 in_ep[__MT_EP_IN_MAX]; 460 bool sg_en; 461 462 struct mt76u_mcu { 463 u8 *data; 464 /* multiple reads */ 465 struct mt76_reg_pair *rp; 466 int rp_len; 467 u32 base; 468 bool burst; 469 } mcu; 470 }; 471 472 #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE) 473 struct mt76_sdio { 474 struct mt76_worker txrx_worker; 475 struct mt76_worker status_worker; 476 struct mt76_worker net_worker; 477 478 struct work_struct stat_work; 479 480 u8 *xmit_buf[IEEE80211_NUM_ACS + 2]; 481 482 struct sdio_func *func; 483 void *intr_data; 484 485 struct { 486 int pse_data_quota; 487 int ple_data_quota; 488 int pse_mcu_quota; 489 int deficit; 490 } sched; 491 }; 492 493 struct mt76_mmio { 494 void __iomem *regs; 495 spinlock_t irq_lock; 496 u32 irqmask; 497 }; 498 499 struct mt76_rx_status { 500 union { 501 struct mt76_wcid *wcid; 502 u16 wcid_idx; 503 }; 504 505 u32 reorder_time; 506 507 u32 ampdu_ref; 508 u32 timestamp; 509 510 u8 iv[6]; 511 512 u8 ext_phy:1; 513 u8 aggr:1; 514 u8 qos_ctl; 515 u16 seqno; 516 517 u16 freq; 518 u32 flag; 519 u8 enc_flags; 520 u8 encoding:2, bw:3, he_ru:3; 521 u8 he_gi:2, he_dcm:1; 522 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 523 u8 rate_idx; 524 u8 nss; 525 u8 band; 526 s8 signal; 527 u8 chains; 528 s8 chain_signal[IEEE80211_MAX_CHAINS]; 529 }; 530 531 struct mt76_testmode_ops { 532 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 533 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 534 enum mt76_testmode_state new_state); 535 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 536 }; 537 538 struct mt76_testmode_data { 539 enum mt76_testmode_state state; 540 541 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 542 struct sk_buff *tx_skb; 543 544 u32 tx_count; 545 u16 tx_mpdu_len; 546 547 u8 tx_rate_mode; 548 u8 tx_rate_idx; 549 u8 tx_rate_nss; 550 u8 tx_rate_sgi; 551 u8 tx_rate_ldpc; 552 u8 tx_rate_stbc; 553 u8 tx_ltf; 554 555 u8 tx_antenna_mask; 556 u8 tx_spe_idx; 557 558 u8 tx_duty_cycle; 559 u32 tx_time; 560 u32 tx_ipg; 561 562 u32 freq_offset; 563 564 u8 tx_power[4]; 565 u8 tx_power_control; 566 567 u32 tx_pending; 568 u32 tx_queued; 569 u16 tx_queued_limit; 570 u32 tx_done; 571 struct { 572 u64 packets[__MT_RXQ_MAX]; 573 u64 fcs_error[__MT_RXQ_MAX]; 574 } rx_stats; 575 }; 576 577 struct mt76_vif { 578 u8 idx; 579 u8 omac_idx; 580 u8 band_idx; 581 u8 wmm_idx; 582 u8 scan_seq_num; 583 }; 584 585 struct mt76_phy { 586 struct ieee80211_hw *hw; 587 struct mt76_dev *dev; 588 void *priv; 589 590 unsigned long state; 591 592 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 593 594 struct cfg80211_chan_def chandef; 595 struct ieee80211_channel *main_chan; 596 597 struct mt76_channel_state *chan_state; 598 ktime_t survey_time; 599 600 struct mt76_hw_cap cap; 601 struct mt76_sband sband_2g; 602 struct mt76_sband sband_5g; 603 604 u8 macaddr[ETH_ALEN]; 605 606 int txpower_cur; 607 u8 antenna_mask; 608 u16 chainmask; 609 610 #ifdef CONFIG_NL80211_TESTMODE 611 struct mt76_testmode_data test; 612 #endif 613 614 struct delayed_work mac_work; 615 u8 mac_work_count; 616 617 struct { 618 struct sk_buff *head; 619 struct sk_buff **tail; 620 u16 seqno; 621 } rx_amsdu[__MT_RXQ_MAX]; 622 }; 623 624 struct mt76_dev { 625 struct mt76_phy phy; /* must be first */ 626 627 struct mt76_phy *phy2; 628 629 struct ieee80211_hw *hw; 630 631 spinlock_t lock; 632 spinlock_t cc_lock; 633 634 u32 cur_cc_bss_rx; 635 636 struct mt76_rx_status rx_ampdu_status; 637 u32 rx_ampdu_len; 638 u32 rx_ampdu_ref; 639 640 struct mutex mutex; 641 642 const struct mt76_bus_ops *bus; 643 const struct mt76_driver_ops *drv; 644 const struct mt76_mcu_ops *mcu_ops; 645 struct device *dev; 646 647 struct mt76_mcu mcu; 648 649 struct net_device napi_dev; 650 struct net_device tx_napi_dev; 651 spinlock_t rx_lock; 652 struct napi_struct napi[__MT_RXQ_MAX]; 653 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 654 655 struct list_head txwi_cache; 656 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 657 struct mt76_queue q_rx[__MT_RXQ_MAX]; 658 const struct mt76_queue_ops *queue_ops; 659 int tx_dma_idx[4]; 660 661 struct mt76_worker tx_worker; 662 struct napi_struct tx_napi; 663 664 spinlock_t token_lock; 665 struct idr token; 666 int token_count; 667 668 wait_queue_head_t tx_wait; 669 struct sk_buff_head status_list; 670 671 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 672 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 673 674 u32 vif_mask; 675 676 struct mt76_wcid global_wcid; 677 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 678 679 u32 rev; 680 681 u32 aggr_stats[32]; 682 683 struct tasklet_struct pre_tbtt_tasklet; 684 int beacon_int; 685 u8 beacon_mask; 686 687 struct debugfs_blob_wrapper eeprom; 688 struct debugfs_blob_wrapper otp; 689 690 struct mt76_rate_power rate_power; 691 692 char alpha2[3]; 693 enum nl80211_dfs_regions region; 694 695 u32 debugfs_reg; 696 697 struct led_classdev led_cdev; 698 char led_name[32]; 699 bool led_al; 700 u8 led_pin; 701 702 u8 csa_complete; 703 704 u32 rxfilter; 705 706 #ifdef CONFIG_NL80211_TESTMODE 707 const struct mt76_testmode_ops *test_ops; 708 struct { 709 const char *name; 710 u32 offset; 711 } test_mtd; 712 #endif 713 struct workqueue_struct *wq; 714 715 union { 716 struct mt76_mmio mmio; 717 struct mt76_usb usb; 718 struct mt76_sdio sdio; 719 }; 720 }; 721 722 struct mt76_power_limits { 723 s8 cck[4]; 724 s8 ofdm[8]; 725 s8 mcs[4][10]; 726 s8 ru[7][12]; 727 }; 728 729 enum mt76_phy_type { 730 MT_PHY_TYPE_CCK, 731 MT_PHY_TYPE_OFDM, 732 MT_PHY_TYPE_HT, 733 MT_PHY_TYPE_HT_GF, 734 MT_PHY_TYPE_VHT, 735 MT_PHY_TYPE_HE_SU = 8, 736 MT_PHY_TYPE_HE_EXT_SU, 737 MT_PHY_TYPE_HE_TB, 738 MT_PHY_TYPE_HE_MU, 739 }; 740 741 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 742 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 743 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 744 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 745 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 746 747 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 748 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 749 750 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 751 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 752 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 753 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 754 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 755 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 756 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 757 758 759 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 760 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 761 762 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 763 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 764 765 #define mt76_get_field(_dev, _reg, _field) \ 766 FIELD_GET(_field, mt76_rr(dev, _reg)) 767 768 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 769 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 770 771 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 772 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 773 774 #define mt76_hw(dev) (dev)->mphy.hw 775 776 static inline struct ieee80211_hw * 777 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 778 { 779 if (wcid <= MT76_N_WCIDS && 780 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 781 return dev->phy2->hw; 782 783 return dev->phy.hw; 784 } 785 786 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 787 int timeout); 788 789 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 790 791 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 792 int timeout); 793 794 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 795 796 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 797 void mt76_pci_disable_aspm(struct pci_dev *pdev); 798 799 static inline u16 mt76_chip(struct mt76_dev *dev) 800 { 801 return dev->rev >> 16; 802 } 803 804 static inline u16 mt76_rev(struct mt76_dev *dev) 805 { 806 return dev->rev & 0xffff; 807 } 808 809 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 810 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 811 812 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 813 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 814 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 815 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 816 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 817 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 818 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 819 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 820 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 821 822 #define mt76_for_each_q_rx(dev, i) \ 823 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 824 (dev)->q_rx[i].ndesc; i++) 825 826 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 827 const struct ieee80211_ops *ops, 828 const struct mt76_driver_ops *drv_ops); 829 int mt76_register_device(struct mt76_dev *dev, bool vht, 830 struct ieee80211_rate *rates, int n_rates); 831 void mt76_unregister_device(struct mt76_dev *dev); 832 void mt76_free_device(struct mt76_dev *dev); 833 void mt76_unregister_phy(struct mt76_phy *phy); 834 835 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 836 const struct ieee80211_ops *ops); 837 int mt76_register_phy(struct mt76_phy *phy, bool vht, 838 struct ieee80211_rate *rates, int n_rates); 839 840 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 841 int mt76_queues_read(struct seq_file *s, void *data); 842 void mt76_seq_puts_array(struct seq_file *file, const char *str, 843 s8 *val, int len); 844 845 int mt76_eeprom_init(struct mt76_dev *dev, int len); 846 void mt76_eeprom_override(struct mt76_phy *phy); 847 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 848 849 struct mt76_queue * 850 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 851 int ring_base); 852 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 853 int n_desc, int ring_base) 854 { 855 struct mt76_queue *q; 856 857 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); 858 if (IS_ERR(q)) 859 return PTR_ERR(q); 860 861 q->qid = qid; 862 phy->q_tx[qid] = q; 863 864 return 0; 865 } 866 867 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 868 int n_desc, int ring_base) 869 { 870 struct mt76_queue *q; 871 872 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); 873 if (IS_ERR(q)) 874 return PTR_ERR(q); 875 876 q->qid = __MT_TXQ_MAX + qid; 877 dev->q_mcu[qid] = q; 878 879 return 0; 880 } 881 882 static inline struct mt76_phy * 883 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 884 { 885 if (phy_ext && dev->phy2) 886 return dev->phy2; 887 return &dev->phy; 888 } 889 890 static inline struct ieee80211_hw * 891 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 892 { 893 return mt76_dev_phy(dev, phy_ext)->hw; 894 } 895 896 static inline u8 * 897 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 898 { 899 return (u8 *)t - dev->drv->txwi_size; 900 } 901 902 /* increment with wrap-around */ 903 static inline int mt76_incr(int val, int size) 904 { 905 return (val + 1) & (size - 1); 906 } 907 908 /* decrement with wrap-around */ 909 static inline int mt76_decr(int val, int size) 910 { 911 return (val - 1) & (size - 1); 912 } 913 914 u8 mt76_ac_to_hwq(u8 ac); 915 916 static inline struct ieee80211_txq * 917 mtxq_to_txq(struct mt76_txq *mtxq) 918 { 919 void *ptr = mtxq; 920 921 return container_of(ptr, struct ieee80211_txq, drv_priv); 922 } 923 924 static inline struct ieee80211_sta * 925 wcid_to_sta(struct mt76_wcid *wcid) 926 { 927 void *ptr = wcid; 928 929 if (!wcid || !wcid->sta) 930 return NULL; 931 932 return container_of(ptr, struct ieee80211_sta, drv_priv); 933 } 934 935 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 936 { 937 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 938 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 939 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 940 } 941 942 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 943 { 944 struct mt76_rx_status mstat; 945 u8 *data = skb->data; 946 947 /* Alignment concerns */ 948 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 949 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 950 951 mstat = *((struct mt76_rx_status *)skb->cb); 952 953 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 954 data += sizeof(struct ieee80211_radiotap_he); 955 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 956 data += sizeof(struct ieee80211_radiotap_he_mu); 957 958 return data; 959 } 960 961 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 962 { 963 int len = ieee80211_get_hdrlen_from_skb(skb); 964 965 if (len % 4 == 0) 966 return; 967 968 skb_push(skb, 2); 969 memmove(skb->data, skb->data + 2, len); 970 971 skb->data[len] = 0; 972 skb->data[len + 1] = 0; 973 } 974 975 static inline bool mt76_is_skb_pktid(u8 pktid) 976 { 977 if (pktid & MT_PACKET_ID_HAS_RATE) 978 return false; 979 980 return pktid >= MT_PACKET_ID_FIRST; 981 } 982 983 static inline u8 mt76_tx_power_nss_delta(u8 nss) 984 { 985 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 986 987 return nss_delta[nss - 1]; 988 } 989 990 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 991 { 992 #ifdef CONFIG_NL80211_TESTMODE 993 return phy->test.state != MT76_TM_STATE_OFF; 994 #else 995 return false; 996 #endif 997 } 998 999 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1000 struct sk_buff *skb, 1001 struct ieee80211_hw **hw) 1002 { 1003 #ifdef CONFIG_NL80211_TESTMODE 1004 if (skb == dev->phy.test.tx_skb) 1005 *hw = dev->phy.hw; 1006 else if (dev->phy2 && skb == dev->phy2->test.tx_skb) 1007 *hw = dev->phy2->hw; 1008 else 1009 return false; 1010 return true; 1011 #else 1012 return false; 1013 #endif 1014 } 1015 1016 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1017 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1018 struct mt76_wcid *wcid, struct sk_buff *skb); 1019 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1020 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1021 bool send_bar); 1022 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1023 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1024 void mt76_txq_schedule_all(struct mt76_phy *phy); 1025 void mt76_tx_worker_run(struct mt76_dev *dev); 1026 void mt76_tx_worker(struct mt76_worker *w); 1027 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1028 struct ieee80211_sta *sta, 1029 u16 tids, int nframes, 1030 enum ieee80211_frame_release_type reason, 1031 bool more_data); 1032 bool mt76_has_tx_pending(struct mt76_phy *phy); 1033 void mt76_set_channel(struct mt76_phy *phy); 1034 void mt76_update_survey(struct mt76_dev *dev); 1035 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1036 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1037 struct survey_info *survey); 1038 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1039 1040 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1041 u16 ssn, u16 size); 1042 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1043 1044 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1045 struct ieee80211_key_conf *key); 1046 1047 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1048 __acquires(&dev->status_list.lock); 1049 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1050 __releases(&dev->status_list.lock); 1051 1052 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1053 struct sk_buff *skb); 1054 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1055 struct mt76_wcid *wcid, int pktid, 1056 struct sk_buff_head *list); 1057 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1058 struct sk_buff_head *list); 1059 void mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb); 1060 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 1061 bool flush); 1062 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1063 struct ieee80211_sta *sta, 1064 enum ieee80211_sta_state old_state, 1065 enum ieee80211_sta_state new_state); 1066 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1067 struct ieee80211_sta *sta); 1068 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1069 struct ieee80211_sta *sta); 1070 1071 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1072 1073 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1074 int *dbm); 1075 1076 void mt76_csa_check(struct mt76_dev *dev); 1077 void mt76_csa_finish(struct mt76_dev *dev); 1078 1079 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1080 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1081 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1082 int mt76_get_rate(struct mt76_dev *dev, 1083 struct ieee80211_supported_band *sband, 1084 int idx, bool cck); 1085 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1086 const u8 *mac); 1087 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1088 struct ieee80211_vif *vif); 1089 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1090 void *data, int len); 1091 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1092 struct netlink_callback *cb, void *data, int len); 1093 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1094 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1095 1096 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1097 { 1098 #ifdef CONFIG_NL80211_TESTMODE 1099 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1100 1101 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1102 state = MT76_TM_STATE_OFF; 1103 1104 mt76_testmode_set_state(phy, state); 1105 #endif 1106 } 1107 1108 1109 /* internal */ 1110 static inline struct ieee80211_hw * 1111 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1112 { 1113 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1114 struct ieee80211_hw *hw = dev->phy.hw; 1115 1116 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 1117 hw = dev->phy2->hw; 1118 1119 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 1120 1121 return hw; 1122 } 1123 1124 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1125 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1126 struct napi_struct *napi); 1127 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1128 struct napi_struct *napi); 1129 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1130 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1131 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1132 struct mt76_queue_entry *e); 1133 1134 /* usb */ 1135 static inline bool mt76u_urb_error(struct urb *urb) 1136 { 1137 return urb->status && 1138 urb->status != -ECONNRESET && 1139 urb->status != -ESHUTDOWN && 1140 urb->status != -ENOENT; 1141 } 1142 1143 /* Map hardware queues to usb endpoints */ 1144 static inline u8 q2ep(u8 qid) 1145 { 1146 /* TODO: take management packets to queue 5 */ 1147 return qid + 1; 1148 } 1149 1150 static inline int 1151 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1152 int timeout, int ep) 1153 { 1154 struct usb_interface *uintf = to_usb_interface(dev->dev); 1155 struct usb_device *udev = interface_to_usbdev(uintf); 1156 struct mt76_usb *usb = &dev->usb; 1157 unsigned int pipe; 1158 1159 if (actual_len) 1160 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1161 else 1162 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1163 1164 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1165 } 1166 1167 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1168 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1169 u8 req_type, u16 val, u16 offset, 1170 void *buf, size_t len); 1171 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1172 const u16 offset, const u32 val); 1173 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1174 bool ext); 1175 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1176 int mt76u_alloc_queues(struct mt76_dev *dev); 1177 void mt76u_stop_tx(struct mt76_dev *dev); 1178 void mt76u_stop_rx(struct mt76_dev *dev); 1179 int mt76u_resume_rx(struct mt76_dev *dev); 1180 void mt76u_queues_deinit(struct mt76_dev *dev); 1181 1182 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1183 const struct mt76_bus_ops *bus_ops); 1184 int mt76s_alloc_queues(struct mt76_dev *dev); 1185 void mt76s_deinit(struct mt76_dev *dev); 1186 1187 struct sk_buff * 1188 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1189 int data_len); 1190 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1191 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1192 unsigned long expires); 1193 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1194 int len, bool wait_resp, struct sk_buff **ret); 1195 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1196 int cmd, bool wait_resp, struct sk_buff **ret); 1197 int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1198 int len); 1199 static inline int 1200 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1201 bool wait_resp) 1202 { 1203 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1204 } 1205 1206 static inline int 1207 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1208 bool wait_resp) 1209 { 1210 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1211 } 1212 1213 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1214 1215 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1216 struct ieee80211_channel *chan, 1217 struct mt76_power_limits *dest, 1218 s8 target_power); 1219 1220 struct mt76_txwi_cache * 1221 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1222 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1223 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1224 1225 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1226 { 1227 spin_lock_bh(&dev->token_lock); 1228 __mt76_set_tx_blocked(dev, blocked); 1229 spin_unlock_bh(&dev->token_lock); 1230 } 1231 1232 static inline int 1233 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1234 { 1235 int token; 1236 1237 spin_lock_bh(&dev->token_lock); 1238 token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size, 1239 GFP_ATOMIC); 1240 spin_unlock_bh(&dev->token_lock); 1241 1242 return token; 1243 } 1244 1245 static inline struct mt76_txwi_cache * 1246 mt76_token_put(struct mt76_dev *dev, int token) 1247 { 1248 struct mt76_txwi_cache *txwi; 1249 1250 spin_lock_bh(&dev->token_lock); 1251 txwi = idr_remove(&dev->token, token); 1252 spin_unlock_bh(&dev->token_lock); 1253 1254 return txwi; 1255 } 1256 #endif 1257