1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 19 #define MT_TX_RING_SIZE 256 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 struct mt76_dev; 25 struct mt76_phy; 26 struct mt76_wcid; 27 28 struct mt76_reg_pair { 29 u32 reg; 30 u32 value; 31 }; 32 33 enum mt76_bus_type { 34 MT76_BUS_MMIO, 35 MT76_BUS_USB, 36 }; 37 38 struct mt76_bus_ops { 39 u32 (*rr)(struct mt76_dev *dev, u32 offset); 40 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 41 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 42 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 43 int len); 44 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 45 int len); 46 int (*wr_rp)(struct mt76_dev *dev, u32 base, 47 const struct mt76_reg_pair *rp, int len); 48 int (*rd_rp)(struct mt76_dev *dev, u32 base, 49 struct mt76_reg_pair *rp, int len); 50 enum mt76_bus_type type; 51 }; 52 53 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 54 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 55 56 enum mt76_txq_id { 57 MT_TXQ_VO = IEEE80211_AC_VO, 58 MT_TXQ_VI = IEEE80211_AC_VI, 59 MT_TXQ_BE = IEEE80211_AC_BE, 60 MT_TXQ_BK = IEEE80211_AC_BK, 61 MT_TXQ_PSD, 62 MT_TXQ_MCU, 63 MT_TXQ_MCU_WA, 64 MT_TXQ_BEACON, 65 MT_TXQ_CAB, 66 MT_TXQ_FWDL, 67 __MT_TXQ_MAX 68 }; 69 70 enum mt76_rxq_id { 71 MT_RXQ_MAIN, 72 MT_RXQ_MCU, 73 MT_RXQ_MCU_WA, 74 __MT_RXQ_MAX 75 }; 76 77 struct mt76_queue_buf { 78 dma_addr_t addr; 79 int len; 80 }; 81 82 struct mt76_tx_info { 83 struct mt76_queue_buf buf[32]; 84 struct sk_buff *skb; 85 int nbuf; 86 u32 info; 87 }; 88 89 struct mt76_queue_entry { 90 union { 91 void *buf; 92 struct sk_buff *skb; 93 }; 94 union { 95 struct mt76_txwi_cache *txwi; 96 struct urb *urb; 97 }; 98 enum mt76_txq_id qid; 99 bool skip_buf0:1; 100 bool schedule:1; 101 bool done:1; 102 }; 103 104 struct mt76_queue_regs { 105 u32 desc_base; 106 u32 ring_size; 107 u32 cpu_idx; 108 u32 dma_idx; 109 } __packed __aligned(4); 110 111 struct mt76_queue { 112 struct mt76_queue_regs __iomem *regs; 113 114 spinlock_t lock; 115 struct mt76_queue_entry *entry; 116 struct mt76_desc *desc; 117 118 u16 first; 119 u16 head; 120 u16 tail; 121 int ndesc; 122 int queued; 123 int buf_size; 124 bool stopped; 125 126 u8 buf_offset; 127 u8 hw_idx; 128 129 dma_addr_t desc_dma; 130 struct sk_buff *rx_head; 131 struct page_frag_cache rx_page; 132 }; 133 134 struct mt76_sw_queue { 135 struct mt76_queue *q; 136 137 struct list_head swq; 138 int swq_queued; 139 }; 140 141 struct mt76_mcu_ops { 142 u32 headroom; 143 u32 tailroom; 144 145 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 146 int len, bool wait_resp); 147 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 148 int cmd, bool wait_resp); 149 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 150 const struct mt76_reg_pair *rp, int len); 151 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 152 struct mt76_reg_pair *rp, int len); 153 int (*mcu_restart)(struct mt76_dev *dev); 154 }; 155 156 struct mt76_queue_ops { 157 int (*init)(struct mt76_dev *dev); 158 159 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 160 int idx, int n_desc, int bufsize, 161 u32 ring_base); 162 163 int (*tx_queue_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 164 struct sk_buff *skb, struct mt76_wcid *wcid, 165 struct ieee80211_sta *sta); 166 167 int (*tx_queue_skb_raw)(struct mt76_dev *dev, enum mt76_txq_id qid, 168 struct sk_buff *skb, u32 tx_info); 169 170 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 171 int *len, u32 *info, bool *more); 172 173 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 174 175 void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, 176 bool flush); 177 178 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 179 }; 180 181 enum mt76_wcid_flags { 182 MT_WCID_FLAG_CHECK_PS, 183 MT_WCID_FLAG_PS, 184 }; 185 186 #define MT76_N_WCIDS 288 187 188 /* stored in ieee80211_tx_info::hw_queue */ 189 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 190 191 DECLARE_EWMA(signal, 10, 8); 192 193 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 194 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 195 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 196 #define MT_WCID_TX_INFO_SET BIT(31) 197 198 struct mt76_wcid { 199 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 200 201 unsigned long flags; 202 203 struct ewma_signal rssi; 204 int inactive_count; 205 206 u16 idx; 207 u8 hw_key_idx; 208 209 u8 sta:1; 210 u8 ext_phy:1; 211 212 u8 rx_check_pn; 213 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 214 u16 cipher; 215 216 u32 tx_info; 217 bool sw_iv; 218 219 u8 packet_id; 220 }; 221 222 struct mt76_txq { 223 struct mt76_sw_queue *swq; 224 struct mt76_wcid *wcid; 225 226 struct sk_buff_head retry_q; 227 228 u16 agg_ssn; 229 bool send_bar; 230 bool aggr; 231 }; 232 233 struct mt76_txwi_cache { 234 struct list_head list; 235 dma_addr_t dma_addr; 236 237 struct sk_buff *skb; 238 }; 239 240 struct mt76_rx_tid { 241 struct rcu_head rcu_head; 242 243 struct mt76_dev *dev; 244 245 spinlock_t lock; 246 struct delayed_work reorder_work; 247 248 u16 head; 249 u16 size; 250 u16 nframes; 251 252 u8 num; 253 254 u8 started:1, stopped:1, timer_pending:1; 255 256 struct sk_buff *reorder_buf[]; 257 }; 258 259 #define MT_TX_CB_DMA_DONE BIT(0) 260 #define MT_TX_CB_TXS_DONE BIT(1) 261 #define MT_TX_CB_TXS_FAILED BIT(2) 262 263 #define MT_PACKET_ID_MASK GENMASK(6, 0) 264 #define MT_PACKET_ID_NO_ACK 0 265 #define MT_PACKET_ID_NO_SKB 1 266 #define MT_PACKET_ID_FIRST 2 267 #define MT_PACKET_ID_HAS_RATE BIT(7) 268 269 #define MT_TX_STATUS_SKB_TIMEOUT HZ 270 271 struct mt76_tx_cb { 272 unsigned long jiffies; 273 u16 wcid; 274 u8 pktid; 275 u8 flags; 276 }; 277 278 enum { 279 MT76_STATE_INITIALIZED, 280 MT76_STATE_RUNNING, 281 MT76_STATE_MCU_RUNNING, 282 MT76_SCANNING, 283 MT76_HW_SCANNING, 284 MT76_HW_SCHED_SCANNING, 285 MT76_RESTART, 286 MT76_RESET, 287 MT76_MCU_RESET, 288 MT76_REMOVED, 289 MT76_READING_STATS, 290 MT76_STATE_POWER_OFF, 291 MT76_STATE_SUSPEND, 292 MT76_STATE_ROC, 293 }; 294 295 struct mt76_hw_cap { 296 bool has_2ghz; 297 bool has_5ghz; 298 }; 299 300 #define MT_DRV_TXWI_NO_FREE BIT(0) 301 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 302 #define MT_DRV_SW_RX_AIRTIME BIT(2) 303 #define MT_DRV_RX_DMA_HDR BIT(3) 304 #define MT_DRV_HW_MGMT_TXQ BIT(4) 305 306 struct mt76_driver_ops { 307 u32 drv_flags; 308 u32 survey_flags; 309 u16 txwi_size; 310 311 void (*update_survey)(struct mt76_dev *dev); 312 313 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 314 enum mt76_txq_id qid, struct mt76_wcid *wcid, 315 struct ieee80211_sta *sta, 316 struct mt76_tx_info *tx_info); 317 318 void (*tx_complete_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 319 struct mt76_queue_entry *e); 320 321 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 322 323 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 324 struct sk_buff *skb); 325 326 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 327 328 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 329 bool ps); 330 331 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 332 struct ieee80211_sta *sta); 333 334 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 335 struct ieee80211_sta *sta); 336 337 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 338 struct ieee80211_sta *sta); 339 }; 340 341 struct mt76_channel_state { 342 u64 cc_active; 343 u64 cc_busy; 344 u64 cc_rx; 345 u64 cc_bss_rx; 346 u64 cc_tx; 347 348 s8 noise; 349 }; 350 351 struct mt76_sband { 352 struct ieee80211_supported_band sband; 353 struct mt76_channel_state *chan; 354 }; 355 356 struct mt76_rate_power { 357 union { 358 struct { 359 s8 cck[4]; 360 s8 ofdm[8]; 361 s8 stbc[10]; 362 s8 ht[16]; 363 s8 vht[10]; 364 }; 365 s8 all[48]; 366 }; 367 }; 368 369 /* addr req mask */ 370 #define MT_VEND_TYPE_EEPROM BIT(31) 371 #define MT_VEND_TYPE_CFG BIT(30) 372 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 373 374 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 375 enum mt_vendor_req { 376 MT_VEND_DEV_MODE = 0x1, 377 MT_VEND_WRITE = 0x2, 378 MT_VEND_POWER_ON = 0x4, 379 MT_VEND_MULTI_WRITE = 0x6, 380 MT_VEND_MULTI_READ = 0x7, 381 MT_VEND_READ_EEPROM = 0x9, 382 MT_VEND_WRITE_FCE = 0x42, 383 MT_VEND_WRITE_CFG = 0x46, 384 MT_VEND_READ_CFG = 0x47, 385 MT_VEND_READ_EXT = 0x63, 386 MT_VEND_WRITE_EXT = 0x66, 387 MT_VEND_FEATURE_SET = 0x91, 388 }; 389 390 enum mt76u_in_ep { 391 MT_EP_IN_PKT_RX, 392 MT_EP_IN_CMD_RESP, 393 __MT_EP_IN_MAX, 394 }; 395 396 enum mt76u_out_ep { 397 MT_EP_OUT_INBAND_CMD, 398 MT_EP_OUT_AC_BE, 399 MT_EP_OUT_AC_BK, 400 MT_EP_OUT_AC_VI, 401 MT_EP_OUT_AC_VO, 402 MT_EP_OUT_HCCA, 403 __MT_EP_OUT_MAX, 404 }; 405 406 struct mt76_mcu { 407 struct mutex mutex; 408 u32 msg_seq; 409 410 struct sk_buff_head res_q; 411 wait_queue_head_t wait; 412 }; 413 414 #define MT_TX_SG_MAX_SIZE 8 415 #define MT_RX_SG_MAX_SIZE 4 416 #define MT_NUM_TX_ENTRIES 256 417 #define MT_NUM_RX_ENTRIES 128 418 #define MCU_RESP_URB_SIZE 1024 419 struct mt76_usb { 420 struct mutex usb_ctrl_mtx; 421 u8 *data; 422 u16 data_len; 423 424 struct tasklet_struct rx_tasklet; 425 struct workqueue_struct *wq; 426 struct work_struct stat_work; 427 428 u8 out_ep[__MT_EP_OUT_MAX]; 429 u8 in_ep[__MT_EP_IN_MAX]; 430 bool sg_en; 431 432 struct mt76u_mcu { 433 u8 *data; 434 /* multiple reads */ 435 struct mt76_reg_pair *rp; 436 int rp_len; 437 u32 base; 438 bool burst; 439 } mcu; 440 }; 441 442 struct mt76_mmio { 443 void __iomem *regs; 444 spinlock_t irq_lock; 445 u32 irqmask; 446 }; 447 448 struct mt76_rx_status { 449 union { 450 struct mt76_wcid *wcid; 451 u16 wcid_idx; 452 }; 453 454 unsigned long reorder_time; 455 456 u32 ampdu_ref; 457 458 u8 iv[6]; 459 460 u8 ext_phy:1; 461 u8 aggr:1; 462 u8 tid; 463 u16 seqno; 464 465 u16 freq; 466 u32 flag; 467 u8 enc_flags; 468 u8 encoding:2, bw:3, he_ru:3; 469 u8 he_gi:2, he_dcm:1; 470 u8 rate_idx; 471 u8 nss; 472 u8 band; 473 s8 signal; 474 u8 chains; 475 s8 chain_signal[IEEE80211_MAX_CHAINS]; 476 }; 477 478 struct mt76_phy { 479 struct ieee80211_hw *hw; 480 struct mt76_dev *dev; 481 void *priv; 482 483 unsigned long state; 484 485 struct cfg80211_chan_def chandef; 486 struct ieee80211_channel *main_chan; 487 488 struct mt76_channel_state *chan_state; 489 ktime_t survey_time; 490 491 struct mt76_sband sband_2g; 492 struct mt76_sband sband_5g; 493 494 int txpower_cur; 495 u8 antenna_mask; 496 }; 497 498 struct mt76_dev { 499 struct mt76_phy phy; /* must be first */ 500 501 struct mt76_phy *phy2; 502 503 struct ieee80211_hw *hw; 504 505 spinlock_t lock; 506 spinlock_t cc_lock; 507 508 u32 cur_cc_bss_rx; 509 510 struct mt76_rx_status rx_ampdu_status; 511 u32 rx_ampdu_len; 512 u32 rx_ampdu_ref; 513 514 struct mutex mutex; 515 516 const struct mt76_bus_ops *bus; 517 const struct mt76_driver_ops *drv; 518 const struct mt76_mcu_ops *mcu_ops; 519 struct device *dev; 520 521 struct mt76_mcu mcu; 522 523 struct net_device napi_dev; 524 spinlock_t rx_lock; 525 struct napi_struct napi[__MT_RXQ_MAX]; 526 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 527 528 struct list_head txwi_cache; 529 struct mt76_sw_queue q_tx[2 * __MT_TXQ_MAX]; 530 struct mt76_queue q_rx[__MT_RXQ_MAX]; 531 const struct mt76_queue_ops *queue_ops; 532 int tx_dma_idx[4]; 533 534 struct tasklet_struct tx_tasklet; 535 struct napi_struct tx_napi; 536 struct delayed_work mac_work; 537 538 wait_queue_head_t tx_wait; 539 struct sk_buff_head status_list; 540 541 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 542 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 543 544 struct mt76_wcid global_wcid; 545 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 546 547 u8 macaddr[ETH_ALEN]; 548 u32 rev; 549 550 u32 aggr_stats[32]; 551 552 struct tasklet_struct pre_tbtt_tasklet; 553 int beacon_int; 554 u8 beacon_mask; 555 556 struct debugfs_blob_wrapper eeprom; 557 struct debugfs_blob_wrapper otp; 558 struct mt76_hw_cap cap; 559 560 struct mt76_rate_power rate_power; 561 562 enum nl80211_dfs_regions region; 563 564 u32 debugfs_reg; 565 566 struct led_classdev led_cdev; 567 char led_name[32]; 568 bool led_al; 569 u8 led_pin; 570 571 u8 csa_complete; 572 573 u32 rxfilter; 574 575 union { 576 struct mt76_mmio mmio; 577 struct mt76_usb usb; 578 }; 579 }; 580 581 enum mt76_phy_type { 582 MT_PHY_TYPE_CCK, 583 MT_PHY_TYPE_OFDM, 584 MT_PHY_TYPE_HT, 585 MT_PHY_TYPE_HT_GF, 586 MT_PHY_TYPE_VHT, 587 MT_PHY_TYPE_HE_SU = 8, 588 MT_PHY_TYPE_HE_EXT_SU, 589 MT_PHY_TYPE_HE_TB, 590 MT_PHY_TYPE_HE_MU, 591 }; 592 593 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 594 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 595 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 596 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 597 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 598 599 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 600 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 601 602 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 603 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 604 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 605 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 606 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 607 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 608 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 609 610 #define mt76_mcu_send_msg(dev, ...) (dev)->mt76.mcu_ops->mcu_send_msg(&((dev)->mt76), __VA_ARGS__) 611 612 #define __mt76_mcu_send_msg(dev, ...) (dev)->mcu_ops->mcu_send_msg((dev), __VA_ARGS__) 613 #define __mt76_mcu_skb_send_msg(dev, ...) (dev)->mcu_ops->mcu_skb_send_msg((dev), __VA_ARGS__) 614 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 615 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 616 617 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 618 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 619 620 #define mt76_get_field(_dev, _reg, _field) \ 621 FIELD_GET(_field, mt76_rr(dev, _reg)) 622 623 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 624 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 625 626 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 627 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 628 629 #define mt76_hw(dev) (dev)->mphy.hw 630 631 static inline struct ieee80211_hw * 632 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 633 { 634 if (wcid <= MT76_N_WCIDS && 635 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 636 return dev->phy2->hw; 637 638 return dev->phy.hw; 639 } 640 641 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 642 int timeout); 643 644 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 645 646 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 647 int timeout); 648 649 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 650 651 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 652 void mt76_pci_disable_aspm(struct pci_dev *pdev); 653 654 static inline u16 mt76_chip(struct mt76_dev *dev) 655 { 656 return dev->rev >> 16; 657 } 658 659 static inline u16 mt76_rev(struct mt76_dev *dev) 660 { 661 return dev->rev & 0xffff; 662 } 663 664 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 665 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 666 667 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 668 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 669 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 670 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 671 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 672 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 673 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 674 675 #define mt76_for_each_q_rx(dev, i) \ 676 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 677 (dev)->q_rx[i].ndesc; i++) 678 679 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 680 const struct ieee80211_ops *ops, 681 const struct mt76_driver_ops *drv_ops); 682 int mt76_register_device(struct mt76_dev *dev, bool vht, 683 struct ieee80211_rate *rates, int n_rates); 684 void mt76_unregister_device(struct mt76_dev *dev); 685 void mt76_free_device(struct mt76_dev *dev); 686 void mt76_unregister_phy(struct mt76_phy *phy); 687 688 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 689 const struct ieee80211_ops *ops); 690 int mt76_register_phy(struct mt76_phy *phy); 691 692 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 693 int mt76_queues_read(struct seq_file *s, void *data); 694 void mt76_seq_puts_array(struct seq_file *file, const char *str, 695 s8 *val, int len); 696 697 int mt76_eeprom_init(struct mt76_dev *dev, int len); 698 void mt76_eeprom_override(struct mt76_dev *dev); 699 700 static inline struct mt76_phy * 701 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 702 { 703 if (phy_ext && dev->phy2) 704 return dev->phy2; 705 return &dev->phy; 706 } 707 708 static inline struct ieee80211_hw * 709 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 710 { 711 return mt76_dev_phy(dev, phy_ext)->hw; 712 } 713 714 static inline u8 * 715 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 716 { 717 return (u8 *)t - dev->drv->txwi_size; 718 } 719 720 /* increment with wrap-around */ 721 static inline int mt76_incr(int val, int size) 722 { 723 return (val + 1) & (size - 1); 724 } 725 726 /* decrement with wrap-around */ 727 static inline int mt76_decr(int val, int size) 728 { 729 return (val - 1) & (size - 1); 730 } 731 732 u8 mt76_ac_to_hwq(u8 ac); 733 734 static inline struct ieee80211_txq * 735 mtxq_to_txq(struct mt76_txq *mtxq) 736 { 737 void *ptr = mtxq; 738 739 return container_of(ptr, struct ieee80211_txq, drv_priv); 740 } 741 742 static inline struct ieee80211_sta * 743 wcid_to_sta(struct mt76_wcid *wcid) 744 { 745 void *ptr = wcid; 746 747 if (!wcid || !wcid->sta) 748 return NULL; 749 750 return container_of(ptr, struct ieee80211_sta, drv_priv); 751 } 752 753 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 754 { 755 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 756 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 757 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 758 } 759 760 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 761 { 762 struct mt76_rx_status mstat; 763 u8 *data = skb->data; 764 765 /* Alignment concerns */ 766 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 767 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 768 769 mstat = *((struct mt76_rx_status *)skb->cb); 770 771 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 772 data += sizeof(struct ieee80211_radiotap_he); 773 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 774 data += sizeof(struct ieee80211_radiotap_he_mu); 775 776 return data; 777 } 778 779 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 780 { 781 int len = ieee80211_get_hdrlen_from_skb(skb); 782 783 if (len % 4 == 0) 784 return; 785 786 skb_push(skb, 2); 787 memmove(skb->data, skb->data + 2, len); 788 789 skb->data[len] = 0; 790 skb->data[len + 1] = 0; 791 } 792 793 static inline bool mt76_is_skb_pktid(u8 pktid) 794 { 795 if (pktid & MT_PACKET_ID_HAS_RATE) 796 return false; 797 798 return pktid >= MT_PACKET_ID_FIRST; 799 } 800 801 static inline u8 mt76_tx_power_nss_delta(u8 nss) 802 { 803 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 804 805 return nss_delta[nss - 1]; 806 } 807 808 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 809 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 810 struct mt76_wcid *wcid, struct sk_buff *skb); 811 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq); 812 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq); 813 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 814 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 815 bool send_bar); 816 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 817 void mt76_txq_schedule_all(struct mt76_phy *phy); 818 void mt76_tx_tasklet(unsigned long data); 819 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 820 struct ieee80211_sta *sta, 821 u16 tids, int nframes, 822 enum ieee80211_frame_release_type reason, 823 bool more_data); 824 bool mt76_has_tx_pending(struct mt76_phy *phy); 825 void mt76_set_channel(struct mt76_phy *phy); 826 void mt76_update_survey(struct mt76_dev *dev); 827 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 828 struct survey_info *survey); 829 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 830 831 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 832 u16 ssn, u16 size); 833 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 834 835 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 836 struct ieee80211_key_conf *key); 837 838 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 839 __acquires(&dev->status_list.lock); 840 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 841 __releases(&dev->status_list.lock); 842 843 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 844 struct sk_buff *skb); 845 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 846 struct mt76_wcid *wcid, int pktid, 847 struct sk_buff_head *list); 848 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 849 struct sk_buff_head *list); 850 void mt76_tx_complete_skb(struct mt76_dev *dev, struct sk_buff *skb); 851 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 852 bool flush); 853 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 854 struct ieee80211_sta *sta, 855 enum ieee80211_sta_state old_state, 856 enum ieee80211_sta_state new_state); 857 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 858 struct ieee80211_sta *sta); 859 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 860 struct ieee80211_sta *sta); 861 862 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 863 864 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 865 int *dbm); 866 867 void mt76_csa_check(struct mt76_dev *dev); 868 void mt76_csa_finish(struct mt76_dev *dev); 869 870 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 871 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 872 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 873 int mt76_get_rate(struct mt76_dev *dev, 874 struct ieee80211_supported_band *sband, 875 int idx, bool cck); 876 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 877 const u8 *mac); 878 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 879 struct ieee80211_vif *vif); 880 881 /* internal */ 882 static inline struct ieee80211_hw * 883 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 884 { 885 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 886 struct ieee80211_hw *hw = dev->phy.hw; 887 888 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 889 hw = dev->phy2->hw; 890 891 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 892 893 return hw; 894 } 895 896 void mt76_tx_free(struct mt76_dev *dev); 897 struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev); 898 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 899 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 900 struct napi_struct *napi); 901 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 902 struct napi_struct *napi); 903 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 904 905 /* usb */ 906 static inline bool mt76u_urb_error(struct urb *urb) 907 { 908 return urb->status && 909 urb->status != -ECONNRESET && 910 urb->status != -ESHUTDOWN && 911 urb->status != -ENOENT; 912 } 913 914 /* Map hardware queues to usb endpoints */ 915 static inline u8 q2ep(u8 qid) 916 { 917 /* TODO: take management packets to queue 5 */ 918 return qid + 1; 919 } 920 921 static inline int 922 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 923 int timeout, int ep) 924 { 925 struct usb_interface *uintf = to_usb_interface(dev->dev); 926 struct usb_device *udev = interface_to_usbdev(uintf); 927 struct mt76_usb *usb = &dev->usb; 928 unsigned int pipe; 929 930 if (actual_len) 931 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 932 else 933 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 934 935 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 936 } 937 938 int mt76u_skb_dma_info(struct sk_buff *skb, u32 info); 939 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 940 u8 req_type, u16 val, u16 offset, 941 void *buf, size_t len); 942 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 943 const u16 offset, const u32 val); 944 void mt76u_deinit(struct mt76_dev *dev); 945 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 946 bool ext); 947 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 948 int mt76u_alloc_queues(struct mt76_dev *dev); 949 void mt76u_stop_tx(struct mt76_dev *dev); 950 void mt76u_stop_rx(struct mt76_dev *dev); 951 int mt76u_resume_rx(struct mt76_dev *dev); 952 void mt76u_queues_deinit(struct mt76_dev *dev); 953 954 struct sk_buff * 955 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 956 int data_len); 957 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 958 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 959 unsigned long expires); 960 961 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 962 963 #endif 964