1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 MT_PHY_TYPE_EHT_SU = 13, 268 MT_PHY_TYPE_EHT_TRIG, 269 MT_PHY_TYPE_EHT_MU, 270 __MT_PHY_TYPE_MAX, 271 }; 272 273 struct mt76_sta_stats { 274 u64 tx_mode[__MT_PHY_TYPE_MAX]; 275 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 276 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 277 u64 tx_mcs[16]; /* mcs idx */ 278 u64 tx_bytes; 279 /* WED TX */ 280 u32 tx_packets; /* unit: MSDU */ 281 u32 tx_retries; 282 u32 tx_failed; 283 /* WED RX */ 284 u64 rx_bytes; 285 u32 rx_packets; 286 u32 rx_errors; 287 u32 rx_drops; 288 }; 289 290 enum mt76_wcid_flags { 291 MT_WCID_FLAG_CHECK_PS, 292 MT_WCID_FLAG_PS, 293 MT_WCID_FLAG_4ADDR, 294 MT_WCID_FLAG_HDR_TRANS, 295 }; 296 297 #define MT76_N_WCIDS 1088 298 299 /* stored in ieee80211_tx_info::hw_queue */ 300 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 301 302 DECLARE_EWMA(signal, 10, 8); 303 304 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 305 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 306 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 307 #define MT_WCID_TX_INFO_SET BIT(31) 308 309 struct mt76_wcid { 310 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 311 312 atomic_t non_aql_packets; 313 unsigned long flags; 314 315 struct ewma_signal rssi; 316 int inactive_count; 317 318 struct rate_info rate; 319 unsigned long ampdu_state; 320 321 u16 idx; 322 u8 hw_key_idx; 323 u8 hw_key_idx2; 324 325 u8 sta:1; 326 u8 amsdu:1; 327 u8 phy_idx:2; 328 329 u8 rx_check_pn; 330 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 331 u16 cipher; 332 333 u32 tx_info; 334 bool sw_iv; 335 336 struct list_head list; 337 struct idr pktid; 338 339 struct mt76_sta_stats stats; 340 341 struct list_head poll_list; 342 }; 343 344 struct mt76_txq { 345 u16 wcid; 346 347 u16 agg_ssn; 348 bool send_bar; 349 bool aggr; 350 }; 351 352 struct mt76_txwi_cache { 353 struct list_head list; 354 dma_addr_t dma_addr; 355 356 union { 357 struct sk_buff *skb; 358 void *ptr; 359 }; 360 }; 361 362 struct mt76_rx_tid { 363 struct rcu_head rcu_head; 364 365 struct mt76_dev *dev; 366 367 spinlock_t lock; 368 struct delayed_work reorder_work; 369 370 u16 head; 371 u16 size; 372 u16 nframes; 373 374 u8 num; 375 376 u8 started:1, stopped:1, timer_pending:1; 377 378 struct sk_buff *reorder_buf[]; 379 }; 380 381 #define MT_TX_CB_DMA_DONE BIT(0) 382 #define MT_TX_CB_TXS_DONE BIT(1) 383 #define MT_TX_CB_TXS_FAILED BIT(2) 384 385 #define MT_PACKET_ID_MASK GENMASK(6, 0) 386 #define MT_PACKET_ID_NO_ACK 0 387 #define MT_PACKET_ID_NO_SKB 1 388 #define MT_PACKET_ID_WED 2 389 #define MT_PACKET_ID_FIRST 3 390 #define MT_PACKET_ID_HAS_RATE BIT(7) 391 /* This is timer for when to give up when waiting for TXS callback, 392 * with starting time being the time at which the DMA_DONE callback 393 * was seen (so, we know packet was processed then, it should not take 394 * long after that for firmware to send the TXS callback if it is going 395 * to do so.) 396 */ 397 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 398 399 struct mt76_tx_cb { 400 unsigned long jiffies; 401 u16 wcid; 402 u8 pktid; 403 u8 flags; 404 }; 405 406 enum { 407 MT76_STATE_INITIALIZED, 408 MT76_STATE_REGISTERED, 409 MT76_STATE_RUNNING, 410 MT76_STATE_MCU_RUNNING, 411 MT76_SCANNING, 412 MT76_HW_SCANNING, 413 MT76_HW_SCHED_SCANNING, 414 MT76_RESTART, 415 MT76_RESET, 416 MT76_MCU_RESET, 417 MT76_REMOVED, 418 MT76_READING_STATS, 419 MT76_STATE_POWER_OFF, 420 MT76_STATE_SUSPEND, 421 MT76_STATE_ROC, 422 MT76_STATE_PM, 423 MT76_STATE_WED_RESET, 424 }; 425 426 struct mt76_hw_cap { 427 bool has_2ghz; 428 bool has_5ghz; 429 bool has_6ghz; 430 }; 431 432 #define MT_DRV_TXWI_NO_FREE BIT(0) 433 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 434 #define MT_DRV_SW_RX_AIRTIME BIT(2) 435 #define MT_DRV_RX_DMA_HDR BIT(3) 436 #define MT_DRV_HW_MGMT_TXQ BIT(4) 437 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 438 439 struct mt76_driver_ops { 440 u32 drv_flags; 441 u32 survey_flags; 442 u16 txwi_size; 443 u16 token_size; 444 u8 mcs_rates; 445 446 void (*update_survey)(struct mt76_phy *phy); 447 448 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 449 enum mt76_txq_id qid, struct mt76_wcid *wcid, 450 struct ieee80211_sta *sta, 451 struct mt76_tx_info *tx_info); 452 453 void (*tx_complete_skb)(struct mt76_dev *dev, 454 struct mt76_queue_entry *e); 455 456 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 457 458 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 459 460 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 461 struct sk_buff *skb, u32 *info); 462 463 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 464 465 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 466 bool ps); 467 468 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 469 struct ieee80211_sta *sta); 470 471 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 472 struct ieee80211_sta *sta); 473 474 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 475 struct ieee80211_sta *sta); 476 }; 477 478 struct mt76_channel_state { 479 u64 cc_active; 480 u64 cc_busy; 481 u64 cc_rx; 482 u64 cc_bss_rx; 483 u64 cc_tx; 484 485 s8 noise; 486 }; 487 488 struct mt76_sband { 489 struct ieee80211_supported_band sband; 490 struct mt76_channel_state *chan; 491 }; 492 493 /* addr req mask */ 494 #define MT_VEND_TYPE_EEPROM BIT(31) 495 #define MT_VEND_TYPE_CFG BIT(30) 496 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 497 498 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 499 enum mt_vendor_req { 500 MT_VEND_DEV_MODE = 0x1, 501 MT_VEND_WRITE = 0x2, 502 MT_VEND_POWER_ON = 0x4, 503 MT_VEND_MULTI_WRITE = 0x6, 504 MT_VEND_MULTI_READ = 0x7, 505 MT_VEND_READ_EEPROM = 0x9, 506 MT_VEND_WRITE_FCE = 0x42, 507 MT_VEND_WRITE_CFG = 0x46, 508 MT_VEND_READ_CFG = 0x47, 509 MT_VEND_READ_EXT = 0x63, 510 MT_VEND_WRITE_EXT = 0x66, 511 MT_VEND_FEATURE_SET = 0x91, 512 }; 513 514 enum mt76u_in_ep { 515 MT_EP_IN_PKT_RX, 516 MT_EP_IN_CMD_RESP, 517 __MT_EP_IN_MAX, 518 }; 519 520 enum mt76u_out_ep { 521 MT_EP_OUT_INBAND_CMD, 522 MT_EP_OUT_AC_BE, 523 MT_EP_OUT_AC_BK, 524 MT_EP_OUT_AC_VI, 525 MT_EP_OUT_AC_VO, 526 MT_EP_OUT_HCCA, 527 __MT_EP_OUT_MAX, 528 }; 529 530 struct mt76_mcu { 531 struct mutex mutex; 532 u32 msg_seq; 533 int timeout; 534 535 struct sk_buff_head res_q; 536 wait_queue_head_t wait; 537 }; 538 539 #define MT_TX_SG_MAX_SIZE 8 540 #define MT_RX_SG_MAX_SIZE 4 541 #define MT_NUM_TX_ENTRIES 256 542 #define MT_NUM_RX_ENTRIES 128 543 #define MCU_RESP_URB_SIZE 1024 544 struct mt76_usb { 545 struct mutex usb_ctrl_mtx; 546 u8 *data; 547 u16 data_len; 548 549 struct mt76_worker status_worker; 550 struct mt76_worker rx_worker; 551 552 struct work_struct stat_work; 553 554 u8 out_ep[__MT_EP_OUT_MAX]; 555 u8 in_ep[__MT_EP_IN_MAX]; 556 bool sg_en; 557 558 struct mt76u_mcu { 559 u8 *data; 560 /* multiple reads */ 561 struct mt76_reg_pair *rp; 562 int rp_len; 563 u32 base; 564 } mcu; 565 }; 566 567 #define MT76S_XMIT_BUF_SZ 0x3fe00 568 #define MT76S_NUM_TX_ENTRIES 256 569 #define MT76S_NUM_RX_ENTRIES 512 570 struct mt76_sdio { 571 struct mt76_worker txrx_worker; 572 struct mt76_worker status_worker; 573 struct mt76_worker net_worker; 574 575 struct work_struct stat_work; 576 577 u8 *xmit_buf; 578 u32 xmit_buf_sz; 579 580 struct sdio_func *func; 581 void *intr_data; 582 u8 hw_ver; 583 wait_queue_head_t wait; 584 585 struct { 586 int pse_data_quota; 587 int ple_data_quota; 588 int pse_mcu_quota; 589 int pse_page_size; 590 int deficit; 591 } sched; 592 593 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 594 }; 595 596 struct mt76_mmio { 597 void __iomem *regs; 598 spinlock_t irq_lock; 599 u32 irqmask; 600 601 struct mtk_wed_device wed; 602 struct completion wed_reset; 603 struct completion wed_reset_complete; 604 }; 605 606 struct mt76_rx_status { 607 union { 608 struct mt76_wcid *wcid; 609 u16 wcid_idx; 610 }; 611 612 u32 reorder_time; 613 614 u32 ampdu_ref; 615 u32 timestamp; 616 617 u8 iv[6]; 618 619 u8 phy_idx:2; 620 u8 aggr:1; 621 u8 qos_ctl; 622 u16 seqno; 623 624 u16 freq; 625 u32 flag; 626 u8 enc_flags; 627 u8 encoding:3, bw:4; 628 union { 629 struct { 630 u8 he_ru:3; 631 u8 he_gi:2; 632 u8 he_dcm:1; 633 }; 634 struct { 635 u8 ru:4; 636 u8 gi:2; 637 } eht; 638 }; 639 640 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 641 u8 rate_idx; 642 u8 nss:5, band:3; 643 s8 signal; 644 u8 chains; 645 s8 chain_signal[IEEE80211_MAX_CHAINS]; 646 }; 647 648 struct mt76_freq_range_power { 649 const struct cfg80211_sar_freq_ranges *range; 650 s8 power; 651 }; 652 653 struct mt76_testmode_ops { 654 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 655 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 656 enum mt76_testmode_state new_state); 657 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 658 }; 659 660 struct mt76_testmode_data { 661 enum mt76_testmode_state state; 662 663 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 664 struct sk_buff *tx_skb; 665 666 u32 tx_count; 667 u16 tx_mpdu_len; 668 669 u8 tx_rate_mode; 670 u8 tx_rate_idx; 671 u8 tx_rate_nss; 672 u8 tx_rate_sgi; 673 u8 tx_rate_ldpc; 674 u8 tx_rate_stbc; 675 u8 tx_ltf; 676 677 u8 tx_antenna_mask; 678 u8 tx_spe_idx; 679 680 u8 tx_duty_cycle; 681 u32 tx_time; 682 u32 tx_ipg; 683 684 u32 freq_offset; 685 686 u8 tx_power[4]; 687 u8 tx_power_control; 688 689 u8 addr[3][ETH_ALEN]; 690 691 u32 tx_pending; 692 u32 tx_queued; 693 u16 tx_queued_limit; 694 u32 tx_done; 695 struct { 696 u64 packets[__MT_RXQ_MAX]; 697 u64 fcs_error[__MT_RXQ_MAX]; 698 } rx_stats; 699 }; 700 701 struct mt76_vif { 702 u8 idx; 703 u8 omac_idx; 704 u8 band_idx; 705 u8 wmm_idx; 706 u8 scan_seq_num; 707 u8 cipher; 708 u8 basic_rates_idx; 709 u8 mcast_rates_idx; 710 u8 beacon_rates_idx; 711 }; 712 713 struct mt76_phy { 714 struct ieee80211_hw *hw; 715 struct mt76_dev *dev; 716 void *priv; 717 718 unsigned long state; 719 u8 band_idx; 720 721 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 722 723 struct cfg80211_chan_def chandef; 724 struct ieee80211_channel *main_chan; 725 726 struct mt76_channel_state *chan_state; 727 enum mt76_dfs_state dfs_state; 728 ktime_t survey_time; 729 730 u32 aggr_stats[32]; 731 732 struct mt76_hw_cap cap; 733 struct mt76_sband sband_2g; 734 struct mt76_sband sband_5g; 735 struct mt76_sband sband_6g; 736 737 u8 macaddr[ETH_ALEN]; 738 739 int txpower_cur; 740 u8 antenna_mask; 741 u16 chainmask; 742 743 #ifdef CONFIG_NL80211_TESTMODE 744 struct mt76_testmode_data test; 745 #endif 746 747 struct delayed_work mac_work; 748 u8 mac_work_count; 749 750 struct { 751 struct sk_buff *head; 752 struct sk_buff **tail; 753 u16 seqno; 754 } rx_amsdu[__MT_RXQ_MAX]; 755 756 struct mt76_freq_range_power *frp; 757 758 struct { 759 struct led_classdev cdev; 760 char name[32]; 761 bool al; 762 u8 pin; 763 } leds; 764 }; 765 766 struct mt76_dev { 767 struct mt76_phy phy; /* must be first */ 768 struct mt76_phy *phys[__MT_MAX_BAND]; 769 770 struct ieee80211_hw *hw; 771 772 spinlock_t wed_lock; 773 spinlock_t lock; 774 spinlock_t cc_lock; 775 776 u32 cur_cc_bss_rx; 777 778 struct mt76_rx_status rx_ampdu_status; 779 u32 rx_ampdu_len; 780 u32 rx_ampdu_ref; 781 782 struct mutex mutex; 783 784 const struct mt76_bus_ops *bus; 785 const struct mt76_driver_ops *drv; 786 const struct mt76_mcu_ops *mcu_ops; 787 struct device *dev; 788 struct device *dma_dev; 789 790 struct mt76_mcu mcu; 791 792 struct net_device napi_dev; 793 struct net_device tx_napi_dev; 794 spinlock_t rx_lock; 795 struct napi_struct napi[__MT_RXQ_MAX]; 796 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 797 struct tasklet_struct irq_tasklet; 798 799 struct list_head txwi_cache; 800 struct list_head rxwi_cache; 801 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 802 struct mt76_queue q_rx[__MT_RXQ_MAX]; 803 const struct mt76_queue_ops *queue_ops; 804 int tx_dma_idx[4]; 805 806 struct mt76_worker tx_worker; 807 struct napi_struct tx_napi; 808 809 spinlock_t token_lock; 810 struct idr token; 811 u16 wed_token_count; 812 u16 token_count; 813 u16 token_size; 814 815 spinlock_t rx_token_lock; 816 struct idr rx_token; 817 u16 rx_token_size; 818 819 wait_queue_head_t tx_wait; 820 /* spinclock used to protect wcid pktid linked list */ 821 spinlock_t status_lock; 822 823 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 824 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 825 826 u64 vif_mask; 827 828 struct mt76_wcid global_wcid; 829 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 830 struct list_head wcid_list; 831 832 struct list_head sta_poll_list; 833 spinlock_t sta_poll_lock; 834 835 u32 rev; 836 837 struct tasklet_struct pre_tbtt_tasklet; 838 int beacon_int; 839 u8 beacon_mask; 840 841 struct debugfs_blob_wrapper eeprom; 842 struct debugfs_blob_wrapper otp; 843 844 char alpha2[3]; 845 enum nl80211_dfs_regions region; 846 847 u32 debugfs_reg; 848 849 u8 csa_complete; 850 851 u32 rxfilter; 852 853 #ifdef CONFIG_NL80211_TESTMODE 854 const struct mt76_testmode_ops *test_ops; 855 struct { 856 const char *name; 857 u32 offset; 858 } test_mtd; 859 #endif 860 struct workqueue_struct *wq; 861 862 union { 863 struct mt76_mmio mmio; 864 struct mt76_usb usb; 865 struct mt76_sdio sdio; 866 }; 867 }; 868 869 /* per-phy stats. */ 870 struct mt76_mib_stats { 871 u32 ack_fail_cnt; 872 u32 fcs_err_cnt; 873 u32 rts_cnt; 874 u32 rts_retries_cnt; 875 u32 ba_miss_cnt; 876 u32 tx_bf_cnt; 877 u32 tx_mu_bf_cnt; 878 u32 tx_mu_mpdu_cnt; 879 u32 tx_mu_acked_mpdu_cnt; 880 u32 tx_su_acked_mpdu_cnt; 881 u32 tx_bf_ibf_ppdu_cnt; 882 u32 tx_bf_ebf_ppdu_cnt; 883 884 u32 tx_bf_rx_fb_all_cnt; 885 u32 tx_bf_rx_fb_eht_cnt; 886 u32 tx_bf_rx_fb_he_cnt; 887 u32 tx_bf_rx_fb_vht_cnt; 888 u32 tx_bf_rx_fb_ht_cnt; 889 890 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 891 u32 tx_bf_rx_fb_nc_cnt; 892 u32 tx_bf_rx_fb_nr_cnt; 893 u32 tx_bf_fb_cpl_cnt; 894 u32 tx_bf_fb_trig_cnt; 895 896 u32 tx_ampdu_cnt; 897 u32 tx_stop_q_empty_cnt; 898 u32 tx_mpdu_attempts_cnt; 899 u32 tx_mpdu_success_cnt; 900 u32 tx_pkt_ebf_cnt; 901 u32 tx_pkt_ibf_cnt; 902 903 u32 tx_rwp_fail_cnt; 904 u32 tx_rwp_need_cnt; 905 906 /* rx stats */ 907 u32 rx_fifo_full_cnt; 908 u32 channel_idle_cnt; 909 u32 primary_cca_busy_time; 910 u32 secondary_cca_busy_time; 911 u32 primary_energy_detect_time; 912 u32 cck_mdrdy_time; 913 u32 ofdm_mdrdy_time; 914 u32 green_mdrdy_time; 915 u32 rx_vector_mismatch_cnt; 916 u32 rx_delimiter_fail_cnt; 917 u32 rx_mrdy_cnt; 918 u32 rx_len_mismatch_cnt; 919 u32 rx_mpdu_cnt; 920 u32 rx_ampdu_cnt; 921 u32 rx_ampdu_bytes_cnt; 922 u32 rx_ampdu_valid_subframe_cnt; 923 u32 rx_ampdu_valid_subframe_bytes_cnt; 924 u32 rx_pfdrop_cnt; 925 u32 rx_vec_queue_overflow_drop_cnt; 926 u32 rx_ba_cnt; 927 928 u32 tx_amsdu[8]; 929 u32 tx_amsdu_cnt; 930 931 /* mcu_muru_stats */ 932 u32 dl_cck_cnt; 933 u32 dl_ofdm_cnt; 934 u32 dl_htmix_cnt; 935 u32 dl_htgf_cnt; 936 u32 dl_vht_su_cnt; 937 u32 dl_vht_2mu_cnt; 938 u32 dl_vht_3mu_cnt; 939 u32 dl_vht_4mu_cnt; 940 u32 dl_he_su_cnt; 941 u32 dl_he_ext_su_cnt; 942 u32 dl_he_2ru_cnt; 943 u32 dl_he_2mu_cnt; 944 u32 dl_he_3ru_cnt; 945 u32 dl_he_3mu_cnt; 946 u32 dl_he_4ru_cnt; 947 u32 dl_he_4mu_cnt; 948 u32 dl_he_5to8ru_cnt; 949 u32 dl_he_9to16ru_cnt; 950 u32 dl_he_gtr16ru_cnt; 951 952 u32 ul_hetrig_su_cnt; 953 u32 ul_hetrig_2ru_cnt; 954 u32 ul_hetrig_3ru_cnt; 955 u32 ul_hetrig_4ru_cnt; 956 u32 ul_hetrig_5to8ru_cnt; 957 u32 ul_hetrig_9to16ru_cnt; 958 u32 ul_hetrig_gtr16ru_cnt; 959 u32 ul_hetrig_2mu_cnt; 960 u32 ul_hetrig_3mu_cnt; 961 u32 ul_hetrig_4mu_cnt; 962 }; 963 964 struct mt76_power_limits { 965 s8 cck[4]; 966 s8 ofdm[8]; 967 s8 mcs[4][10]; 968 s8 ru[7][12]; 969 }; 970 971 struct mt76_ethtool_worker_info { 972 u64 *data; 973 int idx; 974 int initial_stat_idx; 975 int worker_stat_count; 976 int sta_count; 977 }; 978 979 #define CCK_RATE(_idx, _rate) { \ 980 .bitrate = _rate, \ 981 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 982 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 983 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 984 } 985 986 #define OFDM_RATE(_idx, _rate) { \ 987 .bitrate = _rate, \ 988 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 989 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 990 } 991 992 extern struct ieee80211_rate mt76_rates[12]; 993 994 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 995 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 996 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 997 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 998 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 999 1000 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1001 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1002 1003 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1004 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1005 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1006 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1007 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1008 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1009 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1010 1011 1012 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1013 1014 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1015 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1016 1017 #define mt76_get_field(_dev, _reg, _field) \ 1018 FIELD_GET(_field, mt76_rr(dev, _reg)) 1019 1020 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1021 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1022 1023 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1024 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1025 1026 #define mt76_hw(dev) (dev)->mphy.hw 1027 1028 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1029 int timeout); 1030 1031 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1032 1033 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1034 int timeout, int kick); 1035 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1036 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1037 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1038 1039 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1040 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1041 1042 static inline u16 mt76_chip(struct mt76_dev *dev) 1043 { 1044 return dev->rev >> 16; 1045 } 1046 1047 static inline u16 mt76_rev(struct mt76_dev *dev) 1048 { 1049 return dev->rev & 0xffff; 1050 } 1051 1052 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1053 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1054 1055 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1056 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1057 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1058 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 1059 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1060 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1061 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1062 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1063 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1064 1065 #define mt76_for_each_q_rx(dev, i) \ 1066 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1067 if ((dev)->q_rx[i].ndesc) 1068 1069 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1070 const struct ieee80211_ops *ops, 1071 const struct mt76_driver_ops *drv_ops); 1072 int mt76_register_device(struct mt76_dev *dev, bool vht, 1073 struct ieee80211_rate *rates, int n_rates); 1074 void mt76_unregister_device(struct mt76_dev *dev); 1075 void mt76_free_device(struct mt76_dev *dev); 1076 void mt76_unregister_phy(struct mt76_phy *phy); 1077 1078 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1079 const struct ieee80211_ops *ops, 1080 u8 band_idx); 1081 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1082 struct ieee80211_rate *rates, int n_rates); 1083 1084 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1085 const struct file_operations *ops); 1086 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1087 { 1088 return mt76_register_debugfs_fops(&dev->phy, NULL); 1089 } 1090 1091 int mt76_queues_read(struct seq_file *s, void *data); 1092 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1093 s8 *val, int len); 1094 1095 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1096 void mt76_eeprom_override(struct mt76_phy *phy); 1097 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 1098 1099 struct mt76_queue * 1100 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1101 int ring_base, u32 flags); 1102 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 1103 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1104 int n_desc, int ring_base, u32 flags) 1105 { 1106 struct mt76_queue *q; 1107 1108 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 1109 if (IS_ERR(q)) 1110 return PTR_ERR(q); 1111 1112 phy->q_tx[qid] = q; 1113 1114 return 0; 1115 } 1116 1117 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1118 int n_desc, int ring_base) 1119 { 1120 struct mt76_queue *q; 1121 1122 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1123 if (IS_ERR(q)) 1124 return PTR_ERR(q); 1125 1126 dev->q_mcu[qid] = q; 1127 1128 return 0; 1129 } 1130 1131 static inline struct mt76_phy * 1132 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1133 { 1134 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1135 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1136 return dev->phys[phy_idx]; 1137 1138 return &dev->phy; 1139 } 1140 1141 static inline struct ieee80211_hw * 1142 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1143 { 1144 return mt76_dev_phy(dev, phy_idx)->hw; 1145 } 1146 1147 static inline u8 * 1148 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1149 { 1150 return (u8 *)t - dev->drv->txwi_size; 1151 } 1152 1153 /* increment with wrap-around */ 1154 static inline int mt76_incr(int val, int size) 1155 { 1156 return (val + 1) & (size - 1); 1157 } 1158 1159 /* decrement with wrap-around */ 1160 static inline int mt76_decr(int val, int size) 1161 { 1162 return (val - 1) & (size - 1); 1163 } 1164 1165 u8 mt76_ac_to_hwq(u8 ac); 1166 1167 static inline struct ieee80211_txq * 1168 mtxq_to_txq(struct mt76_txq *mtxq) 1169 { 1170 void *ptr = mtxq; 1171 1172 return container_of(ptr, struct ieee80211_txq, drv_priv); 1173 } 1174 1175 static inline struct ieee80211_sta * 1176 wcid_to_sta(struct mt76_wcid *wcid) 1177 { 1178 void *ptr = wcid; 1179 1180 if (!wcid || !wcid->sta) 1181 return NULL; 1182 1183 return container_of(ptr, struct ieee80211_sta, drv_priv); 1184 } 1185 1186 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1187 { 1188 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1189 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1190 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1191 } 1192 1193 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1194 { 1195 struct mt76_rx_status mstat; 1196 u8 *data = skb->data; 1197 1198 /* Alignment concerns */ 1199 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1200 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1201 1202 mstat = *((struct mt76_rx_status *)skb->cb); 1203 1204 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1205 data += sizeof(struct ieee80211_radiotap_he); 1206 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1207 data += sizeof(struct ieee80211_radiotap_he_mu); 1208 1209 return data; 1210 } 1211 1212 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1213 { 1214 int len = ieee80211_get_hdrlen_from_skb(skb); 1215 1216 if (len % 4 == 0) 1217 return; 1218 1219 skb_push(skb, 2); 1220 memmove(skb->data, skb->data + 2, len); 1221 1222 skb->data[len] = 0; 1223 skb->data[len + 1] = 0; 1224 } 1225 1226 static inline bool mt76_is_skb_pktid(u8 pktid) 1227 { 1228 if (pktid & MT_PACKET_ID_HAS_RATE) 1229 return false; 1230 1231 return pktid >= MT_PACKET_ID_FIRST; 1232 } 1233 1234 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1235 { 1236 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1237 u8 idx = nss - 1; 1238 1239 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1240 } 1241 1242 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1243 { 1244 #ifdef CONFIG_NL80211_TESTMODE 1245 return phy->test.state != MT76_TM_STATE_OFF; 1246 #else 1247 return false; 1248 #endif 1249 } 1250 1251 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1252 struct sk_buff *skb, 1253 struct ieee80211_hw **hw) 1254 { 1255 #ifdef CONFIG_NL80211_TESTMODE 1256 int i; 1257 1258 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1259 struct mt76_phy *phy = dev->phys[i]; 1260 1261 if (phy && skb == phy->test.tx_skb) { 1262 *hw = dev->phys[i]->hw; 1263 return true; 1264 } 1265 } 1266 return false; 1267 #else 1268 return false; 1269 #endif 1270 } 1271 1272 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1273 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1274 struct mt76_wcid *wcid, struct sk_buff *skb); 1275 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1276 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1277 bool send_bar); 1278 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1279 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1280 void mt76_txq_schedule_all(struct mt76_phy *phy); 1281 void mt76_tx_worker_run(struct mt76_dev *dev); 1282 void mt76_tx_worker(struct mt76_worker *w); 1283 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1284 struct ieee80211_sta *sta, 1285 u16 tids, int nframes, 1286 enum ieee80211_frame_release_type reason, 1287 bool more_data); 1288 bool mt76_has_tx_pending(struct mt76_phy *phy); 1289 void mt76_set_channel(struct mt76_phy *phy); 1290 void mt76_update_survey(struct mt76_phy *phy); 1291 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1292 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1293 struct survey_info *survey); 1294 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1295 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1296 1297 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1298 u16 ssn, u16 size); 1299 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1300 1301 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1302 struct ieee80211_key_conf *key); 1303 1304 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1305 __acquires(&dev->status_lock); 1306 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1307 __releases(&dev->status_lock); 1308 1309 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1310 struct sk_buff *skb); 1311 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1312 struct mt76_wcid *wcid, int pktid, 1313 struct sk_buff_head *list); 1314 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1315 struct sk_buff_head *list); 1316 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1317 struct list_head *free_list); 1318 static inline void 1319 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1320 { 1321 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1322 } 1323 1324 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1325 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1326 struct ieee80211_sta *sta, 1327 enum ieee80211_sta_state old_state, 1328 enum ieee80211_sta_state new_state); 1329 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1330 struct ieee80211_sta *sta); 1331 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1332 struct ieee80211_sta *sta); 1333 1334 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1335 1336 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1337 int *dbm); 1338 int mt76_init_sar_power(struct ieee80211_hw *hw, 1339 const struct cfg80211_sar_specs *sar); 1340 int mt76_get_sar_power(struct mt76_phy *phy, 1341 struct ieee80211_channel *chan, 1342 int power); 1343 1344 void mt76_csa_check(struct mt76_dev *dev); 1345 void mt76_csa_finish(struct mt76_dev *dev); 1346 1347 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1348 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1349 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1350 int mt76_get_rate(struct mt76_dev *dev, 1351 struct ieee80211_supported_band *sband, 1352 int idx, bool cck); 1353 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1354 const u8 *mac); 1355 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1356 struct ieee80211_vif *vif); 1357 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1358 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1359 void *data, int len); 1360 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1361 struct netlink_callback *cb, void *data, int len); 1362 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1363 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1364 1365 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1366 { 1367 #ifdef CONFIG_NL80211_TESTMODE 1368 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1369 1370 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1371 state = MT76_TM_STATE_OFF; 1372 1373 mt76_testmode_set_state(phy, state); 1374 #endif 1375 } 1376 1377 1378 /* internal */ 1379 static inline struct ieee80211_hw * 1380 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1381 { 1382 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1383 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1384 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1385 1386 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1387 1388 return hw; 1389 } 1390 1391 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1392 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1393 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1394 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1395 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1396 struct napi_struct *napi); 1397 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1398 struct napi_struct *napi); 1399 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1400 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1401 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1402 struct mt76_queue_entry *e); 1403 1404 /* usb */ 1405 static inline bool mt76u_urb_error(struct urb *urb) 1406 { 1407 return urb->status && 1408 urb->status != -ECONNRESET && 1409 urb->status != -ESHUTDOWN && 1410 urb->status != -ENOENT; 1411 } 1412 1413 /* Map hardware queues to usb endpoints */ 1414 static inline u8 q2ep(u8 qid) 1415 { 1416 /* TODO: take management packets to queue 5 */ 1417 return qid + 1; 1418 } 1419 1420 static inline int 1421 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1422 int timeout, int ep) 1423 { 1424 struct usb_interface *uintf = to_usb_interface(dev->dev); 1425 struct usb_device *udev = interface_to_usbdev(uintf); 1426 struct mt76_usb *usb = &dev->usb; 1427 unsigned int pipe; 1428 1429 if (actual_len) 1430 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1431 else 1432 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1433 1434 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1435 } 1436 1437 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1438 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1439 struct mt76_sta_stats *stats, bool eht); 1440 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1441 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1442 u16 val, u16 offset, void *buf, size_t len); 1443 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1444 u8 req_type, u16 val, u16 offset, 1445 void *buf, size_t len); 1446 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1447 const u16 offset, const u32 val); 1448 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1449 void *data, int len); 1450 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1451 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1452 u32 addr, u32 val); 1453 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1454 struct mt76_bus_ops *ops); 1455 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1456 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1457 int mt76u_alloc_queues(struct mt76_dev *dev); 1458 void mt76u_stop_tx(struct mt76_dev *dev); 1459 void mt76u_stop_rx(struct mt76_dev *dev); 1460 int mt76u_resume_rx(struct mt76_dev *dev); 1461 void mt76u_queues_deinit(struct mt76_dev *dev); 1462 1463 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1464 const struct mt76_bus_ops *bus_ops); 1465 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1466 int mt76s_alloc_tx(struct mt76_dev *dev); 1467 void mt76s_deinit(struct mt76_dev *dev); 1468 void mt76s_sdio_irq(struct sdio_func *func); 1469 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1470 bool mt76s_txqs_empty(struct mt76_dev *dev); 1471 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1472 int hw_ver); 1473 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1474 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1475 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1476 u32 mt76s_read_pcr(struct mt76_dev *dev); 1477 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1478 const void *data, int len); 1479 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1480 void *data, int len); 1481 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1482 const struct mt76_reg_pair *data, 1483 int len); 1484 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1485 struct mt76_reg_pair *data, int len); 1486 1487 struct sk_buff * 1488 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1489 int len, int data_len, gfp_t gfp); 1490 static inline struct sk_buff * 1491 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1492 int data_len) 1493 { 1494 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1495 } 1496 1497 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1498 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1499 unsigned long expires); 1500 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1501 int len, bool wait_resp, struct sk_buff **ret); 1502 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1503 int cmd, bool wait_resp, struct sk_buff **ret); 1504 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1505 int len, int max_len); 1506 static inline int 1507 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1508 int len) 1509 { 1510 int max_len = 4096 - dev->mcu_ops->headroom; 1511 1512 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1513 } 1514 1515 static inline int 1516 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1517 bool wait_resp) 1518 { 1519 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1520 } 1521 1522 static inline int 1523 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1524 bool wait_resp) 1525 { 1526 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1527 } 1528 1529 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1530 1531 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1532 struct ieee80211_channel *chan, 1533 struct mt76_power_limits *dest, 1534 s8 target_power); 1535 1536 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1537 { 1538 return (q->flags & MT_QFLAG_WED) && 1539 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1540 } 1541 1542 struct mt76_txwi_cache * 1543 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1544 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1545 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1546 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1547 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1548 struct mt76_txwi_cache *r, dma_addr_t phys); 1549 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1550 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1551 { 1552 struct page *page = virt_to_head_page(buf); 1553 1554 page_pool_put_full_page(page->pp, page, allow_direct); 1555 } 1556 1557 static inline void * 1558 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1559 { 1560 struct page *page; 1561 1562 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1563 if (!page) 1564 return NULL; 1565 1566 return page_address(page) + *offset; 1567 } 1568 1569 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1570 { 1571 spin_lock_bh(&dev->token_lock); 1572 __mt76_set_tx_blocked(dev, blocked); 1573 spin_unlock_bh(&dev->token_lock); 1574 } 1575 1576 static inline int 1577 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1578 { 1579 int token; 1580 1581 spin_lock_bh(&dev->token_lock); 1582 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1583 spin_unlock_bh(&dev->token_lock); 1584 1585 return token; 1586 } 1587 1588 static inline struct mt76_txwi_cache * 1589 mt76_token_put(struct mt76_dev *dev, int token) 1590 { 1591 struct mt76_txwi_cache *txwi; 1592 1593 spin_lock_bh(&dev->token_lock); 1594 txwi = idr_remove(&dev->token, token); 1595 spin_unlock_bh(&dev->token_lock); 1596 1597 return txwi; 1598 } 1599 1600 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1601 { 1602 INIT_LIST_HEAD(&wcid->list); 1603 idr_init(&wcid->pktid); 1604 } 1605 1606 static inline void 1607 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1608 { 1609 struct sk_buff_head list; 1610 1611 mt76_tx_status_lock(dev, &list); 1612 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1613 mt76_tx_status_unlock(dev, &list); 1614 1615 idr_destroy(&wcid->pktid); 1616 } 1617 1618 #endif 1619