1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 39 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 40 41 struct mt76_dev; 42 struct mt76_phy; 43 struct mt76_wcid; 44 struct mt76s_intr; 45 46 struct mt76_reg_pair { 47 u32 reg; 48 u32 value; 49 }; 50 51 enum mt76_bus_type { 52 MT76_BUS_MMIO, 53 MT76_BUS_USB, 54 MT76_BUS_SDIO, 55 }; 56 57 enum mt76_wed_type { 58 MT76_WED_Q_TX, 59 MT76_WED_Q_TXFREE, 60 MT76_WED_Q_RX, 61 }; 62 63 struct mt76_bus_ops { 64 u32 (*rr)(struct mt76_dev *dev, u32 offset); 65 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 66 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 67 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 68 int len); 69 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 70 int len); 71 int (*wr_rp)(struct mt76_dev *dev, u32 base, 72 const struct mt76_reg_pair *rp, int len); 73 int (*rd_rp)(struct mt76_dev *dev, u32 base, 74 struct mt76_reg_pair *rp, int len); 75 enum mt76_bus_type type; 76 }; 77 78 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 79 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 80 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 81 82 enum mt76_txq_id { 83 MT_TXQ_VO = IEEE80211_AC_VO, 84 MT_TXQ_VI = IEEE80211_AC_VI, 85 MT_TXQ_BE = IEEE80211_AC_BE, 86 MT_TXQ_BK = IEEE80211_AC_BK, 87 MT_TXQ_PSD, 88 MT_TXQ_BEACON, 89 MT_TXQ_CAB, 90 __MT_TXQ_MAX 91 }; 92 93 enum mt76_mcuq_id { 94 MT_MCUQ_WM, 95 MT_MCUQ_WA, 96 MT_MCUQ_FWDL, 97 __MT_MCUQ_MAX 98 }; 99 100 enum mt76_rxq_id { 101 MT_RXQ_MAIN, 102 MT_RXQ_MCU, 103 MT_RXQ_MCU_WA, 104 MT_RXQ_BAND1, 105 MT_RXQ_BAND1_WA, 106 MT_RXQ_MAIN_WA, 107 MT_RXQ_BAND2, 108 MT_RXQ_BAND2_WA, 109 __MT_RXQ_MAX 110 }; 111 112 enum mt76_band_id { 113 MT_BAND0, 114 MT_BAND1, 115 MT_BAND2, 116 __MT_MAX_BAND 117 }; 118 119 enum mt76_cipher_type { 120 MT_CIPHER_NONE, 121 MT_CIPHER_WEP40, 122 MT_CIPHER_TKIP, 123 MT_CIPHER_TKIP_NO_MIC, 124 MT_CIPHER_AES_CCMP, 125 MT_CIPHER_WEP104, 126 MT_CIPHER_BIP_CMAC_128, 127 MT_CIPHER_WEP128, 128 MT_CIPHER_WAPI, 129 MT_CIPHER_CCMP_CCX, 130 MT_CIPHER_CCMP_256, 131 MT_CIPHER_GCMP, 132 MT_CIPHER_GCMP_256, 133 }; 134 135 enum mt76_dfs_state { 136 MT_DFS_STATE_UNKNOWN, 137 MT_DFS_STATE_DISABLED, 138 MT_DFS_STATE_CAC, 139 MT_DFS_STATE_ACTIVE, 140 }; 141 142 struct mt76_queue_buf { 143 dma_addr_t addr; 144 u16 len; 145 bool skip_unmap; 146 }; 147 148 struct mt76_tx_info { 149 struct mt76_queue_buf buf[32]; 150 struct sk_buff *skb; 151 int nbuf; 152 u32 info; 153 }; 154 155 struct mt76_queue_entry { 156 union { 157 void *buf; 158 struct sk_buff *skb; 159 }; 160 union { 161 struct mt76_txwi_cache *txwi; 162 struct urb *urb; 163 int buf_sz; 164 }; 165 u32 dma_addr[2]; 166 u16 dma_len[2]; 167 u16 wcid; 168 bool skip_buf0:1; 169 bool skip_buf1:1; 170 bool done:1; 171 }; 172 173 struct mt76_queue_regs { 174 u32 desc_base; 175 u32 ring_size; 176 u32 cpu_idx; 177 u32 dma_idx; 178 } __packed __aligned(4); 179 180 struct mt76_queue { 181 struct mt76_queue_regs __iomem *regs; 182 183 spinlock_t lock; 184 spinlock_t cleanup_lock; 185 struct mt76_queue_entry *entry; 186 struct mt76_desc *desc; 187 188 u16 first; 189 u16 head; 190 u16 tail; 191 int ndesc; 192 int queued; 193 int buf_size; 194 bool stopped; 195 bool blocked; 196 197 u8 buf_offset; 198 u8 hw_idx; 199 u8 flags; 200 201 u32 wed_regs; 202 203 dma_addr_t desc_dma; 204 struct sk_buff *rx_head; 205 struct page_pool *page_pool; 206 }; 207 208 struct mt76_mcu_ops { 209 u32 headroom; 210 u32 tailroom; 211 212 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 213 int len, bool wait_resp); 214 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 215 int cmd, int *seq); 216 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 217 struct sk_buff *skb, int seq); 218 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 219 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 220 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 221 const struct mt76_reg_pair *rp, int len); 222 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 223 struct mt76_reg_pair *rp, int len); 224 int (*mcu_restart)(struct mt76_dev *dev); 225 }; 226 227 struct mt76_queue_ops { 228 int (*init)(struct mt76_dev *dev, 229 int (*poll)(struct napi_struct *napi, int budget)); 230 231 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 232 int idx, int n_desc, int bufsize, 233 u32 ring_base); 234 235 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 236 enum mt76_txq_id qid, struct sk_buff *skb, 237 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 238 239 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 240 struct sk_buff *skb, u32 tx_info); 241 242 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 243 int *len, u32 *info, bool *more); 244 245 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 246 247 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 248 bool flush); 249 250 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 253 254 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 255 }; 256 257 enum mt76_phy_type { 258 MT_PHY_TYPE_CCK, 259 MT_PHY_TYPE_OFDM, 260 MT_PHY_TYPE_HT, 261 MT_PHY_TYPE_HT_GF, 262 MT_PHY_TYPE_VHT, 263 MT_PHY_TYPE_HE_SU = 8, 264 MT_PHY_TYPE_HE_EXT_SU, 265 MT_PHY_TYPE_HE_TB, 266 MT_PHY_TYPE_HE_MU, 267 __MT_PHY_TYPE_HE_MAX, 268 }; 269 270 struct mt76_sta_stats { 271 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 272 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 273 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 274 u64 tx_mcs[16]; /* mcs idx */ 275 u64 tx_bytes; 276 /* WED TX */ 277 u32 tx_packets; 278 u32 tx_retries; 279 u32 tx_failed; 280 /* WED RX */ 281 u64 rx_bytes; 282 u32 rx_packets; 283 u32 rx_errors; 284 u32 rx_drops; 285 }; 286 287 enum mt76_wcid_flags { 288 MT_WCID_FLAG_CHECK_PS, 289 MT_WCID_FLAG_PS, 290 MT_WCID_FLAG_4ADDR, 291 MT_WCID_FLAG_HDR_TRANS, 292 }; 293 294 #define MT76_N_WCIDS 544 295 296 /* stored in ieee80211_tx_info::hw_queue */ 297 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 298 299 DECLARE_EWMA(signal, 10, 8); 300 301 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 302 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 303 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 304 #define MT_WCID_TX_INFO_SET BIT(31) 305 306 struct mt76_wcid { 307 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 308 309 atomic_t non_aql_packets; 310 unsigned long flags; 311 312 struct ewma_signal rssi; 313 int inactive_count; 314 315 struct rate_info rate; 316 317 u16 idx; 318 u8 hw_key_idx; 319 u8 hw_key_idx2; 320 321 u8 sta:1; 322 u8 amsdu:1; 323 u8 phy_idx:2; 324 325 u8 rx_check_pn; 326 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 327 u16 cipher; 328 329 u32 tx_info; 330 bool sw_iv; 331 332 struct list_head list; 333 struct idr pktid; 334 335 struct mt76_sta_stats stats; 336 }; 337 338 struct mt76_txq { 339 u16 wcid; 340 341 u16 agg_ssn; 342 bool send_bar; 343 bool aggr; 344 }; 345 346 struct mt76_txwi_cache { 347 struct list_head list; 348 dma_addr_t dma_addr; 349 350 union { 351 struct sk_buff *skb; 352 void *ptr; 353 }; 354 }; 355 356 struct mt76_rx_tid { 357 struct rcu_head rcu_head; 358 359 struct mt76_dev *dev; 360 361 spinlock_t lock; 362 struct delayed_work reorder_work; 363 364 u16 head; 365 u16 size; 366 u16 nframes; 367 368 u8 num; 369 370 u8 started:1, stopped:1, timer_pending:1; 371 372 struct sk_buff *reorder_buf[]; 373 }; 374 375 #define MT_TX_CB_DMA_DONE BIT(0) 376 #define MT_TX_CB_TXS_DONE BIT(1) 377 #define MT_TX_CB_TXS_FAILED BIT(2) 378 379 #define MT_PACKET_ID_MASK GENMASK(6, 0) 380 #define MT_PACKET_ID_NO_ACK 0 381 #define MT_PACKET_ID_NO_SKB 1 382 #define MT_PACKET_ID_WED 2 383 #define MT_PACKET_ID_FIRST 3 384 #define MT_PACKET_ID_HAS_RATE BIT(7) 385 /* This is timer for when to give up when waiting for TXS callback, 386 * with starting time being the time at which the DMA_DONE callback 387 * was seen (so, we know packet was processed then, it should not take 388 * long after that for firmware to send the TXS callback if it is going 389 * to do so.) 390 */ 391 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 392 393 struct mt76_tx_cb { 394 unsigned long jiffies; 395 u16 wcid; 396 u8 pktid; 397 u8 flags; 398 }; 399 400 enum { 401 MT76_STATE_INITIALIZED, 402 MT76_STATE_RUNNING, 403 MT76_STATE_MCU_RUNNING, 404 MT76_SCANNING, 405 MT76_HW_SCANNING, 406 MT76_HW_SCHED_SCANNING, 407 MT76_RESTART, 408 MT76_RESET, 409 MT76_MCU_RESET, 410 MT76_REMOVED, 411 MT76_READING_STATS, 412 MT76_STATE_POWER_OFF, 413 MT76_STATE_SUSPEND, 414 MT76_STATE_ROC, 415 MT76_STATE_PM, 416 }; 417 418 struct mt76_hw_cap { 419 bool has_2ghz; 420 bool has_5ghz; 421 bool has_6ghz; 422 }; 423 424 #define MT_DRV_TXWI_NO_FREE BIT(0) 425 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 426 #define MT_DRV_SW_RX_AIRTIME BIT(2) 427 #define MT_DRV_RX_DMA_HDR BIT(3) 428 #define MT_DRV_HW_MGMT_TXQ BIT(4) 429 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 430 431 struct mt76_driver_ops { 432 u32 drv_flags; 433 u32 survey_flags; 434 u16 txwi_size; 435 u16 token_size; 436 u8 mcs_rates; 437 438 void (*update_survey)(struct mt76_phy *phy); 439 440 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 441 enum mt76_txq_id qid, struct mt76_wcid *wcid, 442 struct ieee80211_sta *sta, 443 struct mt76_tx_info *tx_info); 444 445 void (*tx_complete_skb)(struct mt76_dev *dev, 446 struct mt76_queue_entry *e); 447 448 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 449 450 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 451 452 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 453 struct sk_buff *skb, u32 *info); 454 455 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 456 457 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 458 bool ps); 459 460 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 461 struct ieee80211_sta *sta); 462 463 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 464 struct ieee80211_sta *sta); 465 466 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 467 struct ieee80211_sta *sta); 468 }; 469 470 struct mt76_channel_state { 471 u64 cc_active; 472 u64 cc_busy; 473 u64 cc_rx; 474 u64 cc_bss_rx; 475 u64 cc_tx; 476 477 s8 noise; 478 }; 479 480 struct mt76_sband { 481 struct ieee80211_supported_band sband; 482 struct mt76_channel_state *chan; 483 }; 484 485 /* addr req mask */ 486 #define MT_VEND_TYPE_EEPROM BIT(31) 487 #define MT_VEND_TYPE_CFG BIT(30) 488 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 489 490 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 491 enum mt_vendor_req { 492 MT_VEND_DEV_MODE = 0x1, 493 MT_VEND_WRITE = 0x2, 494 MT_VEND_POWER_ON = 0x4, 495 MT_VEND_MULTI_WRITE = 0x6, 496 MT_VEND_MULTI_READ = 0x7, 497 MT_VEND_READ_EEPROM = 0x9, 498 MT_VEND_WRITE_FCE = 0x42, 499 MT_VEND_WRITE_CFG = 0x46, 500 MT_VEND_READ_CFG = 0x47, 501 MT_VEND_READ_EXT = 0x63, 502 MT_VEND_WRITE_EXT = 0x66, 503 MT_VEND_FEATURE_SET = 0x91, 504 }; 505 506 enum mt76u_in_ep { 507 MT_EP_IN_PKT_RX, 508 MT_EP_IN_CMD_RESP, 509 __MT_EP_IN_MAX, 510 }; 511 512 enum mt76u_out_ep { 513 MT_EP_OUT_INBAND_CMD, 514 MT_EP_OUT_AC_BE, 515 MT_EP_OUT_AC_BK, 516 MT_EP_OUT_AC_VI, 517 MT_EP_OUT_AC_VO, 518 MT_EP_OUT_HCCA, 519 __MT_EP_OUT_MAX, 520 }; 521 522 struct mt76_mcu { 523 struct mutex mutex; 524 u32 msg_seq; 525 int timeout; 526 527 struct sk_buff_head res_q; 528 wait_queue_head_t wait; 529 }; 530 531 #define MT_TX_SG_MAX_SIZE 8 532 #define MT_RX_SG_MAX_SIZE 4 533 #define MT_NUM_TX_ENTRIES 256 534 #define MT_NUM_RX_ENTRIES 128 535 #define MCU_RESP_URB_SIZE 1024 536 struct mt76_usb { 537 struct mutex usb_ctrl_mtx; 538 u8 *data; 539 u16 data_len; 540 541 struct mt76_worker status_worker; 542 struct mt76_worker rx_worker; 543 544 struct work_struct stat_work; 545 546 u8 out_ep[__MT_EP_OUT_MAX]; 547 u8 in_ep[__MT_EP_IN_MAX]; 548 bool sg_en; 549 550 struct mt76u_mcu { 551 u8 *data; 552 /* multiple reads */ 553 struct mt76_reg_pair *rp; 554 int rp_len; 555 u32 base; 556 } mcu; 557 }; 558 559 #define MT76S_XMIT_BUF_SZ 0x3fe00 560 #define MT76S_NUM_TX_ENTRIES 256 561 #define MT76S_NUM_RX_ENTRIES 512 562 struct mt76_sdio { 563 struct mt76_worker txrx_worker; 564 struct mt76_worker status_worker; 565 struct mt76_worker net_worker; 566 567 struct work_struct stat_work; 568 569 u8 *xmit_buf; 570 u32 xmit_buf_sz; 571 572 struct sdio_func *func; 573 void *intr_data; 574 u8 hw_ver; 575 wait_queue_head_t wait; 576 577 struct { 578 int pse_data_quota; 579 int ple_data_quota; 580 int pse_mcu_quota; 581 int pse_page_size; 582 int deficit; 583 } sched; 584 585 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 586 }; 587 588 struct mt76_mmio { 589 void __iomem *regs; 590 spinlock_t irq_lock; 591 u32 irqmask; 592 593 struct mtk_wed_device wed; 594 }; 595 596 struct mt76_rx_status { 597 union { 598 struct mt76_wcid *wcid; 599 u16 wcid_idx; 600 }; 601 602 u32 reorder_time; 603 604 u32 ampdu_ref; 605 u32 timestamp; 606 607 u8 iv[6]; 608 609 u8 phy_idx:2; 610 u8 aggr:1; 611 u8 qos_ctl; 612 u16 seqno; 613 614 u16 freq; 615 u32 flag; 616 u8 enc_flags; 617 u8 encoding:2, bw:3, he_ru:3; 618 u8 he_gi:2, he_dcm:1; 619 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 620 u8 rate_idx; 621 u8 nss; 622 u8 band; 623 s8 signal; 624 u8 chains; 625 s8 chain_signal[IEEE80211_MAX_CHAINS]; 626 }; 627 628 struct mt76_freq_range_power { 629 const struct cfg80211_sar_freq_ranges *range; 630 s8 power; 631 }; 632 633 struct mt76_testmode_ops { 634 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 635 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 636 enum mt76_testmode_state new_state); 637 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 638 }; 639 640 struct mt76_testmode_data { 641 enum mt76_testmode_state state; 642 643 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 644 struct sk_buff *tx_skb; 645 646 u32 tx_count; 647 u16 tx_mpdu_len; 648 649 u8 tx_rate_mode; 650 u8 tx_rate_idx; 651 u8 tx_rate_nss; 652 u8 tx_rate_sgi; 653 u8 tx_rate_ldpc; 654 u8 tx_rate_stbc; 655 u8 tx_ltf; 656 657 u8 tx_antenna_mask; 658 u8 tx_spe_idx; 659 660 u8 tx_duty_cycle; 661 u32 tx_time; 662 u32 tx_ipg; 663 664 u32 freq_offset; 665 666 u8 tx_power[4]; 667 u8 tx_power_control; 668 669 u8 addr[3][ETH_ALEN]; 670 671 u32 tx_pending; 672 u32 tx_queued; 673 u16 tx_queued_limit; 674 u32 tx_done; 675 struct { 676 u64 packets[__MT_RXQ_MAX]; 677 u64 fcs_error[__MT_RXQ_MAX]; 678 } rx_stats; 679 }; 680 681 struct mt76_vif { 682 u8 idx; 683 u8 omac_idx; 684 u8 band_idx; 685 u8 wmm_idx; 686 u8 scan_seq_num; 687 u8 cipher; 688 }; 689 690 struct mt76_phy { 691 struct ieee80211_hw *hw; 692 struct mt76_dev *dev; 693 void *priv; 694 695 unsigned long state; 696 u8 band_idx; 697 698 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 699 700 struct cfg80211_chan_def chandef; 701 struct ieee80211_channel *main_chan; 702 703 struct mt76_channel_state *chan_state; 704 enum mt76_dfs_state dfs_state; 705 ktime_t survey_time; 706 707 u32 aggr_stats[32]; 708 709 struct mt76_hw_cap cap; 710 struct mt76_sband sband_2g; 711 struct mt76_sband sband_5g; 712 struct mt76_sband sband_6g; 713 714 u8 macaddr[ETH_ALEN]; 715 716 int txpower_cur; 717 u8 antenna_mask; 718 u16 chainmask; 719 720 #ifdef CONFIG_NL80211_TESTMODE 721 struct mt76_testmode_data test; 722 #endif 723 724 struct delayed_work mac_work; 725 u8 mac_work_count; 726 727 struct { 728 struct sk_buff *head; 729 struct sk_buff **tail; 730 u16 seqno; 731 } rx_amsdu[__MT_RXQ_MAX]; 732 733 struct mt76_freq_range_power *frp; 734 735 struct { 736 struct led_classdev cdev; 737 char name[32]; 738 bool al; 739 u8 pin; 740 } leds; 741 }; 742 743 struct mt76_dev { 744 struct mt76_phy phy; /* must be first */ 745 struct mt76_phy *phys[__MT_MAX_BAND]; 746 747 struct ieee80211_hw *hw; 748 749 spinlock_t wed_lock; 750 spinlock_t lock; 751 spinlock_t cc_lock; 752 753 u32 cur_cc_bss_rx; 754 755 struct mt76_rx_status rx_ampdu_status; 756 u32 rx_ampdu_len; 757 u32 rx_ampdu_ref; 758 759 struct mutex mutex; 760 761 const struct mt76_bus_ops *bus; 762 const struct mt76_driver_ops *drv; 763 const struct mt76_mcu_ops *mcu_ops; 764 struct device *dev; 765 struct device *dma_dev; 766 767 struct mt76_mcu mcu; 768 769 struct net_device napi_dev; 770 struct net_device tx_napi_dev; 771 spinlock_t rx_lock; 772 struct napi_struct napi[__MT_RXQ_MAX]; 773 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 774 775 struct list_head txwi_cache; 776 struct list_head rxwi_cache; 777 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 778 struct mt76_queue q_rx[__MT_RXQ_MAX]; 779 const struct mt76_queue_ops *queue_ops; 780 int tx_dma_idx[4]; 781 782 struct mt76_worker tx_worker; 783 struct napi_struct tx_napi; 784 785 spinlock_t token_lock; 786 struct idr token; 787 u16 wed_token_count; 788 u16 token_count; 789 u16 token_size; 790 791 spinlock_t rx_token_lock; 792 struct idr rx_token; 793 u16 rx_token_size; 794 795 wait_queue_head_t tx_wait; 796 /* spinclock used to protect wcid pktid linked list */ 797 spinlock_t status_lock; 798 799 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 800 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 801 802 u64 vif_mask; 803 804 struct mt76_wcid global_wcid; 805 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 806 struct list_head wcid_list; 807 808 u32 rev; 809 810 struct tasklet_struct pre_tbtt_tasklet; 811 int beacon_int; 812 u8 beacon_mask; 813 814 struct debugfs_blob_wrapper eeprom; 815 struct debugfs_blob_wrapper otp; 816 817 char alpha2[3]; 818 enum nl80211_dfs_regions region; 819 820 u32 debugfs_reg; 821 822 u8 csa_complete; 823 824 u32 rxfilter; 825 826 #ifdef CONFIG_NL80211_TESTMODE 827 const struct mt76_testmode_ops *test_ops; 828 struct { 829 const char *name; 830 u32 offset; 831 } test_mtd; 832 #endif 833 struct workqueue_struct *wq; 834 835 union { 836 struct mt76_mmio mmio; 837 struct mt76_usb usb; 838 struct mt76_sdio sdio; 839 }; 840 }; 841 842 struct mt76_power_limits { 843 s8 cck[4]; 844 s8 ofdm[8]; 845 s8 mcs[4][10]; 846 s8 ru[7][12]; 847 }; 848 849 struct mt76_ethtool_worker_info { 850 u64 *data; 851 int idx; 852 int initial_stat_idx; 853 int worker_stat_count; 854 int sta_count; 855 }; 856 857 #define CCK_RATE(_idx, _rate) { \ 858 .bitrate = _rate, \ 859 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 860 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 861 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 862 } 863 864 #define OFDM_RATE(_idx, _rate) { \ 865 .bitrate = _rate, \ 866 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 867 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 868 } 869 870 extern struct ieee80211_rate mt76_rates[12]; 871 872 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 873 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 874 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 875 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 876 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 877 878 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 879 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 880 881 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 882 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 883 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 884 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 885 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 886 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 887 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 888 889 890 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 891 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 892 893 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 894 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 895 896 #define mt76_get_field(_dev, _reg, _field) \ 897 FIELD_GET(_field, mt76_rr(dev, _reg)) 898 899 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 900 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 901 902 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 903 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 904 905 #define mt76_hw(dev) (dev)->mphy.hw 906 907 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 908 int timeout); 909 910 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 911 912 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 913 int timeout, int kick); 914 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 915 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 916 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 917 918 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 919 void mt76_pci_disable_aspm(struct pci_dev *pdev); 920 921 static inline u16 mt76_chip(struct mt76_dev *dev) 922 { 923 return dev->rev >> 16; 924 } 925 926 static inline u16 mt76_rev(struct mt76_dev *dev) 927 { 928 return dev->rev & 0xffff; 929 } 930 931 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 932 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 933 934 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 935 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 936 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 937 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 938 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 939 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 940 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 941 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 942 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 943 944 #define mt76_for_each_q_rx(dev, i) \ 945 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 946 if ((dev)->q_rx[i].ndesc) 947 948 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 949 const struct ieee80211_ops *ops, 950 const struct mt76_driver_ops *drv_ops); 951 int mt76_register_device(struct mt76_dev *dev, bool vht, 952 struct ieee80211_rate *rates, int n_rates); 953 void mt76_unregister_device(struct mt76_dev *dev); 954 void mt76_free_device(struct mt76_dev *dev); 955 void mt76_unregister_phy(struct mt76_phy *phy); 956 957 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 958 const struct ieee80211_ops *ops, 959 u8 band_idx); 960 int mt76_register_phy(struct mt76_phy *phy, bool vht, 961 struct ieee80211_rate *rates, int n_rates); 962 963 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 964 const struct file_operations *ops); 965 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 966 { 967 return mt76_register_debugfs_fops(&dev->phy, NULL); 968 } 969 970 int mt76_queues_read(struct seq_file *s, void *data); 971 void mt76_seq_puts_array(struct seq_file *file, const char *str, 972 s8 *val, int len); 973 974 int mt76_eeprom_init(struct mt76_dev *dev, int len); 975 void mt76_eeprom_override(struct mt76_phy *phy); 976 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 977 978 struct mt76_queue * 979 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 980 int ring_base, u32 flags); 981 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 982 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 983 int n_desc, int ring_base, u32 flags) 984 { 985 struct mt76_queue *q; 986 987 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 988 if (IS_ERR(q)) 989 return PTR_ERR(q); 990 991 phy->q_tx[qid] = q; 992 993 return 0; 994 } 995 996 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 997 int n_desc, int ring_base) 998 { 999 struct mt76_queue *q; 1000 1001 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1002 if (IS_ERR(q)) 1003 return PTR_ERR(q); 1004 1005 dev->q_mcu[qid] = q; 1006 1007 return 0; 1008 } 1009 1010 static inline struct mt76_phy * 1011 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1012 { 1013 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1014 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1015 return dev->phys[phy_idx]; 1016 1017 return &dev->phy; 1018 } 1019 1020 static inline struct ieee80211_hw * 1021 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1022 { 1023 return mt76_dev_phy(dev, phy_idx)->hw; 1024 } 1025 1026 static inline u8 * 1027 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1028 { 1029 return (u8 *)t - dev->drv->txwi_size; 1030 } 1031 1032 /* increment with wrap-around */ 1033 static inline int mt76_incr(int val, int size) 1034 { 1035 return (val + 1) & (size - 1); 1036 } 1037 1038 /* decrement with wrap-around */ 1039 static inline int mt76_decr(int val, int size) 1040 { 1041 return (val - 1) & (size - 1); 1042 } 1043 1044 u8 mt76_ac_to_hwq(u8 ac); 1045 1046 static inline struct ieee80211_txq * 1047 mtxq_to_txq(struct mt76_txq *mtxq) 1048 { 1049 void *ptr = mtxq; 1050 1051 return container_of(ptr, struct ieee80211_txq, drv_priv); 1052 } 1053 1054 static inline struct ieee80211_sta * 1055 wcid_to_sta(struct mt76_wcid *wcid) 1056 { 1057 void *ptr = wcid; 1058 1059 if (!wcid || !wcid->sta) 1060 return NULL; 1061 1062 return container_of(ptr, struct ieee80211_sta, drv_priv); 1063 } 1064 1065 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1066 { 1067 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1068 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1069 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1070 } 1071 1072 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1073 { 1074 struct mt76_rx_status mstat; 1075 u8 *data = skb->data; 1076 1077 /* Alignment concerns */ 1078 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1079 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1080 1081 mstat = *((struct mt76_rx_status *)skb->cb); 1082 1083 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1084 data += sizeof(struct ieee80211_radiotap_he); 1085 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1086 data += sizeof(struct ieee80211_radiotap_he_mu); 1087 1088 return data; 1089 } 1090 1091 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1092 { 1093 int len = ieee80211_get_hdrlen_from_skb(skb); 1094 1095 if (len % 4 == 0) 1096 return; 1097 1098 skb_push(skb, 2); 1099 memmove(skb->data, skb->data + 2, len); 1100 1101 skb->data[len] = 0; 1102 skb->data[len + 1] = 0; 1103 } 1104 1105 static inline bool mt76_is_skb_pktid(u8 pktid) 1106 { 1107 if (pktid & MT_PACKET_ID_HAS_RATE) 1108 return false; 1109 1110 return pktid >= MT_PACKET_ID_FIRST; 1111 } 1112 1113 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1114 { 1115 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1116 u8 idx = nss - 1; 1117 1118 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1119 } 1120 1121 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1122 { 1123 #ifdef CONFIG_NL80211_TESTMODE 1124 return phy->test.state != MT76_TM_STATE_OFF; 1125 #else 1126 return false; 1127 #endif 1128 } 1129 1130 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1131 struct sk_buff *skb, 1132 struct ieee80211_hw **hw) 1133 { 1134 #ifdef CONFIG_NL80211_TESTMODE 1135 int i; 1136 1137 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1138 struct mt76_phy *phy = dev->phys[i]; 1139 1140 if (phy && skb == phy->test.tx_skb) { 1141 *hw = dev->phys[i]->hw; 1142 return true; 1143 } 1144 } 1145 return false; 1146 #else 1147 return false; 1148 #endif 1149 } 1150 1151 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1152 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1153 struct mt76_wcid *wcid, struct sk_buff *skb); 1154 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1155 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1156 bool send_bar); 1157 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1158 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1159 void mt76_txq_schedule_all(struct mt76_phy *phy); 1160 void mt76_tx_worker_run(struct mt76_dev *dev); 1161 void mt76_tx_worker(struct mt76_worker *w); 1162 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1163 struct ieee80211_sta *sta, 1164 u16 tids, int nframes, 1165 enum ieee80211_frame_release_type reason, 1166 bool more_data); 1167 bool mt76_has_tx_pending(struct mt76_phy *phy); 1168 void mt76_set_channel(struct mt76_phy *phy); 1169 void mt76_update_survey(struct mt76_phy *phy); 1170 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1171 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1172 struct survey_info *survey); 1173 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1174 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1175 1176 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1177 u16 ssn, u16 size); 1178 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1179 1180 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1181 struct ieee80211_key_conf *key); 1182 1183 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1184 __acquires(&dev->status_lock); 1185 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1186 __releases(&dev->status_lock); 1187 1188 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1189 struct sk_buff *skb); 1190 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1191 struct mt76_wcid *wcid, int pktid, 1192 struct sk_buff_head *list); 1193 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1194 struct sk_buff_head *list); 1195 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1196 struct list_head *free_list); 1197 static inline void 1198 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1199 { 1200 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1201 } 1202 1203 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1204 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1205 struct ieee80211_sta *sta, 1206 enum ieee80211_sta_state old_state, 1207 enum ieee80211_sta_state new_state); 1208 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1209 struct ieee80211_sta *sta); 1210 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1211 struct ieee80211_sta *sta); 1212 1213 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1214 1215 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1216 int *dbm); 1217 int mt76_init_sar_power(struct ieee80211_hw *hw, 1218 const struct cfg80211_sar_specs *sar); 1219 int mt76_get_sar_power(struct mt76_phy *phy, 1220 struct ieee80211_channel *chan, 1221 int power); 1222 1223 void mt76_csa_check(struct mt76_dev *dev); 1224 void mt76_csa_finish(struct mt76_dev *dev); 1225 1226 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1227 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1228 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1229 int mt76_get_rate(struct mt76_dev *dev, 1230 struct ieee80211_supported_band *sband, 1231 int idx, bool cck); 1232 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1233 const u8 *mac); 1234 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1235 struct ieee80211_vif *vif); 1236 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1237 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1238 void *data, int len); 1239 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1240 struct netlink_callback *cb, void *data, int len); 1241 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1242 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1243 1244 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1245 { 1246 #ifdef CONFIG_NL80211_TESTMODE 1247 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1248 1249 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1250 state = MT76_TM_STATE_OFF; 1251 1252 mt76_testmode_set_state(phy, state); 1253 #endif 1254 } 1255 1256 1257 /* internal */ 1258 static inline struct ieee80211_hw * 1259 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1260 { 1261 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1262 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1263 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1264 1265 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1266 1267 return hw; 1268 } 1269 1270 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1271 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1272 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1273 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1274 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1275 struct napi_struct *napi); 1276 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1277 struct napi_struct *napi); 1278 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1279 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1280 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1281 struct mt76_queue_entry *e); 1282 1283 /* usb */ 1284 static inline bool mt76u_urb_error(struct urb *urb) 1285 { 1286 return urb->status && 1287 urb->status != -ECONNRESET && 1288 urb->status != -ESHUTDOWN && 1289 urb->status != -ENOENT; 1290 } 1291 1292 /* Map hardware queues to usb endpoints */ 1293 static inline u8 q2ep(u8 qid) 1294 { 1295 /* TODO: take management packets to queue 5 */ 1296 return qid + 1; 1297 } 1298 1299 static inline int 1300 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1301 int timeout, int ep) 1302 { 1303 struct usb_interface *uintf = to_usb_interface(dev->dev); 1304 struct usb_device *udev = interface_to_usbdev(uintf); 1305 struct mt76_usb *usb = &dev->usb; 1306 unsigned int pipe; 1307 1308 if (actual_len) 1309 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1310 else 1311 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1312 1313 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1314 } 1315 1316 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1317 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1318 struct mt76_sta_stats *stats); 1319 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1320 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1321 u16 val, u16 offset, void *buf, size_t len); 1322 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1323 u8 req_type, u16 val, u16 offset, 1324 void *buf, size_t len); 1325 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1326 const u16 offset, const u32 val); 1327 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1328 void *data, int len); 1329 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1330 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1331 u32 addr, u32 val); 1332 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1333 struct mt76_bus_ops *ops); 1334 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1335 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1336 int mt76u_alloc_queues(struct mt76_dev *dev); 1337 void mt76u_stop_tx(struct mt76_dev *dev); 1338 void mt76u_stop_rx(struct mt76_dev *dev); 1339 int mt76u_resume_rx(struct mt76_dev *dev); 1340 void mt76u_queues_deinit(struct mt76_dev *dev); 1341 1342 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1343 const struct mt76_bus_ops *bus_ops); 1344 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1345 int mt76s_alloc_tx(struct mt76_dev *dev); 1346 void mt76s_deinit(struct mt76_dev *dev); 1347 void mt76s_sdio_irq(struct sdio_func *func); 1348 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1349 bool mt76s_txqs_empty(struct mt76_dev *dev); 1350 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1351 int hw_ver); 1352 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1353 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1354 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1355 u32 mt76s_read_pcr(struct mt76_dev *dev); 1356 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1357 const void *data, int len); 1358 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1359 void *data, int len); 1360 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1361 const struct mt76_reg_pair *data, 1362 int len); 1363 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1364 struct mt76_reg_pair *data, int len); 1365 1366 struct sk_buff * 1367 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1368 int len, int data_len, gfp_t gfp); 1369 static inline struct sk_buff * 1370 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1371 int data_len) 1372 { 1373 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1374 } 1375 1376 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1377 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1378 unsigned long expires); 1379 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1380 int len, bool wait_resp, struct sk_buff **ret); 1381 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1382 int cmd, bool wait_resp, struct sk_buff **ret); 1383 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1384 int len, int max_len); 1385 static inline int 1386 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1387 int len) 1388 { 1389 int max_len = 4096 - dev->mcu_ops->headroom; 1390 1391 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1392 } 1393 1394 static inline int 1395 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1396 bool wait_resp) 1397 { 1398 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1399 } 1400 1401 static inline int 1402 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1403 bool wait_resp) 1404 { 1405 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1406 } 1407 1408 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1409 1410 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1411 struct ieee80211_channel *chan, 1412 struct mt76_power_limits *dest, 1413 s8 target_power); 1414 1415 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1416 { 1417 return (q->flags & MT_QFLAG_WED) && 1418 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1419 } 1420 1421 struct mt76_txwi_cache * 1422 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1423 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1424 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1425 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1426 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1427 struct mt76_txwi_cache *r, dma_addr_t phys); 1428 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1429 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1430 { 1431 struct page *page = virt_to_head_page(buf); 1432 1433 page_pool_put_full_page(page->pp, page, allow_direct); 1434 } 1435 1436 static inline void * 1437 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1438 { 1439 struct page *page; 1440 1441 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1442 if (!page) 1443 return NULL; 1444 1445 return page_address(page) + *offset; 1446 } 1447 1448 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1449 { 1450 spin_lock_bh(&dev->token_lock); 1451 __mt76_set_tx_blocked(dev, blocked); 1452 spin_unlock_bh(&dev->token_lock); 1453 } 1454 1455 static inline int 1456 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1457 { 1458 int token; 1459 1460 spin_lock_bh(&dev->token_lock); 1461 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1462 spin_unlock_bh(&dev->token_lock); 1463 1464 return token; 1465 } 1466 1467 static inline struct mt76_txwi_cache * 1468 mt76_token_put(struct mt76_dev *dev, int token) 1469 { 1470 struct mt76_txwi_cache *txwi; 1471 1472 spin_lock_bh(&dev->token_lock); 1473 txwi = idr_remove(&dev->token, token); 1474 spin_unlock_bh(&dev->token_lock); 1475 1476 return txwi; 1477 } 1478 1479 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1480 { 1481 INIT_LIST_HEAD(&wcid->list); 1482 idr_init(&wcid->pktid); 1483 } 1484 1485 static inline void 1486 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1487 { 1488 struct sk_buff_head list; 1489 1490 mt76_tx_status_lock(dev, &list); 1491 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1492 mt76_tx_status_unlock(dev, &list); 1493 1494 idr_destroy(&wcid->pktid); 1495 } 1496 1497 #endif 1498