1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #include <net/mac80211.h> 18 #include "util.h" 19 #include "testmode.h" 20 21 #define MT_MCU_RING_SIZE 32 22 #define MT_RX_BUF_SIZE 2048 23 #define MT_SKB_HEAD_LEN 256 24 25 #define MT_MAX_NON_AQL_PKT 16 26 #define MT_TXQ_FREE_THR 32 27 28 #define MT76_TOKEN_FREE_THR 64 29 30 #define MT_QFLAG_WED_RING GENMASK(1, 0) 31 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 32 #define MT_QFLAG_WED BIT(4) 33 34 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 35 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 36 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 37 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 38 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 39 40 struct mt76_dev; 41 struct mt76_phy; 42 struct mt76_wcid; 43 struct mt76s_intr; 44 45 struct mt76_reg_pair { 46 u32 reg; 47 u32 value; 48 }; 49 50 enum mt76_bus_type { 51 MT76_BUS_MMIO, 52 MT76_BUS_USB, 53 MT76_BUS_SDIO, 54 }; 55 56 enum mt76_wed_type { 57 MT76_WED_Q_TX, 58 MT76_WED_Q_TXFREE, 59 }; 60 61 struct mt76_bus_ops { 62 u32 (*rr)(struct mt76_dev *dev, u32 offset); 63 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 64 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 65 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 66 int len); 67 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 68 int len); 69 int (*wr_rp)(struct mt76_dev *dev, u32 base, 70 const struct mt76_reg_pair *rp, int len); 71 int (*rd_rp)(struct mt76_dev *dev, u32 base, 72 struct mt76_reg_pair *rp, int len); 73 enum mt76_bus_type type; 74 }; 75 76 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 77 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 78 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 79 80 enum mt76_txq_id { 81 MT_TXQ_VO = IEEE80211_AC_VO, 82 MT_TXQ_VI = IEEE80211_AC_VI, 83 MT_TXQ_BE = IEEE80211_AC_BE, 84 MT_TXQ_BK = IEEE80211_AC_BK, 85 MT_TXQ_PSD, 86 MT_TXQ_BEACON, 87 MT_TXQ_CAB, 88 __MT_TXQ_MAX 89 }; 90 91 enum mt76_mcuq_id { 92 MT_MCUQ_WM, 93 MT_MCUQ_WA, 94 MT_MCUQ_FWDL, 95 __MT_MCUQ_MAX 96 }; 97 98 enum mt76_rxq_id { 99 MT_RXQ_MAIN, 100 MT_RXQ_MCU, 101 MT_RXQ_MCU_WA, 102 MT_RXQ_BAND1, 103 MT_RXQ_BAND1_WA, 104 MT_RXQ_MAIN_WA, 105 MT_RXQ_BAND2, 106 MT_RXQ_BAND2_WA, 107 __MT_RXQ_MAX 108 }; 109 110 enum mt76_band_id { 111 MT_BAND0, 112 MT_BAND1, 113 MT_BAND2, 114 __MT_MAX_BAND 115 }; 116 117 enum mt76_cipher_type { 118 MT_CIPHER_NONE, 119 MT_CIPHER_WEP40, 120 MT_CIPHER_TKIP, 121 MT_CIPHER_TKIP_NO_MIC, 122 MT_CIPHER_AES_CCMP, 123 MT_CIPHER_WEP104, 124 MT_CIPHER_BIP_CMAC_128, 125 MT_CIPHER_WEP128, 126 MT_CIPHER_WAPI, 127 MT_CIPHER_CCMP_CCX, 128 MT_CIPHER_CCMP_256, 129 MT_CIPHER_GCMP, 130 MT_CIPHER_GCMP_256, 131 }; 132 133 enum mt76_dfs_state { 134 MT_DFS_STATE_UNKNOWN, 135 MT_DFS_STATE_DISABLED, 136 MT_DFS_STATE_CAC, 137 MT_DFS_STATE_ACTIVE, 138 }; 139 140 struct mt76_queue_buf { 141 dma_addr_t addr; 142 u16 len; 143 bool skip_unmap; 144 }; 145 146 struct mt76_tx_info { 147 struct mt76_queue_buf buf[32]; 148 struct sk_buff *skb; 149 int nbuf; 150 u32 info; 151 }; 152 153 struct mt76_queue_entry { 154 union { 155 void *buf; 156 struct sk_buff *skb; 157 }; 158 union { 159 struct mt76_txwi_cache *txwi; 160 struct urb *urb; 161 int buf_sz; 162 }; 163 u32 dma_addr[2]; 164 u16 dma_len[2]; 165 u16 wcid; 166 bool skip_buf0:1; 167 bool skip_buf1:1; 168 bool done:1; 169 }; 170 171 struct mt76_queue_regs { 172 u32 desc_base; 173 u32 ring_size; 174 u32 cpu_idx; 175 u32 dma_idx; 176 } __packed __aligned(4); 177 178 struct mt76_queue { 179 struct mt76_queue_regs __iomem *regs; 180 181 spinlock_t lock; 182 spinlock_t cleanup_lock; 183 struct mt76_queue_entry *entry; 184 struct mt76_desc *desc; 185 186 u16 first; 187 u16 head; 188 u16 tail; 189 int ndesc; 190 int queued; 191 int buf_size; 192 bool stopped; 193 bool blocked; 194 195 u8 buf_offset; 196 u8 hw_idx; 197 u8 flags; 198 199 u32 wed_regs; 200 201 dma_addr_t desc_dma; 202 struct sk_buff *rx_head; 203 struct page_frag_cache rx_page; 204 }; 205 206 struct mt76_mcu_ops { 207 u32 headroom; 208 u32 tailroom; 209 210 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 211 int len, bool wait_resp); 212 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 213 int cmd, int *seq); 214 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 215 struct sk_buff *skb, int seq); 216 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 217 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 218 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 219 const struct mt76_reg_pair *rp, int len); 220 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 221 struct mt76_reg_pair *rp, int len); 222 int (*mcu_restart)(struct mt76_dev *dev); 223 }; 224 225 struct mt76_queue_ops { 226 int (*init)(struct mt76_dev *dev, 227 int (*poll)(struct napi_struct *napi, int budget)); 228 229 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 230 int idx, int n_desc, int bufsize, 231 u32 ring_base); 232 233 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 234 enum mt76_txq_id qid, struct sk_buff *skb, 235 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 236 237 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 238 struct sk_buff *skb, u32 tx_info); 239 240 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 241 int *len, u32 *info, bool *more); 242 243 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 244 245 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 246 bool flush); 247 248 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 249 250 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 251 252 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 253 }; 254 255 enum mt76_wcid_flags { 256 MT_WCID_FLAG_CHECK_PS, 257 MT_WCID_FLAG_PS, 258 MT_WCID_FLAG_4ADDR, 259 MT_WCID_FLAG_HDR_TRANS, 260 }; 261 262 #define MT76_N_WCIDS 544 263 264 /* stored in ieee80211_tx_info::hw_queue */ 265 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 266 267 DECLARE_EWMA(signal, 10, 8); 268 269 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 270 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 271 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 272 #define MT_WCID_TX_INFO_SET BIT(31) 273 274 struct mt76_wcid { 275 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 276 277 atomic_t non_aql_packets; 278 unsigned long flags; 279 280 struct ewma_signal rssi; 281 int inactive_count; 282 283 struct rate_info rate; 284 285 u16 idx; 286 u8 hw_key_idx; 287 u8 hw_key_idx2; 288 289 u8 sta:1; 290 u8 amsdu:1; 291 u8 phy_idx:2; 292 293 u8 rx_check_pn; 294 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 295 u16 cipher; 296 297 u32 tx_info; 298 bool sw_iv; 299 300 struct list_head list; 301 struct idr pktid; 302 }; 303 304 struct mt76_txq { 305 u16 wcid; 306 307 u16 agg_ssn; 308 bool send_bar; 309 bool aggr; 310 }; 311 312 struct mt76_txwi_cache { 313 struct list_head list; 314 dma_addr_t dma_addr; 315 316 struct sk_buff *skb; 317 }; 318 319 struct mt76_rx_tid { 320 struct rcu_head rcu_head; 321 322 struct mt76_dev *dev; 323 324 spinlock_t lock; 325 struct delayed_work reorder_work; 326 327 u16 head; 328 u16 size; 329 u16 nframes; 330 331 u8 num; 332 333 u8 started:1, stopped:1, timer_pending:1; 334 335 struct sk_buff *reorder_buf[]; 336 }; 337 338 #define MT_TX_CB_DMA_DONE BIT(0) 339 #define MT_TX_CB_TXS_DONE BIT(1) 340 #define MT_TX_CB_TXS_FAILED BIT(2) 341 342 #define MT_PACKET_ID_MASK GENMASK(6, 0) 343 #define MT_PACKET_ID_NO_ACK 0 344 #define MT_PACKET_ID_NO_SKB 1 345 #define MT_PACKET_ID_FIRST 2 346 #define MT_PACKET_ID_HAS_RATE BIT(7) 347 /* This is timer for when to give up when waiting for TXS callback, 348 * with starting time being the time at which the DMA_DONE callback 349 * was seen (so, we know packet was processed then, it should not take 350 * long after that for firmware to send the TXS callback if it is going 351 * to do so.) 352 */ 353 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 354 355 struct mt76_tx_cb { 356 unsigned long jiffies; 357 u16 wcid; 358 u8 pktid; 359 u8 flags; 360 }; 361 362 enum { 363 MT76_STATE_INITIALIZED, 364 MT76_STATE_RUNNING, 365 MT76_STATE_MCU_RUNNING, 366 MT76_SCANNING, 367 MT76_HW_SCANNING, 368 MT76_HW_SCHED_SCANNING, 369 MT76_RESTART, 370 MT76_RESET, 371 MT76_MCU_RESET, 372 MT76_REMOVED, 373 MT76_READING_STATS, 374 MT76_STATE_POWER_OFF, 375 MT76_STATE_SUSPEND, 376 MT76_STATE_ROC, 377 MT76_STATE_PM, 378 }; 379 380 struct mt76_hw_cap { 381 bool has_2ghz; 382 bool has_5ghz; 383 bool has_6ghz; 384 }; 385 386 #define MT_DRV_TXWI_NO_FREE BIT(0) 387 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 388 #define MT_DRV_SW_RX_AIRTIME BIT(2) 389 #define MT_DRV_RX_DMA_HDR BIT(3) 390 #define MT_DRV_HW_MGMT_TXQ BIT(4) 391 392 struct mt76_driver_ops { 393 u32 drv_flags; 394 u32 survey_flags; 395 u16 txwi_size; 396 u16 token_size; 397 u8 mcs_rates; 398 399 void (*update_survey)(struct mt76_phy *phy); 400 401 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 402 enum mt76_txq_id qid, struct mt76_wcid *wcid, 403 struct ieee80211_sta *sta, 404 struct mt76_tx_info *tx_info); 405 406 void (*tx_complete_skb)(struct mt76_dev *dev, 407 struct mt76_queue_entry *e); 408 409 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 410 411 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 412 413 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 414 struct sk_buff *skb); 415 416 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 417 418 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 419 bool ps); 420 421 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 422 struct ieee80211_sta *sta); 423 424 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 425 struct ieee80211_sta *sta); 426 427 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 428 struct ieee80211_sta *sta); 429 }; 430 431 struct mt76_channel_state { 432 u64 cc_active; 433 u64 cc_busy; 434 u64 cc_rx; 435 u64 cc_bss_rx; 436 u64 cc_tx; 437 438 s8 noise; 439 }; 440 441 struct mt76_sband { 442 struct ieee80211_supported_band sband; 443 struct mt76_channel_state *chan; 444 }; 445 446 struct mt76_rate_power { 447 union { 448 struct { 449 s8 cck[4]; 450 s8 ofdm[8]; 451 s8 stbc[10]; 452 s8 ht[16]; 453 s8 vht[10]; 454 }; 455 s8 all[48]; 456 }; 457 }; 458 459 /* addr req mask */ 460 #define MT_VEND_TYPE_EEPROM BIT(31) 461 #define MT_VEND_TYPE_CFG BIT(30) 462 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 463 464 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 465 enum mt_vendor_req { 466 MT_VEND_DEV_MODE = 0x1, 467 MT_VEND_WRITE = 0x2, 468 MT_VEND_POWER_ON = 0x4, 469 MT_VEND_MULTI_WRITE = 0x6, 470 MT_VEND_MULTI_READ = 0x7, 471 MT_VEND_READ_EEPROM = 0x9, 472 MT_VEND_WRITE_FCE = 0x42, 473 MT_VEND_WRITE_CFG = 0x46, 474 MT_VEND_READ_CFG = 0x47, 475 MT_VEND_READ_EXT = 0x63, 476 MT_VEND_WRITE_EXT = 0x66, 477 MT_VEND_FEATURE_SET = 0x91, 478 }; 479 480 enum mt76u_in_ep { 481 MT_EP_IN_PKT_RX, 482 MT_EP_IN_CMD_RESP, 483 __MT_EP_IN_MAX, 484 }; 485 486 enum mt76u_out_ep { 487 MT_EP_OUT_INBAND_CMD, 488 MT_EP_OUT_AC_BE, 489 MT_EP_OUT_AC_BK, 490 MT_EP_OUT_AC_VI, 491 MT_EP_OUT_AC_VO, 492 MT_EP_OUT_HCCA, 493 __MT_EP_OUT_MAX, 494 }; 495 496 struct mt76_mcu { 497 struct mutex mutex; 498 u32 msg_seq; 499 int timeout; 500 501 struct sk_buff_head res_q; 502 wait_queue_head_t wait; 503 }; 504 505 #define MT_TX_SG_MAX_SIZE 8 506 #define MT_RX_SG_MAX_SIZE 4 507 #define MT_NUM_TX_ENTRIES 256 508 #define MT_NUM_RX_ENTRIES 128 509 #define MCU_RESP_URB_SIZE 1024 510 struct mt76_usb { 511 struct mutex usb_ctrl_mtx; 512 u8 *data; 513 u16 data_len; 514 515 struct mt76_worker status_worker; 516 struct mt76_worker rx_worker; 517 518 struct work_struct stat_work; 519 520 u8 out_ep[__MT_EP_OUT_MAX]; 521 u8 in_ep[__MT_EP_IN_MAX]; 522 bool sg_en; 523 524 struct mt76u_mcu { 525 u8 *data; 526 /* multiple reads */ 527 struct mt76_reg_pair *rp; 528 int rp_len; 529 u32 base; 530 bool burst; 531 } mcu; 532 }; 533 534 #define MT76S_XMIT_BUF_SZ 0x3fe00 535 #define MT76S_NUM_TX_ENTRIES 256 536 #define MT76S_NUM_RX_ENTRIES 512 537 struct mt76_sdio { 538 struct mt76_worker txrx_worker; 539 struct mt76_worker status_worker; 540 struct mt76_worker net_worker; 541 542 struct work_struct stat_work; 543 544 u8 *xmit_buf; 545 u32 xmit_buf_sz; 546 547 struct sdio_func *func; 548 void *intr_data; 549 u8 hw_ver; 550 wait_queue_head_t wait; 551 552 struct { 553 int pse_data_quota; 554 int ple_data_quota; 555 int pse_mcu_quota; 556 int pse_page_size; 557 int deficit; 558 } sched; 559 560 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 561 }; 562 563 struct mt76_mmio { 564 void __iomem *regs; 565 spinlock_t irq_lock; 566 u32 irqmask; 567 568 struct mtk_wed_device wed; 569 }; 570 571 struct mt76_rx_status { 572 union { 573 struct mt76_wcid *wcid; 574 u16 wcid_idx; 575 }; 576 577 u32 reorder_time; 578 579 u32 ampdu_ref; 580 u32 timestamp; 581 582 u8 iv[6]; 583 584 u8 phy_idx:2; 585 u8 aggr:1; 586 u8 qos_ctl; 587 u16 seqno; 588 589 u16 freq; 590 u32 flag; 591 u8 enc_flags; 592 u8 encoding:2, bw:3, he_ru:3; 593 u8 he_gi:2, he_dcm:1; 594 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 595 u8 rate_idx; 596 u8 nss; 597 u8 band; 598 s8 signal; 599 u8 chains; 600 s8 chain_signal[IEEE80211_MAX_CHAINS]; 601 }; 602 603 struct mt76_freq_range_power { 604 const struct cfg80211_sar_freq_ranges *range; 605 s8 power; 606 }; 607 608 struct mt76_testmode_ops { 609 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 610 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 611 enum mt76_testmode_state new_state); 612 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 613 }; 614 615 struct mt76_testmode_data { 616 enum mt76_testmode_state state; 617 618 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 619 struct sk_buff *tx_skb; 620 621 u32 tx_count; 622 u16 tx_mpdu_len; 623 624 u8 tx_rate_mode; 625 u8 tx_rate_idx; 626 u8 tx_rate_nss; 627 u8 tx_rate_sgi; 628 u8 tx_rate_ldpc; 629 u8 tx_rate_stbc; 630 u8 tx_ltf; 631 632 u8 tx_antenna_mask; 633 u8 tx_spe_idx; 634 635 u8 tx_duty_cycle; 636 u32 tx_time; 637 u32 tx_ipg; 638 639 u32 freq_offset; 640 641 u8 tx_power[4]; 642 u8 tx_power_control; 643 644 u8 addr[3][ETH_ALEN]; 645 646 u32 tx_pending; 647 u32 tx_queued; 648 u16 tx_queued_limit; 649 u32 tx_done; 650 struct { 651 u64 packets[__MT_RXQ_MAX]; 652 u64 fcs_error[__MT_RXQ_MAX]; 653 } rx_stats; 654 }; 655 656 struct mt76_vif { 657 u8 idx; 658 u8 omac_idx; 659 u8 band_idx; 660 u8 wmm_idx; 661 u8 scan_seq_num; 662 u8 cipher; 663 }; 664 665 struct mt76_phy { 666 struct ieee80211_hw *hw; 667 struct mt76_dev *dev; 668 void *priv; 669 670 unsigned long state; 671 u8 band_idx; 672 673 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 674 675 struct cfg80211_chan_def chandef; 676 struct ieee80211_channel *main_chan; 677 678 struct mt76_channel_state *chan_state; 679 enum mt76_dfs_state dfs_state; 680 ktime_t survey_time; 681 682 struct mt76_hw_cap cap; 683 struct mt76_sband sband_2g; 684 struct mt76_sband sband_5g; 685 struct mt76_sband sband_6g; 686 687 u8 macaddr[ETH_ALEN]; 688 689 int txpower_cur; 690 u8 antenna_mask; 691 u16 chainmask; 692 693 #ifdef CONFIG_NL80211_TESTMODE 694 struct mt76_testmode_data test; 695 #endif 696 697 struct delayed_work mac_work; 698 u8 mac_work_count; 699 700 struct { 701 struct sk_buff *head; 702 struct sk_buff **tail; 703 u16 seqno; 704 } rx_amsdu[__MT_RXQ_MAX]; 705 706 struct mt76_freq_range_power *frp; 707 }; 708 709 struct mt76_dev { 710 struct mt76_phy phy; /* must be first */ 711 struct mt76_phy *phys[__MT_MAX_BAND]; 712 713 struct ieee80211_hw *hw; 714 715 spinlock_t lock; 716 spinlock_t cc_lock; 717 718 u32 cur_cc_bss_rx; 719 720 struct mt76_rx_status rx_ampdu_status; 721 u32 rx_ampdu_len; 722 u32 rx_ampdu_ref; 723 724 struct mutex mutex; 725 726 const struct mt76_bus_ops *bus; 727 const struct mt76_driver_ops *drv; 728 const struct mt76_mcu_ops *mcu_ops; 729 struct device *dev; 730 struct device *dma_dev; 731 732 struct mt76_mcu mcu; 733 734 struct net_device napi_dev; 735 struct net_device tx_napi_dev; 736 spinlock_t rx_lock; 737 struct napi_struct napi[__MT_RXQ_MAX]; 738 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 739 740 struct list_head txwi_cache; 741 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 742 struct mt76_queue q_rx[__MT_RXQ_MAX]; 743 const struct mt76_queue_ops *queue_ops; 744 int tx_dma_idx[4]; 745 746 struct mt76_worker tx_worker; 747 struct napi_struct tx_napi; 748 749 spinlock_t token_lock; 750 struct idr token; 751 u16 wed_token_count; 752 u16 token_count; 753 u16 token_size; 754 755 wait_queue_head_t tx_wait; 756 /* spinclock used to protect wcid pktid linked list */ 757 spinlock_t status_lock; 758 759 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 760 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 761 762 u64 vif_mask; 763 764 struct mt76_wcid global_wcid; 765 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 766 struct list_head wcid_list; 767 768 u32 rev; 769 770 u32 aggr_stats[32]; 771 772 struct tasklet_struct pre_tbtt_tasklet; 773 int beacon_int; 774 u8 beacon_mask; 775 776 struct debugfs_blob_wrapper eeprom; 777 struct debugfs_blob_wrapper otp; 778 779 struct mt76_rate_power rate_power; 780 781 char alpha2[3]; 782 enum nl80211_dfs_regions region; 783 784 u32 debugfs_reg; 785 786 struct led_classdev led_cdev; 787 char led_name[32]; 788 bool led_al; 789 u8 led_pin; 790 791 u8 csa_complete; 792 793 u32 rxfilter; 794 795 #ifdef CONFIG_NL80211_TESTMODE 796 const struct mt76_testmode_ops *test_ops; 797 struct { 798 const char *name; 799 u32 offset; 800 } test_mtd; 801 #endif 802 struct workqueue_struct *wq; 803 804 union { 805 struct mt76_mmio mmio; 806 struct mt76_usb usb; 807 struct mt76_sdio sdio; 808 }; 809 }; 810 811 struct mt76_power_limits { 812 s8 cck[4]; 813 s8 ofdm[8]; 814 s8 mcs[4][10]; 815 s8 ru[7][12]; 816 }; 817 818 enum mt76_phy_type { 819 MT_PHY_TYPE_CCK, 820 MT_PHY_TYPE_OFDM, 821 MT_PHY_TYPE_HT, 822 MT_PHY_TYPE_HT_GF, 823 MT_PHY_TYPE_VHT, 824 MT_PHY_TYPE_HE_SU = 8, 825 MT_PHY_TYPE_HE_EXT_SU, 826 MT_PHY_TYPE_HE_TB, 827 MT_PHY_TYPE_HE_MU, 828 __MT_PHY_TYPE_HE_MAX, 829 }; 830 831 struct mt76_sta_stats { 832 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 833 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 834 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 835 u64 tx_mcs[16]; /* mcs idx */ 836 }; 837 838 struct mt76_ethtool_worker_info { 839 u64 *data; 840 int idx; 841 int initial_stat_idx; 842 int worker_stat_count; 843 int sta_count; 844 }; 845 846 #define CCK_RATE(_idx, _rate) { \ 847 .bitrate = _rate, \ 848 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 849 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 850 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 851 } 852 853 #define OFDM_RATE(_idx, _rate) { \ 854 .bitrate = _rate, \ 855 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 856 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 857 } 858 859 extern struct ieee80211_rate mt76_rates[12]; 860 861 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 862 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 863 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 864 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 865 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 866 867 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 868 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 869 870 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 871 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 872 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 873 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 874 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 875 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 876 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 877 878 879 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 880 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 881 882 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 883 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 884 885 #define mt76_get_field(_dev, _reg, _field) \ 886 FIELD_GET(_field, mt76_rr(dev, _reg)) 887 888 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 889 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 890 891 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 892 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 893 894 #define mt76_hw(dev) (dev)->mphy.hw 895 896 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 897 int timeout); 898 899 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 900 901 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 902 int timeout); 903 904 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 905 906 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 907 void mt76_pci_disable_aspm(struct pci_dev *pdev); 908 909 static inline u16 mt76_chip(struct mt76_dev *dev) 910 { 911 return dev->rev >> 16; 912 } 913 914 static inline u16 mt76_rev(struct mt76_dev *dev) 915 { 916 return dev->rev & 0xffff; 917 } 918 919 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 920 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 921 922 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 923 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 924 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 925 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 926 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 927 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 928 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 929 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 930 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 931 932 #define mt76_for_each_q_rx(dev, i) \ 933 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 934 if ((dev)->q_rx[i].ndesc) 935 936 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 937 const struct ieee80211_ops *ops, 938 const struct mt76_driver_ops *drv_ops); 939 int mt76_register_device(struct mt76_dev *dev, bool vht, 940 struct ieee80211_rate *rates, int n_rates); 941 void mt76_unregister_device(struct mt76_dev *dev); 942 void mt76_free_device(struct mt76_dev *dev); 943 void mt76_unregister_phy(struct mt76_phy *phy); 944 945 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 946 const struct ieee80211_ops *ops, 947 u8 band_idx); 948 int mt76_register_phy(struct mt76_phy *phy, bool vht, 949 struct ieee80211_rate *rates, int n_rates); 950 951 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 952 const struct file_operations *ops); 953 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 954 { 955 return mt76_register_debugfs_fops(&dev->phy, NULL); 956 } 957 958 int mt76_queues_read(struct seq_file *s, void *data); 959 void mt76_seq_puts_array(struct seq_file *file, const char *str, 960 s8 *val, int len); 961 962 int mt76_eeprom_init(struct mt76_dev *dev, int len); 963 void mt76_eeprom_override(struct mt76_phy *phy); 964 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 965 966 struct mt76_queue * 967 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 968 int ring_base, u32 flags); 969 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 970 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 971 int n_desc, int ring_base, u32 flags) 972 { 973 struct mt76_queue *q; 974 975 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 976 if (IS_ERR(q)) 977 return PTR_ERR(q); 978 979 phy->q_tx[qid] = q; 980 981 return 0; 982 } 983 984 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 985 int n_desc, int ring_base) 986 { 987 struct mt76_queue *q; 988 989 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 990 if (IS_ERR(q)) 991 return PTR_ERR(q); 992 993 dev->q_mcu[qid] = q; 994 995 return 0; 996 } 997 998 static inline struct mt76_phy * 999 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1000 { 1001 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1002 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1003 return dev->phys[phy_idx]; 1004 1005 return &dev->phy; 1006 } 1007 1008 static inline struct ieee80211_hw * 1009 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1010 { 1011 return mt76_dev_phy(dev, phy_idx)->hw; 1012 } 1013 1014 static inline u8 * 1015 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1016 { 1017 return (u8 *)t - dev->drv->txwi_size; 1018 } 1019 1020 /* increment with wrap-around */ 1021 static inline int mt76_incr(int val, int size) 1022 { 1023 return (val + 1) & (size - 1); 1024 } 1025 1026 /* decrement with wrap-around */ 1027 static inline int mt76_decr(int val, int size) 1028 { 1029 return (val - 1) & (size - 1); 1030 } 1031 1032 u8 mt76_ac_to_hwq(u8 ac); 1033 1034 static inline struct ieee80211_txq * 1035 mtxq_to_txq(struct mt76_txq *mtxq) 1036 { 1037 void *ptr = mtxq; 1038 1039 return container_of(ptr, struct ieee80211_txq, drv_priv); 1040 } 1041 1042 static inline struct ieee80211_sta * 1043 wcid_to_sta(struct mt76_wcid *wcid) 1044 { 1045 void *ptr = wcid; 1046 1047 if (!wcid || !wcid->sta) 1048 return NULL; 1049 1050 return container_of(ptr, struct ieee80211_sta, drv_priv); 1051 } 1052 1053 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1054 { 1055 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1056 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1057 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1058 } 1059 1060 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1061 { 1062 struct mt76_rx_status mstat; 1063 u8 *data = skb->data; 1064 1065 /* Alignment concerns */ 1066 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1067 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1068 1069 mstat = *((struct mt76_rx_status *)skb->cb); 1070 1071 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1072 data += sizeof(struct ieee80211_radiotap_he); 1073 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1074 data += sizeof(struct ieee80211_radiotap_he_mu); 1075 1076 return data; 1077 } 1078 1079 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1080 { 1081 int len = ieee80211_get_hdrlen_from_skb(skb); 1082 1083 if (len % 4 == 0) 1084 return; 1085 1086 skb_push(skb, 2); 1087 memmove(skb->data, skb->data + 2, len); 1088 1089 skb->data[len] = 0; 1090 skb->data[len + 1] = 0; 1091 } 1092 1093 static inline bool mt76_is_skb_pktid(u8 pktid) 1094 { 1095 if (pktid & MT_PACKET_ID_HAS_RATE) 1096 return false; 1097 1098 return pktid >= MT_PACKET_ID_FIRST; 1099 } 1100 1101 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1102 { 1103 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1104 1105 return nss_delta[nss - 1]; 1106 } 1107 1108 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1109 { 1110 #ifdef CONFIG_NL80211_TESTMODE 1111 return phy->test.state != MT76_TM_STATE_OFF; 1112 #else 1113 return false; 1114 #endif 1115 } 1116 1117 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1118 struct sk_buff *skb, 1119 struct ieee80211_hw **hw) 1120 { 1121 #ifdef CONFIG_NL80211_TESTMODE 1122 int i; 1123 1124 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1125 struct mt76_phy *phy = dev->phys[i]; 1126 1127 if (phy && skb == phy->test.tx_skb) { 1128 *hw = dev->phys[i]->hw; 1129 return true; 1130 } 1131 } 1132 return false; 1133 #else 1134 return false; 1135 #endif 1136 } 1137 1138 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1139 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1140 struct mt76_wcid *wcid, struct sk_buff *skb); 1141 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1142 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1143 bool send_bar); 1144 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1145 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1146 void mt76_txq_schedule_all(struct mt76_phy *phy); 1147 void mt76_tx_worker_run(struct mt76_dev *dev); 1148 void mt76_tx_worker(struct mt76_worker *w); 1149 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1150 struct ieee80211_sta *sta, 1151 u16 tids, int nframes, 1152 enum ieee80211_frame_release_type reason, 1153 bool more_data); 1154 bool mt76_has_tx_pending(struct mt76_phy *phy); 1155 void mt76_set_channel(struct mt76_phy *phy); 1156 void mt76_update_survey(struct mt76_phy *phy); 1157 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1158 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1159 struct survey_info *survey); 1160 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1161 1162 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1163 u16 ssn, u16 size); 1164 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1165 1166 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1167 struct ieee80211_key_conf *key); 1168 1169 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1170 __acquires(&dev->status_lock); 1171 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1172 __releases(&dev->status_lock); 1173 1174 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1175 struct sk_buff *skb); 1176 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1177 struct mt76_wcid *wcid, int pktid, 1178 struct sk_buff_head *list); 1179 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1180 struct sk_buff_head *list); 1181 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1182 struct list_head *free_list); 1183 static inline void 1184 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1185 { 1186 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1187 } 1188 1189 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1190 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1191 struct ieee80211_sta *sta, 1192 enum ieee80211_sta_state old_state, 1193 enum ieee80211_sta_state new_state); 1194 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1195 struct ieee80211_sta *sta); 1196 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1197 struct ieee80211_sta *sta); 1198 1199 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1200 1201 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1202 int *dbm); 1203 int mt76_init_sar_power(struct ieee80211_hw *hw, 1204 const struct cfg80211_sar_specs *sar); 1205 int mt76_get_sar_power(struct mt76_phy *phy, 1206 struct ieee80211_channel *chan, 1207 int power); 1208 1209 void mt76_csa_check(struct mt76_dev *dev); 1210 void mt76_csa_finish(struct mt76_dev *dev); 1211 1212 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1213 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1214 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1215 int mt76_get_rate(struct mt76_dev *dev, 1216 struct ieee80211_supported_band *sband, 1217 int idx, bool cck); 1218 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1219 const u8 *mac); 1220 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1221 struct ieee80211_vif *vif); 1222 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1223 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1224 void *data, int len); 1225 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1226 struct netlink_callback *cb, void *data, int len); 1227 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1228 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1229 1230 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1231 { 1232 #ifdef CONFIG_NL80211_TESTMODE 1233 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1234 1235 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1236 state = MT76_TM_STATE_OFF; 1237 1238 mt76_testmode_set_state(phy, state); 1239 #endif 1240 } 1241 1242 1243 /* internal */ 1244 static inline struct ieee80211_hw * 1245 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1246 { 1247 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1248 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1249 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1250 1251 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1252 1253 return hw; 1254 } 1255 1256 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1257 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1258 struct napi_struct *napi); 1259 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1260 struct napi_struct *napi); 1261 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1262 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1263 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1264 struct mt76_queue_entry *e); 1265 1266 /* usb */ 1267 static inline bool mt76u_urb_error(struct urb *urb) 1268 { 1269 return urb->status && 1270 urb->status != -ECONNRESET && 1271 urb->status != -ESHUTDOWN && 1272 urb->status != -ENOENT; 1273 } 1274 1275 /* Map hardware queues to usb endpoints */ 1276 static inline u8 q2ep(u8 qid) 1277 { 1278 /* TODO: take management packets to queue 5 */ 1279 return qid + 1; 1280 } 1281 1282 static inline int 1283 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1284 int timeout, int ep) 1285 { 1286 struct usb_interface *uintf = to_usb_interface(dev->dev); 1287 struct usb_device *udev = interface_to_usbdev(uintf); 1288 struct mt76_usb *usb = &dev->usb; 1289 unsigned int pipe; 1290 1291 if (actual_len) 1292 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1293 else 1294 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1295 1296 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1297 } 1298 1299 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1300 struct mt76_sta_stats *stats); 1301 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1302 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1303 u16 val, u16 offset, void *buf, size_t len); 1304 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1305 u8 req_type, u16 val, u16 offset, 1306 void *buf, size_t len); 1307 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1308 const u16 offset, const u32 val); 1309 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1310 void *data, int len); 1311 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1312 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1313 u32 addr, u32 val); 1314 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1315 struct mt76_bus_ops *ops); 1316 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1317 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1318 int mt76u_alloc_queues(struct mt76_dev *dev); 1319 void mt76u_stop_tx(struct mt76_dev *dev); 1320 void mt76u_stop_rx(struct mt76_dev *dev); 1321 int mt76u_resume_rx(struct mt76_dev *dev); 1322 void mt76u_queues_deinit(struct mt76_dev *dev); 1323 1324 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1325 const struct mt76_bus_ops *bus_ops); 1326 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1327 int mt76s_alloc_tx(struct mt76_dev *dev); 1328 void mt76s_deinit(struct mt76_dev *dev); 1329 void mt76s_sdio_irq(struct sdio_func *func); 1330 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1331 bool mt76s_txqs_empty(struct mt76_dev *dev); 1332 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1333 int hw_ver); 1334 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1335 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1336 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1337 u32 mt76s_read_pcr(struct mt76_dev *dev); 1338 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1339 const void *data, int len); 1340 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1341 void *data, int len); 1342 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1343 const struct mt76_reg_pair *data, 1344 int len); 1345 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1346 struct mt76_reg_pair *data, int len); 1347 1348 struct sk_buff * 1349 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1350 int len, int data_len, gfp_t gfp); 1351 static inline struct sk_buff * 1352 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1353 int data_len) 1354 { 1355 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1356 } 1357 1358 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1359 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1360 unsigned long expires); 1361 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1362 int len, bool wait_resp, struct sk_buff **ret); 1363 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1364 int cmd, bool wait_resp, struct sk_buff **ret); 1365 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1366 int len, int max_len); 1367 static inline int 1368 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1369 int len) 1370 { 1371 int max_len = 4096 - dev->mcu_ops->headroom; 1372 1373 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1374 } 1375 1376 static inline int 1377 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1378 bool wait_resp) 1379 { 1380 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1381 } 1382 1383 static inline int 1384 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1385 bool wait_resp) 1386 { 1387 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1388 } 1389 1390 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1391 1392 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1393 struct ieee80211_channel *chan, 1394 struct mt76_power_limits *dest, 1395 s8 target_power); 1396 1397 struct mt76_txwi_cache * 1398 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1399 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1400 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1401 1402 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1403 { 1404 spin_lock_bh(&dev->token_lock); 1405 __mt76_set_tx_blocked(dev, blocked); 1406 spin_unlock_bh(&dev->token_lock); 1407 } 1408 1409 static inline int 1410 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1411 { 1412 int token; 1413 1414 spin_lock_bh(&dev->token_lock); 1415 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1416 spin_unlock_bh(&dev->token_lock); 1417 1418 return token; 1419 } 1420 1421 static inline struct mt76_txwi_cache * 1422 mt76_token_put(struct mt76_dev *dev, int token) 1423 { 1424 struct mt76_txwi_cache *txwi; 1425 1426 spin_lock_bh(&dev->token_lock); 1427 txwi = idr_remove(&dev->token, token); 1428 spin_unlock_bh(&dev->token_lock); 1429 1430 return txwi; 1431 } 1432 1433 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1434 { 1435 INIT_LIST_HEAD(&wcid->list); 1436 idr_init(&wcid->pktid); 1437 } 1438 1439 static inline void 1440 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1441 { 1442 struct sk_buff_head list; 1443 1444 mt76_tx_status_lock(dev, &list); 1445 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1446 mt76_tx_status_unlock(dev, &list); 1447 1448 idr_destroy(&wcid->pktid); 1449 } 1450 1451 #endif 1452