1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 #include "testmode.h" 19 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 256 23 24 #define MT_MAX_NON_AQL_PKT 16 25 #define MT_TXQ_FREE_THR 32 26 27 #define MT76_TOKEN_FREE_THR 64 28 29 struct mt76_dev; 30 struct mt76_phy; 31 struct mt76_wcid; 32 struct mt76s_intr; 33 34 struct mt76_reg_pair { 35 u32 reg; 36 u32 value; 37 }; 38 39 enum mt76_bus_type { 40 MT76_BUS_MMIO, 41 MT76_BUS_USB, 42 MT76_BUS_SDIO, 43 }; 44 45 struct mt76_bus_ops { 46 u32 (*rr)(struct mt76_dev *dev, u32 offset); 47 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 48 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 49 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 50 int len); 51 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 52 int len); 53 int (*wr_rp)(struct mt76_dev *dev, u32 base, 54 const struct mt76_reg_pair *rp, int len); 55 int (*rd_rp)(struct mt76_dev *dev, u32 base, 56 struct mt76_reg_pair *rp, int len); 57 enum mt76_bus_type type; 58 }; 59 60 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 61 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 62 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 63 64 enum mt76_txq_id { 65 MT_TXQ_VO = IEEE80211_AC_VO, 66 MT_TXQ_VI = IEEE80211_AC_VI, 67 MT_TXQ_BE = IEEE80211_AC_BE, 68 MT_TXQ_BK = IEEE80211_AC_BK, 69 MT_TXQ_PSD, 70 MT_TXQ_BEACON, 71 MT_TXQ_CAB, 72 __MT_TXQ_MAX 73 }; 74 75 enum mt76_mcuq_id { 76 MT_MCUQ_WM, 77 MT_MCUQ_WA, 78 MT_MCUQ_FWDL, 79 __MT_MCUQ_MAX 80 }; 81 82 enum mt76_rxq_id { 83 MT_RXQ_MAIN, 84 MT_RXQ_MCU, 85 MT_RXQ_MCU_WA, 86 MT_RXQ_EXT, 87 MT_RXQ_EXT_WA, 88 MT_RXQ_MAIN_WA, 89 __MT_RXQ_MAX 90 }; 91 92 enum mt76_cipher_type { 93 MT_CIPHER_NONE, 94 MT_CIPHER_WEP40, 95 MT_CIPHER_TKIP, 96 MT_CIPHER_TKIP_NO_MIC, 97 MT_CIPHER_AES_CCMP, 98 MT_CIPHER_WEP104, 99 MT_CIPHER_BIP_CMAC_128, 100 MT_CIPHER_WEP128, 101 MT_CIPHER_WAPI, 102 MT_CIPHER_CCMP_CCX, 103 MT_CIPHER_CCMP_256, 104 MT_CIPHER_GCMP, 105 MT_CIPHER_GCMP_256, 106 }; 107 108 enum mt76_dfs_state { 109 MT_DFS_STATE_UNKNOWN, 110 MT_DFS_STATE_DISABLED, 111 MT_DFS_STATE_CAC, 112 MT_DFS_STATE_ACTIVE, 113 }; 114 115 struct mt76_queue_buf { 116 dma_addr_t addr; 117 u16 len; 118 bool skip_unmap; 119 }; 120 121 struct mt76_tx_info { 122 struct mt76_queue_buf buf[32]; 123 struct sk_buff *skb; 124 int nbuf; 125 u32 info; 126 }; 127 128 struct mt76_queue_entry { 129 union { 130 void *buf; 131 struct sk_buff *skb; 132 }; 133 union { 134 struct mt76_txwi_cache *txwi; 135 struct urb *urb; 136 int buf_sz; 137 }; 138 u32 dma_addr[2]; 139 u16 dma_len[2]; 140 u16 wcid; 141 bool skip_buf0:1; 142 bool skip_buf1:1; 143 bool done:1; 144 }; 145 146 struct mt76_queue_regs { 147 u32 desc_base; 148 u32 ring_size; 149 u32 cpu_idx; 150 u32 dma_idx; 151 } __packed __aligned(4); 152 153 struct mt76_queue { 154 struct mt76_queue_regs __iomem *regs; 155 156 spinlock_t lock; 157 spinlock_t cleanup_lock; 158 struct mt76_queue_entry *entry; 159 struct mt76_desc *desc; 160 161 u16 first; 162 u16 head; 163 u16 tail; 164 int ndesc; 165 int queued; 166 int buf_size; 167 bool stopped; 168 bool blocked; 169 170 u8 buf_offset; 171 u8 hw_idx; 172 u8 qid; 173 174 dma_addr_t desc_dma; 175 struct sk_buff *rx_head; 176 struct page_frag_cache rx_page; 177 }; 178 179 struct mt76_mcu_ops { 180 u32 headroom; 181 u32 tailroom; 182 183 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 184 int len, bool wait_resp); 185 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 186 int cmd, int *seq); 187 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 188 struct sk_buff *skb, int seq); 189 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 190 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 191 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 192 const struct mt76_reg_pair *rp, int len); 193 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 194 struct mt76_reg_pair *rp, int len); 195 int (*mcu_restart)(struct mt76_dev *dev); 196 }; 197 198 struct mt76_queue_ops { 199 int (*init)(struct mt76_dev *dev, 200 int (*poll)(struct napi_struct *napi, int budget)); 201 202 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 203 int idx, int n_desc, int bufsize, 204 u32 ring_base); 205 206 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 207 struct sk_buff *skb, struct mt76_wcid *wcid, 208 struct ieee80211_sta *sta); 209 210 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 211 struct sk_buff *skb, u32 tx_info); 212 213 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 214 int *len, u32 *info, bool *more); 215 216 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 217 218 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 219 bool flush); 220 221 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 222 223 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 224 225 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 226 }; 227 228 enum mt76_wcid_flags { 229 MT_WCID_FLAG_CHECK_PS, 230 MT_WCID_FLAG_PS, 231 MT_WCID_FLAG_4ADDR, 232 MT_WCID_FLAG_HDR_TRANS, 233 }; 234 235 #define MT76_N_WCIDS 544 236 237 /* stored in ieee80211_tx_info::hw_queue */ 238 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 239 240 DECLARE_EWMA(signal, 10, 8); 241 242 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 243 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 244 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 245 #define MT_WCID_TX_INFO_SET BIT(31) 246 247 struct mt76_wcid { 248 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 249 250 atomic_t non_aql_packets; 251 unsigned long flags; 252 253 struct ewma_signal rssi; 254 int inactive_count; 255 256 struct rate_info rate; 257 258 u16 idx; 259 u8 hw_key_idx; 260 u8 hw_key_idx2; 261 262 u8 sta:1; 263 u8 ext_phy:1; 264 u8 amsdu:1; 265 266 u8 rx_check_pn; 267 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 268 u16 cipher; 269 270 u32 tx_info; 271 bool sw_iv; 272 273 struct list_head list; 274 struct idr pktid; 275 }; 276 277 struct mt76_txq { 278 struct mt76_wcid *wcid; 279 280 u16 agg_ssn; 281 bool send_bar; 282 bool aggr; 283 }; 284 285 struct mt76_txwi_cache { 286 struct list_head list; 287 dma_addr_t dma_addr; 288 289 struct sk_buff *skb; 290 }; 291 292 struct mt76_rx_tid { 293 struct rcu_head rcu_head; 294 295 struct mt76_dev *dev; 296 297 spinlock_t lock; 298 struct delayed_work reorder_work; 299 300 u16 head; 301 u16 size; 302 u16 nframes; 303 304 u8 num; 305 306 u8 started:1, stopped:1, timer_pending:1; 307 308 struct sk_buff *reorder_buf[]; 309 }; 310 311 #define MT_TX_CB_DMA_DONE BIT(0) 312 #define MT_TX_CB_TXS_DONE BIT(1) 313 #define MT_TX_CB_TXS_FAILED BIT(2) 314 315 #define MT_PACKET_ID_MASK GENMASK(6, 0) 316 #define MT_PACKET_ID_NO_ACK 0 317 #define MT_PACKET_ID_NO_SKB 1 318 #define MT_PACKET_ID_FIRST 2 319 #define MT_PACKET_ID_HAS_RATE BIT(7) 320 /* This is timer for when to give up when waiting for TXS callback, 321 * with starting time being the time at which the DMA_DONE callback 322 * was seen (so, we know packet was processed then, it should not take 323 * long after that for firmware to send the TXS callback if it is going 324 * to do so.) 325 */ 326 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 327 328 struct mt76_tx_cb { 329 unsigned long jiffies; 330 u16 wcid; 331 u8 pktid; 332 u8 flags; 333 }; 334 335 enum { 336 MT76_STATE_INITIALIZED, 337 MT76_STATE_RUNNING, 338 MT76_STATE_MCU_RUNNING, 339 MT76_SCANNING, 340 MT76_HW_SCANNING, 341 MT76_HW_SCHED_SCANNING, 342 MT76_RESTART, 343 MT76_RESET, 344 MT76_MCU_RESET, 345 MT76_REMOVED, 346 MT76_READING_STATS, 347 MT76_STATE_POWER_OFF, 348 MT76_STATE_SUSPEND, 349 MT76_STATE_ROC, 350 MT76_STATE_PM, 351 }; 352 353 struct mt76_hw_cap { 354 bool has_2ghz; 355 bool has_5ghz; 356 bool has_6ghz; 357 }; 358 359 #define MT_DRV_TXWI_NO_FREE BIT(0) 360 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 361 #define MT_DRV_SW_RX_AIRTIME BIT(2) 362 #define MT_DRV_RX_DMA_HDR BIT(3) 363 #define MT_DRV_HW_MGMT_TXQ BIT(4) 364 365 struct mt76_driver_ops { 366 u32 drv_flags; 367 u32 survey_flags; 368 u16 txwi_size; 369 u16 token_size; 370 u8 mcs_rates; 371 372 void (*update_survey)(struct mt76_phy *phy); 373 374 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 375 enum mt76_txq_id qid, struct mt76_wcid *wcid, 376 struct ieee80211_sta *sta, 377 struct mt76_tx_info *tx_info); 378 379 void (*tx_complete_skb)(struct mt76_dev *dev, 380 struct mt76_queue_entry *e); 381 382 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 383 384 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 385 386 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 387 struct sk_buff *skb); 388 389 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 390 391 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 392 bool ps); 393 394 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 395 struct ieee80211_sta *sta); 396 397 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 398 struct ieee80211_sta *sta); 399 400 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 401 struct ieee80211_sta *sta); 402 }; 403 404 struct mt76_channel_state { 405 u64 cc_active; 406 u64 cc_busy; 407 u64 cc_rx; 408 u64 cc_bss_rx; 409 u64 cc_tx; 410 411 s8 noise; 412 }; 413 414 struct mt76_sband { 415 struct ieee80211_supported_band sband; 416 struct mt76_channel_state *chan; 417 }; 418 419 struct mt76_rate_power { 420 union { 421 struct { 422 s8 cck[4]; 423 s8 ofdm[8]; 424 s8 stbc[10]; 425 s8 ht[16]; 426 s8 vht[10]; 427 }; 428 s8 all[48]; 429 }; 430 }; 431 432 /* addr req mask */ 433 #define MT_VEND_TYPE_EEPROM BIT(31) 434 #define MT_VEND_TYPE_CFG BIT(30) 435 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 436 437 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 438 enum mt_vendor_req { 439 MT_VEND_DEV_MODE = 0x1, 440 MT_VEND_WRITE = 0x2, 441 MT_VEND_POWER_ON = 0x4, 442 MT_VEND_MULTI_WRITE = 0x6, 443 MT_VEND_MULTI_READ = 0x7, 444 MT_VEND_READ_EEPROM = 0x9, 445 MT_VEND_WRITE_FCE = 0x42, 446 MT_VEND_WRITE_CFG = 0x46, 447 MT_VEND_READ_CFG = 0x47, 448 MT_VEND_READ_EXT = 0x63, 449 MT_VEND_WRITE_EXT = 0x66, 450 MT_VEND_FEATURE_SET = 0x91, 451 }; 452 453 enum mt76u_in_ep { 454 MT_EP_IN_PKT_RX, 455 MT_EP_IN_CMD_RESP, 456 __MT_EP_IN_MAX, 457 }; 458 459 enum mt76u_out_ep { 460 MT_EP_OUT_INBAND_CMD, 461 MT_EP_OUT_AC_BE, 462 MT_EP_OUT_AC_BK, 463 MT_EP_OUT_AC_VI, 464 MT_EP_OUT_AC_VO, 465 MT_EP_OUT_HCCA, 466 __MT_EP_OUT_MAX, 467 }; 468 469 struct mt76_mcu { 470 struct mutex mutex; 471 u32 msg_seq; 472 int timeout; 473 474 struct sk_buff_head res_q; 475 wait_queue_head_t wait; 476 }; 477 478 #define MT_TX_SG_MAX_SIZE 8 479 #define MT_RX_SG_MAX_SIZE 4 480 #define MT_NUM_TX_ENTRIES 256 481 #define MT_NUM_RX_ENTRIES 128 482 #define MCU_RESP_URB_SIZE 1024 483 struct mt76_usb { 484 struct mutex usb_ctrl_mtx; 485 u8 *data; 486 u16 data_len; 487 488 struct mt76_worker status_worker; 489 struct mt76_worker rx_worker; 490 491 struct work_struct stat_work; 492 493 u8 out_ep[__MT_EP_OUT_MAX]; 494 u8 in_ep[__MT_EP_IN_MAX]; 495 bool sg_en; 496 497 struct mt76u_mcu { 498 u8 *data; 499 /* multiple reads */ 500 struct mt76_reg_pair *rp; 501 int rp_len; 502 u32 base; 503 bool burst; 504 } mcu; 505 }; 506 507 #define MT76S_XMIT_BUF_SZ 0x3fe00 508 #define MT76S_NUM_TX_ENTRIES 256 509 #define MT76S_NUM_RX_ENTRIES 512 510 struct mt76_sdio { 511 struct mt76_worker txrx_worker; 512 struct mt76_worker status_worker; 513 struct mt76_worker net_worker; 514 515 struct work_struct stat_work; 516 517 u8 *xmit_buf; 518 u32 xmit_buf_sz; 519 520 struct sdio_func *func; 521 void *intr_data; 522 u8 hw_ver; 523 wait_queue_head_t wait; 524 525 struct { 526 int pse_data_quota; 527 int ple_data_quota; 528 int pse_mcu_quota; 529 int pse_page_size; 530 int deficit; 531 } sched; 532 533 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 534 }; 535 536 struct mt76_mmio { 537 void __iomem *regs; 538 spinlock_t irq_lock; 539 u32 irqmask; 540 }; 541 542 struct mt76_rx_status { 543 union { 544 struct mt76_wcid *wcid; 545 u16 wcid_idx; 546 }; 547 548 u32 reorder_time; 549 550 u32 ampdu_ref; 551 u32 timestamp; 552 553 u8 iv[6]; 554 555 u8 ext_phy:1; 556 u8 aggr:1; 557 u8 qos_ctl; 558 u16 seqno; 559 560 u16 freq; 561 u32 flag; 562 u8 enc_flags; 563 u8 encoding:2, bw:3, he_ru:3; 564 u8 he_gi:2, he_dcm:1; 565 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 566 u8 rate_idx; 567 u8 nss; 568 u8 band; 569 s8 signal; 570 u8 chains; 571 s8 chain_signal[IEEE80211_MAX_CHAINS]; 572 }; 573 574 struct mt76_freq_range_power { 575 const struct cfg80211_sar_freq_ranges *range; 576 s8 power; 577 }; 578 579 struct mt76_testmode_ops { 580 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 581 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 582 enum mt76_testmode_state new_state); 583 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 584 }; 585 586 struct mt76_testmode_data { 587 enum mt76_testmode_state state; 588 589 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 590 struct sk_buff *tx_skb; 591 592 u32 tx_count; 593 u16 tx_mpdu_len; 594 595 u8 tx_rate_mode; 596 u8 tx_rate_idx; 597 u8 tx_rate_nss; 598 u8 tx_rate_sgi; 599 u8 tx_rate_ldpc; 600 u8 tx_rate_stbc; 601 u8 tx_ltf; 602 603 u8 tx_antenna_mask; 604 u8 tx_spe_idx; 605 606 u8 tx_duty_cycle; 607 u32 tx_time; 608 u32 tx_ipg; 609 610 u32 freq_offset; 611 612 u8 tx_power[4]; 613 u8 tx_power_control; 614 615 u8 addr[3][ETH_ALEN]; 616 617 u32 tx_pending; 618 u32 tx_queued; 619 u16 tx_queued_limit; 620 u32 tx_done; 621 struct { 622 u64 packets[__MT_RXQ_MAX]; 623 u64 fcs_error[__MT_RXQ_MAX]; 624 } rx_stats; 625 }; 626 627 struct mt76_vif { 628 u8 idx; 629 u8 omac_idx; 630 u8 band_idx; 631 u8 wmm_idx; 632 u8 scan_seq_num; 633 u8 cipher; 634 }; 635 636 struct mt76_phy { 637 struct ieee80211_hw *hw; 638 struct mt76_dev *dev; 639 void *priv; 640 641 unsigned long state; 642 643 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 644 645 struct cfg80211_chan_def chandef; 646 struct ieee80211_channel *main_chan; 647 648 struct mt76_channel_state *chan_state; 649 enum mt76_dfs_state dfs_state; 650 ktime_t survey_time; 651 652 struct mt76_hw_cap cap; 653 struct mt76_sband sband_2g; 654 struct mt76_sband sband_5g; 655 struct mt76_sband sband_6g; 656 657 u8 macaddr[ETH_ALEN]; 658 659 int txpower_cur; 660 u8 antenna_mask; 661 u16 chainmask; 662 663 #ifdef CONFIG_NL80211_TESTMODE 664 struct mt76_testmode_data test; 665 #endif 666 667 struct delayed_work mac_work; 668 u8 mac_work_count; 669 670 struct { 671 struct sk_buff *head; 672 struct sk_buff **tail; 673 u16 seqno; 674 } rx_amsdu[__MT_RXQ_MAX]; 675 676 struct mt76_freq_range_power *frp; 677 }; 678 679 struct mt76_dev { 680 struct mt76_phy phy; /* must be first */ 681 682 struct mt76_phy *phy2; 683 684 struct ieee80211_hw *hw; 685 686 spinlock_t lock; 687 spinlock_t cc_lock; 688 689 u32 cur_cc_bss_rx; 690 691 struct mt76_rx_status rx_ampdu_status; 692 u32 rx_ampdu_len; 693 u32 rx_ampdu_ref; 694 695 struct mutex mutex; 696 697 const struct mt76_bus_ops *bus; 698 const struct mt76_driver_ops *drv; 699 const struct mt76_mcu_ops *mcu_ops; 700 struct device *dev; 701 702 struct mt76_mcu mcu; 703 704 struct net_device napi_dev; 705 struct net_device tx_napi_dev; 706 spinlock_t rx_lock; 707 struct napi_struct napi[__MT_RXQ_MAX]; 708 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 709 710 struct list_head txwi_cache; 711 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 712 struct mt76_queue q_rx[__MT_RXQ_MAX]; 713 const struct mt76_queue_ops *queue_ops; 714 int tx_dma_idx[4]; 715 716 struct mt76_worker tx_worker; 717 struct napi_struct tx_napi; 718 719 spinlock_t token_lock; 720 struct idr token; 721 int token_count; 722 723 wait_queue_head_t tx_wait; 724 /* spinclock used to protect wcid pktid linked list */ 725 spinlock_t status_lock; 726 727 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 728 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 729 730 u32 vif_mask; 731 732 struct mt76_wcid global_wcid; 733 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 734 struct list_head wcid_list; 735 736 u32 rev; 737 738 u32 aggr_stats[32]; 739 740 struct tasklet_struct pre_tbtt_tasklet; 741 int beacon_int; 742 u8 beacon_mask; 743 744 struct debugfs_blob_wrapper eeprom; 745 struct debugfs_blob_wrapper otp; 746 747 struct mt76_rate_power rate_power; 748 749 char alpha2[3]; 750 enum nl80211_dfs_regions region; 751 752 u32 debugfs_reg; 753 754 struct led_classdev led_cdev; 755 char led_name[32]; 756 bool led_al; 757 u8 led_pin; 758 759 u8 csa_complete; 760 761 u32 rxfilter; 762 763 #ifdef CONFIG_NL80211_TESTMODE 764 const struct mt76_testmode_ops *test_ops; 765 struct { 766 const char *name; 767 u32 offset; 768 } test_mtd; 769 #endif 770 struct workqueue_struct *wq; 771 772 union { 773 struct mt76_mmio mmio; 774 struct mt76_usb usb; 775 struct mt76_sdio sdio; 776 }; 777 }; 778 779 struct mt76_power_limits { 780 s8 cck[4]; 781 s8 ofdm[8]; 782 s8 mcs[4][10]; 783 s8 ru[7][12]; 784 }; 785 786 enum mt76_phy_type { 787 MT_PHY_TYPE_CCK, 788 MT_PHY_TYPE_OFDM, 789 MT_PHY_TYPE_HT, 790 MT_PHY_TYPE_HT_GF, 791 MT_PHY_TYPE_VHT, 792 MT_PHY_TYPE_HE_SU = 8, 793 MT_PHY_TYPE_HE_EXT_SU, 794 MT_PHY_TYPE_HE_TB, 795 MT_PHY_TYPE_HE_MU, 796 __MT_PHY_TYPE_HE_MAX, 797 }; 798 799 struct mt76_sta_stats { 800 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 801 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 802 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 803 u64 tx_mcs[16]; /* mcs idx */ 804 }; 805 806 struct mt76_ethtool_worker_info { 807 u64 *data; 808 int idx; 809 int initial_stat_idx; 810 int worker_stat_count; 811 int sta_count; 812 }; 813 814 #define CCK_RATE(_idx, _rate) { \ 815 .bitrate = _rate, \ 816 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 817 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 818 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 819 } 820 821 #define OFDM_RATE(_idx, _rate) { \ 822 .bitrate = _rate, \ 823 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 824 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 825 } 826 827 extern struct ieee80211_rate mt76_rates[12]; 828 829 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 830 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 831 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 832 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 833 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 834 835 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 836 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 837 838 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 839 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 840 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 841 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 842 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 843 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 844 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 845 846 847 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 848 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 849 850 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 851 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 852 853 #define mt76_get_field(_dev, _reg, _field) \ 854 FIELD_GET(_field, mt76_rr(dev, _reg)) 855 856 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 857 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 858 859 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 860 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 861 862 #define mt76_hw(dev) (dev)->mphy.hw 863 864 static inline struct ieee80211_hw * 865 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 866 { 867 if (wcid <= MT76_N_WCIDS && 868 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 869 return dev->phy2->hw; 870 871 return dev->phy.hw; 872 } 873 874 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 875 int timeout); 876 877 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 878 879 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 880 int timeout); 881 882 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 883 884 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 885 void mt76_pci_disable_aspm(struct pci_dev *pdev); 886 887 static inline u16 mt76_chip(struct mt76_dev *dev) 888 { 889 return dev->rev >> 16; 890 } 891 892 static inline u16 mt76_rev(struct mt76_dev *dev) 893 { 894 return dev->rev & 0xffff; 895 } 896 897 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 898 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 899 900 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 901 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 902 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 903 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 904 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 905 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 906 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 907 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 908 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 909 910 #define mt76_for_each_q_rx(dev, i) \ 911 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 912 if ((dev)->q_rx[i].ndesc) 913 914 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 915 const struct ieee80211_ops *ops, 916 const struct mt76_driver_ops *drv_ops); 917 int mt76_register_device(struct mt76_dev *dev, bool vht, 918 struct ieee80211_rate *rates, int n_rates); 919 void mt76_unregister_device(struct mt76_dev *dev); 920 void mt76_free_device(struct mt76_dev *dev); 921 void mt76_unregister_phy(struct mt76_phy *phy); 922 923 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 924 const struct ieee80211_ops *ops); 925 int mt76_register_phy(struct mt76_phy *phy, bool vht, 926 struct ieee80211_rate *rates, int n_rates); 927 928 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 929 const struct file_operations *ops); 930 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 931 { 932 return mt76_register_debugfs_fops(&dev->phy, NULL); 933 } 934 935 int mt76_queues_read(struct seq_file *s, void *data); 936 void mt76_seq_puts_array(struct seq_file *file, const char *str, 937 s8 *val, int len); 938 939 int mt76_eeprom_init(struct mt76_dev *dev, int len); 940 void mt76_eeprom_override(struct mt76_phy *phy); 941 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 942 943 struct mt76_queue * 944 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 945 int ring_base); 946 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 947 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 948 int n_desc, int ring_base) 949 { 950 struct mt76_queue *q; 951 952 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); 953 if (IS_ERR(q)) 954 return PTR_ERR(q); 955 956 q->qid = qid; 957 phy->q_tx[qid] = q; 958 959 return 0; 960 } 961 962 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 963 int n_desc, int ring_base) 964 { 965 struct mt76_queue *q; 966 967 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); 968 if (IS_ERR(q)) 969 return PTR_ERR(q); 970 971 q->qid = __MT_TXQ_MAX + qid; 972 dev->q_mcu[qid] = q; 973 974 return 0; 975 } 976 977 static inline struct mt76_phy * 978 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 979 { 980 if (phy_ext && dev->phy2) 981 return dev->phy2; 982 return &dev->phy; 983 } 984 985 static inline struct ieee80211_hw * 986 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 987 { 988 return mt76_dev_phy(dev, phy_ext)->hw; 989 } 990 991 static inline u8 * 992 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 993 { 994 return (u8 *)t - dev->drv->txwi_size; 995 } 996 997 /* increment with wrap-around */ 998 static inline int mt76_incr(int val, int size) 999 { 1000 return (val + 1) & (size - 1); 1001 } 1002 1003 /* decrement with wrap-around */ 1004 static inline int mt76_decr(int val, int size) 1005 { 1006 return (val - 1) & (size - 1); 1007 } 1008 1009 u8 mt76_ac_to_hwq(u8 ac); 1010 1011 static inline struct ieee80211_txq * 1012 mtxq_to_txq(struct mt76_txq *mtxq) 1013 { 1014 void *ptr = mtxq; 1015 1016 return container_of(ptr, struct ieee80211_txq, drv_priv); 1017 } 1018 1019 static inline struct ieee80211_sta * 1020 wcid_to_sta(struct mt76_wcid *wcid) 1021 { 1022 void *ptr = wcid; 1023 1024 if (!wcid || !wcid->sta) 1025 return NULL; 1026 1027 return container_of(ptr, struct ieee80211_sta, drv_priv); 1028 } 1029 1030 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1031 { 1032 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1033 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1034 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1035 } 1036 1037 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1038 { 1039 struct mt76_rx_status mstat; 1040 u8 *data = skb->data; 1041 1042 /* Alignment concerns */ 1043 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1044 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1045 1046 mstat = *((struct mt76_rx_status *)skb->cb); 1047 1048 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1049 data += sizeof(struct ieee80211_radiotap_he); 1050 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1051 data += sizeof(struct ieee80211_radiotap_he_mu); 1052 1053 return data; 1054 } 1055 1056 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1057 { 1058 int len = ieee80211_get_hdrlen_from_skb(skb); 1059 1060 if (len % 4 == 0) 1061 return; 1062 1063 skb_push(skb, 2); 1064 memmove(skb->data, skb->data + 2, len); 1065 1066 skb->data[len] = 0; 1067 skb->data[len + 1] = 0; 1068 } 1069 1070 static inline bool mt76_is_skb_pktid(u8 pktid) 1071 { 1072 if (pktid & MT_PACKET_ID_HAS_RATE) 1073 return false; 1074 1075 return pktid >= MT_PACKET_ID_FIRST; 1076 } 1077 1078 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1079 { 1080 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1081 1082 return nss_delta[nss - 1]; 1083 } 1084 1085 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1086 { 1087 #ifdef CONFIG_NL80211_TESTMODE 1088 return phy->test.state != MT76_TM_STATE_OFF; 1089 #else 1090 return false; 1091 #endif 1092 } 1093 1094 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1095 struct sk_buff *skb, 1096 struct ieee80211_hw **hw) 1097 { 1098 #ifdef CONFIG_NL80211_TESTMODE 1099 if (skb == dev->phy.test.tx_skb) 1100 *hw = dev->phy.hw; 1101 else if (dev->phy2 && skb == dev->phy2->test.tx_skb) 1102 *hw = dev->phy2->hw; 1103 else 1104 return false; 1105 return true; 1106 #else 1107 return false; 1108 #endif 1109 } 1110 1111 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1112 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1113 struct mt76_wcid *wcid, struct sk_buff *skb); 1114 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1115 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1116 bool send_bar); 1117 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1118 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1119 void mt76_txq_schedule_all(struct mt76_phy *phy); 1120 void mt76_tx_worker_run(struct mt76_dev *dev); 1121 void mt76_tx_worker(struct mt76_worker *w); 1122 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1123 struct ieee80211_sta *sta, 1124 u16 tids, int nframes, 1125 enum ieee80211_frame_release_type reason, 1126 bool more_data); 1127 bool mt76_has_tx_pending(struct mt76_phy *phy); 1128 void mt76_set_channel(struct mt76_phy *phy); 1129 void mt76_update_survey(struct mt76_phy *phy); 1130 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1131 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1132 struct survey_info *survey); 1133 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1134 1135 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1136 u16 ssn, u16 size); 1137 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1138 1139 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1140 struct ieee80211_key_conf *key); 1141 1142 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1143 __acquires(&dev->status_lock); 1144 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1145 __releases(&dev->status_lock); 1146 1147 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1148 struct sk_buff *skb); 1149 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1150 struct mt76_wcid *wcid, int pktid, 1151 struct sk_buff_head *list); 1152 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1153 struct sk_buff_head *list); 1154 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1155 struct list_head *free_list); 1156 static inline void 1157 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1158 { 1159 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1160 } 1161 1162 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1163 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1164 struct ieee80211_sta *sta, 1165 enum ieee80211_sta_state old_state, 1166 enum ieee80211_sta_state new_state); 1167 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1168 struct ieee80211_sta *sta); 1169 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1170 struct ieee80211_sta *sta); 1171 1172 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1173 1174 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1175 int *dbm); 1176 int mt76_init_sar_power(struct ieee80211_hw *hw, 1177 const struct cfg80211_sar_specs *sar); 1178 int mt76_get_sar_power(struct mt76_phy *phy, 1179 struct ieee80211_channel *chan, 1180 int power); 1181 1182 void mt76_csa_check(struct mt76_dev *dev); 1183 void mt76_csa_finish(struct mt76_dev *dev); 1184 1185 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1186 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1187 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1188 int mt76_get_rate(struct mt76_dev *dev, 1189 struct ieee80211_supported_band *sband, 1190 int idx, bool cck); 1191 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1192 const u8 *mac); 1193 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1194 struct ieee80211_vif *vif); 1195 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1196 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1197 void *data, int len); 1198 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1199 struct netlink_callback *cb, void *data, int len); 1200 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1201 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1202 1203 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1204 { 1205 #ifdef CONFIG_NL80211_TESTMODE 1206 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1207 1208 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1209 state = MT76_TM_STATE_OFF; 1210 1211 mt76_testmode_set_state(phy, state); 1212 #endif 1213 } 1214 1215 1216 /* internal */ 1217 static inline struct ieee80211_hw * 1218 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1219 { 1220 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1221 struct ieee80211_hw *hw = dev->phy.hw; 1222 1223 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 1224 hw = dev->phy2->hw; 1225 1226 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 1227 1228 return hw; 1229 } 1230 1231 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1232 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1233 struct napi_struct *napi); 1234 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1235 struct napi_struct *napi); 1236 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1237 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1238 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1239 struct mt76_queue_entry *e); 1240 1241 /* usb */ 1242 static inline bool mt76u_urb_error(struct urb *urb) 1243 { 1244 return urb->status && 1245 urb->status != -ECONNRESET && 1246 urb->status != -ESHUTDOWN && 1247 urb->status != -ENOENT; 1248 } 1249 1250 /* Map hardware queues to usb endpoints */ 1251 static inline u8 q2ep(u8 qid) 1252 { 1253 /* TODO: take management packets to queue 5 */ 1254 return qid + 1; 1255 } 1256 1257 static inline int 1258 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1259 int timeout, int ep) 1260 { 1261 struct usb_interface *uintf = to_usb_interface(dev->dev); 1262 struct usb_device *udev = interface_to_usbdev(uintf); 1263 struct mt76_usb *usb = &dev->usb; 1264 unsigned int pipe; 1265 1266 if (actual_len) 1267 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1268 else 1269 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1270 1271 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1272 } 1273 1274 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1275 struct mt76_sta_stats *stats); 1276 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1277 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1278 u16 val, u16 offset, void *buf, size_t len); 1279 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1280 u8 req_type, u16 val, u16 offset, 1281 void *buf, size_t len); 1282 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1283 const u16 offset, const u32 val); 1284 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1285 void *data, int len); 1286 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1287 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1288 u32 addr, u32 val); 1289 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1290 struct mt76_bus_ops *ops); 1291 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1292 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1293 int mt76u_alloc_queues(struct mt76_dev *dev); 1294 void mt76u_stop_tx(struct mt76_dev *dev); 1295 void mt76u_stop_rx(struct mt76_dev *dev); 1296 int mt76u_resume_rx(struct mt76_dev *dev); 1297 void mt76u_queues_deinit(struct mt76_dev *dev); 1298 1299 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1300 const struct mt76_bus_ops *bus_ops); 1301 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1302 int mt76s_alloc_tx(struct mt76_dev *dev); 1303 void mt76s_deinit(struct mt76_dev *dev); 1304 void mt76s_sdio_irq(struct sdio_func *func); 1305 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1306 bool mt76s_txqs_empty(struct mt76_dev *dev); 1307 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1308 int hw_ver); 1309 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1310 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1311 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1312 u32 mt76s_read_pcr(struct mt76_dev *dev); 1313 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1314 const void *data, int len); 1315 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1316 void *data, int len); 1317 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1318 const struct mt76_reg_pair *data, 1319 int len); 1320 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1321 struct mt76_reg_pair *data, int len); 1322 1323 struct sk_buff * 1324 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1325 int data_len); 1326 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1327 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1328 unsigned long expires); 1329 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1330 int len, bool wait_resp, struct sk_buff **ret); 1331 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1332 int cmd, bool wait_resp, struct sk_buff **ret); 1333 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1334 int len, int max_len); 1335 static inline int 1336 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1337 int len) 1338 { 1339 int max_len = 4096 - dev->mcu_ops->headroom; 1340 1341 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1342 } 1343 1344 static inline int 1345 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1346 bool wait_resp) 1347 { 1348 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1349 } 1350 1351 static inline int 1352 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1353 bool wait_resp) 1354 { 1355 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1356 } 1357 1358 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1359 1360 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1361 struct ieee80211_channel *chan, 1362 struct mt76_power_limits *dest, 1363 s8 target_power); 1364 1365 struct mt76_txwi_cache * 1366 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1367 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1368 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1369 1370 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1371 { 1372 spin_lock_bh(&dev->token_lock); 1373 __mt76_set_tx_blocked(dev, blocked); 1374 spin_unlock_bh(&dev->token_lock); 1375 } 1376 1377 static inline int 1378 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1379 { 1380 int token; 1381 1382 spin_lock_bh(&dev->token_lock); 1383 token = idr_alloc(&dev->token, *ptxwi, 0, dev->drv->token_size, 1384 GFP_ATOMIC); 1385 spin_unlock_bh(&dev->token_lock); 1386 1387 return token; 1388 } 1389 1390 static inline struct mt76_txwi_cache * 1391 mt76_token_put(struct mt76_dev *dev, int token) 1392 { 1393 struct mt76_txwi_cache *txwi; 1394 1395 spin_lock_bh(&dev->token_lock); 1396 txwi = idr_remove(&dev->token, token); 1397 spin_unlock_bh(&dev->token_lock); 1398 1399 return txwi; 1400 } 1401 1402 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1403 { 1404 INIT_LIST_HEAD(&wcid->list); 1405 idr_init(&wcid->pktid); 1406 } 1407 1408 static inline void 1409 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1410 { 1411 struct sk_buff_head list; 1412 1413 mt76_tx_status_lock(dev, &list); 1414 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1415 mt76_tx_status_unlock(dev, &list); 1416 1417 idr_destroy(&wcid->pktid); 1418 } 1419 1420 #endif 1421