1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 19 #define MT_TX_RING_SIZE 256 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 struct mt76_dev; 25 struct mt76_phy; 26 struct mt76_wcid; 27 28 struct mt76_reg_pair { 29 u32 reg; 30 u32 value; 31 }; 32 33 enum mt76_bus_type { 34 MT76_BUS_MMIO, 35 MT76_BUS_USB, 36 }; 37 38 struct mt76_bus_ops { 39 u32 (*rr)(struct mt76_dev *dev, u32 offset); 40 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 41 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 42 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 43 int len); 44 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 45 int len); 46 int (*wr_rp)(struct mt76_dev *dev, u32 base, 47 const struct mt76_reg_pair *rp, int len); 48 int (*rd_rp)(struct mt76_dev *dev, u32 base, 49 struct mt76_reg_pair *rp, int len); 50 enum mt76_bus_type type; 51 }; 52 53 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 54 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 55 56 enum mt76_txq_id { 57 MT_TXQ_VO = IEEE80211_AC_VO, 58 MT_TXQ_VI = IEEE80211_AC_VI, 59 MT_TXQ_BE = IEEE80211_AC_BE, 60 MT_TXQ_BK = IEEE80211_AC_BK, 61 MT_TXQ_PSD, 62 MT_TXQ_MCU, 63 MT_TXQ_MCU_WA, 64 MT_TXQ_BEACON, 65 MT_TXQ_CAB, 66 MT_TXQ_FWDL, 67 __MT_TXQ_MAX 68 }; 69 70 enum mt76_rxq_id { 71 MT_RXQ_MAIN, 72 MT_RXQ_MCU, 73 MT_RXQ_MCU_WA, 74 __MT_RXQ_MAX 75 }; 76 77 struct mt76_queue_buf { 78 dma_addr_t addr; 79 int len; 80 }; 81 82 struct mt76_tx_info { 83 struct mt76_queue_buf buf[32]; 84 struct sk_buff *skb; 85 int nbuf; 86 u32 info; 87 }; 88 89 struct mt76_queue_entry { 90 union { 91 void *buf; 92 struct sk_buff *skb; 93 }; 94 union { 95 struct mt76_txwi_cache *txwi; 96 struct urb *urb; 97 }; 98 enum mt76_txq_id qid; 99 bool skip_buf0:1; 100 bool schedule:1; 101 bool done:1; 102 }; 103 104 struct mt76_queue_regs { 105 u32 desc_base; 106 u32 ring_size; 107 u32 cpu_idx; 108 u32 dma_idx; 109 } __packed __aligned(4); 110 111 struct mt76_queue { 112 struct mt76_queue_regs __iomem *regs; 113 114 spinlock_t lock; 115 struct mt76_queue_entry *entry; 116 struct mt76_desc *desc; 117 118 u16 first; 119 u16 head; 120 u16 tail; 121 int ndesc; 122 int queued; 123 int buf_size; 124 bool stopped; 125 126 u8 buf_offset; 127 u8 hw_idx; 128 129 dma_addr_t desc_dma; 130 struct sk_buff *rx_head; 131 struct page_frag_cache rx_page; 132 }; 133 134 struct mt76_sw_queue { 135 struct mt76_queue *q; 136 137 struct list_head swq; 138 int swq_queued; 139 }; 140 141 struct mt76_mcu_ops { 142 u32 headroom; 143 u32 tailroom; 144 145 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 146 int len, bool wait_resp); 147 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 148 int cmd, bool wait_resp); 149 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 150 const struct mt76_reg_pair *rp, int len); 151 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 152 struct mt76_reg_pair *rp, int len); 153 int (*mcu_restart)(struct mt76_dev *dev); 154 }; 155 156 struct mt76_queue_ops { 157 int (*init)(struct mt76_dev *dev); 158 159 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 160 int idx, int n_desc, int bufsize, 161 u32 ring_base); 162 163 int (*tx_queue_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 164 struct sk_buff *skb, struct mt76_wcid *wcid, 165 struct ieee80211_sta *sta); 166 167 int (*tx_queue_skb_raw)(struct mt76_dev *dev, enum mt76_txq_id qid, 168 struct sk_buff *skb, u32 tx_info); 169 170 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 171 int *len, u32 *info, bool *more); 172 173 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 174 175 void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, 176 bool flush); 177 178 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 179 }; 180 181 enum mt76_wcid_flags { 182 MT_WCID_FLAG_CHECK_PS, 183 MT_WCID_FLAG_PS, 184 }; 185 186 #define MT76_N_WCIDS 288 187 188 /* stored in ieee80211_tx_info::hw_queue */ 189 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 190 191 DECLARE_EWMA(signal, 10, 8); 192 193 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 194 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 195 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 196 #define MT_WCID_TX_INFO_SET BIT(31) 197 198 struct mt76_wcid { 199 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 200 201 unsigned long flags; 202 203 struct ewma_signal rssi; 204 int inactive_count; 205 206 u16 idx; 207 u8 hw_key_idx; 208 209 u8 sta:1; 210 u8 ext_phy:1; 211 212 u8 rx_check_pn; 213 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 214 u16 cipher; 215 216 u32 tx_info; 217 bool sw_iv; 218 219 u8 packet_id; 220 }; 221 222 struct mt76_txq { 223 struct mt76_sw_queue *swq; 224 struct mt76_wcid *wcid; 225 226 struct sk_buff_head retry_q; 227 228 u16 agg_ssn; 229 bool send_bar; 230 bool aggr; 231 }; 232 233 struct mt76_txwi_cache { 234 struct list_head list; 235 dma_addr_t dma_addr; 236 237 struct sk_buff *skb; 238 }; 239 240 struct mt76_rx_tid { 241 struct rcu_head rcu_head; 242 243 struct mt76_dev *dev; 244 245 spinlock_t lock; 246 struct delayed_work reorder_work; 247 248 u16 head; 249 u16 size; 250 u16 nframes; 251 252 u8 num; 253 254 u8 started:1, stopped:1, timer_pending:1; 255 256 struct sk_buff *reorder_buf[]; 257 }; 258 259 #define MT_TX_CB_DMA_DONE BIT(0) 260 #define MT_TX_CB_TXS_DONE BIT(1) 261 #define MT_TX_CB_TXS_FAILED BIT(2) 262 263 #define MT_PACKET_ID_MASK GENMASK(6, 0) 264 #define MT_PACKET_ID_NO_ACK 0 265 #define MT_PACKET_ID_NO_SKB 1 266 #define MT_PACKET_ID_FIRST 2 267 #define MT_PACKET_ID_HAS_RATE BIT(7) 268 269 #define MT_TX_STATUS_SKB_TIMEOUT HZ 270 271 struct mt76_tx_cb { 272 unsigned long jiffies; 273 u16 wcid; 274 u8 pktid; 275 u8 flags; 276 }; 277 278 enum { 279 MT76_STATE_INITIALIZED, 280 MT76_STATE_RUNNING, 281 MT76_STATE_MCU_RUNNING, 282 MT76_SCANNING, 283 MT76_HW_SCANNING, 284 MT76_HW_SCHED_SCANNING, 285 MT76_RESTART, 286 MT76_RESET, 287 MT76_MCU_RESET, 288 MT76_REMOVED, 289 MT76_READING_STATS, 290 MT76_STATE_POWER_OFF, 291 MT76_STATE_SUSPEND, 292 MT76_STATE_ROC, 293 }; 294 295 struct mt76_hw_cap { 296 bool has_2ghz; 297 bool has_5ghz; 298 }; 299 300 #define MT_DRV_TXWI_NO_FREE BIT(0) 301 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 302 #define MT_DRV_SW_RX_AIRTIME BIT(2) 303 #define MT_DRV_RX_DMA_HDR BIT(3) 304 305 struct mt76_driver_ops { 306 u32 drv_flags; 307 u32 survey_flags; 308 u16 txwi_size; 309 310 void (*update_survey)(struct mt76_dev *dev); 311 312 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 313 enum mt76_txq_id qid, struct mt76_wcid *wcid, 314 struct ieee80211_sta *sta, 315 struct mt76_tx_info *tx_info); 316 317 void (*tx_complete_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 318 struct mt76_queue_entry *e); 319 320 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 321 322 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 323 struct sk_buff *skb); 324 325 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 326 327 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 328 bool ps); 329 330 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 331 struct ieee80211_sta *sta); 332 333 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 334 struct ieee80211_sta *sta); 335 336 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 337 struct ieee80211_sta *sta); 338 }; 339 340 struct mt76_channel_state { 341 u64 cc_active; 342 u64 cc_busy; 343 u64 cc_rx; 344 u64 cc_bss_rx; 345 u64 cc_tx; 346 347 s8 noise; 348 }; 349 350 struct mt76_sband { 351 struct ieee80211_supported_band sband; 352 struct mt76_channel_state *chan; 353 }; 354 355 struct mt76_rate_power { 356 union { 357 struct { 358 s8 cck[4]; 359 s8 ofdm[8]; 360 s8 stbc[10]; 361 s8 ht[16]; 362 s8 vht[10]; 363 }; 364 s8 all[48]; 365 }; 366 }; 367 368 /* addr req mask */ 369 #define MT_VEND_TYPE_EEPROM BIT(31) 370 #define MT_VEND_TYPE_CFG BIT(30) 371 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 372 373 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 374 enum mt_vendor_req { 375 MT_VEND_DEV_MODE = 0x1, 376 MT_VEND_WRITE = 0x2, 377 MT_VEND_POWER_ON = 0x4, 378 MT_VEND_MULTI_WRITE = 0x6, 379 MT_VEND_MULTI_READ = 0x7, 380 MT_VEND_READ_EEPROM = 0x9, 381 MT_VEND_WRITE_FCE = 0x42, 382 MT_VEND_WRITE_CFG = 0x46, 383 MT_VEND_READ_CFG = 0x47, 384 MT_VEND_READ_EXT = 0x63, 385 MT_VEND_WRITE_EXT = 0x66, 386 MT_VEND_FEATURE_SET = 0x91, 387 }; 388 389 enum mt76u_in_ep { 390 MT_EP_IN_PKT_RX, 391 MT_EP_IN_CMD_RESP, 392 __MT_EP_IN_MAX, 393 }; 394 395 enum mt76u_out_ep { 396 MT_EP_OUT_INBAND_CMD, 397 MT_EP_OUT_AC_BE, 398 MT_EP_OUT_AC_BK, 399 MT_EP_OUT_AC_VI, 400 MT_EP_OUT_AC_VO, 401 MT_EP_OUT_HCCA, 402 __MT_EP_OUT_MAX, 403 }; 404 405 struct mt76_mcu { 406 struct mutex mutex; 407 u32 msg_seq; 408 409 struct sk_buff_head res_q; 410 wait_queue_head_t wait; 411 }; 412 413 #define MT_TX_SG_MAX_SIZE 8 414 #define MT_RX_SG_MAX_SIZE 4 415 #define MT_NUM_TX_ENTRIES 256 416 #define MT_NUM_RX_ENTRIES 128 417 #define MCU_RESP_URB_SIZE 1024 418 struct mt76_usb { 419 struct mutex usb_ctrl_mtx; 420 u8 *data; 421 u16 data_len; 422 423 struct tasklet_struct rx_tasklet; 424 struct workqueue_struct *wq; 425 struct work_struct stat_work; 426 427 u8 out_ep[__MT_EP_OUT_MAX]; 428 u8 in_ep[__MT_EP_IN_MAX]; 429 bool sg_en; 430 431 struct mt76u_mcu { 432 u8 *data; 433 /* multiple reads */ 434 struct mt76_reg_pair *rp; 435 int rp_len; 436 u32 base; 437 bool burst; 438 } mcu; 439 }; 440 441 struct mt76_mmio { 442 void __iomem *regs; 443 spinlock_t irq_lock; 444 u32 irqmask; 445 }; 446 447 struct mt76_rx_status { 448 union { 449 struct mt76_wcid *wcid; 450 u16 wcid_idx; 451 }; 452 453 unsigned long reorder_time; 454 455 u32 ampdu_ref; 456 457 u8 iv[6]; 458 459 u8 ext_phy:1; 460 u8 aggr:1; 461 u8 tid; 462 u16 seqno; 463 464 u16 freq; 465 u32 flag; 466 u8 enc_flags; 467 u8 encoding:2, bw:3, he_ru:3; 468 u8 he_gi:2, he_dcm:1; 469 u8 rate_idx; 470 u8 nss; 471 u8 band; 472 s8 signal; 473 u8 chains; 474 s8 chain_signal[IEEE80211_MAX_CHAINS]; 475 }; 476 477 struct mt76_phy { 478 struct ieee80211_hw *hw; 479 struct mt76_dev *dev; 480 void *priv; 481 482 unsigned long state; 483 484 struct cfg80211_chan_def chandef; 485 struct ieee80211_channel *main_chan; 486 487 struct mt76_channel_state *chan_state; 488 ktime_t survey_time; 489 490 struct mt76_sband sband_2g; 491 struct mt76_sband sband_5g; 492 493 int txpower_cur; 494 u8 antenna_mask; 495 }; 496 497 struct mt76_dev { 498 struct mt76_phy phy; /* must be first */ 499 500 struct mt76_phy *phy2; 501 502 struct ieee80211_hw *hw; 503 504 spinlock_t lock; 505 spinlock_t cc_lock; 506 507 u32 cur_cc_bss_rx; 508 509 struct mt76_rx_status rx_ampdu_status; 510 u32 rx_ampdu_len; 511 u32 rx_ampdu_ref; 512 513 struct mutex mutex; 514 515 const struct mt76_bus_ops *bus; 516 const struct mt76_driver_ops *drv; 517 const struct mt76_mcu_ops *mcu_ops; 518 struct device *dev; 519 520 struct mt76_mcu mcu; 521 522 struct net_device napi_dev; 523 spinlock_t rx_lock; 524 struct napi_struct napi[__MT_RXQ_MAX]; 525 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 526 527 struct list_head txwi_cache; 528 struct mt76_sw_queue q_tx[2 * __MT_TXQ_MAX]; 529 struct mt76_queue q_rx[__MT_RXQ_MAX]; 530 const struct mt76_queue_ops *queue_ops; 531 int tx_dma_idx[4]; 532 533 struct tasklet_struct tx_tasklet; 534 struct napi_struct tx_napi; 535 struct delayed_work mac_work; 536 537 wait_queue_head_t tx_wait; 538 struct sk_buff_head status_list; 539 540 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 541 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 542 543 struct mt76_wcid global_wcid; 544 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 545 546 u8 macaddr[ETH_ALEN]; 547 u32 rev; 548 549 u32 aggr_stats[32]; 550 551 struct tasklet_struct pre_tbtt_tasklet; 552 int beacon_int; 553 u8 beacon_mask; 554 555 struct debugfs_blob_wrapper eeprom; 556 struct debugfs_blob_wrapper otp; 557 struct mt76_hw_cap cap; 558 559 struct mt76_rate_power rate_power; 560 561 enum nl80211_dfs_regions region; 562 563 u32 debugfs_reg; 564 565 struct led_classdev led_cdev; 566 char led_name[32]; 567 bool led_al; 568 u8 led_pin; 569 570 u8 csa_complete; 571 572 u32 rxfilter; 573 574 union { 575 struct mt76_mmio mmio; 576 struct mt76_usb usb; 577 }; 578 }; 579 580 enum mt76_phy_type { 581 MT_PHY_TYPE_CCK, 582 MT_PHY_TYPE_OFDM, 583 MT_PHY_TYPE_HT, 584 MT_PHY_TYPE_HT_GF, 585 MT_PHY_TYPE_VHT, 586 MT_PHY_TYPE_HE_SU = 8, 587 MT_PHY_TYPE_HE_EXT_SU, 588 MT_PHY_TYPE_HE_TB, 589 MT_PHY_TYPE_HE_MU, 590 }; 591 592 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 593 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 594 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 595 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 596 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 597 598 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 599 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 600 601 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 602 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 603 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 604 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 605 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 606 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 607 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 608 609 #define mt76_mcu_send_msg(dev, ...) (dev)->mt76.mcu_ops->mcu_send_msg(&((dev)->mt76), __VA_ARGS__) 610 611 #define __mt76_mcu_send_msg(dev, ...) (dev)->mcu_ops->mcu_send_msg((dev), __VA_ARGS__) 612 #define __mt76_mcu_skb_send_msg(dev, ...) (dev)->mcu_ops->mcu_skb_send_msg((dev), __VA_ARGS__) 613 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 614 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 615 616 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 617 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 618 619 #define mt76_get_field(_dev, _reg, _field) \ 620 FIELD_GET(_field, mt76_rr(dev, _reg)) 621 622 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 623 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 624 625 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 626 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 627 628 #define mt76_hw(dev) (dev)->mphy.hw 629 630 static inline struct ieee80211_hw * 631 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 632 { 633 if (wcid <= MT76_N_WCIDS && 634 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 635 return dev->phy2->hw; 636 637 return dev->phy.hw; 638 } 639 640 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 641 int timeout); 642 643 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 644 645 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 646 int timeout); 647 648 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 649 650 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 651 void mt76_pci_disable_aspm(struct pci_dev *pdev); 652 653 static inline u16 mt76_chip(struct mt76_dev *dev) 654 { 655 return dev->rev >> 16; 656 } 657 658 static inline u16 mt76_rev(struct mt76_dev *dev) 659 { 660 return dev->rev & 0xffff; 661 } 662 663 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 664 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 665 666 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 667 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 668 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 669 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 670 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 671 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 672 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 673 674 #define mt76_for_each_q_rx(dev, i) \ 675 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 676 (dev)->q_rx[i].ndesc; i++) 677 678 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 679 const struct ieee80211_ops *ops, 680 const struct mt76_driver_ops *drv_ops); 681 int mt76_register_device(struct mt76_dev *dev, bool vht, 682 struct ieee80211_rate *rates, int n_rates); 683 void mt76_unregister_device(struct mt76_dev *dev); 684 void mt76_free_device(struct mt76_dev *dev); 685 void mt76_unregister_phy(struct mt76_phy *phy); 686 687 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 688 const struct ieee80211_ops *ops); 689 int mt76_register_phy(struct mt76_phy *phy); 690 691 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 692 int mt76_queues_read(struct seq_file *s, void *data); 693 void mt76_seq_puts_array(struct seq_file *file, const char *str, 694 s8 *val, int len); 695 696 int mt76_eeprom_init(struct mt76_dev *dev, int len); 697 void mt76_eeprom_override(struct mt76_dev *dev); 698 699 static inline struct mt76_phy * 700 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 701 { 702 if (phy_ext && dev->phy2) 703 return dev->phy2; 704 return &dev->phy; 705 } 706 707 static inline struct ieee80211_hw * 708 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 709 { 710 return mt76_dev_phy(dev, phy_ext)->hw; 711 } 712 713 static inline u8 * 714 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 715 { 716 return (u8 *)t - dev->drv->txwi_size; 717 } 718 719 /* increment with wrap-around */ 720 static inline int mt76_incr(int val, int size) 721 { 722 return (val + 1) & (size - 1); 723 } 724 725 /* decrement with wrap-around */ 726 static inline int mt76_decr(int val, int size) 727 { 728 return (val - 1) & (size - 1); 729 } 730 731 u8 mt76_ac_to_hwq(u8 ac); 732 733 static inline struct ieee80211_txq * 734 mtxq_to_txq(struct mt76_txq *mtxq) 735 { 736 void *ptr = mtxq; 737 738 return container_of(ptr, struct ieee80211_txq, drv_priv); 739 } 740 741 static inline struct ieee80211_sta * 742 wcid_to_sta(struct mt76_wcid *wcid) 743 { 744 void *ptr = wcid; 745 746 if (!wcid || !wcid->sta) 747 return NULL; 748 749 return container_of(ptr, struct ieee80211_sta, drv_priv); 750 } 751 752 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 753 { 754 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 755 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 756 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 757 } 758 759 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 760 { 761 struct mt76_rx_status mstat; 762 u8 *data = skb->data; 763 764 /* Alignment concerns */ 765 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 766 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 767 768 mstat = *((struct mt76_rx_status *)skb->cb); 769 770 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 771 data += sizeof(struct ieee80211_radiotap_he); 772 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 773 data += sizeof(struct ieee80211_radiotap_he_mu); 774 775 return data; 776 } 777 778 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 779 { 780 int len = ieee80211_get_hdrlen_from_skb(skb); 781 782 if (len % 4 == 0) 783 return; 784 785 skb_push(skb, 2); 786 memmove(skb->data, skb->data + 2, len); 787 788 skb->data[len] = 0; 789 skb->data[len + 1] = 0; 790 } 791 792 static inline bool mt76_is_skb_pktid(u8 pktid) 793 { 794 if (pktid & MT_PACKET_ID_HAS_RATE) 795 return false; 796 797 return pktid >= MT_PACKET_ID_FIRST; 798 } 799 800 static inline u8 mt76_tx_power_nss_delta(u8 nss) 801 { 802 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 803 804 return nss_delta[nss - 1]; 805 } 806 807 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 808 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 809 struct mt76_wcid *wcid, struct sk_buff *skb); 810 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq); 811 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq); 812 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 813 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 814 bool send_bar); 815 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 816 void mt76_txq_schedule_all(struct mt76_phy *phy); 817 void mt76_tx_tasklet(unsigned long data); 818 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 819 struct ieee80211_sta *sta, 820 u16 tids, int nframes, 821 enum ieee80211_frame_release_type reason, 822 bool more_data); 823 bool mt76_has_tx_pending(struct mt76_phy *phy); 824 void mt76_set_channel(struct mt76_phy *phy); 825 void mt76_update_survey(struct mt76_dev *dev); 826 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 827 struct survey_info *survey); 828 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 829 830 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 831 u16 ssn, u16 size); 832 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 833 834 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 835 struct ieee80211_key_conf *key); 836 837 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 838 __acquires(&dev->status_list.lock); 839 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 840 __releases(&dev->status_list.lock); 841 842 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 843 struct sk_buff *skb); 844 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 845 struct mt76_wcid *wcid, int pktid, 846 struct sk_buff_head *list); 847 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 848 struct sk_buff_head *list); 849 void mt76_tx_complete_skb(struct mt76_dev *dev, struct sk_buff *skb); 850 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 851 bool flush); 852 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 853 struct ieee80211_sta *sta, 854 enum ieee80211_sta_state old_state, 855 enum ieee80211_sta_state new_state); 856 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 857 struct ieee80211_sta *sta); 858 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 859 struct ieee80211_sta *sta); 860 861 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 862 863 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 864 int *dbm); 865 866 void mt76_csa_check(struct mt76_dev *dev); 867 void mt76_csa_finish(struct mt76_dev *dev); 868 869 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 870 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 871 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 872 int mt76_get_rate(struct mt76_dev *dev, 873 struct ieee80211_supported_band *sband, 874 int idx, bool cck); 875 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 876 const u8 *mac); 877 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 878 struct ieee80211_vif *vif); 879 880 /* internal */ 881 static inline struct ieee80211_hw * 882 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 883 { 884 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 885 struct ieee80211_hw *hw = dev->phy.hw; 886 887 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 888 hw = dev->phy2->hw; 889 890 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 891 892 return hw; 893 } 894 895 void mt76_tx_free(struct mt76_dev *dev); 896 struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev); 897 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 898 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 899 struct napi_struct *napi); 900 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 901 struct napi_struct *napi); 902 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 903 904 /* usb */ 905 static inline bool mt76u_urb_error(struct urb *urb) 906 { 907 return urb->status && 908 urb->status != -ECONNRESET && 909 urb->status != -ESHUTDOWN && 910 urb->status != -ENOENT; 911 } 912 913 /* Map hardware queues to usb endpoints */ 914 static inline u8 q2ep(u8 qid) 915 { 916 /* TODO: take management packets to queue 5 */ 917 return qid + 1; 918 } 919 920 static inline int 921 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 922 int timeout, int ep) 923 { 924 struct usb_interface *uintf = to_usb_interface(dev->dev); 925 struct usb_device *udev = interface_to_usbdev(uintf); 926 struct mt76_usb *usb = &dev->usb; 927 unsigned int pipe; 928 929 if (actual_len) 930 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 931 else 932 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 933 934 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 935 } 936 937 int mt76u_skb_dma_info(struct sk_buff *skb, u32 info); 938 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 939 u8 req_type, u16 val, u16 offset, 940 void *buf, size_t len); 941 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 942 const u16 offset, const u32 val); 943 void mt76u_deinit(struct mt76_dev *dev); 944 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 945 bool ext); 946 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 947 int mt76u_alloc_queues(struct mt76_dev *dev); 948 void mt76u_stop_tx(struct mt76_dev *dev); 949 void mt76u_stop_rx(struct mt76_dev *dev); 950 int mt76u_resume_rx(struct mt76_dev *dev); 951 void mt76u_queues_deinit(struct mt76_dev *dev); 952 953 struct sk_buff * 954 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 955 int data_len); 956 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 957 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 958 unsigned long expires); 959 960 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 961 962 #endif 963