1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __MT76_H 18 #define __MT76_H 19 20 #include <linux/kernel.h> 21 #include <linux/io.h> 22 #include <linux/spinlock.h> 23 #include <linux/skbuff.h> 24 #include <linux/leds.h> 25 #include <linux/usb.h> 26 #include <net/mac80211.h> 27 #include "util.h" 28 29 #define MT_TX_RING_SIZE 256 30 #define MT_MCU_RING_SIZE 32 31 #define MT_RX_BUF_SIZE 2048 32 33 struct mt76_dev; 34 struct mt76_wcid; 35 36 struct mt76_reg_pair { 37 u32 reg; 38 u32 value; 39 }; 40 41 enum mt76_bus_type { 42 MT76_BUS_MMIO, 43 MT76_BUS_USB, 44 }; 45 46 struct mt76_bus_ops { 47 u32 (*rr)(struct mt76_dev *dev, u32 offset); 48 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 49 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 50 void (*copy)(struct mt76_dev *dev, u32 offset, const void *data, 51 int len); 52 int (*wr_rp)(struct mt76_dev *dev, u32 base, 53 const struct mt76_reg_pair *rp, int len); 54 int (*rd_rp)(struct mt76_dev *dev, u32 base, 55 struct mt76_reg_pair *rp, int len); 56 enum mt76_bus_type type; 57 }; 58 59 #define mt76_is_usb(dev) ((dev)->mt76.bus->type == MT76_BUS_USB) 60 #define mt76_is_mmio(dev) ((dev)->mt76.bus->type == MT76_BUS_MMIO) 61 62 enum mt76_txq_id { 63 MT_TXQ_VO = IEEE80211_AC_VO, 64 MT_TXQ_VI = IEEE80211_AC_VI, 65 MT_TXQ_BE = IEEE80211_AC_BE, 66 MT_TXQ_BK = IEEE80211_AC_BK, 67 MT_TXQ_PSD, 68 MT_TXQ_MCU, 69 MT_TXQ_BEACON, 70 MT_TXQ_CAB, 71 __MT_TXQ_MAX 72 }; 73 74 enum mt76_rxq_id { 75 MT_RXQ_MAIN, 76 MT_RXQ_MCU, 77 __MT_RXQ_MAX 78 }; 79 80 struct mt76_queue_buf { 81 dma_addr_t addr; 82 int len; 83 }; 84 85 struct mt76u_buf { 86 struct mt76_dev *dev; 87 struct urb *urb; 88 size_t len; 89 bool done; 90 }; 91 92 struct mt76_queue_entry { 93 union { 94 void *buf; 95 struct sk_buff *skb; 96 }; 97 union { 98 struct mt76_txwi_cache *txwi; 99 struct mt76u_buf ubuf; 100 }; 101 bool schedule; 102 }; 103 104 struct mt76_queue_regs { 105 u32 desc_base; 106 u32 ring_size; 107 u32 cpu_idx; 108 u32 dma_idx; 109 } __packed __aligned(4); 110 111 struct mt76_queue { 112 struct mt76_queue_regs __iomem *regs; 113 114 spinlock_t lock; 115 struct mt76_queue_entry *entry; 116 struct mt76_desc *desc; 117 118 struct list_head swq; 119 int swq_queued; 120 121 u16 first; 122 u16 head; 123 u16 tail; 124 int ndesc; 125 int queued; 126 int buf_size; 127 128 u8 buf_offset; 129 u8 hw_idx; 130 131 dma_addr_t desc_dma; 132 struct sk_buff *rx_head; 133 struct page_frag_cache rx_page; 134 spinlock_t rx_page_lock; 135 }; 136 137 struct mt76_mcu_ops { 138 struct sk_buff *(*mcu_msg_alloc)(const void *data, int len); 139 int (*mcu_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 140 int cmd, bool wait_resp); 141 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 142 const struct mt76_reg_pair *rp, int len); 143 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 144 struct mt76_reg_pair *rp, int len); 145 }; 146 147 struct mt76_queue_ops { 148 int (*init)(struct mt76_dev *dev); 149 150 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q); 151 152 int (*add_buf)(struct mt76_dev *dev, struct mt76_queue *q, 153 struct mt76_queue_buf *buf, int nbufs, u32 info, 154 struct sk_buff *skb, void *txwi); 155 156 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 157 struct sk_buff *skb, struct mt76_wcid *wcid, 158 struct ieee80211_sta *sta); 159 160 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 161 int *len, u32 *info, bool *more); 162 163 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 164 165 void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, 166 bool flush); 167 168 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 169 }; 170 171 enum mt76_wcid_flags { 172 MT_WCID_FLAG_CHECK_PS, 173 MT_WCID_FLAG_PS, 174 }; 175 176 #define MT76_N_WCIDS 128 177 178 struct mt76_wcid { 179 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 180 181 struct work_struct aggr_work; 182 183 unsigned long flags; 184 185 u8 idx; 186 u8 hw_key_idx; 187 188 u8 sta:1; 189 190 u8 rx_check_pn; 191 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 192 193 __le16 tx_rate; 194 bool tx_rate_set; 195 u8 tx_rate_nss; 196 s8 max_txpwr_adj; 197 bool sw_iv; 198 }; 199 200 struct mt76_txq { 201 struct list_head list; 202 struct mt76_queue *hwq; 203 struct mt76_wcid *wcid; 204 205 struct sk_buff_head retry_q; 206 207 u16 agg_ssn; 208 bool send_bar; 209 bool aggr; 210 }; 211 212 struct mt76_txwi_cache { 213 u32 txwi[8]; 214 dma_addr_t dma_addr; 215 struct list_head list; 216 }; 217 218 219 struct mt76_rx_tid { 220 struct rcu_head rcu_head; 221 222 struct mt76_dev *dev; 223 224 spinlock_t lock; 225 struct delayed_work reorder_work; 226 227 u16 head; 228 u8 size; 229 u8 nframes; 230 231 u8 started:1, stopped:1, timer_pending:1; 232 233 struct sk_buff *reorder_buf[]; 234 }; 235 236 enum { 237 MT76_STATE_INITIALIZED, 238 MT76_STATE_RUNNING, 239 MT76_STATE_MCU_RUNNING, 240 MT76_SCANNING, 241 MT76_RESET, 242 MT76_OFFCHANNEL, 243 MT76_REMOVED, 244 MT76_READING_STATS, 245 }; 246 247 struct mt76_hw_cap { 248 bool has_2ghz; 249 bool has_5ghz; 250 }; 251 252 struct mt76_driver_ops { 253 u16 txwi_size; 254 255 void (*update_survey)(struct mt76_dev *dev); 256 257 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 258 struct sk_buff *skb, struct mt76_queue *q, 259 struct mt76_wcid *wcid, 260 struct ieee80211_sta *sta, u32 *tx_info); 261 262 void (*tx_complete_skb)(struct mt76_dev *dev, struct mt76_queue *q, 263 struct mt76_queue_entry *e, bool flush); 264 265 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 266 267 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 268 struct sk_buff *skb); 269 270 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 271 272 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 273 bool ps); 274 }; 275 276 struct mt76_channel_state { 277 u64 cc_active; 278 u64 cc_busy; 279 }; 280 281 struct mt76_sband { 282 struct ieee80211_supported_band sband; 283 struct mt76_channel_state *chan; 284 }; 285 286 struct mt76_rate_power { 287 union { 288 struct { 289 s8 cck[4]; 290 s8 ofdm[8]; 291 s8 stbc[10]; 292 s8 ht[16]; 293 s8 vht[10]; 294 }; 295 s8 all[48]; 296 }; 297 }; 298 299 /* addr req mask */ 300 #define MT_VEND_TYPE_EEPROM BIT(31) 301 #define MT_VEND_TYPE_CFG BIT(30) 302 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 303 304 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 305 enum mt_vendor_req { 306 MT_VEND_DEV_MODE = 0x1, 307 MT_VEND_WRITE = 0x2, 308 MT_VEND_MULTI_WRITE = 0x6, 309 MT_VEND_MULTI_READ = 0x7, 310 MT_VEND_READ_EEPROM = 0x9, 311 MT_VEND_WRITE_FCE = 0x42, 312 MT_VEND_WRITE_CFG = 0x46, 313 MT_VEND_READ_CFG = 0x47, 314 }; 315 316 enum mt76u_in_ep { 317 MT_EP_IN_PKT_RX, 318 MT_EP_IN_CMD_RESP, 319 __MT_EP_IN_MAX, 320 }; 321 322 enum mt76u_out_ep { 323 MT_EP_OUT_INBAND_CMD, 324 MT_EP_OUT_AC_BK, 325 MT_EP_OUT_AC_BE, 326 MT_EP_OUT_AC_VI, 327 MT_EP_OUT_AC_VO, 328 MT_EP_OUT_HCCA, 329 __MT_EP_OUT_MAX, 330 }; 331 332 #define MT_SG_MAX_SIZE 8 333 #define MT_NUM_TX_ENTRIES 256 334 #define MT_NUM_RX_ENTRIES 128 335 #define MCU_RESP_URB_SIZE 1024 336 struct mt76_usb { 337 struct mutex usb_ctrl_mtx; 338 u8 data[32]; 339 340 struct tasklet_struct rx_tasklet; 341 struct tasklet_struct tx_tasklet; 342 struct delayed_work stat_work; 343 344 u8 out_ep[__MT_EP_OUT_MAX]; 345 u16 out_max_packet; 346 u8 in_ep[__MT_EP_IN_MAX]; 347 u16 in_max_packet; 348 349 struct mt76u_mcu { 350 struct mutex mutex; 351 struct completion cmpl; 352 struct mt76u_buf res; 353 u32 msg_seq; 354 355 /* multiple reads */ 356 struct mt76_reg_pair *rp; 357 int rp_len; 358 u32 base; 359 bool burst; 360 } mcu; 361 }; 362 363 struct mt76_mmio { 364 struct mt76e_mcu { 365 struct mutex mutex; 366 367 wait_queue_head_t wait; 368 struct sk_buff_head res_q; 369 370 u32 msg_seq; 371 } mcu; 372 void __iomem *regs; 373 spinlock_t irq_lock; 374 u32 irqmask; 375 }; 376 377 struct mt76_dev { 378 struct ieee80211_hw *hw; 379 struct cfg80211_chan_def chandef; 380 struct ieee80211_channel *main_chan; 381 382 spinlock_t lock; 383 spinlock_t cc_lock; 384 385 struct mutex mutex; 386 387 const struct mt76_bus_ops *bus; 388 const struct mt76_driver_ops *drv; 389 const struct mt76_mcu_ops *mcu_ops; 390 struct device *dev; 391 392 struct net_device napi_dev; 393 spinlock_t rx_lock; 394 struct napi_struct napi[__MT_RXQ_MAX]; 395 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 396 397 struct list_head txwi_cache; 398 struct mt76_queue q_tx[__MT_TXQ_MAX]; 399 struct mt76_queue q_rx[__MT_RXQ_MAX]; 400 const struct mt76_queue_ops *queue_ops; 401 402 wait_queue_head_t tx_wait; 403 404 unsigned long wcid_mask[MT76_N_WCIDS / BITS_PER_LONG]; 405 406 struct mt76_wcid global_wcid; 407 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 408 409 u8 macaddr[ETH_ALEN]; 410 u32 rev; 411 unsigned long state; 412 413 u8 antenna_mask; 414 u16 chainmask; 415 416 struct mt76_sband sband_2g; 417 struct mt76_sband sband_5g; 418 struct debugfs_blob_wrapper eeprom; 419 struct debugfs_blob_wrapper otp; 420 struct mt76_hw_cap cap; 421 422 struct mt76_rate_power rate_power; 423 int txpower_conf; 424 int txpower_cur; 425 426 u32 debugfs_reg; 427 428 struct led_classdev led_cdev; 429 char led_name[32]; 430 bool led_al; 431 u8 led_pin; 432 433 u32 rxfilter; 434 435 union { 436 struct mt76_mmio mmio; 437 struct mt76_usb usb; 438 }; 439 }; 440 441 enum mt76_phy_type { 442 MT_PHY_TYPE_CCK, 443 MT_PHY_TYPE_OFDM, 444 MT_PHY_TYPE_HT, 445 MT_PHY_TYPE_HT_GF, 446 MT_PHY_TYPE_VHT, 447 }; 448 449 struct mt76_rx_status { 450 struct mt76_wcid *wcid; 451 452 unsigned long reorder_time; 453 454 u8 iv[6]; 455 456 u8 aggr:1; 457 u8 tid; 458 u16 seqno; 459 460 u16 freq; 461 u32 flag; 462 u8 enc_flags; 463 u8 encoding:2, bw:3; 464 u8 rate_idx; 465 u8 nss; 466 u8 band; 467 u8 signal; 468 u8 chains; 469 s8 chain_signal[IEEE80211_MAX_CHAINS]; 470 }; 471 472 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 473 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 474 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 475 #define __mt76_wr_copy(dev, ...) (dev)->bus->copy((dev), __VA_ARGS__) 476 477 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 478 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 479 480 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 481 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 482 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 483 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->copy(&((dev)->mt76), __VA_ARGS__) 484 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 485 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 486 487 #define mt76_mcu_msg_alloc(dev, ...) (dev)->mt76.mcu_ops->mcu_msg_alloc(__VA_ARGS__) 488 #define mt76_mcu_send_msg(dev, ...) (dev)->mt76.mcu_ops->mcu_send_msg(&((dev)->mt76), __VA_ARGS__) 489 490 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 491 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 492 493 #define mt76_get_field(_dev, _reg, _field) \ 494 FIELD_GET(_field, mt76_rr(dev, _reg)) 495 496 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 497 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 498 499 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 500 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 501 502 #define mt76_hw(dev) (dev)->mt76.hw 503 504 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 505 int timeout); 506 507 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 508 509 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 510 int timeout); 511 512 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 513 514 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 515 516 static inline u16 mt76_chip(struct mt76_dev *dev) 517 { 518 return dev->rev >> 16; 519 } 520 521 static inline u16 mt76_rev(struct mt76_dev *dev) 522 { 523 return dev->rev & 0xffff; 524 } 525 526 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 527 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 528 529 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 530 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 531 #define mt76_queue_add_buf(dev, ...) (dev)->mt76.queue_ops->add_buf(&((dev)->mt76), __VA_ARGS__) 532 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 533 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 534 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 535 536 static inline struct mt76_channel_state * 537 mt76_channel_state(struct mt76_dev *dev, struct ieee80211_channel *c) 538 { 539 struct mt76_sband *msband; 540 int idx; 541 542 if (c->band == NL80211_BAND_2GHZ) 543 msband = &dev->sband_2g; 544 else 545 msband = &dev->sband_5g; 546 547 idx = c - &msband->sband.channels[0]; 548 return &msband->chan[idx]; 549 } 550 551 struct mt76_dev *mt76_alloc_device(unsigned int size, 552 const struct ieee80211_ops *ops); 553 int mt76_register_device(struct mt76_dev *dev, bool vht, 554 struct ieee80211_rate *rates, int n_rates); 555 void mt76_unregister_device(struct mt76_dev *dev); 556 557 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 558 void mt76_seq_puts_array(struct seq_file *file, const char *str, 559 s8 *val, int len); 560 561 int mt76_eeprom_init(struct mt76_dev *dev, int len); 562 void mt76_eeprom_override(struct mt76_dev *dev); 563 564 /* increment with wrap-around */ 565 static inline int mt76_incr(int val, int size) 566 { 567 return (val + 1) & (size - 1); 568 } 569 570 /* decrement with wrap-around */ 571 static inline int mt76_decr(int val, int size) 572 { 573 return (val - 1) & (size - 1); 574 } 575 576 u8 mt76_ac_to_hwq(u8 ac); 577 578 static inline struct ieee80211_txq * 579 mtxq_to_txq(struct mt76_txq *mtxq) 580 { 581 void *ptr = mtxq; 582 583 return container_of(ptr, struct ieee80211_txq, drv_priv); 584 } 585 586 static inline struct ieee80211_sta * 587 wcid_to_sta(struct mt76_wcid *wcid) 588 { 589 void *ptr = wcid; 590 591 if (!wcid || !wcid->sta) 592 return NULL; 593 594 return container_of(ptr, struct ieee80211_sta, drv_priv); 595 } 596 597 int mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q, 598 struct sk_buff *skb, struct mt76_wcid *wcid, 599 struct ieee80211_sta *sta); 600 601 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 602 void mt76_tx(struct mt76_dev *dev, struct ieee80211_sta *sta, 603 struct mt76_wcid *wcid, struct sk_buff *skb); 604 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq); 605 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq); 606 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 607 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 608 bool send_bar); 609 void mt76_txq_schedule(struct mt76_dev *dev, struct mt76_queue *hwq); 610 void mt76_txq_schedule_all(struct mt76_dev *dev); 611 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 612 struct ieee80211_sta *sta, 613 u16 tids, int nframes, 614 enum ieee80211_frame_release_type reason, 615 bool more_data); 616 void mt76_set_channel(struct mt76_dev *dev); 617 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 618 struct survey_info *survey); 619 void mt76_set_stream_caps(struct mt76_dev *dev, bool vht); 620 621 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 622 u16 ssn, u8 size); 623 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 624 625 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 626 struct ieee80211_key_conf *key); 627 628 struct ieee80211_sta *mt76_rx_convert(struct sk_buff *skb); 629 630 /* internal */ 631 void mt76_tx_free(struct mt76_dev *dev); 632 struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev); 633 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 634 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 635 struct napi_struct *napi); 636 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 637 struct napi_struct *napi); 638 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 639 640 /* usb */ 641 static inline bool mt76u_urb_error(struct urb *urb) 642 { 643 return urb->status && 644 urb->status != -ECONNRESET && 645 urb->status != -ESHUTDOWN && 646 urb->status != -ENOENT; 647 } 648 649 /* Map hardware queues to usb endpoints */ 650 static inline u8 q2ep(u8 qid) 651 { 652 /* TODO: take management packets to queue 5 */ 653 return qid + 1; 654 } 655 656 static inline bool mt76u_check_sg(struct mt76_dev *dev) 657 { 658 struct usb_interface *intf = to_usb_interface(dev->dev); 659 struct usb_device *udev = interface_to_usbdev(intf); 660 661 return (udev->bus->sg_tablesize > 0 && 662 (udev->bus->no_sg_constraint || 663 udev->speed == USB_SPEED_WIRELESS)); 664 } 665 666 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 667 u8 req_type, u16 val, u16 offset, 668 void *buf, size_t len); 669 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 670 const u16 offset, const u32 val); 671 u32 mt76u_rr(struct mt76_dev *dev, u32 addr); 672 void mt76u_wr(struct mt76_dev *dev, u32 addr, u32 val); 673 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 674 void mt76u_deinit(struct mt76_dev *dev); 675 int mt76u_buf_alloc(struct mt76_dev *dev, struct mt76u_buf *buf, 676 int nsgs, int len, int sglen, gfp_t gfp); 677 void mt76u_buf_free(struct mt76u_buf *buf); 678 int mt76u_submit_buf(struct mt76_dev *dev, int dir, int index, 679 struct mt76u_buf *buf, gfp_t gfp, 680 usb_complete_t complete_fn, void *context); 681 int mt76u_submit_rx_buffers(struct mt76_dev *dev); 682 int mt76u_alloc_queues(struct mt76_dev *dev); 683 void mt76u_stop_queues(struct mt76_dev *dev); 684 void mt76u_stop_stat_wk(struct mt76_dev *dev); 685 void mt76u_queues_deinit(struct mt76_dev *dev); 686 687 void mt76u_mcu_complete_urb(struct urb *urb); 688 int mt76u_mcu_init_rx(struct mt76_dev *dev); 689 void mt76u_mcu_deinit(struct mt76_dev *dev); 690 691 #endif 692