1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 #include "testmode.h" 19 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 #define MT_MAX_NON_AQL_PKT 16 25 #define MT_TXQ_FREE_THR 32 26 27 struct mt76_dev; 28 struct mt76_phy; 29 struct mt76_wcid; 30 31 struct mt76_reg_pair { 32 u32 reg; 33 u32 value; 34 }; 35 36 enum mt76_bus_type { 37 MT76_BUS_MMIO, 38 MT76_BUS_USB, 39 MT76_BUS_SDIO, 40 }; 41 42 struct mt76_bus_ops { 43 u32 (*rr)(struct mt76_dev *dev, u32 offset); 44 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 45 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 46 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 47 int len); 48 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 49 int len); 50 int (*wr_rp)(struct mt76_dev *dev, u32 base, 51 const struct mt76_reg_pair *rp, int len); 52 int (*rd_rp)(struct mt76_dev *dev, u32 base, 53 struct mt76_reg_pair *rp, int len); 54 enum mt76_bus_type type; 55 }; 56 57 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 58 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 59 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 60 61 enum mt76_txq_id { 62 MT_TXQ_VO = IEEE80211_AC_VO, 63 MT_TXQ_VI = IEEE80211_AC_VI, 64 MT_TXQ_BE = IEEE80211_AC_BE, 65 MT_TXQ_BK = IEEE80211_AC_BK, 66 MT_TXQ_PSD, 67 MT_TXQ_BEACON, 68 MT_TXQ_CAB, 69 __MT_TXQ_MAX 70 }; 71 72 enum mt76_mcuq_id { 73 MT_MCUQ_WM, 74 MT_MCUQ_WA, 75 MT_MCUQ_FWDL, 76 __MT_MCUQ_MAX 77 }; 78 79 enum mt76_rxq_id { 80 MT_RXQ_MAIN, 81 MT_RXQ_MCU, 82 MT_RXQ_MCU_WA, 83 MT_RXQ_EXT, 84 MT_RXQ_EXT_WA, 85 __MT_RXQ_MAX 86 }; 87 88 struct mt76_queue_buf { 89 dma_addr_t addr; 90 u16 len; 91 bool skip_unmap; 92 }; 93 94 struct mt76_tx_info { 95 struct mt76_queue_buf buf[32]; 96 struct sk_buff *skb; 97 int nbuf; 98 u32 info; 99 }; 100 101 struct mt76_queue_entry { 102 union { 103 void *buf; 104 struct sk_buff *skb; 105 }; 106 union { 107 struct mt76_txwi_cache *txwi; 108 struct urb *urb; 109 int buf_sz; 110 }; 111 u32 dma_addr[2]; 112 u16 dma_len[2]; 113 u16 wcid; 114 bool skip_buf0:1; 115 bool skip_buf1:1; 116 bool done:1; 117 }; 118 119 struct mt76_queue_regs { 120 u32 desc_base; 121 u32 ring_size; 122 u32 cpu_idx; 123 u32 dma_idx; 124 } __packed __aligned(4); 125 126 struct mt76_queue { 127 struct mt76_queue_regs __iomem *regs; 128 129 spinlock_t lock; 130 spinlock_t cleanup_lock; 131 struct mt76_queue_entry *entry; 132 struct mt76_desc *desc; 133 134 u16 first; 135 u16 head; 136 u16 tail; 137 int ndesc; 138 int queued; 139 int buf_size; 140 bool stopped; 141 bool blocked; 142 143 u8 buf_offset; 144 u8 hw_idx; 145 u8 qid; 146 147 dma_addr_t desc_dma; 148 struct sk_buff *rx_head; 149 struct page_frag_cache rx_page; 150 }; 151 152 struct mt76_mcu_ops { 153 u32 headroom; 154 u32 tailroom; 155 156 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 157 int len, bool wait_resp); 158 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 159 int cmd, int *seq); 160 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 161 struct sk_buff *skb, int seq); 162 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 163 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 164 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 165 const struct mt76_reg_pair *rp, int len); 166 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 167 struct mt76_reg_pair *rp, int len); 168 int (*mcu_restart)(struct mt76_dev *dev); 169 }; 170 171 struct mt76_queue_ops { 172 int (*init)(struct mt76_dev *dev); 173 174 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 175 int idx, int n_desc, int bufsize, 176 u32 ring_base); 177 178 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 179 struct sk_buff *skb, struct mt76_wcid *wcid, 180 struct ieee80211_sta *sta); 181 182 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 183 struct sk_buff *skb, u32 tx_info); 184 185 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 186 int *len, u32 *info, bool *more); 187 188 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 189 190 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 191 bool flush); 192 193 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 194 }; 195 196 enum mt76_wcid_flags { 197 MT_WCID_FLAG_CHECK_PS, 198 MT_WCID_FLAG_PS, 199 MT_WCID_FLAG_4ADDR, 200 }; 201 202 #define MT76_N_WCIDS 288 203 204 /* stored in ieee80211_tx_info::hw_queue */ 205 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 206 207 DECLARE_EWMA(signal, 10, 8); 208 209 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 210 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 211 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 212 #define MT_WCID_TX_INFO_SET BIT(31) 213 214 struct mt76_wcid { 215 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 216 217 atomic_t non_aql_packets; 218 unsigned long flags; 219 220 struct ewma_signal rssi; 221 int inactive_count; 222 223 u16 idx; 224 u8 hw_key_idx; 225 226 u8 sta:1; 227 u8 ext_phy:1; 228 u8 amsdu:1; 229 230 u8 rx_check_pn; 231 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 232 u16 cipher; 233 234 u32 tx_info; 235 bool sw_iv; 236 237 u8 packet_id; 238 }; 239 240 struct mt76_txq { 241 struct mt76_wcid *wcid; 242 243 u16 agg_ssn; 244 bool send_bar; 245 bool aggr; 246 }; 247 248 struct mt76_txwi_cache { 249 struct list_head list; 250 dma_addr_t dma_addr; 251 252 struct sk_buff *skb; 253 }; 254 255 struct mt76_rx_tid { 256 struct rcu_head rcu_head; 257 258 struct mt76_dev *dev; 259 260 spinlock_t lock; 261 struct delayed_work reorder_work; 262 263 u16 head; 264 u16 size; 265 u16 nframes; 266 267 u8 num; 268 269 u8 started:1, stopped:1, timer_pending:1; 270 271 struct sk_buff *reorder_buf[]; 272 }; 273 274 #define MT_TX_CB_DMA_DONE BIT(0) 275 #define MT_TX_CB_TXS_DONE BIT(1) 276 #define MT_TX_CB_TXS_FAILED BIT(2) 277 278 #define MT_PACKET_ID_MASK GENMASK(6, 0) 279 #define MT_PACKET_ID_NO_ACK 0 280 #define MT_PACKET_ID_NO_SKB 1 281 #define MT_PACKET_ID_FIRST 2 282 #define MT_PACKET_ID_HAS_RATE BIT(7) 283 284 #define MT_TX_STATUS_SKB_TIMEOUT HZ 285 286 struct mt76_tx_cb { 287 unsigned long jiffies; 288 u16 wcid; 289 u8 pktid; 290 u8 flags; 291 }; 292 293 enum { 294 MT76_STATE_INITIALIZED, 295 MT76_STATE_RUNNING, 296 MT76_STATE_MCU_RUNNING, 297 MT76_SCANNING, 298 MT76_HW_SCANNING, 299 MT76_HW_SCHED_SCANNING, 300 MT76_RESTART, 301 MT76_RESET, 302 MT76_MCU_RESET, 303 MT76_REMOVED, 304 MT76_READING_STATS, 305 MT76_STATE_POWER_OFF, 306 MT76_STATE_SUSPEND, 307 MT76_STATE_ROC, 308 MT76_STATE_PM, 309 }; 310 311 struct mt76_hw_cap { 312 bool has_2ghz; 313 bool has_5ghz; 314 }; 315 316 #define MT_DRV_TXWI_NO_FREE BIT(0) 317 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 318 #define MT_DRV_SW_RX_AIRTIME BIT(2) 319 #define MT_DRV_RX_DMA_HDR BIT(3) 320 #define MT_DRV_HW_MGMT_TXQ BIT(4) 321 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 322 323 struct mt76_driver_ops { 324 u32 drv_flags; 325 u32 survey_flags; 326 u16 txwi_size; 327 328 void (*update_survey)(struct mt76_dev *dev); 329 330 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 331 enum mt76_txq_id qid, struct mt76_wcid *wcid, 332 struct ieee80211_sta *sta, 333 struct mt76_tx_info *tx_info); 334 335 void (*tx_complete_skb)(struct mt76_dev *dev, 336 struct mt76_queue_entry *e); 337 338 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 339 340 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 341 struct sk_buff *skb); 342 343 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 344 345 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 346 bool ps); 347 348 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 349 struct ieee80211_sta *sta); 350 351 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 352 struct ieee80211_sta *sta); 353 354 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 355 struct ieee80211_sta *sta); 356 }; 357 358 struct mt76_channel_state { 359 u64 cc_active; 360 u64 cc_busy; 361 u64 cc_rx; 362 u64 cc_bss_rx; 363 u64 cc_tx; 364 365 s8 noise; 366 }; 367 368 struct mt76_sband { 369 struct ieee80211_supported_band sband; 370 struct mt76_channel_state *chan; 371 }; 372 373 struct mt76_rate_power { 374 union { 375 struct { 376 s8 cck[4]; 377 s8 ofdm[8]; 378 s8 stbc[10]; 379 s8 ht[16]; 380 s8 vht[10]; 381 }; 382 s8 all[48]; 383 }; 384 }; 385 386 /* addr req mask */ 387 #define MT_VEND_TYPE_EEPROM BIT(31) 388 #define MT_VEND_TYPE_CFG BIT(30) 389 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 390 391 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 392 enum mt_vendor_req { 393 MT_VEND_DEV_MODE = 0x1, 394 MT_VEND_WRITE = 0x2, 395 MT_VEND_POWER_ON = 0x4, 396 MT_VEND_MULTI_WRITE = 0x6, 397 MT_VEND_MULTI_READ = 0x7, 398 MT_VEND_READ_EEPROM = 0x9, 399 MT_VEND_WRITE_FCE = 0x42, 400 MT_VEND_WRITE_CFG = 0x46, 401 MT_VEND_READ_CFG = 0x47, 402 MT_VEND_READ_EXT = 0x63, 403 MT_VEND_WRITE_EXT = 0x66, 404 MT_VEND_FEATURE_SET = 0x91, 405 }; 406 407 enum mt76u_in_ep { 408 MT_EP_IN_PKT_RX, 409 MT_EP_IN_CMD_RESP, 410 __MT_EP_IN_MAX, 411 }; 412 413 enum mt76u_out_ep { 414 MT_EP_OUT_INBAND_CMD, 415 MT_EP_OUT_AC_BE, 416 MT_EP_OUT_AC_BK, 417 MT_EP_OUT_AC_VI, 418 MT_EP_OUT_AC_VO, 419 MT_EP_OUT_HCCA, 420 __MT_EP_OUT_MAX, 421 }; 422 423 struct mt76_mcu { 424 struct mutex mutex; 425 u32 msg_seq; 426 int timeout; 427 428 struct sk_buff_head res_q; 429 wait_queue_head_t wait; 430 }; 431 432 #define MT_TX_SG_MAX_SIZE 8 433 #define MT_RX_SG_MAX_SIZE 4 434 #define MT_NUM_TX_ENTRIES 256 435 #define MT_NUM_RX_ENTRIES 128 436 #define MCU_RESP_URB_SIZE 1024 437 struct mt76_usb { 438 struct mutex usb_ctrl_mtx; 439 u8 *data; 440 u16 data_len; 441 442 struct mt76_worker status_worker; 443 struct mt76_worker rx_worker; 444 445 struct work_struct stat_work; 446 447 u8 out_ep[__MT_EP_OUT_MAX]; 448 u8 in_ep[__MT_EP_IN_MAX]; 449 bool sg_en; 450 451 struct mt76u_mcu { 452 u8 *data; 453 /* multiple reads */ 454 struct mt76_reg_pair *rp; 455 int rp_len; 456 u32 base; 457 bool burst; 458 } mcu; 459 }; 460 461 #define MT76S_XMIT_BUF_SZ (16 * PAGE_SIZE) 462 struct mt76_sdio { 463 struct mt76_worker txrx_worker; 464 struct mt76_worker status_worker; 465 struct mt76_worker net_worker; 466 467 struct work_struct stat_work; 468 469 u8 *xmit_buf[IEEE80211_NUM_ACS + 2]; 470 471 struct sdio_func *func; 472 void *intr_data; 473 474 struct { 475 int pse_data_quota; 476 int ple_data_quota; 477 int pse_mcu_quota; 478 int deficit; 479 } sched; 480 }; 481 482 struct mt76_mmio { 483 void __iomem *regs; 484 spinlock_t irq_lock; 485 u32 irqmask; 486 }; 487 488 struct mt76_rx_status { 489 union { 490 struct mt76_wcid *wcid; 491 u16 wcid_idx; 492 }; 493 494 unsigned long reorder_time; 495 496 u32 ampdu_ref; 497 498 u8 iv[6]; 499 500 u8 ext_phy:1; 501 u8 aggr:1; 502 u8 tid; 503 u16 seqno; 504 505 u16 freq; 506 u32 flag; 507 u8 enc_flags; 508 u8 encoding:2, bw:3, he_ru:3; 509 u8 he_gi:2, he_dcm:1; 510 u8 rate_idx; 511 u8 nss; 512 u8 band; 513 s8 signal; 514 u8 chains; 515 s8 chain_signal[IEEE80211_MAX_CHAINS]; 516 }; 517 518 struct mt76_testmode_ops { 519 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 520 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 521 enum mt76_testmode_state new_state); 522 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 523 }; 524 525 struct mt76_testmode_data { 526 enum mt76_testmode_state state; 527 528 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 529 struct sk_buff *tx_skb; 530 531 u32 tx_count; 532 u16 tx_msdu_len; 533 534 u8 tx_rate_mode; 535 u8 tx_rate_idx; 536 u8 tx_rate_nss; 537 u8 tx_rate_sgi; 538 u8 tx_rate_ldpc; 539 u8 tx_rate_stbc; 540 u8 tx_ltf; 541 542 u8 tx_antenna_mask; 543 u8 tx_spe_idx; 544 545 u8 tx_duty_cycle; 546 u32 tx_time; 547 u32 tx_ipg; 548 549 u32 freq_offset; 550 551 u8 tx_power[4]; 552 u8 tx_power_control; 553 554 u32 tx_pending; 555 u32 tx_queued; 556 u16 tx_queued_limit; 557 u32 tx_done; 558 struct { 559 u64 packets[__MT_RXQ_MAX]; 560 u64 fcs_error[__MT_RXQ_MAX]; 561 } rx_stats; 562 }; 563 564 struct mt76_vif { 565 u8 idx; 566 u8 omac_idx; 567 u8 band_idx; 568 u8 wmm_idx; 569 u8 scan_seq_num; 570 }; 571 572 struct mt76_phy { 573 struct ieee80211_hw *hw; 574 struct mt76_dev *dev; 575 void *priv; 576 577 unsigned long state; 578 579 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 580 581 struct cfg80211_chan_def chandef; 582 struct ieee80211_channel *main_chan; 583 584 struct mt76_channel_state *chan_state; 585 ktime_t survey_time; 586 587 struct mt76_hw_cap cap; 588 struct mt76_sband sband_2g; 589 struct mt76_sband sband_5g; 590 591 u8 macaddr[ETH_ALEN]; 592 593 int txpower_cur; 594 u8 antenna_mask; 595 u16 chainmask; 596 597 #ifdef CONFIG_NL80211_TESTMODE 598 struct mt76_testmode_data test; 599 #endif 600 601 struct delayed_work mac_work; 602 u8 mac_work_count; 603 }; 604 605 struct mt76_dev { 606 struct mt76_phy phy; /* must be first */ 607 608 struct mt76_phy *phy2; 609 610 struct ieee80211_hw *hw; 611 612 spinlock_t lock; 613 spinlock_t cc_lock; 614 615 u32 cur_cc_bss_rx; 616 617 struct mt76_rx_status rx_ampdu_status; 618 u32 rx_ampdu_len; 619 u32 rx_ampdu_ref; 620 621 struct mutex mutex; 622 623 const struct mt76_bus_ops *bus; 624 const struct mt76_driver_ops *drv; 625 const struct mt76_mcu_ops *mcu_ops; 626 struct device *dev; 627 628 struct mt76_mcu mcu; 629 630 struct net_device napi_dev; 631 spinlock_t rx_lock; 632 struct napi_struct napi[__MT_RXQ_MAX]; 633 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 634 635 struct list_head txwi_cache; 636 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 637 struct mt76_queue q_rx[__MT_RXQ_MAX]; 638 const struct mt76_queue_ops *queue_ops; 639 int tx_dma_idx[4]; 640 641 struct mt76_worker tx_worker; 642 struct napi_struct tx_napi; 643 644 wait_queue_head_t tx_wait; 645 struct sk_buff_head status_list; 646 647 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 648 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 649 650 u32 vif_mask; 651 652 struct mt76_wcid global_wcid; 653 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 654 655 u32 rev; 656 657 u32 aggr_stats[32]; 658 659 struct tasklet_struct pre_tbtt_tasklet; 660 int beacon_int; 661 u8 beacon_mask; 662 663 struct debugfs_blob_wrapper eeprom; 664 struct debugfs_blob_wrapper otp; 665 666 struct mt76_rate_power rate_power; 667 668 char alpha2[3]; 669 enum nl80211_dfs_regions region; 670 671 u32 debugfs_reg; 672 673 struct led_classdev led_cdev; 674 char led_name[32]; 675 bool led_al; 676 u8 led_pin; 677 678 u8 csa_complete; 679 680 u32 rxfilter; 681 682 #ifdef CONFIG_NL80211_TESTMODE 683 const struct mt76_testmode_ops *test_ops; 684 struct { 685 const char *name; 686 u32 offset; 687 } test_mtd; 688 #endif 689 struct workqueue_struct *wq; 690 691 union { 692 struct mt76_mmio mmio; 693 struct mt76_usb usb; 694 struct mt76_sdio sdio; 695 }; 696 }; 697 698 enum mt76_phy_type { 699 MT_PHY_TYPE_CCK, 700 MT_PHY_TYPE_OFDM, 701 MT_PHY_TYPE_HT, 702 MT_PHY_TYPE_HT_GF, 703 MT_PHY_TYPE_VHT, 704 MT_PHY_TYPE_HE_SU = 8, 705 MT_PHY_TYPE_HE_EXT_SU, 706 MT_PHY_TYPE_HE_TB, 707 MT_PHY_TYPE_HE_MU, 708 }; 709 710 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 711 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 712 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 713 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 714 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 715 716 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 717 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 718 719 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 720 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 721 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 722 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 723 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 724 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 725 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 726 727 728 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 729 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 730 731 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 732 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 733 734 #define mt76_get_field(_dev, _reg, _field) \ 735 FIELD_GET(_field, mt76_rr(dev, _reg)) 736 737 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 738 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 739 740 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 741 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 742 743 #define mt76_hw(dev) (dev)->mphy.hw 744 745 static inline struct ieee80211_hw * 746 mt76_wcid_hw(struct mt76_dev *dev, u16 wcid) 747 { 748 if (wcid <= MT76_N_WCIDS && 749 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 750 return dev->phy2->hw; 751 752 return dev->phy.hw; 753 } 754 755 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 756 int timeout); 757 758 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 759 760 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 761 int timeout); 762 763 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 764 765 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 766 void mt76_pci_disable_aspm(struct pci_dev *pdev); 767 768 static inline u16 mt76_chip(struct mt76_dev *dev) 769 { 770 return dev->rev >> 16; 771 } 772 773 static inline u16 mt76_rev(struct mt76_dev *dev) 774 { 775 return dev->rev & 0xffff; 776 } 777 778 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 779 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 780 781 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 782 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 783 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 784 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 785 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 786 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 787 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 788 789 #define mt76_for_each_q_rx(dev, i) \ 790 for (i = 0; i < ARRAY_SIZE((dev)->q_rx) && \ 791 (dev)->q_rx[i].ndesc; i++) 792 793 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 794 const struct ieee80211_ops *ops, 795 const struct mt76_driver_ops *drv_ops); 796 int mt76_register_device(struct mt76_dev *dev, bool vht, 797 struct ieee80211_rate *rates, int n_rates); 798 void mt76_unregister_device(struct mt76_dev *dev); 799 void mt76_free_device(struct mt76_dev *dev); 800 void mt76_unregister_phy(struct mt76_phy *phy); 801 802 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 803 const struct ieee80211_ops *ops); 804 int mt76_register_phy(struct mt76_phy *phy, bool vht, 805 struct ieee80211_rate *rates, int n_rates); 806 807 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 808 int mt76_queues_read(struct seq_file *s, void *data); 809 void mt76_seq_puts_array(struct seq_file *file, const char *str, 810 s8 *val, int len); 811 812 int mt76_eeprom_init(struct mt76_dev *dev, int len); 813 void mt76_eeprom_override(struct mt76_phy *phy); 814 815 struct mt76_queue * 816 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 817 int ring_base); 818 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 819 int n_desc, int ring_base) 820 { 821 struct mt76_queue *q; 822 823 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base); 824 if (IS_ERR(q)) 825 return PTR_ERR(q); 826 827 q->qid = qid; 828 phy->q_tx[qid] = q; 829 830 return 0; 831 } 832 833 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 834 int n_desc, int ring_base) 835 { 836 struct mt76_queue *q; 837 838 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base); 839 if (IS_ERR(q)) 840 return PTR_ERR(q); 841 842 q->qid = __MT_TXQ_MAX + qid; 843 dev->q_mcu[qid] = q; 844 845 return 0; 846 } 847 848 static inline struct mt76_phy * 849 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 850 { 851 if (phy_ext && dev->phy2) 852 return dev->phy2; 853 return &dev->phy; 854 } 855 856 static inline struct ieee80211_hw * 857 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 858 { 859 return mt76_dev_phy(dev, phy_ext)->hw; 860 } 861 862 static inline u8 * 863 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 864 { 865 return (u8 *)t - dev->drv->txwi_size; 866 } 867 868 /* increment with wrap-around */ 869 static inline int mt76_incr(int val, int size) 870 { 871 return (val + 1) & (size - 1); 872 } 873 874 /* decrement with wrap-around */ 875 static inline int mt76_decr(int val, int size) 876 { 877 return (val - 1) & (size - 1); 878 } 879 880 u8 mt76_ac_to_hwq(u8 ac); 881 882 static inline struct ieee80211_txq * 883 mtxq_to_txq(struct mt76_txq *mtxq) 884 { 885 void *ptr = mtxq; 886 887 return container_of(ptr, struct ieee80211_txq, drv_priv); 888 } 889 890 static inline struct ieee80211_sta * 891 wcid_to_sta(struct mt76_wcid *wcid) 892 { 893 void *ptr = wcid; 894 895 if (!wcid || !wcid->sta) 896 return NULL; 897 898 return container_of(ptr, struct ieee80211_sta, drv_priv); 899 } 900 901 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 902 { 903 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 904 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 905 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 906 } 907 908 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 909 { 910 struct mt76_rx_status mstat; 911 u8 *data = skb->data; 912 913 /* Alignment concerns */ 914 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 915 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 916 917 mstat = *((struct mt76_rx_status *)skb->cb); 918 919 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 920 data += sizeof(struct ieee80211_radiotap_he); 921 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 922 data += sizeof(struct ieee80211_radiotap_he_mu); 923 924 return data; 925 } 926 927 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 928 { 929 int len = ieee80211_get_hdrlen_from_skb(skb); 930 931 if (len % 4 == 0) 932 return; 933 934 skb_push(skb, 2); 935 memmove(skb->data, skb->data + 2, len); 936 937 skb->data[len] = 0; 938 skb->data[len + 1] = 0; 939 } 940 941 static inline bool mt76_is_skb_pktid(u8 pktid) 942 { 943 if (pktid & MT_PACKET_ID_HAS_RATE) 944 return false; 945 946 return pktid >= MT_PACKET_ID_FIRST; 947 } 948 949 static inline u8 mt76_tx_power_nss_delta(u8 nss) 950 { 951 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 952 953 return nss_delta[nss - 1]; 954 } 955 956 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 957 { 958 #ifdef CONFIG_NL80211_TESTMODE 959 return phy->test.state != MT76_TM_STATE_OFF; 960 #else 961 return false; 962 #endif 963 } 964 965 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 966 struct sk_buff *skb, 967 struct ieee80211_hw **hw) 968 { 969 #ifdef CONFIG_NL80211_TESTMODE 970 if (skb == dev->phy.test.tx_skb) 971 *hw = dev->phy.hw; 972 else if (dev->phy2 && skb == dev->phy2->test.tx_skb) 973 *hw = dev->phy2->hw; 974 else 975 return false; 976 return true; 977 #else 978 return false; 979 #endif 980 } 981 982 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 983 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 984 struct mt76_wcid *wcid, struct sk_buff *skb); 985 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 986 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 987 bool send_bar); 988 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 989 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 990 void mt76_txq_schedule_all(struct mt76_phy *phy); 991 void mt76_tx_worker(struct mt76_worker *w); 992 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 993 struct ieee80211_sta *sta, 994 u16 tids, int nframes, 995 enum ieee80211_frame_release_type reason, 996 bool more_data); 997 bool mt76_has_tx_pending(struct mt76_phy *phy); 998 void mt76_set_channel(struct mt76_phy *phy); 999 void mt76_update_survey(struct mt76_dev *dev); 1000 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1001 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1002 struct survey_info *survey); 1003 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1004 1005 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1006 u16 ssn, u16 size); 1007 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1008 1009 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1010 struct ieee80211_key_conf *key); 1011 1012 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1013 __acquires(&dev->status_list.lock); 1014 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1015 __releases(&dev->status_list.lock); 1016 1017 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1018 struct sk_buff *skb); 1019 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1020 struct mt76_wcid *wcid, int pktid, 1021 struct sk_buff_head *list); 1022 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1023 struct sk_buff_head *list); 1024 void mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb); 1025 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 1026 bool flush); 1027 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1028 struct ieee80211_sta *sta, 1029 enum ieee80211_sta_state old_state, 1030 enum ieee80211_sta_state new_state); 1031 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1032 struct ieee80211_sta *sta); 1033 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1034 struct ieee80211_sta *sta); 1035 1036 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1037 1038 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1039 int *dbm); 1040 1041 void mt76_csa_check(struct mt76_dev *dev); 1042 void mt76_csa_finish(struct mt76_dev *dev); 1043 1044 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1045 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1046 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1047 int mt76_get_rate(struct mt76_dev *dev, 1048 struct ieee80211_supported_band *sband, 1049 int idx, bool cck); 1050 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1051 const u8 *mac); 1052 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1053 struct ieee80211_vif *vif); 1054 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1055 void *data, int len); 1056 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1057 struct netlink_callback *cb, void *data, int len); 1058 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1059 1060 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1061 { 1062 #ifdef CONFIG_NL80211_TESTMODE 1063 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1064 1065 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1066 state = MT76_TM_STATE_OFF; 1067 1068 mt76_testmode_set_state(phy, state); 1069 #endif 1070 } 1071 1072 1073 /* internal */ 1074 static inline struct ieee80211_hw * 1075 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1076 { 1077 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1078 struct ieee80211_hw *hw = dev->phy.hw; 1079 1080 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 1081 hw = dev->phy2->hw; 1082 1083 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 1084 1085 return hw; 1086 } 1087 1088 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1089 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1090 struct napi_struct *napi); 1091 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1092 struct napi_struct *napi); 1093 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1094 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1095 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1096 struct mt76_queue_entry *e); 1097 1098 /* usb */ 1099 static inline bool mt76u_urb_error(struct urb *urb) 1100 { 1101 return urb->status && 1102 urb->status != -ECONNRESET && 1103 urb->status != -ESHUTDOWN && 1104 urb->status != -ENOENT; 1105 } 1106 1107 /* Map hardware queues to usb endpoints */ 1108 static inline u8 q2ep(u8 qid) 1109 { 1110 /* TODO: take management packets to queue 5 */ 1111 return qid + 1; 1112 } 1113 1114 static inline int 1115 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1116 int timeout, int ep) 1117 { 1118 struct usb_interface *uintf = to_usb_interface(dev->dev); 1119 struct usb_device *udev = interface_to_usbdev(uintf); 1120 struct mt76_usb *usb = &dev->usb; 1121 unsigned int pipe; 1122 1123 if (actual_len) 1124 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1125 else 1126 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1127 1128 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1129 } 1130 1131 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1132 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1133 u8 req_type, u16 val, u16 offset, 1134 void *buf, size_t len); 1135 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1136 const u16 offset, const u32 val); 1137 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1138 bool ext); 1139 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1140 int mt76u_alloc_queues(struct mt76_dev *dev); 1141 void mt76u_stop_tx(struct mt76_dev *dev); 1142 void mt76u_stop_rx(struct mt76_dev *dev); 1143 int mt76u_resume_rx(struct mt76_dev *dev); 1144 void mt76u_queues_deinit(struct mt76_dev *dev); 1145 1146 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1147 const struct mt76_bus_ops *bus_ops); 1148 int mt76s_alloc_queues(struct mt76_dev *dev); 1149 void mt76s_deinit(struct mt76_dev *dev); 1150 1151 struct sk_buff * 1152 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1153 int data_len); 1154 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1155 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1156 unsigned long expires); 1157 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1158 int len, bool wait_resp, struct sk_buff **ret); 1159 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1160 int cmd, bool wait_resp, struct sk_buff **ret); 1161 int mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1162 int len); 1163 static inline int 1164 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1165 bool wait_resp) 1166 { 1167 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1168 } 1169 1170 static inline int 1171 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1172 bool wait_resp) 1173 { 1174 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1175 } 1176 1177 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1178 1179 #endif 1180