1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <net/mac80211.h> 17 #include "util.h" 18 19 #define MT_TX_RING_SIZE 256 20 #define MT_MCU_RING_SIZE 32 21 #define MT_RX_BUF_SIZE 2048 22 #define MT_SKB_HEAD_LEN 128 23 24 struct mt76_dev; 25 struct mt76_phy; 26 struct mt76_wcid; 27 28 struct mt76_reg_pair { 29 u32 reg; 30 u32 value; 31 }; 32 33 enum mt76_bus_type { 34 MT76_BUS_MMIO, 35 MT76_BUS_USB, 36 }; 37 38 struct mt76_bus_ops { 39 u32 (*rr)(struct mt76_dev *dev, u32 offset); 40 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 41 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 42 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 43 int len); 44 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 45 int len); 46 int (*wr_rp)(struct mt76_dev *dev, u32 base, 47 const struct mt76_reg_pair *rp, int len); 48 int (*rd_rp)(struct mt76_dev *dev, u32 base, 49 struct mt76_reg_pair *rp, int len); 50 enum mt76_bus_type type; 51 }; 52 53 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 54 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 55 56 enum mt76_txq_id { 57 MT_TXQ_VO = IEEE80211_AC_VO, 58 MT_TXQ_VI = IEEE80211_AC_VI, 59 MT_TXQ_BE = IEEE80211_AC_BE, 60 MT_TXQ_BK = IEEE80211_AC_BK, 61 MT_TXQ_PSD, 62 MT_TXQ_MCU, 63 MT_TXQ_BEACON, 64 MT_TXQ_CAB, 65 MT_TXQ_FWDL, 66 __MT_TXQ_MAX 67 }; 68 69 enum mt76_rxq_id { 70 MT_RXQ_MAIN, 71 MT_RXQ_MCU, 72 __MT_RXQ_MAX 73 }; 74 75 struct mt76_queue_buf { 76 dma_addr_t addr; 77 int len; 78 }; 79 80 struct mt76_tx_info { 81 struct mt76_queue_buf buf[32]; 82 struct sk_buff *skb; 83 int nbuf; 84 u32 info; 85 }; 86 87 struct mt76_queue_entry { 88 union { 89 void *buf; 90 struct sk_buff *skb; 91 }; 92 union { 93 struct mt76_txwi_cache *txwi; 94 struct urb *urb; 95 }; 96 enum mt76_txq_id qid; 97 bool skip_buf0:1; 98 bool schedule:1; 99 bool done:1; 100 }; 101 102 struct mt76_queue_regs { 103 u32 desc_base; 104 u32 ring_size; 105 u32 cpu_idx; 106 u32 dma_idx; 107 } __packed __aligned(4); 108 109 struct mt76_queue { 110 struct mt76_queue_regs __iomem *regs; 111 112 spinlock_t lock; 113 struct mt76_queue_entry *entry; 114 struct mt76_desc *desc; 115 116 u16 first; 117 u16 head; 118 u16 tail; 119 int ndesc; 120 int queued; 121 int buf_size; 122 bool stopped; 123 124 u8 buf_offset; 125 u8 hw_idx; 126 127 dma_addr_t desc_dma; 128 struct sk_buff *rx_head; 129 struct page_frag_cache rx_page; 130 }; 131 132 struct mt76_sw_queue { 133 struct mt76_queue *q; 134 135 struct list_head swq; 136 int swq_queued; 137 }; 138 139 struct mt76_mcu_ops { 140 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 141 int len, bool wait_resp); 142 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 143 const struct mt76_reg_pair *rp, int len); 144 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 145 struct mt76_reg_pair *rp, int len); 146 int (*mcu_restart)(struct mt76_dev *dev); 147 }; 148 149 struct mt76_queue_ops { 150 int (*init)(struct mt76_dev *dev); 151 152 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 153 int idx, int n_desc, int bufsize, 154 u32 ring_base); 155 156 int (*tx_queue_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 157 struct sk_buff *skb, struct mt76_wcid *wcid, 158 struct ieee80211_sta *sta); 159 160 int (*tx_queue_skb_raw)(struct mt76_dev *dev, enum mt76_txq_id qid, 161 struct sk_buff *skb, u32 tx_info); 162 163 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 164 int *len, u32 *info, bool *more); 165 166 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 167 168 void (*tx_cleanup)(struct mt76_dev *dev, enum mt76_txq_id qid, 169 bool flush); 170 171 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 172 }; 173 174 enum mt76_wcid_flags { 175 MT_WCID_FLAG_CHECK_PS, 176 MT_WCID_FLAG_PS, 177 }; 178 179 #define MT76_N_WCIDS 128 180 181 /* stored in ieee80211_tx_info::hw_queue */ 182 #define MT_TX_HW_QUEUE_EXT_PHY BIT(3) 183 184 DECLARE_EWMA(signal, 10, 8); 185 186 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 187 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 188 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 189 #define MT_WCID_TX_INFO_SET BIT(31) 190 191 struct mt76_wcid { 192 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 193 194 unsigned long flags; 195 196 struct ewma_signal rssi; 197 int inactive_count; 198 199 u8 idx; 200 u8 hw_key_idx; 201 202 u8 sta:1; 203 204 u8 rx_check_pn; 205 u8 rx_key_pn[IEEE80211_NUM_TIDS][6]; 206 u16 cipher; 207 208 u32 tx_info; 209 bool sw_iv; 210 211 u8 packet_id; 212 }; 213 214 struct mt76_txq { 215 struct mt76_sw_queue *swq; 216 struct mt76_wcid *wcid; 217 218 struct sk_buff_head retry_q; 219 220 u16 agg_ssn; 221 bool send_bar; 222 bool aggr; 223 }; 224 225 struct mt76_txwi_cache { 226 struct list_head list; 227 dma_addr_t dma_addr; 228 229 struct sk_buff *skb; 230 }; 231 232 struct mt76_rx_tid { 233 struct rcu_head rcu_head; 234 235 struct mt76_dev *dev; 236 237 spinlock_t lock; 238 struct delayed_work reorder_work; 239 240 u16 head; 241 u8 size; 242 u8 nframes; 243 244 u8 started:1, stopped:1, timer_pending:1; 245 246 struct sk_buff *reorder_buf[]; 247 }; 248 249 #define MT_TX_CB_DMA_DONE BIT(0) 250 #define MT_TX_CB_TXS_DONE BIT(1) 251 #define MT_TX_CB_TXS_FAILED BIT(2) 252 253 #define MT_PACKET_ID_MASK GENMASK(6, 0) 254 #define MT_PACKET_ID_NO_ACK 0 255 #define MT_PACKET_ID_NO_SKB 1 256 #define MT_PACKET_ID_FIRST 2 257 #define MT_PACKET_ID_HAS_RATE BIT(7) 258 259 #define MT_TX_STATUS_SKB_TIMEOUT HZ 260 261 struct mt76_tx_cb { 262 unsigned long jiffies; 263 u8 wcid; 264 u8 pktid; 265 u8 flags; 266 }; 267 268 enum { 269 MT76_STATE_INITIALIZED, 270 MT76_STATE_RUNNING, 271 MT76_STATE_MCU_RUNNING, 272 MT76_SCANNING, 273 MT76_RESET, 274 MT76_REMOVED, 275 MT76_READING_STATS, 276 }; 277 278 struct mt76_hw_cap { 279 bool has_2ghz; 280 bool has_5ghz; 281 }; 282 283 #define MT_DRV_TXWI_NO_FREE BIT(0) 284 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 285 #define MT_DRV_SW_RX_AIRTIME BIT(2) 286 287 struct mt76_driver_ops { 288 u32 drv_flags; 289 u32 survey_flags; 290 u16 txwi_size; 291 292 void (*update_survey)(struct mt76_dev *dev); 293 294 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 295 enum mt76_txq_id qid, struct mt76_wcid *wcid, 296 struct ieee80211_sta *sta, 297 struct mt76_tx_info *tx_info); 298 299 void (*tx_complete_skb)(struct mt76_dev *dev, enum mt76_txq_id qid, 300 struct mt76_queue_entry *e); 301 302 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 303 304 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 305 struct sk_buff *skb); 306 307 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 308 309 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 310 bool ps); 311 312 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 313 struct ieee80211_sta *sta); 314 315 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 316 struct ieee80211_sta *sta); 317 318 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 319 struct ieee80211_sta *sta); 320 }; 321 322 struct mt76_channel_state { 323 u64 cc_active; 324 u64 cc_busy; 325 u64 cc_rx; 326 u64 cc_bss_rx; 327 u64 cc_tx; 328 }; 329 330 struct mt76_sband { 331 struct ieee80211_supported_band sband; 332 struct mt76_channel_state *chan; 333 }; 334 335 struct mt76_rate_power { 336 union { 337 struct { 338 s8 cck[4]; 339 s8 ofdm[8]; 340 s8 stbc[10]; 341 s8 ht[16]; 342 s8 vht[10]; 343 }; 344 s8 all[48]; 345 }; 346 }; 347 348 /* addr req mask */ 349 #define MT_VEND_TYPE_EEPROM BIT(31) 350 #define MT_VEND_TYPE_CFG BIT(30) 351 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 352 353 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 354 enum mt_vendor_req { 355 MT_VEND_DEV_MODE = 0x1, 356 MT_VEND_WRITE = 0x2, 357 MT_VEND_MULTI_WRITE = 0x6, 358 MT_VEND_MULTI_READ = 0x7, 359 MT_VEND_READ_EEPROM = 0x9, 360 MT_VEND_WRITE_FCE = 0x42, 361 MT_VEND_WRITE_CFG = 0x46, 362 MT_VEND_READ_CFG = 0x47, 363 }; 364 365 enum mt76u_in_ep { 366 MT_EP_IN_PKT_RX, 367 MT_EP_IN_CMD_RESP, 368 __MT_EP_IN_MAX, 369 }; 370 371 enum mt76u_out_ep { 372 MT_EP_OUT_INBAND_CMD, 373 MT_EP_OUT_AC_BE, 374 MT_EP_OUT_AC_BK, 375 MT_EP_OUT_AC_VI, 376 MT_EP_OUT_AC_VO, 377 MT_EP_OUT_HCCA, 378 __MT_EP_OUT_MAX, 379 }; 380 381 #define MT_TX_SG_MAX_SIZE 8 382 #define MT_RX_SG_MAX_SIZE 1 383 #define MT_NUM_TX_ENTRIES 256 384 #define MT_NUM_RX_ENTRIES 128 385 #define MCU_RESP_URB_SIZE 1024 386 struct mt76_usb { 387 struct mutex usb_ctrl_mtx; 388 union { 389 u8 data[32]; 390 __le32 reg_val; 391 }; 392 393 struct tasklet_struct rx_tasklet; 394 struct workqueue_struct *stat_wq; 395 struct work_struct stat_work; 396 397 u8 out_ep[__MT_EP_OUT_MAX]; 398 u8 in_ep[__MT_EP_IN_MAX]; 399 bool sg_en; 400 401 struct mt76u_mcu { 402 struct mutex mutex; 403 u8 *data; 404 u32 msg_seq; 405 406 /* multiple reads */ 407 struct mt76_reg_pair *rp; 408 int rp_len; 409 u32 base; 410 bool burst; 411 } mcu; 412 }; 413 414 struct mt76_mmio { 415 struct mt76e_mcu { 416 struct mutex mutex; 417 418 wait_queue_head_t wait; 419 struct sk_buff_head res_q; 420 421 u32 msg_seq; 422 } mcu; 423 void __iomem *regs; 424 spinlock_t irq_lock; 425 u32 irqmask; 426 }; 427 428 struct mt76_rx_status { 429 union { 430 struct mt76_wcid *wcid; 431 u8 wcid_idx; 432 }; 433 434 unsigned long reorder_time; 435 436 u32 ampdu_ref; 437 438 u8 iv[6]; 439 440 u8 ext_phy:1; 441 u8 aggr:1; 442 u8 tid; 443 u16 seqno; 444 445 u16 freq; 446 u32 flag; 447 u8 enc_flags; 448 u8 encoding:2, bw:3; 449 u8 rate_idx; 450 u8 nss; 451 u8 band; 452 s8 signal; 453 u8 chains; 454 s8 chain_signal[IEEE80211_MAX_CHAINS]; 455 }; 456 457 struct mt76_phy { 458 struct ieee80211_hw *hw; 459 struct mt76_dev *dev; 460 461 unsigned long state; 462 463 struct cfg80211_chan_def chandef; 464 struct ieee80211_channel *main_chan; 465 466 struct mt76_channel_state *chan_state; 467 ktime_t survey_time; 468 469 struct mt76_sband sband_2g; 470 struct mt76_sband sband_5g; 471 }; 472 473 struct mt76_dev { 474 struct mt76_phy phy; /* must be first */ 475 476 struct mt76_phy *phy2; 477 478 struct ieee80211_hw *hw; 479 480 spinlock_t lock; 481 spinlock_t cc_lock; 482 483 u32 cur_cc_bss_rx; 484 485 struct mt76_rx_status rx_ampdu_status; 486 u32 rx_ampdu_len; 487 u32 rx_ampdu_ref; 488 489 struct mutex mutex; 490 491 const struct mt76_bus_ops *bus; 492 const struct mt76_driver_ops *drv; 493 const struct mt76_mcu_ops *mcu_ops; 494 struct device *dev; 495 496 struct net_device napi_dev; 497 spinlock_t rx_lock; 498 struct napi_struct napi[__MT_RXQ_MAX]; 499 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 500 u32 ampdu_ref; 501 502 struct list_head txwi_cache; 503 struct mt76_sw_queue q_tx[2 * __MT_TXQ_MAX]; 504 struct mt76_queue q_rx[__MT_RXQ_MAX]; 505 const struct mt76_queue_ops *queue_ops; 506 int tx_dma_idx[4]; 507 508 struct tasklet_struct tx_tasklet; 509 struct napi_struct tx_napi; 510 struct delayed_work mac_work; 511 512 wait_queue_head_t tx_wait; 513 struct sk_buff_head status_list; 514 515 unsigned long wcid_mask[MT76_N_WCIDS / BITS_PER_LONG]; 516 unsigned long wcid_phy_mask[MT76_N_WCIDS / BITS_PER_LONG]; 517 518 struct mt76_wcid global_wcid; 519 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 520 521 u8 macaddr[ETH_ALEN]; 522 u32 rev; 523 524 u32 aggr_stats[32]; 525 526 u8 antenna_mask; 527 u16 chainmask; 528 529 struct tasklet_struct pre_tbtt_tasklet; 530 int beacon_int; 531 u8 beacon_mask; 532 533 struct debugfs_blob_wrapper eeprom; 534 struct debugfs_blob_wrapper otp; 535 struct mt76_hw_cap cap; 536 537 struct mt76_rate_power rate_power; 538 int txpower_conf; 539 int txpower_cur; 540 541 enum nl80211_dfs_regions region; 542 543 u32 debugfs_reg; 544 545 struct led_classdev led_cdev; 546 char led_name[32]; 547 bool led_al; 548 u8 led_pin; 549 550 u8 csa_complete; 551 552 u32 rxfilter; 553 554 union { 555 struct mt76_mmio mmio; 556 struct mt76_usb usb; 557 }; 558 }; 559 560 enum mt76_phy_type { 561 MT_PHY_TYPE_CCK, 562 MT_PHY_TYPE_OFDM, 563 MT_PHY_TYPE_HT, 564 MT_PHY_TYPE_HT_GF, 565 MT_PHY_TYPE_VHT, 566 }; 567 568 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 569 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 570 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 571 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 572 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 573 574 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 575 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 576 577 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 578 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 579 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 580 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 581 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 582 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 583 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 584 585 #define mt76_mcu_send_msg(dev, ...) (dev)->mt76.mcu_ops->mcu_send_msg(&((dev)->mt76), __VA_ARGS__) 586 #define __mt76_mcu_send_msg(dev, ...) (dev)->mcu_ops->mcu_send_msg((dev), __VA_ARGS__) 587 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 588 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 589 590 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 591 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 592 593 #define mt76_get_field(_dev, _reg, _field) \ 594 FIELD_GET(_field, mt76_rr(dev, _reg)) 595 596 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 597 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 598 599 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 600 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 601 602 #define mt76_hw(dev) (dev)->mphy.hw 603 604 static inline struct ieee80211_hw * 605 mt76_wcid_hw(struct mt76_dev *dev, u8 wcid) 606 { 607 if (wcid <= MT76_N_WCIDS && 608 mt76_wcid_mask_test(dev->wcid_phy_mask, wcid)) 609 return dev->phy2->hw; 610 611 return dev->phy.hw; 612 } 613 614 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 615 int timeout); 616 617 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 618 619 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 620 int timeout); 621 622 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 623 624 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 625 void mt76_pci_disable_aspm(struct pci_dev *pdev); 626 627 static inline u16 mt76_chip(struct mt76_dev *dev) 628 { 629 return dev->rev >> 16; 630 } 631 632 static inline u16 mt76_rev(struct mt76_dev *dev) 633 { 634 return dev->rev & 0xffff; 635 } 636 637 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 638 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 639 640 #define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76)) 641 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 642 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 643 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 644 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 645 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 646 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 647 648 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 649 const struct ieee80211_ops *ops, 650 const struct mt76_driver_ops *drv_ops); 651 int mt76_register_device(struct mt76_dev *dev, bool vht, 652 struct ieee80211_rate *rates, int n_rates); 653 void mt76_unregister_device(struct mt76_dev *dev); 654 void mt76_free_device(struct mt76_dev *dev); 655 656 struct dentry *mt76_register_debugfs(struct mt76_dev *dev); 657 int mt76_queues_read(struct seq_file *s, void *data); 658 void mt76_seq_puts_array(struct seq_file *file, const char *str, 659 s8 *val, int len); 660 661 int mt76_eeprom_init(struct mt76_dev *dev, int len); 662 void mt76_eeprom_override(struct mt76_dev *dev); 663 664 static inline struct mt76_phy * 665 mt76_dev_phy(struct mt76_dev *dev, bool phy_ext) 666 { 667 if (phy_ext && dev->phy2) 668 return dev->phy2; 669 return &dev->phy; 670 } 671 672 static inline struct ieee80211_hw * 673 mt76_phy_hw(struct mt76_dev *dev, bool phy_ext) 674 { 675 return mt76_dev_phy(dev, phy_ext)->hw; 676 } 677 678 static inline u8 * 679 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 680 { 681 return (u8 *)t - dev->drv->txwi_size; 682 } 683 684 /* increment with wrap-around */ 685 static inline int mt76_incr(int val, int size) 686 { 687 return (val + 1) & (size - 1); 688 } 689 690 /* decrement with wrap-around */ 691 static inline int mt76_decr(int val, int size) 692 { 693 return (val - 1) & (size - 1); 694 } 695 696 u8 mt76_ac_to_hwq(u8 ac); 697 698 static inline struct ieee80211_txq * 699 mtxq_to_txq(struct mt76_txq *mtxq) 700 { 701 void *ptr = mtxq; 702 703 return container_of(ptr, struct ieee80211_txq, drv_priv); 704 } 705 706 static inline struct ieee80211_sta * 707 wcid_to_sta(struct mt76_wcid *wcid) 708 { 709 void *ptr = wcid; 710 711 if (!wcid || !wcid->sta) 712 return NULL; 713 714 return container_of(ptr, struct ieee80211_sta, drv_priv); 715 } 716 717 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 718 { 719 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 720 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 721 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 722 } 723 724 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 725 { 726 int len = ieee80211_get_hdrlen_from_skb(skb); 727 728 if (len % 4 == 0) 729 return; 730 731 skb_push(skb, 2); 732 memmove(skb->data, skb->data + 2, len); 733 734 skb->data[len] = 0; 735 skb->data[len + 1] = 0; 736 } 737 738 static inline bool mt76_is_skb_pktid(u8 pktid) 739 { 740 if (pktid & MT_PACKET_ID_HAS_RATE) 741 return false; 742 743 return pktid >= MT_PACKET_ID_FIRST; 744 } 745 746 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 747 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 748 struct mt76_wcid *wcid, struct sk_buff *skb); 749 void mt76_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq); 750 void mt76_txq_remove(struct mt76_dev *dev, struct ieee80211_txq *txq); 751 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 752 void mt76_stop_tx_queues(struct mt76_dev *dev, struct ieee80211_sta *sta, 753 bool send_bar); 754 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 755 void mt76_txq_schedule_all(struct mt76_phy *phy); 756 void mt76_tx_tasklet(unsigned long data); 757 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 758 struct ieee80211_sta *sta, 759 u16 tids, int nframes, 760 enum ieee80211_frame_release_type reason, 761 bool more_data); 762 bool mt76_has_tx_pending(struct mt76_phy *phy); 763 void mt76_set_channel(struct mt76_phy *phy); 764 void mt76_update_survey(struct mt76_dev *dev); 765 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 766 struct survey_info *survey); 767 void mt76_set_stream_caps(struct mt76_dev *dev, bool vht); 768 769 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 770 u16 ssn, u8 size); 771 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 772 773 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 774 struct ieee80211_key_conf *key); 775 776 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 777 __acquires(&dev->status_list.lock); 778 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 779 __releases(&dev->status_list.lock); 780 781 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 782 struct sk_buff *skb); 783 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 784 struct mt76_wcid *wcid, int pktid, 785 struct sk_buff_head *list); 786 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 787 struct sk_buff_head *list); 788 void mt76_tx_complete_skb(struct mt76_dev *dev, struct sk_buff *skb); 789 void mt76_tx_status_check(struct mt76_dev *dev, struct mt76_wcid *wcid, 790 bool flush); 791 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 792 struct ieee80211_sta *sta, 793 enum ieee80211_sta_state old_state, 794 enum ieee80211_sta_state new_state); 795 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 796 struct ieee80211_sta *sta); 797 798 int mt76_get_min_avg_rssi(struct mt76_dev *dev); 799 800 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 801 int *dbm); 802 803 void mt76_csa_check(struct mt76_dev *dev); 804 void mt76_csa_finish(struct mt76_dev *dev); 805 806 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 807 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 808 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 809 int mt76_get_rate(struct mt76_dev *dev, 810 struct ieee80211_supported_band *sband, 811 int idx, bool cck); 812 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 813 const u8 *mac); 814 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 815 struct ieee80211_vif *vif); 816 u32 mt76_calc_tx_airtime(struct mt76_dev *dev, struct ieee80211_tx_info *info, 817 int len); 818 819 /* internal */ 820 static inline struct ieee80211_hw * 821 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 822 { 823 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 824 struct ieee80211_hw *hw = dev->phy.hw; 825 826 if ((info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY) && dev->phy2) 827 hw = dev->phy2->hw; 828 829 info->hw_queue &= ~MT_TX_HW_QUEUE_EXT_PHY; 830 831 return hw; 832 } 833 834 void mt76_tx_free(struct mt76_dev *dev); 835 struct mt76_txwi_cache *mt76_get_txwi(struct mt76_dev *dev); 836 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 837 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 838 struct napi_struct *napi); 839 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 840 struct napi_struct *napi); 841 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 842 u32 mt76_calc_rx_airtime(struct mt76_dev *dev, struct mt76_rx_status *status, 843 int len); 844 845 /* usb */ 846 static inline bool mt76u_urb_error(struct urb *urb) 847 { 848 return urb->status && 849 urb->status != -ECONNRESET && 850 urb->status != -ESHUTDOWN && 851 urb->status != -ENOENT; 852 } 853 854 /* Map hardware queues to usb endpoints */ 855 static inline u8 q2ep(u8 qid) 856 { 857 /* TODO: take management packets to queue 5 */ 858 return qid + 1; 859 } 860 861 static inline int 862 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 863 int timeout) 864 { 865 struct usb_interface *uintf = to_usb_interface(dev->dev); 866 struct usb_device *udev = interface_to_usbdev(uintf); 867 struct mt76_usb *usb = &dev->usb; 868 unsigned int pipe; 869 870 if (actual_len) 871 pipe = usb_rcvbulkpipe(udev, usb->in_ep[MT_EP_IN_CMD_RESP]); 872 else 873 pipe = usb_sndbulkpipe(udev, usb->out_ep[MT_EP_OUT_INBAND_CMD]); 874 875 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 876 } 877 878 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 879 u8 req_type, u16 val, u16 offset, 880 void *buf, size_t len); 881 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 882 const u16 offset, const u32 val); 883 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 884 void mt76u_deinit(struct mt76_dev *dev); 885 int mt76u_alloc_queues(struct mt76_dev *dev); 886 void mt76u_stop_tx(struct mt76_dev *dev); 887 void mt76u_stop_rx(struct mt76_dev *dev); 888 int mt76u_resume_rx(struct mt76_dev *dev); 889 void mt76u_queues_deinit(struct mt76_dev *dev); 890 891 struct sk_buff * 892 mt76_mcu_msg_alloc(const void *data, int head_len, 893 int data_len, int tail_len); 894 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 895 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 896 unsigned long expires); 897 898 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 899 900 #endif 901