1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #include "mt76.h" 8 #include "dma.h" 9 10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) 11 12 #define Q_READ(_dev, _q, _field) ({ \ 13 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 14 u32 _val; \ 15 if ((_q)->flags & MT_QFLAG_WED) \ 16 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \ 17 ((_q)->wed_regs + \ 18 _offset)); \ 19 else \ 20 _val = readl(&(_q)->regs->_field); \ 21 _val; \ 22 }) 23 24 #define Q_WRITE(_dev, _q, _field, _val) do { \ 25 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 26 if ((_q)->flags & MT_QFLAG_WED) \ 27 mtk_wed_device_reg_write(&(_dev)->mmio.wed, \ 28 ((_q)->wed_regs + _offset), \ 29 _val); \ 30 else \ 31 writel(_val, &(_q)->regs->_field); \ 32 } while (0) 33 34 #else 35 36 #define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field) 37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) 38 39 #endif 40 41 static struct mt76_txwi_cache * 42 mt76_alloc_txwi(struct mt76_dev *dev) 43 { 44 struct mt76_txwi_cache *t; 45 dma_addr_t addr; 46 u8 *txwi; 47 int size; 48 49 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t)); 50 txwi = kzalloc(size, GFP_ATOMIC); 51 if (!txwi) 52 return NULL; 53 54 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size, 55 DMA_TO_DEVICE); 56 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size); 57 t->dma_addr = addr; 58 59 return t; 60 } 61 62 static struct mt76_txwi_cache * 63 mt76_alloc_rxwi(struct mt76_dev *dev) 64 { 65 struct mt76_txwi_cache *t; 66 67 t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC); 68 if (!t) 69 return NULL; 70 71 t->ptr = NULL; 72 return t; 73 } 74 75 static struct mt76_txwi_cache * 76 __mt76_get_txwi(struct mt76_dev *dev) 77 { 78 struct mt76_txwi_cache *t = NULL; 79 80 spin_lock(&dev->lock); 81 if (!list_empty(&dev->txwi_cache)) { 82 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 83 list); 84 list_del(&t->list); 85 } 86 spin_unlock(&dev->lock); 87 88 return t; 89 } 90 91 static struct mt76_txwi_cache * 92 __mt76_get_rxwi(struct mt76_dev *dev) 93 { 94 struct mt76_txwi_cache *t = NULL; 95 96 spin_lock(&dev->wed_lock); 97 if (!list_empty(&dev->rxwi_cache)) { 98 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache, 99 list); 100 list_del(&t->list); 101 } 102 spin_unlock(&dev->wed_lock); 103 104 return t; 105 } 106 107 static struct mt76_txwi_cache * 108 mt76_get_txwi(struct mt76_dev *dev) 109 { 110 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 111 112 if (t) 113 return t; 114 115 return mt76_alloc_txwi(dev); 116 } 117 118 struct mt76_txwi_cache * 119 mt76_get_rxwi(struct mt76_dev *dev) 120 { 121 struct mt76_txwi_cache *t = __mt76_get_rxwi(dev); 122 123 if (t) 124 return t; 125 126 return mt76_alloc_rxwi(dev); 127 } 128 EXPORT_SYMBOL_GPL(mt76_get_rxwi); 129 130 void 131 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 132 { 133 if (!t) 134 return; 135 136 spin_lock(&dev->lock); 137 list_add(&t->list, &dev->txwi_cache); 138 spin_unlock(&dev->lock); 139 } 140 EXPORT_SYMBOL_GPL(mt76_put_txwi); 141 142 void 143 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 144 { 145 if (!t) 146 return; 147 148 spin_lock(&dev->wed_lock); 149 list_add(&t->list, &dev->rxwi_cache); 150 spin_unlock(&dev->wed_lock); 151 } 152 EXPORT_SYMBOL_GPL(mt76_put_rxwi); 153 154 static void 155 mt76_free_pending_txwi(struct mt76_dev *dev) 156 { 157 struct mt76_txwi_cache *t; 158 159 local_bh_disable(); 160 while ((t = __mt76_get_txwi(dev)) != NULL) { 161 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 162 DMA_TO_DEVICE); 163 kfree(mt76_get_txwi_ptr(dev, t)); 164 } 165 local_bh_enable(); 166 } 167 168 void 169 mt76_free_pending_rxwi(struct mt76_dev *dev) 170 { 171 struct mt76_txwi_cache *t; 172 173 local_bh_disable(); 174 while ((t = __mt76_get_rxwi(dev)) != NULL) { 175 if (t->ptr) 176 mt76_put_page_pool_buf(t->ptr, false); 177 kfree(t); 178 } 179 local_bh_enable(); 180 } 181 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 182 183 static void 184 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 185 { 186 Q_WRITE(dev, q, desc_base, q->desc_dma); 187 Q_WRITE(dev, q, ring_size, q->ndesc); 188 q->head = Q_READ(dev, q, dma_idx); 189 q->tail = q->head; 190 } 191 192 static void 193 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 194 { 195 int i; 196 197 if (!q || !q->ndesc) 198 return; 199 200 /* clear descriptors */ 201 for (i = 0; i < q->ndesc; i++) 202 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 203 204 Q_WRITE(dev, q, cpu_idx, 0); 205 Q_WRITE(dev, q, dma_idx, 0); 206 mt76_dma_sync_idx(dev, q); 207 } 208 209 static int 210 mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q, 211 struct mt76_queue_buf *buf, void *data) 212 { 213 struct mt76_desc *desc = &q->desc[q->head]; 214 struct mt76_queue_entry *entry = &q->entry[q->head]; 215 struct mt76_txwi_cache *txwi = NULL; 216 u32 buf1 = 0, ctrl; 217 int idx = q->head; 218 int rx_token; 219 220 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 221 222 if (mt76_queue_is_wed_rx(q)) { 223 txwi = mt76_get_rxwi(dev); 224 if (!txwi) 225 return -ENOMEM; 226 227 rx_token = mt76_rx_token_consume(dev, data, txwi, buf->addr); 228 if (rx_token < 0) { 229 mt76_put_rxwi(dev, txwi); 230 return -ENOMEM; 231 } 232 233 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 234 ctrl |= MT_DMA_CTL_TO_HOST; 235 } 236 237 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 238 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 239 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 240 WRITE_ONCE(desc->info, 0); 241 242 entry->dma_addr[0] = buf->addr; 243 entry->dma_len[0] = buf->len; 244 entry->txwi = txwi; 245 entry->buf = data; 246 entry->wcid = 0xffff; 247 entry->skip_buf1 = true; 248 q->head = (q->head + 1) % q->ndesc; 249 q->queued++; 250 251 return idx; 252 } 253 254 static int 255 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 256 struct mt76_queue_buf *buf, int nbufs, u32 info, 257 struct sk_buff *skb, void *txwi) 258 { 259 struct mt76_queue_entry *entry; 260 struct mt76_desc *desc; 261 int i, idx = -1; 262 u32 ctrl, next; 263 264 if (txwi) { 265 q->entry[q->head].txwi = DMA_DUMMY_DATA; 266 q->entry[q->head].skip_buf0 = true; 267 } 268 269 for (i = 0; i < nbufs; i += 2, buf += 2) { 270 u32 buf0 = buf[0].addr, buf1 = 0; 271 272 idx = q->head; 273 next = (q->head + 1) % q->ndesc; 274 275 desc = &q->desc[idx]; 276 entry = &q->entry[idx]; 277 278 if (buf[0].skip_unmap) 279 entry->skip_buf0 = true; 280 entry->skip_buf1 = i == nbufs - 1; 281 282 entry->dma_addr[0] = buf[0].addr; 283 entry->dma_len[0] = buf[0].len; 284 285 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 286 if (i < nbufs - 1) { 287 entry->dma_addr[1] = buf[1].addr; 288 entry->dma_len[1] = buf[1].len; 289 buf1 = buf[1].addr; 290 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 291 if (buf[1].skip_unmap) 292 entry->skip_buf1 = true; 293 } 294 295 if (i == nbufs - 1) 296 ctrl |= MT_DMA_CTL_LAST_SEC0; 297 else if (i == nbufs - 2) 298 ctrl |= MT_DMA_CTL_LAST_SEC1; 299 300 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 301 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 302 WRITE_ONCE(desc->info, cpu_to_le32(info)); 303 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 304 305 q->head = next; 306 q->queued++; 307 } 308 309 q->entry[idx].txwi = txwi; 310 q->entry[idx].skb = skb; 311 q->entry[idx].wcid = 0xffff; 312 313 return idx; 314 } 315 316 static void 317 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 318 struct mt76_queue_entry *prev_e) 319 { 320 struct mt76_queue_entry *e = &q->entry[idx]; 321 322 if (!e->skip_buf0) 323 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0], 324 DMA_TO_DEVICE); 325 326 if (!e->skip_buf1) 327 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1], 328 DMA_TO_DEVICE); 329 330 if (e->txwi == DMA_DUMMY_DATA) 331 e->txwi = NULL; 332 333 if (e->skb == DMA_DUMMY_DATA) 334 e->skb = NULL; 335 336 *prev_e = *e; 337 memset(e, 0, sizeof(*e)); 338 } 339 340 static void 341 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 342 { 343 wmb(); 344 Q_WRITE(dev, q, cpu_idx, q->head); 345 } 346 347 static void 348 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush) 349 { 350 struct mt76_queue_entry entry; 351 int last; 352 353 if (!q || !q->ndesc) 354 return; 355 356 spin_lock_bh(&q->cleanup_lock); 357 if (flush) 358 last = -1; 359 else 360 last = Q_READ(dev, q, dma_idx); 361 362 while (q->queued > 0 && q->tail != last) { 363 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 364 mt76_queue_tx_complete(dev, q, &entry); 365 366 if (entry.txwi) { 367 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 368 mt76_put_txwi(dev, entry.txwi); 369 } 370 371 if (!flush && q->tail == last) 372 last = Q_READ(dev, q, dma_idx); 373 } 374 spin_unlock_bh(&q->cleanup_lock); 375 376 if (flush) { 377 spin_lock_bh(&q->lock); 378 mt76_dma_sync_idx(dev, q); 379 mt76_dma_kick_queue(dev, q); 380 spin_unlock_bh(&q->lock); 381 } 382 383 if (!q->queued) 384 wake_up(&dev->tx_wait); 385 } 386 387 static void * 388 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 389 int *len, u32 *info, bool *more, bool *drop) 390 { 391 struct mt76_queue_entry *e = &q->entry[idx]; 392 struct mt76_desc *desc = &q->desc[idx]; 393 void *buf; 394 395 if (len) { 396 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 397 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 398 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0); 399 } 400 401 if (info) 402 *info = le32_to_cpu(desc->info); 403 404 if (mt76_queue_is_wed_rx(q)) { 405 u32 buf1 = le32_to_cpu(desc->buf1); 406 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN, buf1); 407 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token); 408 409 if (!t) 410 return NULL; 411 412 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 413 SKB_WITH_OVERHEAD(q->buf_size), 414 page_pool_get_dma_dir(q->page_pool)); 415 416 buf = t->ptr; 417 t->dma_addr = 0; 418 t->ptr = NULL; 419 420 mt76_put_rxwi(dev, t); 421 422 if (drop) { 423 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 424 425 *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | 426 MT_DMA_CTL_DROP)); 427 428 *drop |= !!(buf1 & MT_DMA_CTL_WO_DROP); 429 } 430 } else { 431 buf = e->buf; 432 e->buf = NULL; 433 dma_sync_single_for_cpu(dev->dma_dev, e->dma_addr[0], 434 SKB_WITH_OVERHEAD(q->buf_size), 435 page_pool_get_dma_dir(q->page_pool)); 436 } 437 438 return buf; 439 } 440 441 static void * 442 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 443 int *len, u32 *info, bool *more, bool *drop) 444 { 445 int idx = q->tail; 446 447 *more = false; 448 if (!q->queued) 449 return NULL; 450 451 if (flush) 452 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 453 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 454 return NULL; 455 456 q->tail = (q->tail + 1) % q->ndesc; 457 q->queued--; 458 459 return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 460 } 461 462 static int 463 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q, 464 struct sk_buff *skb, u32 tx_info) 465 { 466 struct mt76_queue_buf buf = {}; 467 dma_addr_t addr; 468 469 if (q->queued + 1 >= q->ndesc - 1) 470 goto error; 471 472 addr = dma_map_single(dev->dma_dev, skb->data, skb->len, 473 DMA_TO_DEVICE); 474 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 475 goto error; 476 477 buf.addr = addr; 478 buf.len = skb->len; 479 480 spin_lock_bh(&q->lock); 481 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 482 mt76_dma_kick_queue(dev, q); 483 spin_unlock_bh(&q->lock); 484 485 return 0; 486 487 error: 488 dev_kfree_skb(skb); 489 return -ENOMEM; 490 } 491 492 static int 493 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q, 494 enum mt76_txq_id qid, struct sk_buff *skb, 495 struct mt76_wcid *wcid, struct ieee80211_sta *sta) 496 { 497 struct ieee80211_tx_status status = { 498 .sta = sta, 499 }; 500 struct mt76_tx_info tx_info = { 501 .skb = skb, 502 }; 503 struct ieee80211_hw *hw; 504 int len, n = 0, ret = -ENOMEM; 505 struct mt76_txwi_cache *t; 506 struct sk_buff *iter; 507 dma_addr_t addr; 508 u8 *txwi; 509 510 t = mt76_get_txwi(dev); 511 if (!t) 512 goto free_skb; 513 514 txwi = mt76_get_txwi_ptr(dev, t); 515 516 skb->prev = skb->next = NULL; 517 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 518 mt76_insert_hdr_pad(skb); 519 520 len = skb_headlen(skb); 521 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE); 522 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 523 goto free; 524 525 tx_info.buf[n].addr = t->dma_addr; 526 tx_info.buf[n++].len = dev->drv->txwi_size; 527 tx_info.buf[n].addr = addr; 528 tx_info.buf[n++].len = len; 529 530 skb_walk_frags(skb, iter) { 531 if (n == ARRAY_SIZE(tx_info.buf)) 532 goto unmap; 533 534 addr = dma_map_single(dev->dma_dev, iter->data, iter->len, 535 DMA_TO_DEVICE); 536 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 537 goto unmap; 538 539 tx_info.buf[n].addr = addr; 540 tx_info.buf[n++].len = iter->len; 541 } 542 tx_info.nbuf = n; 543 544 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 545 ret = -ENOMEM; 546 goto unmap; 547 } 548 549 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 550 DMA_TO_DEVICE); 551 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 552 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 553 DMA_TO_DEVICE); 554 if (ret < 0) 555 goto unmap; 556 557 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 558 tx_info.info, tx_info.skb, t); 559 560 unmap: 561 for (n--; n > 0; n--) 562 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr, 563 tx_info.buf[n].len, DMA_TO_DEVICE); 564 565 free: 566 #ifdef CONFIG_NL80211_TESTMODE 567 /* fix tx_done accounting on queue overflow */ 568 if (mt76_is_testmode_skb(dev, skb, &hw)) { 569 struct mt76_phy *phy = hw->priv; 570 571 if (tx_info.skb == phy->test.tx_skb) 572 phy->test.tx_done--; 573 } 574 #endif 575 576 mt76_put_txwi(dev, t); 577 578 free_skb: 579 status.skb = tx_info.skb; 580 hw = mt76_tx_status_get_hw(dev, tx_info.skb); 581 spin_lock_bh(&dev->rx_lock); 582 ieee80211_tx_status_ext(hw, &status); 583 spin_unlock_bh(&dev->rx_lock); 584 585 return ret; 586 } 587 588 static int 589 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 590 bool allow_direct) 591 { 592 int len = SKB_WITH_OVERHEAD(q->buf_size); 593 int frames = 0; 594 595 if (!q->ndesc) 596 return 0; 597 598 spin_lock_bh(&q->lock); 599 600 while (q->queued < q->ndesc - 1) { 601 enum dma_data_direction dir; 602 struct mt76_queue_buf qbuf; 603 dma_addr_t addr; 604 int offset; 605 void *buf; 606 607 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); 608 if (!buf) 609 break; 610 611 addr = page_pool_get_dma_addr(virt_to_head_page(buf)) + offset; 612 dir = page_pool_get_dma_dir(q->page_pool); 613 dma_sync_single_for_device(dev->dma_dev, addr, len, dir); 614 615 qbuf.addr = addr + q->buf_offset; 616 qbuf.len = len - q->buf_offset; 617 qbuf.skip_unmap = false; 618 if (mt76_dma_add_rx_buf(dev, q, &qbuf, buf) < 0) { 619 mt76_put_page_pool_buf(buf, allow_direct); 620 break; 621 } 622 frames++; 623 } 624 625 if (frames) 626 mt76_dma_kick_queue(dev, q); 627 628 spin_unlock_bh(&q->lock); 629 630 return frames; 631 } 632 633 int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) 634 { 635 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 636 struct mtk_wed_device *wed = &dev->mmio.wed; 637 int ret, type, ring; 638 u8 flags; 639 640 if (!q || !q->ndesc) 641 return -EINVAL; 642 643 flags = q->flags; 644 if (!mtk_wed_device_active(wed)) 645 q->flags &= ~MT_QFLAG_WED; 646 647 if (!(q->flags & MT_QFLAG_WED)) 648 return 0; 649 650 type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); 651 ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); 652 653 switch (type) { 654 case MT76_WED_Q_TX: 655 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs, reset); 656 if (!ret) 657 q->wed_regs = wed->tx_ring[ring].reg_base; 658 break; 659 case MT76_WED_Q_TXFREE: 660 /* WED txfree queue needs ring to be initialized before setup */ 661 q->flags = 0; 662 mt76_dma_queue_reset(dev, q); 663 mt76_dma_rx_fill(dev, q, false); 664 q->flags = flags; 665 666 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs); 667 if (!ret) 668 q->wed_regs = wed->txfree_ring.reg_base; 669 break; 670 case MT76_WED_Q_RX: 671 ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, reset); 672 if (!ret) 673 q->wed_regs = wed->rx_ring[ring].reg_base; 674 break; 675 default: 676 ret = -EINVAL; 677 } 678 679 return ret; 680 #else 681 return 0; 682 #endif 683 } 684 EXPORT_SYMBOL_GPL(mt76_dma_wed_setup); 685 686 static int 687 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 688 int idx, int n_desc, int bufsize, 689 u32 ring_base) 690 { 691 int ret, size; 692 693 spin_lock_init(&q->lock); 694 spin_lock_init(&q->cleanup_lock); 695 696 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 697 q->ndesc = n_desc; 698 q->buf_size = bufsize; 699 q->hw_idx = idx; 700 701 size = q->ndesc * sizeof(struct mt76_desc); 702 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL); 703 if (!q->desc) 704 return -ENOMEM; 705 706 size = q->ndesc * sizeof(*q->entry); 707 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 708 if (!q->entry) 709 return -ENOMEM; 710 711 ret = mt76_create_page_pool(dev, q); 712 if (ret) 713 return ret; 714 715 ret = mt76_dma_wed_setup(dev, q, false); 716 if (ret) 717 return ret; 718 719 if (q->flags != MT_WED_Q_TXFREE) 720 mt76_dma_queue_reset(dev, q); 721 722 return 0; 723 } 724 725 static void 726 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 727 { 728 void *buf; 729 bool more; 730 731 if (!q->ndesc) 732 return; 733 734 spin_lock_bh(&q->lock); 735 736 do { 737 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL); 738 if (!buf) 739 break; 740 741 mt76_put_page_pool_buf(buf, false); 742 } while (1); 743 744 if (q->rx_head) { 745 dev_kfree_skb(q->rx_head); 746 q->rx_head = NULL; 747 } 748 749 spin_unlock_bh(&q->lock); 750 } 751 752 static void 753 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 754 { 755 struct mt76_queue *q = &dev->q_rx[qid]; 756 int i; 757 758 if (!q->ndesc) 759 return; 760 761 for (i = 0; i < q->ndesc; i++) 762 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 763 764 mt76_dma_rx_cleanup(dev, q); 765 766 /* reset WED rx queues */ 767 mt76_dma_wed_setup(dev, q, true); 768 if (q->flags != MT_WED_Q_TXFREE) { 769 mt76_dma_sync_idx(dev, q); 770 mt76_dma_rx_fill(dev, q, false); 771 } 772 } 773 774 static void 775 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 776 int len, bool more, u32 info) 777 { 778 struct sk_buff *skb = q->rx_head; 779 struct skb_shared_info *shinfo = skb_shinfo(skb); 780 int nr_frags = shinfo->nr_frags; 781 782 if (nr_frags < ARRAY_SIZE(shinfo->frags)) { 783 struct page *page = virt_to_head_page(data); 784 int offset = data - page_address(page) + q->buf_offset; 785 786 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size); 787 } else { 788 mt76_put_page_pool_buf(data, true); 789 } 790 791 if (more) 792 return; 793 794 q->rx_head = NULL; 795 if (nr_frags < ARRAY_SIZE(shinfo->frags)) 796 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 797 else 798 dev_kfree_skb(skb); 799 } 800 801 static int 802 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 803 { 804 int len, data_len, done = 0, dma_idx; 805 struct sk_buff *skb; 806 unsigned char *data; 807 bool check_ddone = false; 808 bool more; 809 810 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 811 q->flags == MT_WED_Q_TXFREE) { 812 dma_idx = Q_READ(dev, q, dma_idx); 813 check_ddone = true; 814 } 815 816 while (done < budget) { 817 bool drop = false; 818 u32 info; 819 820 if (check_ddone) { 821 if (q->tail == dma_idx) 822 dma_idx = Q_READ(dev, q, dma_idx); 823 824 if (q->tail == dma_idx) 825 break; 826 } 827 828 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, 829 &drop); 830 if (!data) 831 break; 832 833 if (drop) 834 goto free_frag; 835 836 if (q->rx_head) 837 data_len = q->buf_size; 838 else 839 data_len = SKB_WITH_OVERHEAD(q->buf_size); 840 841 if (data_len < len + q->buf_offset) { 842 dev_kfree_skb(q->rx_head); 843 q->rx_head = NULL; 844 goto free_frag; 845 } 846 847 if (q->rx_head) { 848 mt76_add_fragment(dev, q, data, len, more, info); 849 continue; 850 } 851 852 if (!more && dev->drv->rx_check && 853 !(dev->drv->rx_check(dev, data, len))) 854 goto free_frag; 855 856 skb = napi_build_skb(data, q->buf_size); 857 if (!skb) 858 goto free_frag; 859 860 skb_reserve(skb, q->buf_offset); 861 skb_mark_for_recycle(skb); 862 863 *(u32 *)skb->cb = info; 864 865 __skb_put(skb, len); 866 done++; 867 868 if (more) { 869 q->rx_head = skb; 870 continue; 871 } 872 873 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 874 continue; 875 876 free_frag: 877 mt76_put_page_pool_buf(data, true); 878 } 879 880 mt76_dma_rx_fill(dev, q, true); 881 return done; 882 } 883 884 int mt76_dma_rx_poll(struct napi_struct *napi, int budget) 885 { 886 struct mt76_dev *dev; 887 int qid, done = 0, cur; 888 889 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 890 qid = napi - dev->napi; 891 892 rcu_read_lock(); 893 894 do { 895 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 896 mt76_rx_poll_complete(dev, qid, napi); 897 done += cur; 898 } while (cur && done < budget); 899 900 rcu_read_unlock(); 901 902 if (done < budget && napi_complete(napi)) 903 dev->drv->rx_poll_complete(dev, qid); 904 905 return done; 906 } 907 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 908 909 static int 910 mt76_dma_init(struct mt76_dev *dev, 911 int (*poll)(struct napi_struct *napi, int budget)) 912 { 913 int i; 914 915 init_dummy_netdev(&dev->napi_dev); 916 init_dummy_netdev(&dev->tx_napi_dev); 917 snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s", 918 wiphy_name(dev->hw->wiphy)); 919 dev->napi_dev.threaded = 1; 920 init_completion(&dev->mmio.wed_reset); 921 init_completion(&dev->mmio.wed_reset_complete); 922 923 mt76_for_each_q_rx(dev, i) { 924 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll); 925 mt76_dma_rx_fill(dev, &dev->q_rx[i], false); 926 napi_enable(&dev->napi[i]); 927 } 928 929 return 0; 930 } 931 932 static const struct mt76_queue_ops mt76_dma_ops = { 933 .init = mt76_dma_init, 934 .alloc = mt76_dma_alloc_queue, 935 .reset_q = mt76_dma_queue_reset, 936 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 937 .tx_queue_skb = mt76_dma_tx_queue_skb, 938 .tx_cleanup = mt76_dma_tx_cleanup, 939 .rx_cleanup = mt76_dma_rx_cleanup, 940 .rx_reset = mt76_dma_rx_reset, 941 .kick = mt76_dma_kick_queue, 942 }; 943 944 void mt76_dma_attach(struct mt76_dev *dev) 945 { 946 dev->queue_ops = &mt76_dma_ops; 947 } 948 EXPORT_SYMBOL_GPL(mt76_dma_attach); 949 950 void mt76_dma_cleanup(struct mt76_dev *dev) 951 { 952 int i; 953 954 mt76_worker_disable(&dev->tx_worker); 955 netif_napi_del(&dev->tx_napi); 956 957 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 958 struct mt76_phy *phy = dev->phys[i]; 959 int j; 960 961 if (!phy) 962 continue; 963 964 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++) 965 mt76_dma_tx_cleanup(dev, phy->q_tx[j], true); 966 } 967 968 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++) 969 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true); 970 971 mt76_for_each_q_rx(dev, i) { 972 struct mt76_queue *q = &dev->q_rx[i]; 973 974 netif_napi_del(&dev->napi[i]); 975 mt76_dma_rx_cleanup(dev, q); 976 977 page_pool_destroy(q->page_pool); 978 } 979 980 mt76_free_pending_txwi(dev); 981 mt76_free_pending_rxwi(dev); 982 983 if (mtk_wed_device_active(&dev->mmio.wed)) 984 mtk_wed_device_detach(&dev->mmio.wed); 985 } 986 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 987