1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #include "mt76.h" 8 #include "dma.h" 9 10 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) 11 12 #define Q_READ(_dev, _q, _field) ({ \ 13 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 14 u32 _val; \ 15 if ((_q)->flags & MT_QFLAG_WED) \ 16 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \ 17 ((_q)->wed_regs + \ 18 _offset)); \ 19 else \ 20 _val = readl(&(_q)->regs->_field); \ 21 _val; \ 22 }) 23 24 #define Q_WRITE(_dev, _q, _field, _val) do { \ 25 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 26 if ((_q)->flags & MT_QFLAG_WED) \ 27 mtk_wed_device_reg_write(&(_dev)->mmio.wed, \ 28 ((_q)->wed_regs + _offset), \ 29 _val); \ 30 else \ 31 writel(_val, &(_q)->regs->_field); \ 32 } while (0) 33 34 #else 35 36 #define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field) 37 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) 38 39 #endif 40 41 static struct mt76_txwi_cache * 42 mt76_alloc_txwi(struct mt76_dev *dev) 43 { 44 struct mt76_txwi_cache *t; 45 dma_addr_t addr; 46 u8 *txwi; 47 int size; 48 49 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t)); 50 txwi = kzalloc(size, GFP_ATOMIC); 51 if (!txwi) 52 return NULL; 53 54 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size, 55 DMA_TO_DEVICE); 56 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size); 57 t->dma_addr = addr; 58 59 return t; 60 } 61 62 static struct mt76_txwi_cache * 63 mt76_alloc_rxwi(struct mt76_dev *dev) 64 { 65 struct mt76_txwi_cache *t; 66 67 t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC); 68 if (!t) 69 return NULL; 70 71 t->ptr = NULL; 72 return t; 73 } 74 75 static struct mt76_txwi_cache * 76 __mt76_get_txwi(struct mt76_dev *dev) 77 { 78 struct mt76_txwi_cache *t = NULL; 79 80 spin_lock(&dev->lock); 81 if (!list_empty(&dev->txwi_cache)) { 82 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 83 list); 84 list_del(&t->list); 85 } 86 spin_unlock(&dev->lock); 87 88 return t; 89 } 90 91 static struct mt76_txwi_cache * 92 __mt76_get_rxwi(struct mt76_dev *dev) 93 { 94 struct mt76_txwi_cache *t = NULL; 95 96 spin_lock(&dev->wed_lock); 97 if (!list_empty(&dev->rxwi_cache)) { 98 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache, 99 list); 100 list_del(&t->list); 101 } 102 spin_unlock(&dev->wed_lock); 103 104 return t; 105 } 106 107 static struct mt76_txwi_cache * 108 mt76_get_txwi(struct mt76_dev *dev) 109 { 110 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 111 112 if (t) 113 return t; 114 115 return mt76_alloc_txwi(dev); 116 } 117 118 struct mt76_txwi_cache * 119 mt76_get_rxwi(struct mt76_dev *dev) 120 { 121 struct mt76_txwi_cache *t = __mt76_get_rxwi(dev); 122 123 if (t) 124 return t; 125 126 return mt76_alloc_rxwi(dev); 127 } 128 EXPORT_SYMBOL_GPL(mt76_get_rxwi); 129 130 void 131 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 132 { 133 if (!t) 134 return; 135 136 spin_lock(&dev->lock); 137 list_add(&t->list, &dev->txwi_cache); 138 spin_unlock(&dev->lock); 139 } 140 EXPORT_SYMBOL_GPL(mt76_put_txwi); 141 142 void 143 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 144 { 145 if (!t) 146 return; 147 148 spin_lock(&dev->wed_lock); 149 list_add(&t->list, &dev->rxwi_cache); 150 spin_unlock(&dev->wed_lock); 151 } 152 EXPORT_SYMBOL_GPL(mt76_put_rxwi); 153 154 static void 155 mt76_free_pending_txwi(struct mt76_dev *dev) 156 { 157 struct mt76_txwi_cache *t; 158 159 local_bh_disable(); 160 while ((t = __mt76_get_txwi(dev)) != NULL) { 161 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 162 DMA_TO_DEVICE); 163 kfree(mt76_get_txwi_ptr(dev, t)); 164 } 165 local_bh_enable(); 166 } 167 168 void 169 mt76_free_pending_rxwi(struct mt76_dev *dev) 170 { 171 struct mt76_txwi_cache *t; 172 173 local_bh_disable(); 174 while ((t = __mt76_get_rxwi(dev)) != NULL) { 175 if (t->ptr) 176 mt76_put_page_pool_buf(t->ptr, false); 177 kfree(t); 178 } 179 local_bh_enable(); 180 } 181 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 182 183 static void 184 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 185 { 186 Q_WRITE(dev, q, desc_base, q->desc_dma); 187 Q_WRITE(dev, q, ring_size, q->ndesc); 188 q->head = Q_READ(dev, q, dma_idx); 189 q->tail = q->head; 190 } 191 192 static void 193 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 194 { 195 int i; 196 197 if (!q || !q->ndesc) 198 return; 199 200 /* clear descriptors */ 201 for (i = 0; i < q->ndesc; i++) 202 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 203 204 Q_WRITE(dev, q, cpu_idx, 0); 205 Q_WRITE(dev, q, dma_idx, 0); 206 mt76_dma_sync_idx(dev, q); 207 } 208 209 static int 210 mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q, 211 struct mt76_queue_buf *buf, void *data) 212 { 213 struct mt76_desc *desc = &q->desc[q->head]; 214 struct mt76_queue_entry *entry = &q->entry[q->head]; 215 struct mt76_txwi_cache *txwi = NULL; 216 u32 buf1 = 0, ctrl; 217 int idx = q->head; 218 int rx_token; 219 220 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 221 222 if (mt76_queue_is_wed_rx(q)) { 223 txwi = mt76_get_rxwi(dev); 224 if (!txwi) 225 return -ENOMEM; 226 227 rx_token = mt76_rx_token_consume(dev, data, txwi, buf->addr); 228 if (rx_token < 0) { 229 mt76_put_rxwi(dev, txwi); 230 return -ENOMEM; 231 } 232 233 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 234 ctrl |= MT_DMA_CTL_TO_HOST; 235 } 236 237 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 238 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 239 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 240 WRITE_ONCE(desc->info, 0); 241 242 entry->dma_addr[0] = buf->addr; 243 entry->dma_len[0] = buf->len; 244 entry->txwi = txwi; 245 entry->buf = data; 246 entry->wcid = 0xffff; 247 entry->skip_buf1 = true; 248 q->head = (q->head + 1) % q->ndesc; 249 q->queued++; 250 251 return idx; 252 } 253 254 static int 255 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 256 struct mt76_queue_buf *buf, int nbufs, u32 info, 257 struct sk_buff *skb, void *txwi) 258 { 259 struct mt76_queue_entry *entry; 260 struct mt76_desc *desc; 261 int i, idx = -1; 262 u32 ctrl, next; 263 264 if (txwi) { 265 q->entry[q->head].txwi = DMA_DUMMY_DATA; 266 q->entry[q->head].skip_buf0 = true; 267 } 268 269 for (i = 0; i < nbufs; i += 2, buf += 2) { 270 u32 buf0 = buf[0].addr, buf1 = 0; 271 272 idx = q->head; 273 next = (q->head + 1) % q->ndesc; 274 275 desc = &q->desc[idx]; 276 entry = &q->entry[idx]; 277 278 if (buf[0].skip_unmap) 279 entry->skip_buf0 = true; 280 entry->skip_buf1 = i == nbufs - 1; 281 282 entry->dma_addr[0] = buf[0].addr; 283 entry->dma_len[0] = buf[0].len; 284 285 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 286 if (i < nbufs - 1) { 287 entry->dma_addr[1] = buf[1].addr; 288 entry->dma_len[1] = buf[1].len; 289 buf1 = buf[1].addr; 290 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 291 if (buf[1].skip_unmap) 292 entry->skip_buf1 = true; 293 } 294 295 if (i == nbufs - 1) 296 ctrl |= MT_DMA_CTL_LAST_SEC0; 297 else if (i == nbufs - 2) 298 ctrl |= MT_DMA_CTL_LAST_SEC1; 299 300 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 301 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 302 WRITE_ONCE(desc->info, cpu_to_le32(info)); 303 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 304 305 q->head = next; 306 q->queued++; 307 } 308 309 q->entry[idx].txwi = txwi; 310 q->entry[idx].skb = skb; 311 q->entry[idx].wcid = 0xffff; 312 313 return idx; 314 } 315 316 static void 317 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 318 struct mt76_queue_entry *prev_e) 319 { 320 struct mt76_queue_entry *e = &q->entry[idx]; 321 322 if (!e->skip_buf0) 323 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0], 324 DMA_TO_DEVICE); 325 326 if (!e->skip_buf1) 327 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1], 328 DMA_TO_DEVICE); 329 330 if (e->txwi == DMA_DUMMY_DATA) 331 e->txwi = NULL; 332 333 if (e->skb == DMA_DUMMY_DATA) 334 e->skb = NULL; 335 336 *prev_e = *e; 337 memset(e, 0, sizeof(*e)); 338 } 339 340 static void 341 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 342 { 343 wmb(); 344 Q_WRITE(dev, q, cpu_idx, q->head); 345 } 346 347 static void 348 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush) 349 { 350 struct mt76_queue_entry entry; 351 int last; 352 353 if (!q || !q->ndesc) 354 return; 355 356 spin_lock_bh(&q->cleanup_lock); 357 if (flush) 358 last = -1; 359 else 360 last = Q_READ(dev, q, dma_idx); 361 362 while (q->queued > 0 && q->tail != last) { 363 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 364 mt76_queue_tx_complete(dev, q, &entry); 365 366 if (entry.txwi) { 367 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 368 mt76_put_txwi(dev, entry.txwi); 369 } 370 371 if (!flush && q->tail == last) 372 last = Q_READ(dev, q, dma_idx); 373 } 374 spin_unlock_bh(&q->cleanup_lock); 375 376 if (flush) { 377 spin_lock_bh(&q->lock); 378 mt76_dma_sync_idx(dev, q); 379 mt76_dma_kick_queue(dev, q); 380 spin_unlock_bh(&q->lock); 381 } 382 383 if (!q->queued) 384 wake_up(&dev->tx_wait); 385 } 386 387 static void * 388 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 389 int *len, u32 *info, bool *more, bool *drop) 390 { 391 struct mt76_queue_entry *e = &q->entry[idx]; 392 struct mt76_desc *desc = &q->desc[idx]; 393 void *buf; 394 395 if (len) { 396 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 397 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 398 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0); 399 } 400 401 if (info) 402 *info = le32_to_cpu(desc->info); 403 404 if (mt76_queue_is_wed_rx(q)) { 405 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN, 406 le32_to_cpu(desc->buf1)); 407 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token); 408 409 if (!t) 410 return NULL; 411 412 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 413 SKB_WITH_OVERHEAD(q->buf_size), 414 page_pool_get_dma_dir(q->page_pool)); 415 416 buf = t->ptr; 417 t->dma_addr = 0; 418 t->ptr = NULL; 419 420 mt76_put_rxwi(dev, t); 421 422 if (drop) { 423 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 424 425 *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | 426 MT_DMA_CTL_DROP)); 427 } 428 } else { 429 buf = e->buf; 430 e->buf = NULL; 431 dma_sync_single_for_cpu(dev->dma_dev, e->dma_addr[0], 432 SKB_WITH_OVERHEAD(q->buf_size), 433 page_pool_get_dma_dir(q->page_pool)); 434 } 435 436 return buf; 437 } 438 439 static void * 440 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 441 int *len, u32 *info, bool *more, bool *drop) 442 { 443 int idx = q->tail; 444 445 *more = false; 446 if (!q->queued) 447 return NULL; 448 449 if (flush) 450 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 451 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 452 return NULL; 453 454 q->tail = (q->tail + 1) % q->ndesc; 455 q->queued--; 456 457 return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 458 } 459 460 static int 461 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q, 462 struct sk_buff *skb, u32 tx_info) 463 { 464 struct mt76_queue_buf buf = {}; 465 dma_addr_t addr; 466 467 if (q->queued + 1 >= q->ndesc - 1) 468 goto error; 469 470 addr = dma_map_single(dev->dma_dev, skb->data, skb->len, 471 DMA_TO_DEVICE); 472 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 473 goto error; 474 475 buf.addr = addr; 476 buf.len = skb->len; 477 478 spin_lock_bh(&q->lock); 479 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 480 mt76_dma_kick_queue(dev, q); 481 spin_unlock_bh(&q->lock); 482 483 return 0; 484 485 error: 486 dev_kfree_skb(skb); 487 return -ENOMEM; 488 } 489 490 static int 491 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q, 492 enum mt76_txq_id qid, struct sk_buff *skb, 493 struct mt76_wcid *wcid, struct ieee80211_sta *sta) 494 { 495 struct ieee80211_tx_status status = { 496 .sta = sta, 497 }; 498 struct mt76_tx_info tx_info = { 499 .skb = skb, 500 }; 501 struct ieee80211_hw *hw; 502 int len, n = 0, ret = -ENOMEM; 503 struct mt76_txwi_cache *t; 504 struct sk_buff *iter; 505 dma_addr_t addr; 506 u8 *txwi; 507 508 t = mt76_get_txwi(dev); 509 if (!t) 510 goto free_skb; 511 512 txwi = mt76_get_txwi_ptr(dev, t); 513 514 skb->prev = skb->next = NULL; 515 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 516 mt76_insert_hdr_pad(skb); 517 518 len = skb_headlen(skb); 519 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE); 520 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 521 goto free; 522 523 tx_info.buf[n].addr = t->dma_addr; 524 tx_info.buf[n++].len = dev->drv->txwi_size; 525 tx_info.buf[n].addr = addr; 526 tx_info.buf[n++].len = len; 527 528 skb_walk_frags(skb, iter) { 529 if (n == ARRAY_SIZE(tx_info.buf)) 530 goto unmap; 531 532 addr = dma_map_single(dev->dma_dev, iter->data, iter->len, 533 DMA_TO_DEVICE); 534 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 535 goto unmap; 536 537 tx_info.buf[n].addr = addr; 538 tx_info.buf[n++].len = iter->len; 539 } 540 tx_info.nbuf = n; 541 542 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 543 ret = -ENOMEM; 544 goto unmap; 545 } 546 547 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 548 DMA_TO_DEVICE); 549 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 550 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 551 DMA_TO_DEVICE); 552 if (ret < 0) 553 goto unmap; 554 555 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 556 tx_info.info, tx_info.skb, t); 557 558 unmap: 559 for (n--; n > 0; n--) 560 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr, 561 tx_info.buf[n].len, DMA_TO_DEVICE); 562 563 free: 564 #ifdef CONFIG_NL80211_TESTMODE 565 /* fix tx_done accounting on queue overflow */ 566 if (mt76_is_testmode_skb(dev, skb, &hw)) { 567 struct mt76_phy *phy = hw->priv; 568 569 if (tx_info.skb == phy->test.tx_skb) 570 phy->test.tx_done--; 571 } 572 #endif 573 574 mt76_put_txwi(dev, t); 575 576 free_skb: 577 status.skb = tx_info.skb; 578 hw = mt76_tx_status_get_hw(dev, tx_info.skb); 579 ieee80211_tx_status_ext(hw, &status); 580 581 return ret; 582 } 583 584 static int 585 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 586 bool allow_direct) 587 { 588 int len = SKB_WITH_OVERHEAD(q->buf_size); 589 int frames = 0; 590 591 if (!q->ndesc) 592 return 0; 593 594 spin_lock_bh(&q->lock); 595 596 while (q->queued < q->ndesc - 1) { 597 enum dma_data_direction dir; 598 struct mt76_queue_buf qbuf; 599 dma_addr_t addr; 600 int offset; 601 void *buf; 602 603 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); 604 if (!buf) 605 break; 606 607 addr = page_pool_get_dma_addr(virt_to_head_page(buf)) + offset; 608 dir = page_pool_get_dma_dir(q->page_pool); 609 dma_sync_single_for_device(dev->dma_dev, addr, len, dir); 610 611 qbuf.addr = addr + q->buf_offset; 612 qbuf.len = len - q->buf_offset; 613 qbuf.skip_unmap = false; 614 if (mt76_dma_add_rx_buf(dev, q, &qbuf, buf) < 0) { 615 mt76_put_page_pool_buf(buf, allow_direct); 616 break; 617 } 618 frames++; 619 } 620 621 if (frames) 622 mt76_dma_kick_queue(dev, q); 623 624 spin_unlock_bh(&q->lock); 625 626 return frames; 627 } 628 629 int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) 630 { 631 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 632 struct mtk_wed_device *wed = &dev->mmio.wed; 633 int ret, type, ring; 634 u8 flags; 635 636 if (!q || !q->ndesc) 637 return -EINVAL; 638 639 flags = q->flags; 640 if (!mtk_wed_device_active(wed)) 641 q->flags &= ~MT_QFLAG_WED; 642 643 if (!(q->flags & MT_QFLAG_WED)) 644 return 0; 645 646 type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); 647 ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); 648 649 switch (type) { 650 case MT76_WED_Q_TX: 651 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs, reset); 652 if (!ret) 653 q->wed_regs = wed->tx_ring[ring].reg_base; 654 break; 655 case MT76_WED_Q_TXFREE: 656 /* WED txfree queue needs ring to be initialized before setup */ 657 q->flags = 0; 658 mt76_dma_queue_reset(dev, q); 659 mt76_dma_rx_fill(dev, q, false); 660 q->flags = flags; 661 662 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs); 663 if (!ret) 664 q->wed_regs = wed->txfree_ring.reg_base; 665 break; 666 case MT76_WED_Q_RX: 667 ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, reset); 668 if (!ret) 669 q->wed_regs = wed->rx_ring[ring].reg_base; 670 break; 671 default: 672 ret = -EINVAL; 673 } 674 675 return ret; 676 #else 677 return 0; 678 #endif 679 } 680 EXPORT_SYMBOL_GPL(mt76_dma_wed_setup); 681 682 static int 683 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 684 int idx, int n_desc, int bufsize, 685 u32 ring_base) 686 { 687 int ret, size; 688 689 spin_lock_init(&q->lock); 690 spin_lock_init(&q->cleanup_lock); 691 692 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 693 q->ndesc = n_desc; 694 q->buf_size = bufsize; 695 q->hw_idx = idx; 696 697 size = q->ndesc * sizeof(struct mt76_desc); 698 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL); 699 if (!q->desc) 700 return -ENOMEM; 701 702 size = q->ndesc * sizeof(*q->entry); 703 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 704 if (!q->entry) 705 return -ENOMEM; 706 707 ret = mt76_create_page_pool(dev, q); 708 if (ret) 709 return ret; 710 711 ret = mt76_dma_wed_setup(dev, q, false); 712 if (ret) 713 return ret; 714 715 if (q->flags != MT_WED_Q_TXFREE) 716 mt76_dma_queue_reset(dev, q); 717 718 return 0; 719 } 720 721 static void 722 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 723 { 724 void *buf; 725 bool more; 726 727 if (!q->ndesc) 728 return; 729 730 spin_lock_bh(&q->lock); 731 732 do { 733 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL); 734 if (!buf) 735 break; 736 737 mt76_put_page_pool_buf(buf, false); 738 } while (1); 739 740 if (q->rx_head) { 741 dev_kfree_skb(q->rx_head); 742 q->rx_head = NULL; 743 } 744 745 spin_unlock_bh(&q->lock); 746 } 747 748 static void 749 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 750 { 751 struct mt76_queue *q = &dev->q_rx[qid]; 752 int i; 753 754 if (!q->ndesc) 755 return; 756 757 for (i = 0; i < q->ndesc; i++) 758 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 759 760 mt76_dma_rx_cleanup(dev, q); 761 762 /* reset WED rx queues */ 763 mt76_dma_wed_setup(dev, q, true); 764 if (q->flags != MT_WED_Q_TXFREE) { 765 mt76_dma_sync_idx(dev, q); 766 mt76_dma_rx_fill(dev, q, false); 767 } 768 } 769 770 static void 771 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 772 int len, bool more, u32 info) 773 { 774 struct sk_buff *skb = q->rx_head; 775 struct skb_shared_info *shinfo = skb_shinfo(skb); 776 int nr_frags = shinfo->nr_frags; 777 778 if (nr_frags < ARRAY_SIZE(shinfo->frags)) { 779 struct page *page = virt_to_head_page(data); 780 int offset = data - page_address(page) + q->buf_offset; 781 782 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size); 783 } else { 784 mt76_put_page_pool_buf(data, true); 785 } 786 787 if (more) 788 return; 789 790 q->rx_head = NULL; 791 if (nr_frags < ARRAY_SIZE(shinfo->frags)) 792 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 793 else 794 dev_kfree_skb(skb); 795 } 796 797 static int 798 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 799 { 800 int len, data_len, done = 0, dma_idx; 801 struct sk_buff *skb; 802 unsigned char *data; 803 bool check_ddone = false; 804 bool more; 805 806 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 807 q->flags == MT_WED_Q_TXFREE) { 808 dma_idx = Q_READ(dev, q, dma_idx); 809 check_ddone = true; 810 } 811 812 while (done < budget) { 813 bool drop = false; 814 u32 info; 815 816 if (check_ddone) { 817 if (q->tail == dma_idx) 818 dma_idx = Q_READ(dev, q, dma_idx); 819 820 if (q->tail == dma_idx) 821 break; 822 } 823 824 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, 825 &drop); 826 if (!data) 827 break; 828 829 if (drop) 830 goto free_frag; 831 832 if (q->rx_head) 833 data_len = q->buf_size; 834 else 835 data_len = SKB_WITH_OVERHEAD(q->buf_size); 836 837 if (data_len < len + q->buf_offset) { 838 dev_kfree_skb(q->rx_head); 839 q->rx_head = NULL; 840 goto free_frag; 841 } 842 843 if (q->rx_head) { 844 mt76_add_fragment(dev, q, data, len, more, info); 845 continue; 846 } 847 848 if (!more && dev->drv->rx_check && 849 !(dev->drv->rx_check(dev, data, len))) 850 goto free_frag; 851 852 skb = build_skb(data, q->buf_size); 853 if (!skb) 854 goto free_frag; 855 856 skb_reserve(skb, q->buf_offset); 857 skb_mark_for_recycle(skb); 858 859 *(u32 *)skb->cb = info; 860 861 __skb_put(skb, len); 862 done++; 863 864 if (more) { 865 q->rx_head = skb; 866 continue; 867 } 868 869 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 870 continue; 871 872 free_frag: 873 mt76_put_page_pool_buf(data, true); 874 } 875 876 mt76_dma_rx_fill(dev, q, true); 877 return done; 878 } 879 880 int mt76_dma_rx_poll(struct napi_struct *napi, int budget) 881 { 882 struct mt76_dev *dev; 883 int qid, done = 0, cur; 884 885 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 886 qid = napi - dev->napi; 887 888 rcu_read_lock(); 889 890 do { 891 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 892 mt76_rx_poll_complete(dev, qid, napi); 893 done += cur; 894 } while (cur && done < budget); 895 896 rcu_read_unlock(); 897 898 if (done < budget && napi_complete(napi)) 899 dev->drv->rx_poll_complete(dev, qid); 900 901 return done; 902 } 903 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 904 905 static int 906 mt76_dma_init(struct mt76_dev *dev, 907 int (*poll)(struct napi_struct *napi, int budget)) 908 { 909 int i; 910 911 init_dummy_netdev(&dev->napi_dev); 912 init_dummy_netdev(&dev->tx_napi_dev); 913 snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s", 914 wiphy_name(dev->hw->wiphy)); 915 dev->napi_dev.threaded = 1; 916 init_completion(&dev->mmio.wed_reset); 917 init_completion(&dev->mmio.wed_reset_complete); 918 919 mt76_for_each_q_rx(dev, i) { 920 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll); 921 mt76_dma_rx_fill(dev, &dev->q_rx[i], false); 922 napi_enable(&dev->napi[i]); 923 } 924 925 return 0; 926 } 927 928 static const struct mt76_queue_ops mt76_dma_ops = { 929 .init = mt76_dma_init, 930 .alloc = mt76_dma_alloc_queue, 931 .reset_q = mt76_dma_queue_reset, 932 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 933 .tx_queue_skb = mt76_dma_tx_queue_skb, 934 .tx_cleanup = mt76_dma_tx_cleanup, 935 .rx_cleanup = mt76_dma_rx_cleanup, 936 .rx_reset = mt76_dma_rx_reset, 937 .kick = mt76_dma_kick_queue, 938 }; 939 940 void mt76_dma_attach(struct mt76_dev *dev) 941 { 942 dev->queue_ops = &mt76_dma_ops; 943 } 944 EXPORT_SYMBOL_GPL(mt76_dma_attach); 945 946 void mt76_dma_cleanup(struct mt76_dev *dev) 947 { 948 int i; 949 950 mt76_worker_disable(&dev->tx_worker); 951 netif_napi_del(&dev->tx_napi); 952 953 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 954 struct mt76_phy *phy = dev->phys[i]; 955 int j; 956 957 if (!phy) 958 continue; 959 960 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++) 961 mt76_dma_tx_cleanup(dev, phy->q_tx[j], true); 962 } 963 964 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++) 965 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true); 966 967 mt76_for_each_q_rx(dev, i) { 968 struct mt76_queue *q = &dev->q_rx[i]; 969 970 netif_napi_del(&dev->napi[i]); 971 mt76_dma_rx_cleanup(dev, q); 972 973 page_pool_destroy(q->page_pool); 974 } 975 976 mt76_free_pending_txwi(dev); 977 mt76_free_pending_rxwi(dev); 978 979 if (mtk_wed_device_active(&dev->mmio.wed)) 980 mtk_wed_device_detach(&dev->mmio.wed); 981 } 982 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 983