1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #include "mt76.h" 8 #include "dma.h" 9 10 static int 11 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 12 int idx, int n_desc, int bufsize, 13 u32 ring_base) 14 { 15 int size; 16 int i; 17 18 spin_lock_init(&q->lock); 19 20 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 21 q->ndesc = n_desc; 22 q->buf_size = bufsize; 23 q->hw_idx = idx; 24 25 size = q->ndesc * sizeof(struct mt76_desc); 26 q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL); 27 if (!q->desc) 28 return -ENOMEM; 29 30 size = q->ndesc * sizeof(*q->entry); 31 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 32 if (!q->entry) 33 return -ENOMEM; 34 35 /* clear descriptors */ 36 for (i = 0; i < q->ndesc; i++) 37 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 38 39 writel(q->desc_dma, &q->regs->desc_base); 40 writel(0, &q->regs->cpu_idx); 41 writel(0, &q->regs->dma_idx); 42 writel(q->ndesc, &q->regs->ring_size); 43 44 return 0; 45 } 46 47 static int 48 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 49 struct mt76_queue_buf *buf, int nbufs, u32 info, 50 struct sk_buff *skb, void *txwi) 51 { 52 struct mt76_desc *desc; 53 u32 ctrl; 54 int i, idx = -1; 55 56 if (txwi) { 57 q->entry[q->head].txwi = DMA_DUMMY_DATA; 58 q->entry[q->head].skip_buf0 = true; 59 } 60 61 for (i = 0; i < nbufs; i += 2, buf += 2) { 62 u32 buf0 = buf[0].addr, buf1 = 0; 63 64 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 65 if (i < nbufs - 1) { 66 buf1 = buf[1].addr; 67 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 68 } 69 70 if (i == nbufs - 1) 71 ctrl |= MT_DMA_CTL_LAST_SEC0; 72 else if (i == nbufs - 2) 73 ctrl |= MT_DMA_CTL_LAST_SEC1; 74 75 idx = q->head; 76 q->head = (q->head + 1) % q->ndesc; 77 78 desc = &q->desc[idx]; 79 80 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 81 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 82 WRITE_ONCE(desc->info, cpu_to_le32(info)); 83 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 84 85 q->queued++; 86 } 87 88 q->entry[idx].txwi = txwi; 89 q->entry[idx].skb = skb; 90 91 return idx; 92 } 93 94 static void 95 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 96 struct mt76_queue_entry *prev_e) 97 { 98 struct mt76_queue_entry *e = &q->entry[idx]; 99 __le32 __ctrl = READ_ONCE(q->desc[idx].ctrl); 100 u32 ctrl = le32_to_cpu(__ctrl); 101 102 if (!e->skip_buf0) { 103 __le32 addr = READ_ONCE(q->desc[idx].buf0); 104 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 105 106 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 107 DMA_TO_DEVICE); 108 } 109 110 if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) { 111 __le32 addr = READ_ONCE(q->desc[idx].buf1); 112 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl); 113 114 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 115 DMA_TO_DEVICE); 116 } 117 118 if (e->txwi == DMA_DUMMY_DATA) 119 e->txwi = NULL; 120 121 if (e->skb == DMA_DUMMY_DATA) 122 e->skb = NULL; 123 124 *prev_e = *e; 125 memset(e, 0, sizeof(*e)); 126 } 127 128 static void 129 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 130 { 131 writel(q->desc_dma, &q->regs->desc_base); 132 writel(q->ndesc, &q->regs->ring_size); 133 q->head = readl(&q->regs->dma_idx); 134 q->tail = q->head; 135 } 136 137 static void 138 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 139 { 140 writel(q->head, &q->regs->cpu_idx); 141 } 142 143 static void 144 mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) 145 { 146 struct mt76_sw_queue *sq = &dev->q_tx[qid]; 147 struct mt76_queue *q = sq->q; 148 struct mt76_queue_entry entry; 149 unsigned int n_swq_queued[8] = {}; 150 unsigned int n_queued = 0; 151 bool wake = false; 152 int i, last; 153 154 if (!q) 155 return; 156 157 if (flush) 158 last = -1; 159 else 160 last = readl(&q->regs->dma_idx); 161 162 while ((q->queued > n_queued) && q->tail != last) { 163 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 164 if (entry.schedule) 165 n_swq_queued[entry.qid]++; 166 167 q->tail = (q->tail + 1) % q->ndesc; 168 n_queued++; 169 170 if (entry.skb) 171 dev->drv->tx_complete_skb(dev, qid, &entry); 172 173 if (entry.txwi) { 174 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 175 mt76_put_txwi(dev, entry.txwi); 176 wake = !flush; 177 } 178 179 if (!flush && q->tail == last) 180 last = readl(&q->regs->dma_idx); 181 } 182 183 spin_lock_bh(&q->lock); 184 185 q->queued -= n_queued; 186 for (i = 0; i < 4; i++) { 187 if (!n_swq_queued[i]) 188 continue; 189 190 dev->q_tx[i].swq_queued -= n_swq_queued[i]; 191 } 192 193 /* ext PHY */ 194 for (i = 0; i < 4; i++) { 195 if (!n_swq_queued[i]) 196 continue; 197 198 dev->q_tx[__MT_TXQ_MAX + i].swq_queued -= n_swq_queued[4 + i]; 199 } 200 201 if (flush) { 202 mt76_dma_sync_idx(dev, q); 203 mt76_dma_kick_queue(dev, q); 204 } 205 206 wake = wake && q->stopped && 207 qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8; 208 if (wake) 209 q->stopped = false; 210 211 if (!q->queued) 212 wake_up(&dev->tx_wait); 213 214 spin_unlock_bh(&q->lock); 215 216 if (wake) 217 ieee80211_wake_queue(dev->hw, qid); 218 } 219 220 static void * 221 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 222 int *len, u32 *info, bool *more) 223 { 224 struct mt76_queue_entry *e = &q->entry[idx]; 225 struct mt76_desc *desc = &q->desc[idx]; 226 dma_addr_t buf_addr; 227 void *buf = e->buf; 228 int buf_len = SKB_WITH_OVERHEAD(q->buf_size); 229 230 buf_addr = le32_to_cpu(READ_ONCE(desc->buf0)); 231 if (len) { 232 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl)); 233 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl); 234 *more = !(ctl & MT_DMA_CTL_LAST_SEC0); 235 } 236 237 if (info) 238 *info = le32_to_cpu(desc->info); 239 240 dma_unmap_single(dev->dev, buf_addr, buf_len, DMA_FROM_DEVICE); 241 e->buf = NULL; 242 243 return buf; 244 } 245 246 static void * 247 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 248 int *len, u32 *info, bool *more) 249 { 250 int idx = q->tail; 251 252 *more = false; 253 if (!q->queued) 254 return NULL; 255 256 if (flush) 257 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 258 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 259 return NULL; 260 261 q->tail = (q->tail + 1) % q->ndesc; 262 q->queued--; 263 264 return mt76_dma_get_buf(dev, q, idx, len, info, more); 265 } 266 267 static int 268 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid, 269 struct sk_buff *skb, u32 tx_info) 270 { 271 struct mt76_queue *q = dev->q_tx[qid].q; 272 struct mt76_queue_buf buf; 273 dma_addr_t addr; 274 275 if (q->queued + 1 >= q->ndesc - 1) 276 goto error; 277 278 addr = dma_map_single(dev->dev, skb->data, skb->len, 279 DMA_TO_DEVICE); 280 if (unlikely(dma_mapping_error(dev->dev, addr))) 281 goto error; 282 283 buf.addr = addr; 284 buf.len = skb->len; 285 286 spin_lock_bh(&q->lock); 287 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 288 mt76_dma_kick_queue(dev, q); 289 spin_unlock_bh(&q->lock); 290 291 return 0; 292 293 error: 294 dev_kfree_skb(skb); 295 return -ENOMEM; 296 } 297 298 static int 299 mt76_dma_tx_queue_skb(struct mt76_dev *dev, enum mt76_txq_id qid, 300 struct sk_buff *skb, struct mt76_wcid *wcid, 301 struct ieee80211_sta *sta) 302 { 303 struct mt76_queue *q = dev->q_tx[qid].q; 304 struct mt76_tx_info tx_info = { 305 .skb = skb, 306 }; 307 struct ieee80211_hw *hw; 308 int len, n = 0, ret = -ENOMEM; 309 struct mt76_queue_entry e; 310 struct mt76_txwi_cache *t; 311 struct sk_buff *iter; 312 dma_addr_t addr; 313 u8 *txwi; 314 315 t = mt76_get_txwi(dev); 316 if (!t) { 317 hw = mt76_tx_status_get_hw(dev, skb); 318 ieee80211_free_txskb(hw, skb); 319 return -ENOMEM; 320 } 321 txwi = mt76_get_txwi_ptr(dev, t); 322 323 skb->prev = skb->next = NULL; 324 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 325 mt76_insert_hdr_pad(skb); 326 327 len = skb_headlen(skb); 328 addr = dma_map_single(dev->dev, skb->data, len, DMA_TO_DEVICE); 329 if (unlikely(dma_mapping_error(dev->dev, addr))) 330 goto free; 331 332 tx_info.buf[n].addr = t->dma_addr; 333 tx_info.buf[n++].len = dev->drv->txwi_size; 334 tx_info.buf[n].addr = addr; 335 tx_info.buf[n++].len = len; 336 337 skb_walk_frags(skb, iter) { 338 if (n == ARRAY_SIZE(tx_info.buf)) 339 goto unmap; 340 341 addr = dma_map_single(dev->dev, iter->data, iter->len, 342 DMA_TO_DEVICE); 343 if (unlikely(dma_mapping_error(dev->dev, addr))) 344 goto unmap; 345 346 tx_info.buf[n].addr = addr; 347 tx_info.buf[n++].len = iter->len; 348 } 349 tx_info.nbuf = n; 350 351 dma_sync_single_for_cpu(dev->dev, t->dma_addr, dev->drv->txwi_size, 352 DMA_TO_DEVICE); 353 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 354 dma_sync_single_for_device(dev->dev, t->dma_addr, dev->drv->txwi_size, 355 DMA_TO_DEVICE); 356 if (ret < 0) 357 goto unmap; 358 359 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 360 ret = -ENOMEM; 361 goto unmap; 362 } 363 364 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 365 tx_info.info, tx_info.skb, t); 366 367 unmap: 368 for (n--; n > 0; n--) 369 dma_unmap_single(dev->dev, tx_info.buf[n].addr, 370 tx_info.buf[n].len, DMA_TO_DEVICE); 371 372 free: 373 #ifdef CONFIG_NL80211_TESTMODE 374 /* fix tx_done accounting on queue overflow */ 375 if (tx_info.skb == dev->test.tx_skb) 376 dev->test.tx_done--; 377 #endif 378 379 e.skb = tx_info.skb; 380 e.txwi = t; 381 dev->drv->tx_complete_skb(dev, qid, &e); 382 mt76_put_txwi(dev, t); 383 return ret; 384 } 385 386 static int 387 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) 388 { 389 dma_addr_t addr; 390 void *buf; 391 int frames = 0; 392 int len = SKB_WITH_OVERHEAD(q->buf_size); 393 int offset = q->buf_offset; 394 395 spin_lock_bh(&q->lock); 396 397 while (q->queued < q->ndesc - 1) { 398 struct mt76_queue_buf qbuf; 399 400 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC); 401 if (!buf) 402 break; 403 404 addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE); 405 if (unlikely(dma_mapping_error(dev->dev, addr))) { 406 skb_free_frag(buf); 407 break; 408 } 409 410 qbuf.addr = addr + offset; 411 qbuf.len = len - offset; 412 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL); 413 frames++; 414 } 415 416 if (frames) 417 mt76_dma_kick_queue(dev, q); 418 419 spin_unlock_bh(&q->lock); 420 421 return frames; 422 } 423 424 static void 425 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 426 { 427 struct page *page; 428 void *buf; 429 bool more; 430 431 spin_lock_bh(&q->lock); 432 do { 433 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more); 434 if (!buf) 435 break; 436 437 skb_free_frag(buf); 438 } while (1); 439 spin_unlock_bh(&q->lock); 440 441 if (!q->rx_page.va) 442 return; 443 444 page = virt_to_page(q->rx_page.va); 445 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias); 446 memset(&q->rx_page, 0, sizeof(q->rx_page)); 447 } 448 449 static void 450 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 451 { 452 struct mt76_queue *q = &dev->q_rx[qid]; 453 int i; 454 455 for (i = 0; i < q->ndesc; i++) 456 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 457 458 mt76_dma_rx_cleanup(dev, q); 459 mt76_dma_sync_idx(dev, q); 460 mt76_dma_rx_fill(dev, q); 461 462 if (!q->rx_head) 463 return; 464 465 dev_kfree_skb(q->rx_head); 466 q->rx_head = NULL; 467 } 468 469 static void 470 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 471 int len, bool more) 472 { 473 struct page *page = virt_to_head_page(data); 474 int offset = data - page_address(page); 475 struct sk_buff *skb = q->rx_head; 476 struct skb_shared_info *shinfo = skb_shinfo(skb); 477 478 if (shinfo->nr_frags < ARRAY_SIZE(shinfo->frags)) { 479 offset += q->buf_offset; 480 skb_add_rx_frag(skb, shinfo->nr_frags, page, offset, len, 481 q->buf_size); 482 } 483 484 if (more) 485 return; 486 487 q->rx_head = NULL; 488 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 489 } 490 491 static int 492 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 493 { 494 int len, data_len, done = 0; 495 struct sk_buff *skb; 496 unsigned char *data; 497 bool more; 498 499 while (done < budget) { 500 u32 info; 501 502 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more); 503 if (!data) 504 break; 505 506 if (q->rx_head) 507 data_len = q->buf_size; 508 else 509 data_len = SKB_WITH_OVERHEAD(q->buf_size); 510 511 if (data_len < len + q->buf_offset) { 512 dev_kfree_skb(q->rx_head); 513 q->rx_head = NULL; 514 515 skb_free_frag(data); 516 continue; 517 } 518 519 if (q->rx_head) { 520 mt76_add_fragment(dev, q, data, len, more); 521 continue; 522 } 523 524 skb = build_skb(data, q->buf_size); 525 if (!skb) { 526 skb_free_frag(data); 527 continue; 528 } 529 skb_reserve(skb, q->buf_offset); 530 531 if (q == &dev->q_rx[MT_RXQ_MCU]) { 532 u32 *rxfce = (u32 *)skb->cb; 533 *rxfce = info; 534 } 535 536 __skb_put(skb, len); 537 done++; 538 539 if (more) { 540 q->rx_head = skb; 541 continue; 542 } 543 544 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 545 } 546 547 mt76_dma_rx_fill(dev, q); 548 return done; 549 } 550 551 static int 552 mt76_dma_rx_poll(struct napi_struct *napi, int budget) 553 { 554 struct mt76_dev *dev; 555 int qid, done = 0, cur; 556 557 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 558 qid = napi - dev->napi; 559 560 local_bh_disable(); 561 rcu_read_lock(); 562 563 do { 564 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 565 mt76_rx_poll_complete(dev, qid, napi); 566 done += cur; 567 } while (cur && done < budget); 568 569 rcu_read_unlock(); 570 local_bh_enable(); 571 572 if (done < budget && napi_complete(napi)) 573 dev->drv->rx_poll_complete(dev, qid); 574 575 return done; 576 } 577 578 static int 579 mt76_dma_init(struct mt76_dev *dev) 580 { 581 int i; 582 583 init_dummy_netdev(&dev->napi_dev); 584 585 mt76_for_each_q_rx(dev, i) { 586 netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll, 587 64); 588 mt76_dma_rx_fill(dev, &dev->q_rx[i]); 589 napi_enable(&dev->napi[i]); 590 } 591 592 return 0; 593 } 594 595 static const struct mt76_queue_ops mt76_dma_ops = { 596 .init = mt76_dma_init, 597 .alloc = mt76_dma_alloc_queue, 598 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 599 .tx_queue_skb = mt76_dma_tx_queue_skb, 600 .tx_cleanup = mt76_dma_tx_cleanup, 601 .rx_reset = mt76_dma_rx_reset, 602 .kick = mt76_dma_kick_queue, 603 }; 604 605 void mt76_dma_attach(struct mt76_dev *dev) 606 { 607 dev->queue_ops = &mt76_dma_ops; 608 } 609 EXPORT_SYMBOL_GPL(mt76_dma_attach); 610 611 void mt76_dma_cleanup(struct mt76_dev *dev) 612 { 613 int i; 614 615 netif_napi_del(&dev->tx_napi); 616 for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++) 617 mt76_dma_tx_cleanup(dev, i, true); 618 619 mt76_for_each_q_rx(dev, i) { 620 netif_napi_del(&dev->napi[i]); 621 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]); 622 } 623 } 624 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 625