1 /* 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "mt76.h" 19 #include "dma.h" 20 21 static int 22 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 23 int idx, int n_desc, int bufsize, 24 u32 ring_base) 25 { 26 int size; 27 int i; 28 29 spin_lock_init(&q->lock); 30 31 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 32 q->ndesc = n_desc; 33 q->buf_size = bufsize; 34 q->hw_idx = idx; 35 36 size = q->ndesc * sizeof(struct mt76_desc); 37 q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL); 38 if (!q->desc) 39 return -ENOMEM; 40 41 size = q->ndesc * sizeof(*q->entry); 42 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 43 if (!q->entry) 44 return -ENOMEM; 45 46 /* clear descriptors */ 47 for (i = 0; i < q->ndesc; i++) 48 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 49 50 writel(q->desc_dma, &q->regs->desc_base); 51 writel(0, &q->regs->cpu_idx); 52 writel(0, &q->regs->dma_idx); 53 writel(q->ndesc, &q->regs->ring_size); 54 55 return 0; 56 } 57 58 static int 59 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 60 struct mt76_queue_buf *buf, int nbufs, u32 info, 61 struct sk_buff *skb, void *txwi) 62 { 63 struct mt76_desc *desc; 64 u32 ctrl; 65 int i, idx = -1; 66 67 if (txwi) 68 q->entry[q->head].txwi = DMA_DUMMY_DATA; 69 70 for (i = 0; i < nbufs; i += 2, buf += 2) { 71 u32 buf0 = buf[0].addr, buf1 = 0; 72 73 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 74 if (i < nbufs - 1) { 75 buf1 = buf[1].addr; 76 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 77 } 78 79 if (i == nbufs - 1) 80 ctrl |= MT_DMA_CTL_LAST_SEC0; 81 else if (i == nbufs - 2) 82 ctrl |= MT_DMA_CTL_LAST_SEC1; 83 84 idx = q->head; 85 q->head = (q->head + 1) % q->ndesc; 86 87 desc = &q->desc[idx]; 88 89 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 90 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 91 WRITE_ONCE(desc->info, cpu_to_le32(info)); 92 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 93 94 q->queued++; 95 } 96 97 q->entry[idx].txwi = txwi; 98 q->entry[idx].skb = skb; 99 100 return idx; 101 } 102 103 static void 104 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 105 struct mt76_queue_entry *prev_e) 106 { 107 struct mt76_queue_entry *e = &q->entry[idx]; 108 __le32 __ctrl = READ_ONCE(q->desc[idx].ctrl); 109 u32 ctrl = le32_to_cpu(__ctrl); 110 111 if (!e->txwi || !e->skb) { 112 __le32 addr = READ_ONCE(q->desc[idx].buf0); 113 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 114 115 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 116 DMA_TO_DEVICE); 117 } 118 119 if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) { 120 __le32 addr = READ_ONCE(q->desc[idx].buf1); 121 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl); 122 123 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 124 DMA_TO_DEVICE); 125 } 126 127 if (e->txwi == DMA_DUMMY_DATA) 128 e->txwi = NULL; 129 130 if (e->skb == DMA_DUMMY_DATA) 131 e->skb = NULL; 132 133 *prev_e = *e; 134 memset(e, 0, sizeof(*e)); 135 } 136 137 static void 138 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 139 { 140 writel(q->desc_dma, &q->regs->desc_base); 141 writel(q->ndesc, &q->regs->ring_size); 142 q->head = readl(&q->regs->dma_idx); 143 q->tail = q->head; 144 writel(q->head, &q->regs->cpu_idx); 145 } 146 147 static void 148 mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) 149 { 150 struct mt76_sw_queue *sq = &dev->q_tx[qid]; 151 struct mt76_queue *q = sq->q; 152 struct mt76_queue_entry entry; 153 unsigned int n_swq_queued[4] = {}; 154 unsigned int n_queued = 0; 155 bool wake = false; 156 int i, last; 157 158 if (!q) 159 return; 160 161 if (flush) 162 last = -1; 163 else 164 last = readl(&q->regs->dma_idx); 165 166 while ((q->queued > n_queued) && q->tail != last) { 167 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 168 if (entry.schedule) 169 n_swq_queued[entry.qid]++; 170 171 q->tail = (q->tail + 1) % q->ndesc; 172 n_queued++; 173 174 if (entry.skb) 175 dev->drv->tx_complete_skb(dev, qid, &entry); 176 177 if (entry.txwi) { 178 if (!(dev->drv->txwi_flags & MT_TXWI_NO_FREE)) 179 mt76_put_txwi(dev, entry.txwi); 180 wake = !flush; 181 } 182 183 if (!flush && q->tail == last) 184 last = readl(&q->regs->dma_idx); 185 } 186 187 spin_lock_bh(&q->lock); 188 189 q->queued -= n_queued; 190 for (i = 0; i < ARRAY_SIZE(n_swq_queued); i++) { 191 if (!n_swq_queued[i]) 192 continue; 193 194 dev->q_tx[i].swq_queued -= n_swq_queued[i]; 195 } 196 197 if (flush) 198 mt76_dma_sync_idx(dev, q); 199 200 wake = wake && q->stopped && 201 qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8; 202 if (wake) 203 q->stopped = false; 204 205 if (!q->queued) 206 wake_up(&dev->tx_wait); 207 208 spin_unlock_bh(&q->lock); 209 210 if (wake) 211 ieee80211_wake_queue(dev->hw, qid); 212 } 213 214 static void * 215 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 216 int *len, u32 *info, bool *more) 217 { 218 struct mt76_queue_entry *e = &q->entry[idx]; 219 struct mt76_desc *desc = &q->desc[idx]; 220 dma_addr_t buf_addr; 221 void *buf = e->buf; 222 int buf_len = SKB_WITH_OVERHEAD(q->buf_size); 223 224 buf_addr = le32_to_cpu(READ_ONCE(desc->buf0)); 225 if (len) { 226 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl)); 227 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl); 228 *more = !(ctl & MT_DMA_CTL_LAST_SEC0); 229 } 230 231 if (info) 232 *info = le32_to_cpu(desc->info); 233 234 dma_unmap_single(dev->dev, buf_addr, buf_len, DMA_FROM_DEVICE); 235 e->buf = NULL; 236 237 return buf; 238 } 239 240 static void * 241 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 242 int *len, u32 *info, bool *more) 243 { 244 int idx = q->tail; 245 246 *more = false; 247 if (!q->queued) 248 return NULL; 249 250 if (!flush && !(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 251 return NULL; 252 253 q->tail = (q->tail + 1) % q->ndesc; 254 q->queued--; 255 256 return mt76_dma_get_buf(dev, q, idx, len, info, more); 257 } 258 259 static void 260 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 261 { 262 writel(q->head, &q->regs->cpu_idx); 263 } 264 265 static int 266 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid, 267 struct sk_buff *skb, u32 tx_info) 268 { 269 struct mt76_queue *q = dev->q_tx[qid].q; 270 struct mt76_queue_buf buf; 271 dma_addr_t addr; 272 273 addr = dma_map_single(dev->dev, skb->data, skb->len, 274 DMA_TO_DEVICE); 275 if (unlikely(dma_mapping_error(dev->dev, addr))) 276 return -ENOMEM; 277 278 buf.addr = addr; 279 buf.len = skb->len; 280 281 spin_lock_bh(&q->lock); 282 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 283 mt76_dma_kick_queue(dev, q); 284 spin_unlock_bh(&q->lock); 285 286 return 0; 287 } 288 289 static int 290 mt76_dma_tx_queue_skb(struct mt76_dev *dev, enum mt76_txq_id qid, 291 struct sk_buff *skb, struct mt76_wcid *wcid, 292 struct ieee80211_sta *sta) 293 { 294 struct mt76_queue *q = dev->q_tx[qid].q; 295 struct mt76_tx_info tx_info = { 296 .skb = skb, 297 }; 298 int len, n = 0, ret = -ENOMEM; 299 struct mt76_queue_entry e; 300 struct mt76_txwi_cache *t; 301 struct sk_buff *iter; 302 dma_addr_t addr; 303 u8 *txwi; 304 305 t = mt76_get_txwi(dev); 306 if (!t) { 307 ieee80211_free_txskb(dev->hw, skb); 308 return -ENOMEM; 309 } 310 txwi = mt76_get_txwi_ptr(dev, t); 311 312 skb->prev = skb->next = NULL; 313 if (dev->drv->tx_aligned4_skbs) 314 mt76_insert_hdr_pad(skb); 315 316 len = skb_headlen(skb); 317 addr = dma_map_single(dev->dev, skb->data, len, DMA_TO_DEVICE); 318 if (unlikely(dma_mapping_error(dev->dev, addr))) 319 goto free; 320 321 tx_info.buf[n].addr = t->dma_addr; 322 tx_info.buf[n++].len = dev->drv->txwi_size; 323 tx_info.buf[n].addr = addr; 324 tx_info.buf[n++].len = len; 325 326 skb_walk_frags(skb, iter) { 327 if (n == ARRAY_SIZE(tx_info.buf)) 328 goto unmap; 329 330 addr = dma_map_single(dev->dev, iter->data, iter->len, 331 DMA_TO_DEVICE); 332 if (unlikely(dma_mapping_error(dev->dev, addr))) 333 goto unmap; 334 335 tx_info.buf[n].addr = addr; 336 tx_info.buf[n++].len = iter->len; 337 } 338 tx_info.nbuf = n; 339 340 dma_sync_single_for_cpu(dev->dev, t->dma_addr, dev->drv->txwi_size, 341 DMA_TO_DEVICE); 342 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 343 dma_sync_single_for_device(dev->dev, t->dma_addr, dev->drv->txwi_size, 344 DMA_TO_DEVICE); 345 if (ret < 0) 346 goto unmap; 347 348 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 349 ret = -ENOMEM; 350 goto unmap; 351 } 352 353 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 354 tx_info.info, tx_info.skb, t); 355 356 unmap: 357 for (n--; n > 0; n--) 358 dma_unmap_single(dev->dev, tx_info.buf[n].addr, 359 tx_info.buf[n].len, DMA_TO_DEVICE); 360 361 free: 362 e.skb = tx_info.skb; 363 e.txwi = t; 364 dev->drv->tx_complete_skb(dev, qid, &e); 365 mt76_put_txwi(dev, t); 366 return ret; 367 } 368 369 static int 370 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) 371 { 372 dma_addr_t addr; 373 void *buf; 374 int frames = 0; 375 int len = SKB_WITH_OVERHEAD(q->buf_size); 376 int offset = q->buf_offset; 377 int idx; 378 379 spin_lock_bh(&q->lock); 380 381 while (q->queued < q->ndesc - 1) { 382 struct mt76_queue_buf qbuf; 383 384 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC); 385 if (!buf) 386 break; 387 388 addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE); 389 if (unlikely(dma_mapping_error(dev->dev, addr))) { 390 skb_free_frag(buf); 391 break; 392 } 393 394 qbuf.addr = addr + offset; 395 qbuf.len = len - offset; 396 idx = mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL); 397 frames++; 398 } 399 400 if (frames) 401 mt76_dma_kick_queue(dev, q); 402 403 spin_unlock_bh(&q->lock); 404 405 return frames; 406 } 407 408 static void 409 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 410 { 411 struct page *page; 412 void *buf; 413 bool more; 414 415 spin_lock_bh(&q->lock); 416 do { 417 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more); 418 if (!buf) 419 break; 420 421 skb_free_frag(buf); 422 } while (1); 423 spin_unlock_bh(&q->lock); 424 425 if (!q->rx_page.va) 426 return; 427 428 page = virt_to_page(q->rx_page.va); 429 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias); 430 memset(&q->rx_page, 0, sizeof(q->rx_page)); 431 } 432 433 static void 434 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 435 { 436 struct mt76_queue *q = &dev->q_rx[qid]; 437 int i; 438 439 for (i = 0; i < q->ndesc; i++) 440 q->desc[i].ctrl &= ~cpu_to_le32(MT_DMA_CTL_DMA_DONE); 441 442 mt76_dma_rx_cleanup(dev, q); 443 mt76_dma_sync_idx(dev, q); 444 mt76_dma_rx_fill(dev, q); 445 } 446 447 static void 448 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 449 int len, bool more) 450 { 451 struct page *page = virt_to_head_page(data); 452 int offset = data - page_address(page); 453 struct sk_buff *skb = q->rx_head; 454 455 offset += q->buf_offset; 456 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, offset, len, 457 q->buf_size); 458 459 if (more) 460 return; 461 462 q->rx_head = NULL; 463 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 464 } 465 466 static int 467 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 468 { 469 int len, data_len, done = 0; 470 struct sk_buff *skb; 471 unsigned char *data; 472 bool more; 473 474 while (done < budget) { 475 u32 info; 476 477 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more); 478 if (!data) 479 break; 480 481 if (q->rx_head) 482 data_len = q->buf_size; 483 else 484 data_len = SKB_WITH_OVERHEAD(q->buf_size); 485 486 if (data_len < len + q->buf_offset) { 487 dev_kfree_skb(q->rx_head); 488 q->rx_head = NULL; 489 490 skb_free_frag(data); 491 continue; 492 } 493 494 if (q->rx_head) { 495 mt76_add_fragment(dev, q, data, len, more); 496 continue; 497 } 498 499 skb = build_skb(data, q->buf_size); 500 if (!skb) { 501 skb_free_frag(data); 502 continue; 503 } 504 skb_reserve(skb, q->buf_offset); 505 506 if (q == &dev->q_rx[MT_RXQ_MCU]) { 507 u32 *rxfce = (u32 *) skb->cb; 508 *rxfce = info; 509 } 510 511 __skb_put(skb, len); 512 done++; 513 514 if (more) { 515 q->rx_head = skb; 516 continue; 517 } 518 519 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 520 } 521 522 mt76_dma_rx_fill(dev, q); 523 return done; 524 } 525 526 static int 527 mt76_dma_rx_poll(struct napi_struct *napi, int budget) 528 { 529 struct mt76_dev *dev; 530 int qid, done = 0, cur; 531 532 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 533 qid = napi - dev->napi; 534 535 rcu_read_lock(); 536 537 do { 538 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 539 mt76_rx_poll_complete(dev, qid, napi); 540 done += cur; 541 } while (cur && done < budget); 542 543 rcu_read_unlock(); 544 545 if (done < budget) { 546 napi_complete(napi); 547 dev->drv->rx_poll_complete(dev, qid); 548 } 549 550 return done; 551 } 552 553 static int 554 mt76_dma_init(struct mt76_dev *dev) 555 { 556 int i; 557 558 init_dummy_netdev(&dev->napi_dev); 559 560 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 561 netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll, 562 64); 563 mt76_dma_rx_fill(dev, &dev->q_rx[i]); 564 skb_queue_head_init(&dev->rx_skb[i]); 565 napi_enable(&dev->napi[i]); 566 } 567 568 return 0; 569 } 570 571 static const struct mt76_queue_ops mt76_dma_ops = { 572 .init = mt76_dma_init, 573 .alloc = mt76_dma_alloc_queue, 574 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 575 .tx_queue_skb = mt76_dma_tx_queue_skb, 576 .tx_cleanup = mt76_dma_tx_cleanup, 577 .rx_reset = mt76_dma_rx_reset, 578 .kick = mt76_dma_kick_queue, 579 }; 580 581 void mt76_dma_attach(struct mt76_dev *dev) 582 { 583 dev->queue_ops = &mt76_dma_ops; 584 } 585 EXPORT_SYMBOL_GPL(mt76_dma_attach); 586 587 void mt76_dma_cleanup(struct mt76_dev *dev) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++) 592 mt76_dma_tx_cleanup(dev, i, true); 593 594 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 595 netif_napi_del(&dev->napi[i]); 596 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]); 597 } 598 } 599 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 600