1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * NXP Wireless LAN device driver: SDIO specific definitions 4 * 5 * Copyright 2011-2020 NXP 6 */ 7 8 #ifndef _MWIFIEX_SDIO_H 9 #define _MWIFIEX_SDIO_H 10 11 12 #include <linux/completion.h> 13 #include <linux/mmc/sdio.h> 14 #include <linux/mmc/sdio_ids.h> 15 #include <linux/mmc/sdio_func.h> 16 #include <linux/mmc/card.h> 17 #include <linux/mmc/host.h> 18 19 #include "main.h" 20 21 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" 22 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" 23 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" 24 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" 25 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin" 26 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin" 27 #define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin" 28 #define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin" 29 #define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin" 30 #define SD8997_SDIOUART_FW_NAME "mrvl/sdiouart8997_combo_v4.bin" 31 32 #define BLOCK_MODE 1 33 #define BYTE_MODE 0 34 35 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff 36 37 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 38 39 #define MWIFIEX_MAX_FUNC2_REG_NUM 13 40 #define MWIFIEX_SDIO_SCRATCH_SIZE 10 41 42 #define SDIO_MPA_ADDR_BASE 0x1000 43 #define CTRL_PORT 0 44 #define CTRL_PORT_MASK 0x0001 45 46 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6) 47 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7) 48 #define HOST_TERM_CMD53 (0x1U << 2) 49 #define REG_PORT 0 50 #define MEM_PORT 0x10000 51 52 #define CMD53_NEW_MODE (0x1U << 0) 53 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 54 #define CMD_PORT_AUTO_EN (0x1U << 0) 55 #define CMD_PORT_SLCT 0x8000 56 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 57 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 58 59 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384) 60 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768) 61 /* we leave one block of 256 bytes for DMA alignment*/ 62 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280) 63 64 /* Misc. Config Register : Auto Re-enable interrupts */ 65 #define AUTO_RE_ENABLE_INT BIT(4) 66 67 /* Host Control Registers : Configuration */ 68 #define CONFIGURATION_REG 0x00 69 /* Host Control Registers : Host power up */ 70 #define HOST_POWER_UP (0x1U << 1) 71 72 /* Host Control Registers : Upload host interrupt mask */ 73 #define UP_LD_HOST_INT_MASK (0x1U) 74 /* Host Control Registers : Download host interrupt mask */ 75 #define DN_LD_HOST_INT_MASK (0x2U) 76 77 /* Host Control Registers : Upload host interrupt status */ 78 #define UP_LD_HOST_INT_STATUS (0x1U) 79 /* Host Control Registers : Download host interrupt status */ 80 #define DN_LD_HOST_INT_STATUS (0x2U) 81 82 /* Host Control Registers : Host interrupt status */ 83 #define CARD_INT_STATUS_REG 0x28 84 85 /* Card Control Registers : Card I/O ready */ 86 #define CARD_IO_READY (0x1U << 3) 87 /* Card Control Registers : Download card ready */ 88 #define DN_LD_CARD_RDY (0x1U << 0) 89 90 /* Max retry number of CMD53 write */ 91 #define MAX_WRITE_IOMEM_RETRY 2 92 93 /* SDIO Tx aggregation in progress ? */ 94 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 95 96 /* SDIO Tx aggregation buffer room for next packet ? */ 97 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ 98 <= a->mpa_tx.buf_size) 99 100 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 101 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ 102 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ 103 payload, pkt_len); \ 104 a->mpa_tx.buf_len += pkt_len; \ 105 if (!a->mpa_tx.pkt_cnt) \ 106 a->mpa_tx.start_port = port; \ 107 if (a->mpa_tx.start_port <= port) \ 108 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ 109 else \ 110 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ 111 (a->max_ports - \ 112 a->mp_end_port))); \ 113 a->mpa_tx.pkt_cnt++; \ 114 } while (0) 115 116 /* SDIO Tx aggregation limit ? */ 117 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 118 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) 119 120 /* Reset SDIO Tx aggregation buffer parameters */ 121 #define MP_TX_AGGR_BUF_RESET(a) do { \ 122 a->mpa_tx.pkt_cnt = 0; \ 123 a->mpa_tx.buf_len = 0; \ 124 a->mpa_tx.ports = 0; \ 125 a->mpa_tx.start_port = 0; \ 126 } while (0) 127 128 /* SDIO Rx aggregation limit ? */ 129 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 130 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) 131 132 /* SDIO Rx aggregation in progress ? */ 133 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 134 135 /* SDIO Rx aggregation buffer room for next packet ? */ 136 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 137 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) 138 139 /* Reset SDIO Rx aggregation buffer parameters */ 140 #define MP_RX_AGGR_BUF_RESET(a) do { \ 141 a->mpa_rx.pkt_cnt = 0; \ 142 a->mpa_rx.buf_len = 0; \ 143 a->mpa_rx.ports = 0; \ 144 a->mpa_rx.start_port = 0; \ 145 } while (0) 146 147 /* data structure for SDIO MPA TX */ 148 struct mwifiex_sdio_mpa_tx { 149 /* multiport tx aggregation buffer pointer */ 150 u8 *buf; 151 u32 buf_len; 152 u32 pkt_cnt; 153 u32 ports; 154 u16 start_port; 155 u8 enabled; 156 u32 buf_size; 157 u32 pkt_aggr_limit; 158 }; 159 160 struct mwifiex_sdio_mpa_rx { 161 u8 *buf; 162 u32 buf_len; 163 u32 pkt_cnt; 164 u32 ports; 165 u16 start_port; 166 167 struct sk_buff **skb_arr; 168 u32 *len_arr; 169 170 u8 enabled; 171 u32 buf_size; 172 u32 pkt_aggr_limit; 173 }; 174 175 int mwifiex_bus_register(void); 176 void mwifiex_bus_unregister(void); 177 178 struct mwifiex_sdio_card_reg { 179 u8 start_rd_port; 180 u8 start_wr_port; 181 u8 base_0_reg; 182 u8 base_1_reg; 183 u8 poll_reg; 184 u8 host_int_enable; 185 u8 host_int_rsr_reg; 186 u8 host_int_status_reg; 187 u8 host_int_mask_reg; 188 u8 host_strap_reg; 189 u8 host_strap_mask; 190 u8 host_strap_value; 191 u8 status_reg_0; 192 u8 status_reg_1; 193 u8 sdio_int_mask; 194 u32 data_port_mask; 195 u8 io_port_0_reg; 196 u8 io_port_1_reg; 197 u8 io_port_2_reg; 198 u8 max_mp_regs; 199 u8 rd_bitmap_l; 200 u8 rd_bitmap_u; 201 u8 rd_bitmap_1l; 202 u8 rd_bitmap_1u; 203 u8 wr_bitmap_l; 204 u8 wr_bitmap_u; 205 u8 wr_bitmap_1l; 206 u8 wr_bitmap_1u; 207 u8 rd_len_p0_l; 208 u8 rd_len_p0_u; 209 u8 card_misc_cfg_reg; 210 u8 card_cfg_2_1_reg; 211 u8 cmd_rd_len_0; 212 u8 cmd_rd_len_1; 213 u8 cmd_rd_len_2; 214 u8 cmd_rd_len_3; 215 u8 cmd_cfg_0; 216 u8 cmd_cfg_1; 217 u8 cmd_cfg_2; 218 u8 cmd_cfg_3; 219 u8 fw_dump_host_ready; 220 u8 fw_dump_ctrl; 221 u8 fw_dump_start; 222 u8 fw_dump_end; 223 u8 func1_dump_reg_start; 224 u8 func1_dump_reg_end; 225 u8 func1_scratch_reg; 226 u8 func1_spec_reg_num; 227 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM]; 228 }; 229 230 struct sdio_mmc_card { 231 struct sdio_func *func; 232 struct mwifiex_adapter *adapter; 233 234 struct completion fw_done; 235 const char *firmware; 236 const char *firmware_sdiouart; 237 const struct mwifiex_sdio_card_reg *reg; 238 u8 max_ports; 239 u8 mp_agg_pkt_limit; 240 u16 tx_buf_size; 241 u32 mp_tx_agg_buf_size; 242 u32 mp_rx_agg_buf_size; 243 244 u32 mp_rd_bitmap; 245 u32 mp_wr_bitmap; 246 247 u16 mp_end_port; 248 u32 mp_data_port_mask; 249 250 u8 curr_rd_port; 251 u8 curr_wr_port; 252 253 u8 *mp_regs; 254 bool supports_sdio_new_mode; 255 bool has_control_mask; 256 bool can_dump_fw; 257 bool fw_dump_enh; 258 bool can_auto_tdls; 259 bool can_ext_scan; 260 261 struct mwifiex_sdio_mpa_tx mpa_tx; 262 struct mwifiex_sdio_mpa_rx mpa_rx; 263 264 struct work_struct work; 265 unsigned long work_flags; 266 }; 267 268 struct mwifiex_sdio_device { 269 const char *firmware; 270 const char *firmware_sdiouart; 271 const struct mwifiex_sdio_card_reg *reg; 272 u8 max_ports; 273 u8 mp_agg_pkt_limit; 274 u16 tx_buf_size; 275 u32 mp_tx_agg_buf_size; 276 u32 mp_rx_agg_buf_size; 277 bool supports_sdio_new_mode; 278 bool has_control_mask; 279 bool can_dump_fw; 280 bool fw_dump_enh; 281 bool can_auto_tdls; 282 bool can_ext_scan; 283 }; 284 285 /* 286 * .cmdrsp_complete handler 287 */ 288 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, 289 struct sk_buff *skb) 290 { 291 dev_kfree_skb_any(skb); 292 return 0; 293 } 294 295 /* 296 * .event_complete handler 297 */ 298 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, 299 struct sk_buff *skb) 300 { 301 dev_kfree_skb_any(skb); 302 return 0; 303 } 304 305 static inline bool 306 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) 307 { 308 u8 tmp; 309 310 if (card->curr_rd_port < card->mpa_rx.start_port) { 311 if (card->supports_sdio_new_mode) 312 tmp = card->mp_end_port >> 1; 313 else 314 tmp = card->mp_agg_pkt_limit; 315 316 if (((card->max_ports - card->mpa_rx.start_port) + 317 card->curr_rd_port) >= tmp) 318 return true; 319 } 320 321 if (!card->supports_sdio_new_mode) 322 return false; 323 324 if ((card->curr_rd_port - card->mpa_rx.start_port) >= 325 (card->mp_end_port >> 1)) 326 return true; 327 328 return false; 329 } 330 331 static inline bool 332 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) 333 { 334 u16 tmp; 335 336 if (card->curr_wr_port < card->mpa_tx.start_port) { 337 if (card->supports_sdio_new_mode) 338 tmp = card->mp_end_port >> 1; 339 else 340 tmp = card->mp_agg_pkt_limit; 341 342 if (((card->max_ports - card->mpa_tx.start_port) + 343 card->curr_wr_port) >= tmp) 344 return true; 345 } 346 347 if (!card->supports_sdio_new_mode) 348 return false; 349 350 if ((card->curr_wr_port - card->mpa_tx.start_port) >= 351 (card->mp_end_port >> 1)) 352 return true; 353 354 return false; 355 } 356 357 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 358 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, 359 u16 rx_len, u8 port) 360 { 361 card->mpa_rx.buf_len += rx_len; 362 363 if (!card->mpa_rx.pkt_cnt) 364 card->mpa_rx.start_port = port; 365 366 if (card->supports_sdio_new_mode) { 367 card->mpa_rx.ports |= (1 << port); 368 } else { 369 if (card->mpa_rx.start_port <= port) 370 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); 371 else 372 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); 373 } 374 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL; 375 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len; 376 card->mpa_rx.pkt_cnt++; 377 } 378 #endif /* _MWIFIEX_SDIO_H */ 379