1 /* 2 * Marvell Wireless LAN device driver: SDIO specific definitions 3 * 4 * Copyright (C) 2011-2014, Marvell International Ltd. 5 * 6 * This software file (the "File") is distributed by Marvell International 7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #ifndef _MWIFIEX_SDIO_H 21 #define _MWIFIEX_SDIO_H 22 23 24 #include <linux/mmc/sdio.h> 25 #include <linux/mmc/sdio_ids.h> 26 #include <linux/mmc/sdio_func.h> 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/host.h> 29 30 #include "main.h" 31 32 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" 33 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" 34 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" 35 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" 36 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin" 37 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin" 38 #define SD8997_DEFAULT_FW_NAME "mrvl/sd8997_uapsta.bin" 39 40 #define BLOCK_MODE 1 41 #define BYTE_MODE 0 42 43 #define REG_PORT 0 44 45 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff 46 47 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 48 49 #define MWIFIEX_MAX_FUNC2_REG_NUM 13 50 #define MWIFIEX_SDIO_SCRATCH_SIZE 10 51 52 #define SDIO_MPA_ADDR_BASE 0x1000 53 #define CTRL_PORT 0 54 #define CTRL_PORT_MASK 0x0001 55 56 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6) 57 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7) 58 #define HOST_TERM_CMD53 (0x1U << 2) 59 #define REG_PORT 0 60 #define MEM_PORT 0x10000 61 62 #define CMD53_NEW_MODE (0x1U << 0) 63 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 64 #define CMD_PORT_AUTO_EN (0x1U << 0) 65 #define CMD_PORT_SLCT 0x8000 66 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 67 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 68 69 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384) 70 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768) 71 /* we leave one block of 256 bytes for DMA alignment*/ 72 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280) 73 74 /* Misc. Config Register : Auto Re-enable interrupts */ 75 #define AUTO_RE_ENABLE_INT BIT(4) 76 77 /* Host Control Registers : Configuration */ 78 #define CONFIGURATION_REG 0x00 79 /* Host Control Registers : Host power up */ 80 #define HOST_POWER_UP (0x1U << 1) 81 82 /* Host Control Registers : Upload host interrupt mask */ 83 #define UP_LD_HOST_INT_MASK (0x1U) 84 /* Host Control Registers : Download host interrupt mask */ 85 #define DN_LD_HOST_INT_MASK (0x2U) 86 87 /* Host Control Registers : Upload host interrupt status */ 88 #define UP_LD_HOST_INT_STATUS (0x1U) 89 /* Host Control Registers : Download host interrupt status */ 90 #define DN_LD_HOST_INT_STATUS (0x2U) 91 92 /* Host Control Registers : Host interrupt status */ 93 #define CARD_INT_STATUS_REG 0x28 94 95 /* Card Control Registers : Card I/O ready */ 96 #define CARD_IO_READY (0x1U << 3) 97 /* Card Control Registers : Download card ready */ 98 #define DN_LD_CARD_RDY (0x1U << 0) 99 100 /* Max retry number of CMD53 write */ 101 #define MAX_WRITE_IOMEM_RETRY 2 102 103 /* SDIO Tx aggregation in progress ? */ 104 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 105 106 /* SDIO Tx aggregation buffer room for next packet ? */ 107 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ 108 <= a->mpa_tx.buf_size) 109 110 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 111 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ 112 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ 113 payload, pkt_len); \ 114 a->mpa_tx.buf_len += pkt_len; \ 115 if (!a->mpa_tx.pkt_cnt) \ 116 a->mpa_tx.start_port = port; \ 117 if (a->mpa_tx.start_port <= port) \ 118 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ 119 else \ 120 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ 121 (a->max_ports - \ 122 a->mp_end_port))); \ 123 a->mpa_tx.pkt_cnt++; \ 124 } while (0) 125 126 /* SDIO Tx aggregation limit ? */ 127 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 128 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) 129 130 /* Reset SDIO Tx aggregation buffer parameters */ 131 #define MP_TX_AGGR_BUF_RESET(a) do { \ 132 a->mpa_tx.pkt_cnt = 0; \ 133 a->mpa_tx.buf_len = 0; \ 134 a->mpa_tx.ports = 0; \ 135 a->mpa_tx.start_port = 0; \ 136 } while (0) 137 138 /* SDIO Rx aggregation limit ? */ 139 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 140 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) 141 142 /* SDIO Rx aggregation in progress ? */ 143 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 144 145 /* SDIO Rx aggregation buffer room for next packet ? */ 146 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 147 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) 148 149 /* Reset SDIO Rx aggregation buffer parameters */ 150 #define MP_RX_AGGR_BUF_RESET(a) do { \ 151 a->mpa_rx.pkt_cnt = 0; \ 152 a->mpa_rx.buf_len = 0; \ 153 a->mpa_rx.ports = 0; \ 154 a->mpa_rx.start_port = 0; \ 155 } while (0) 156 157 /* data structure for SDIO MPA TX */ 158 struct mwifiex_sdio_mpa_tx { 159 /* multiport tx aggregation buffer pointer */ 160 u8 *buf; 161 u32 buf_len; 162 u32 pkt_cnt; 163 u32 ports; 164 u16 start_port; 165 u8 enabled; 166 u32 buf_size; 167 u32 pkt_aggr_limit; 168 }; 169 170 struct mwifiex_sdio_mpa_rx { 171 u8 *buf; 172 u32 buf_len; 173 u32 pkt_cnt; 174 u32 ports; 175 u16 start_port; 176 177 struct sk_buff **skb_arr; 178 u32 *len_arr; 179 180 u8 enabled; 181 u32 buf_size; 182 u32 pkt_aggr_limit; 183 }; 184 185 int mwifiex_bus_register(void); 186 void mwifiex_bus_unregister(void); 187 188 struct mwifiex_sdio_card_reg { 189 u8 start_rd_port; 190 u8 start_wr_port; 191 u8 base_0_reg; 192 u8 base_1_reg; 193 u8 poll_reg; 194 u8 host_int_enable; 195 u8 host_int_rsr_reg; 196 u8 host_int_status_reg; 197 u8 host_int_mask_reg; 198 u8 status_reg_0; 199 u8 status_reg_1; 200 u8 sdio_int_mask; 201 u32 data_port_mask; 202 u8 io_port_0_reg; 203 u8 io_port_1_reg; 204 u8 io_port_2_reg; 205 u8 max_mp_regs; 206 u8 rd_bitmap_l; 207 u8 rd_bitmap_u; 208 u8 rd_bitmap_1l; 209 u8 rd_bitmap_1u; 210 u8 wr_bitmap_l; 211 u8 wr_bitmap_u; 212 u8 wr_bitmap_1l; 213 u8 wr_bitmap_1u; 214 u8 rd_len_p0_l; 215 u8 rd_len_p0_u; 216 u8 card_misc_cfg_reg; 217 u8 card_cfg_2_1_reg; 218 u8 cmd_rd_len_0; 219 u8 cmd_rd_len_1; 220 u8 cmd_rd_len_2; 221 u8 cmd_rd_len_3; 222 u8 cmd_cfg_0; 223 u8 cmd_cfg_1; 224 u8 cmd_cfg_2; 225 u8 cmd_cfg_3; 226 u8 fw_dump_host_ready; 227 u8 fw_dump_ctrl; 228 u8 fw_dump_start; 229 u8 fw_dump_end; 230 u8 func1_dump_reg_start; 231 u8 func1_dump_reg_end; 232 u8 func1_scratch_reg; 233 u8 func1_spec_reg_num; 234 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM]; 235 }; 236 237 struct sdio_mmc_card { 238 struct sdio_func *func; 239 struct mwifiex_adapter *adapter; 240 241 const char *firmware; 242 const struct mwifiex_sdio_card_reg *reg; 243 u8 max_ports; 244 u8 mp_agg_pkt_limit; 245 u16 tx_buf_size; 246 u32 mp_tx_agg_buf_size; 247 u32 mp_rx_agg_buf_size; 248 249 u32 mp_rd_bitmap; 250 u32 mp_wr_bitmap; 251 252 u16 mp_end_port; 253 u32 mp_data_port_mask; 254 255 u8 curr_rd_port; 256 u8 curr_wr_port; 257 258 u8 *mp_regs; 259 bool supports_sdio_new_mode; 260 bool has_control_mask; 261 bool can_dump_fw; 262 bool fw_dump_enh; 263 bool can_auto_tdls; 264 bool can_ext_scan; 265 266 struct mwifiex_sdio_mpa_tx mpa_tx; 267 struct mwifiex_sdio_mpa_rx mpa_rx; 268 269 /* needed for card reset */ 270 const struct sdio_device_id *device_id; 271 }; 272 273 struct mwifiex_sdio_device { 274 const char *firmware; 275 const struct mwifiex_sdio_card_reg *reg; 276 u8 max_ports; 277 u8 mp_agg_pkt_limit; 278 u16 tx_buf_size; 279 u32 mp_tx_agg_buf_size; 280 u32 mp_rx_agg_buf_size; 281 bool supports_sdio_new_mode; 282 bool has_control_mask; 283 bool can_dump_fw; 284 bool fw_dump_enh; 285 bool can_auto_tdls; 286 bool can_ext_scan; 287 }; 288 289 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = { 290 .start_rd_port = 1, 291 .start_wr_port = 1, 292 .base_0_reg = 0x0040, 293 .base_1_reg = 0x0041, 294 .poll_reg = 0x30, 295 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK, 296 .host_int_rsr_reg = 0x1, 297 .host_int_mask_reg = 0x02, 298 .host_int_status_reg = 0x03, 299 .status_reg_0 = 0x60, 300 .status_reg_1 = 0x61, 301 .sdio_int_mask = 0x3f, 302 .data_port_mask = 0x0000fffe, 303 .io_port_0_reg = 0x78, 304 .io_port_1_reg = 0x79, 305 .io_port_2_reg = 0x7A, 306 .max_mp_regs = 64, 307 .rd_bitmap_l = 0x04, 308 .rd_bitmap_u = 0x05, 309 .wr_bitmap_l = 0x06, 310 .wr_bitmap_u = 0x07, 311 .rd_len_p0_l = 0x08, 312 .rd_len_p0_u = 0x09, 313 .card_misc_cfg_reg = 0x6c, 314 .func1_dump_reg_start = 0x0, 315 .func1_dump_reg_end = 0x9, 316 .func1_scratch_reg = 0x60, 317 .func1_spec_reg_num = 5, 318 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c}, 319 }; 320 321 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = { 322 .start_rd_port = 0, 323 .start_wr_port = 0, 324 .base_0_reg = 0x60, 325 .base_1_reg = 0x61, 326 .poll_reg = 0x50, 327 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 328 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 329 .host_int_rsr_reg = 0x1, 330 .host_int_status_reg = 0x03, 331 .host_int_mask_reg = 0x02, 332 .status_reg_0 = 0xc0, 333 .status_reg_1 = 0xc1, 334 .sdio_int_mask = 0xff, 335 .data_port_mask = 0xffffffff, 336 .io_port_0_reg = 0xD8, 337 .io_port_1_reg = 0xD9, 338 .io_port_2_reg = 0xDA, 339 .max_mp_regs = 184, 340 .rd_bitmap_l = 0x04, 341 .rd_bitmap_u = 0x05, 342 .rd_bitmap_1l = 0x06, 343 .rd_bitmap_1u = 0x07, 344 .wr_bitmap_l = 0x08, 345 .wr_bitmap_u = 0x09, 346 .wr_bitmap_1l = 0x0a, 347 .wr_bitmap_1u = 0x0b, 348 .rd_len_p0_l = 0x0c, 349 .rd_len_p0_u = 0x0d, 350 .card_misc_cfg_reg = 0xcc, 351 .card_cfg_2_1_reg = 0xcd, 352 .cmd_rd_len_0 = 0xb4, 353 .cmd_rd_len_1 = 0xb5, 354 .cmd_rd_len_2 = 0xb6, 355 .cmd_rd_len_3 = 0xb7, 356 .cmd_cfg_0 = 0xb8, 357 .cmd_cfg_1 = 0xb9, 358 .cmd_cfg_2 = 0xba, 359 .cmd_cfg_3 = 0xbb, 360 .fw_dump_host_ready = 0xee, 361 .fw_dump_ctrl = 0xe2, 362 .fw_dump_start = 0xe3, 363 .fw_dump_end = 0xea, 364 .func1_dump_reg_start = 0x0, 365 .func1_dump_reg_end = 0xb, 366 .func1_scratch_reg = 0xc0, 367 .func1_spec_reg_num = 8, 368 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58, 369 0x59, 0x5c, 0x5d}, 370 }; 371 372 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = { 373 .start_rd_port = 0, 374 .start_wr_port = 0, 375 .base_0_reg = 0xF8, 376 .base_1_reg = 0xF9, 377 .poll_reg = 0x5C, 378 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 379 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 380 .host_int_rsr_reg = 0x4, 381 .host_int_status_reg = 0x0C, 382 .host_int_mask_reg = 0x08, 383 .status_reg_0 = 0xE8, 384 .status_reg_1 = 0xE9, 385 .sdio_int_mask = 0xff, 386 .data_port_mask = 0xffffffff, 387 .io_port_0_reg = 0xE4, 388 .io_port_1_reg = 0xE5, 389 .io_port_2_reg = 0xE6, 390 .max_mp_regs = 196, 391 .rd_bitmap_l = 0x10, 392 .rd_bitmap_u = 0x11, 393 .rd_bitmap_1l = 0x12, 394 .rd_bitmap_1u = 0x13, 395 .wr_bitmap_l = 0x14, 396 .wr_bitmap_u = 0x15, 397 .wr_bitmap_1l = 0x16, 398 .wr_bitmap_1u = 0x17, 399 .rd_len_p0_l = 0x18, 400 .rd_len_p0_u = 0x19, 401 .card_misc_cfg_reg = 0xd8, 402 .card_cfg_2_1_reg = 0xd9, 403 .cmd_rd_len_0 = 0xc0, 404 .cmd_rd_len_1 = 0xc1, 405 .cmd_rd_len_2 = 0xc2, 406 .cmd_rd_len_3 = 0xc3, 407 .cmd_cfg_0 = 0xc4, 408 .cmd_cfg_1 = 0xc5, 409 .cmd_cfg_2 = 0xc6, 410 .cmd_cfg_3 = 0xc7, 411 .fw_dump_host_ready = 0xcc, 412 .fw_dump_ctrl = 0xf0, 413 .fw_dump_start = 0xf1, 414 .fw_dump_end = 0xf8, 415 .func1_dump_reg_start = 0x10, 416 .func1_dump_reg_end = 0x17, 417 .func1_scratch_reg = 0xe8, 418 .func1_spec_reg_num = 13, 419 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 420 0x60, 0x61, 0x62, 0x64, 421 0x65, 0x66, 0x68, 0x69, 422 0x6a}, 423 }; 424 425 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = { 426 .start_rd_port = 0, 427 .start_wr_port = 0, 428 .base_0_reg = 0x6C, 429 .base_1_reg = 0x6D, 430 .poll_reg = 0x5C, 431 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 432 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 433 .host_int_rsr_reg = 0x4, 434 .host_int_status_reg = 0x0C, 435 .host_int_mask_reg = 0x08, 436 .status_reg_0 = 0x90, 437 .status_reg_1 = 0x91, 438 .sdio_int_mask = 0xff, 439 .data_port_mask = 0xffffffff, 440 .io_port_0_reg = 0xE4, 441 .io_port_1_reg = 0xE5, 442 .io_port_2_reg = 0xE6, 443 .max_mp_regs = 196, 444 .rd_bitmap_l = 0x10, 445 .rd_bitmap_u = 0x11, 446 .rd_bitmap_1l = 0x12, 447 .rd_bitmap_1u = 0x13, 448 .wr_bitmap_l = 0x14, 449 .wr_bitmap_u = 0x15, 450 .wr_bitmap_1l = 0x16, 451 .wr_bitmap_1u = 0x17, 452 .rd_len_p0_l = 0x18, 453 .rd_len_p0_u = 0x19, 454 .card_misc_cfg_reg = 0xd8, 455 .card_cfg_2_1_reg = 0xd9, 456 .cmd_rd_len_0 = 0xc0, 457 .cmd_rd_len_1 = 0xc1, 458 .cmd_rd_len_2 = 0xc2, 459 .cmd_rd_len_3 = 0xc3, 460 .cmd_cfg_0 = 0xc4, 461 .cmd_cfg_1 = 0xc5, 462 .cmd_cfg_2 = 0xc6, 463 .cmd_cfg_3 = 0xc7, 464 .func1_dump_reg_start = 0x10, 465 .func1_dump_reg_end = 0x17, 466 .func1_scratch_reg = 0x90, 467 .func1_spec_reg_num = 13, 468 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60, 469 0x61, 0x62, 0x64, 0x65, 0x66, 470 0x68, 0x69, 0x6a}, 471 }; 472 473 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = { 474 .firmware = SD8786_DEFAULT_FW_NAME, 475 .reg = &mwifiex_reg_sd87xx, 476 .max_ports = 16, 477 .mp_agg_pkt_limit = 8, 478 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 479 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 480 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 481 .supports_sdio_new_mode = false, 482 .has_control_mask = true, 483 .can_dump_fw = false, 484 .can_auto_tdls = false, 485 .can_ext_scan = false, 486 }; 487 488 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = { 489 .firmware = SD8787_DEFAULT_FW_NAME, 490 .reg = &mwifiex_reg_sd87xx, 491 .max_ports = 16, 492 .mp_agg_pkt_limit = 8, 493 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 494 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 495 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 496 .supports_sdio_new_mode = false, 497 .has_control_mask = true, 498 .can_dump_fw = false, 499 .can_auto_tdls = false, 500 .can_ext_scan = true, 501 }; 502 503 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = { 504 .firmware = SD8797_DEFAULT_FW_NAME, 505 .reg = &mwifiex_reg_sd87xx, 506 .max_ports = 16, 507 .mp_agg_pkt_limit = 8, 508 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 509 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 510 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 511 .supports_sdio_new_mode = false, 512 .has_control_mask = true, 513 .can_dump_fw = false, 514 .can_auto_tdls = false, 515 .can_ext_scan = true, 516 }; 517 518 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = { 519 .firmware = SD8897_DEFAULT_FW_NAME, 520 .reg = &mwifiex_reg_sd8897, 521 .max_ports = 32, 522 .mp_agg_pkt_limit = 16, 523 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 524 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 525 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 526 .supports_sdio_new_mode = true, 527 .has_control_mask = false, 528 .can_dump_fw = true, 529 .can_auto_tdls = false, 530 .can_ext_scan = true, 531 }; 532 533 static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = { 534 .firmware = SD8997_DEFAULT_FW_NAME, 535 .reg = &mwifiex_reg_sd8997, 536 .max_ports = 32, 537 .mp_agg_pkt_limit = 16, 538 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 539 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 540 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 541 .supports_sdio_new_mode = true, 542 .has_control_mask = false, 543 .can_dump_fw = true, 544 .fw_dump_enh = true, 545 .can_auto_tdls = false, 546 .can_ext_scan = true, 547 }; 548 549 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = { 550 .firmware = SD8887_DEFAULT_FW_NAME, 551 .reg = &mwifiex_reg_sd8887, 552 .max_ports = 32, 553 .mp_agg_pkt_limit = 16, 554 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 555 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 556 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 557 .supports_sdio_new_mode = true, 558 .has_control_mask = false, 559 .can_dump_fw = false, 560 .can_auto_tdls = true, 561 .can_ext_scan = true, 562 }; 563 564 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = { 565 .firmware = SD8801_DEFAULT_FW_NAME, 566 .reg = &mwifiex_reg_sd87xx, 567 .max_ports = 16, 568 .mp_agg_pkt_limit = 8, 569 .supports_sdio_new_mode = false, 570 .has_control_mask = true, 571 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 572 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 573 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 574 .can_dump_fw = false, 575 .can_auto_tdls = false, 576 .can_ext_scan = true, 577 }; 578 579 /* 580 * .cmdrsp_complete handler 581 */ 582 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, 583 struct sk_buff *skb) 584 { 585 dev_kfree_skb_any(skb); 586 return 0; 587 } 588 589 /* 590 * .event_complete handler 591 */ 592 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, 593 struct sk_buff *skb) 594 { 595 dev_kfree_skb_any(skb); 596 return 0; 597 } 598 599 static inline bool 600 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) 601 { 602 u8 tmp; 603 604 if (card->curr_rd_port < card->mpa_rx.start_port) { 605 if (card->supports_sdio_new_mode) 606 tmp = card->mp_end_port >> 1; 607 else 608 tmp = card->mp_agg_pkt_limit; 609 610 if (((card->max_ports - card->mpa_rx.start_port) + 611 card->curr_rd_port) >= tmp) 612 return true; 613 } 614 615 if (!card->supports_sdio_new_mode) 616 return false; 617 618 if ((card->curr_rd_port - card->mpa_rx.start_port) >= 619 (card->mp_end_port >> 1)) 620 return true; 621 622 return false; 623 } 624 625 static inline bool 626 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) 627 { 628 u16 tmp; 629 630 if (card->curr_wr_port < card->mpa_tx.start_port) { 631 if (card->supports_sdio_new_mode) 632 tmp = card->mp_end_port >> 1; 633 else 634 tmp = card->mp_agg_pkt_limit; 635 636 if (((card->max_ports - card->mpa_tx.start_port) + 637 card->curr_wr_port) >= tmp) 638 return true; 639 } 640 641 if (!card->supports_sdio_new_mode) 642 return false; 643 644 if ((card->curr_wr_port - card->mpa_tx.start_port) >= 645 (card->mp_end_port >> 1)) 646 return true; 647 648 return false; 649 } 650 651 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 652 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, 653 u16 rx_len, u8 port) 654 { 655 card->mpa_rx.buf_len += rx_len; 656 657 if (!card->mpa_rx.pkt_cnt) 658 card->mpa_rx.start_port = port; 659 660 if (card->supports_sdio_new_mode) { 661 card->mpa_rx.ports |= (1 << port); 662 } else { 663 if (card->mpa_rx.start_port <= port) 664 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); 665 else 666 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); 667 } 668 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL; 669 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len; 670 card->mpa_rx.pkt_cnt++; 671 } 672 #endif /* _MWIFIEX_SDIO_H */ 673