1 /* @file mwifiex_pcie.h 2 * 3 * @brief This file contains definitions for PCI-E interface. 4 * driver. 5 * 6 * Copyright (C) 2011-2014, Marvell International Ltd. 7 * 8 * This software file (the "File") is distributed by Marvell International 9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 10 * (the "License"). You may use, redistribute and/or modify this File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 */ 21 22 #ifndef _MWIFIEX_PCIE_H 23 #define _MWIFIEX_PCIE_H 24 25 #include <linux/pci.h> 26 #include <linux/interrupt.h> 27 28 #include "decl.h" 29 #include "main.h" 30 31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" 32 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" 33 #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin" 34 #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin" 35 #define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin" 36 #define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin" 37 #define PCIE8997_DEFAULT_WIFIFW_NAME "mrvl/pcie8997_wlan_v4.bin" 38 39 #define PCIE_VENDOR_ID_MARVELL (0x11ab) 40 #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b) 41 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) 42 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) 43 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) 44 45 #define PCIE8897_A0 0x1100 46 #define PCIE8897_B0 0x1200 47 #define PCIE8997_A0 0x10 48 #define PCIE8997_A1 0x11 49 #define CHIP_VER_PCIEUART 0x3 50 #define CHIP_MAGIC_VALUE 0x24 51 52 /* Constants for Buffer Descriptor (BD) rings */ 53 #define MWIFIEX_MAX_TXRX_BD 0x20 54 #define MWIFIEX_TXBD_MASK 0x3F 55 #define MWIFIEX_RXBD_MASK 0x3F 56 57 #define MWIFIEX_MAX_EVT_BD 0x08 58 #define MWIFIEX_EVTBD_MASK 0x0f 59 60 /* PCIE INTERNAL REGISTERS */ 61 #define PCIE_SCRATCH_0_REG 0xC10 62 #define PCIE_SCRATCH_1_REG 0xC14 63 #define PCIE_CPU_INT_EVENT 0xC18 64 #define PCIE_CPU_INT_STATUS 0xC1C 65 #define PCIE_HOST_INT_STATUS 0xC30 66 #define PCIE_HOST_INT_MASK 0xC34 67 #define PCIE_HOST_INT_STATUS_MASK 0xC3C 68 #define PCIE_SCRATCH_2_REG 0xC40 69 #define PCIE_SCRATCH_3_REG 0xC44 70 #define PCIE_SCRATCH_4_REG 0xCD0 71 #define PCIE_SCRATCH_5_REG 0xCD4 72 #define PCIE_SCRATCH_6_REG 0xCD8 73 #define PCIE_SCRATCH_7_REG 0xCDC 74 #define PCIE_SCRATCH_8_REG 0xCE0 75 #define PCIE_SCRATCH_9_REG 0xCE4 76 #define PCIE_SCRATCH_10_REG 0xCE8 77 #define PCIE_SCRATCH_11_REG 0xCEC 78 #define PCIE_SCRATCH_12_REG 0xCF0 79 #define PCIE_SCRATCH_13_REG 0xCF8 80 #define PCIE_SCRATCH_14_REG 0xCFC 81 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C 82 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C 83 84 #define CPU_INTR_DNLD_RDY BIT(0) 85 #define CPU_INTR_DOOR_BELL BIT(1) 86 #define CPU_INTR_SLEEP_CFM_DONE BIT(2) 87 #define CPU_INTR_RESET BIT(3) 88 #define CPU_INTR_EVENT_DONE BIT(5) 89 90 #define HOST_INTR_DNLD_DONE BIT(0) 91 #define HOST_INTR_UPLD_RDY BIT(1) 92 #define HOST_INTR_CMD_DONE BIT(2) 93 #define HOST_INTR_EVENT_RDY BIT(3) 94 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ 95 HOST_INTR_UPLD_RDY | \ 96 HOST_INTR_CMD_DONE | \ 97 HOST_INTR_EVENT_RDY) 98 99 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) 100 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) 101 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) 102 #define MWIFIEX_BD_FLAG_SOP BIT(0) 103 #define MWIFIEX_BD_FLAG_EOP BIT(1) 104 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) 105 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) 106 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) 107 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) 108 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) 109 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) 110 111 /* Max retry number of command write */ 112 #define MAX_WRITE_IOMEM_RETRY 2 113 /* Define PCIE block size for firmware download */ 114 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 115 /* FW awake cookie after FW ready */ 116 #define FW_AWAKE_COOKIE (0xAA55AA55) 117 #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF 118 #define MWIFIEX_MAX_DELAY_COUNT 100 119 120 struct mwifiex_pcie_card_reg { 121 u16 cmd_addr_lo; 122 u16 cmd_addr_hi; 123 u16 fw_status; 124 u16 cmd_size; 125 u16 cmdrsp_addr_lo; 126 u16 cmdrsp_addr_hi; 127 u16 tx_rdptr; 128 u16 tx_wrptr; 129 u16 rx_rdptr; 130 u16 rx_wrptr; 131 u16 evt_rdptr; 132 u16 evt_wrptr; 133 u16 drv_rdy; 134 u16 tx_start_ptr; 135 u32 tx_mask; 136 u32 tx_wrap_mask; 137 u32 rx_mask; 138 u32 rx_wrap_mask; 139 u32 tx_rollover_ind; 140 u32 rx_rollover_ind; 141 u32 evt_rollover_ind; 142 u8 ring_flag_sop; 143 u8 ring_flag_eop; 144 u8 ring_flag_xs_sop; 145 u8 ring_flag_xs_eop; 146 u32 ring_tx_start_ptr; 147 u8 pfu_enabled; 148 u8 sleep_cookie; 149 u16 fw_dump_ctrl; 150 u16 fw_dump_start; 151 u16 fw_dump_end; 152 u8 fw_dump_host_ready; 153 u8 fw_dump_read_done; 154 u8 msix_support; 155 }; 156 157 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 158 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 159 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 160 .cmd_size = PCIE_SCRATCH_2_REG, 161 .fw_status = PCIE_SCRATCH_3_REG, 162 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 163 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 164 .tx_rdptr = PCIE_SCRATCH_6_REG, 165 .tx_wrptr = PCIE_SCRATCH_7_REG, 166 .rx_rdptr = PCIE_SCRATCH_8_REG, 167 .rx_wrptr = PCIE_SCRATCH_9_REG, 168 .evt_rdptr = PCIE_SCRATCH_10_REG, 169 .evt_wrptr = PCIE_SCRATCH_11_REG, 170 .drv_rdy = PCIE_SCRATCH_12_REG, 171 .tx_start_ptr = 0, 172 .tx_mask = MWIFIEX_TXBD_MASK, 173 .tx_wrap_mask = 0, 174 .rx_mask = MWIFIEX_RXBD_MASK, 175 .rx_wrap_mask = 0, 176 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 177 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 178 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 179 .ring_flag_sop = 0, 180 .ring_flag_eop = 0, 181 .ring_flag_xs_sop = 0, 182 .ring_flag_xs_eop = 0, 183 .ring_tx_start_ptr = 0, 184 .pfu_enabled = 0, 185 .sleep_cookie = 1, 186 .msix_support = 0, 187 }; 188 189 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 190 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 191 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 192 .cmd_size = PCIE_SCRATCH_2_REG, 193 .fw_status = PCIE_SCRATCH_3_REG, 194 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 195 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 196 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 197 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 198 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 199 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 200 .evt_rdptr = PCIE_SCRATCH_10_REG, 201 .evt_wrptr = PCIE_SCRATCH_11_REG, 202 .drv_rdy = PCIE_SCRATCH_12_REG, 203 .tx_start_ptr = 16, 204 .tx_mask = 0x03FF0000, 205 .tx_wrap_mask = 0x07FF0000, 206 .rx_mask = 0x000003FF, 207 .rx_wrap_mask = 0x000007FF, 208 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 209 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 210 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 211 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 212 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 213 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 214 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 215 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 216 .pfu_enabled = 1, 217 .sleep_cookie = 0, 218 .fw_dump_ctrl = 0xcf4, 219 .fw_dump_start = 0xcf8, 220 .fw_dump_end = 0xcff, 221 .fw_dump_host_ready = 0xee, 222 .fw_dump_read_done = 0xfe, 223 .msix_support = 0, 224 }; 225 226 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 227 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 228 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 229 .cmd_size = PCIE_SCRATCH_2_REG, 230 .fw_status = PCIE_SCRATCH_3_REG, 231 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 232 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 233 .tx_rdptr = 0xC1A4, 234 .tx_wrptr = 0xC174, 235 .rx_rdptr = 0xC174, 236 .rx_wrptr = 0xC1A4, 237 .evt_rdptr = PCIE_SCRATCH_10_REG, 238 .evt_wrptr = PCIE_SCRATCH_11_REG, 239 .drv_rdy = PCIE_SCRATCH_12_REG, 240 .tx_start_ptr = 16, 241 .tx_mask = 0x0FFF0000, 242 .tx_wrap_mask = 0x1FFF0000, 243 .rx_mask = 0x00000FFF, 244 .rx_wrap_mask = 0x00001FFF, 245 .tx_rollover_ind = BIT(28), 246 .rx_rollover_ind = BIT(12), 247 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 248 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 249 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 250 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 251 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 252 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 253 .pfu_enabled = 1, 254 .sleep_cookie = 0, 255 .fw_dump_ctrl = 0xcf4, 256 .fw_dump_start = 0xcf8, 257 .fw_dump_end = 0xcff, 258 .fw_dump_host_ready = 0xcc, 259 .fw_dump_read_done = 0xdd, 260 .msix_support = 0, 261 }; 262 263 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 264 {"ITCM", NULL, 0, 0xF0}, 265 {"DTCM", NULL, 0, 0xF1}, 266 {"SQRAM", NULL, 0, 0xF2}, 267 {"IRAM", NULL, 0, 0xF3}, 268 {"APU", NULL, 0, 0xF4}, 269 {"CIU", NULL, 0, 0xF5}, 270 {"ICU", NULL, 0, 0xF6}, 271 {"MAC", NULL, 0, 0xF7}, 272 }; 273 274 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 275 {"DUMP", NULL, 0, 0xDD}, 276 }; 277 278 struct mwifiex_pcie_device { 279 const struct mwifiex_pcie_card_reg *reg; 280 u16 blksz_fw_dl; 281 u16 tx_buf_size; 282 bool can_dump_fw; 283 struct memory_type_mapping *mem_type_mapping_tbl; 284 u8 num_mem_types; 285 bool can_ext_scan; 286 }; 287 288 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 289 .reg = &mwifiex_reg_8766, 290 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 291 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 292 .can_dump_fw = false, 293 .can_ext_scan = true, 294 }; 295 296 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 297 .reg = &mwifiex_reg_8897, 298 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 299 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 300 .can_dump_fw = true, 301 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 302 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 303 .can_ext_scan = true, 304 }; 305 306 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 307 .reg = &mwifiex_reg_8997, 308 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 309 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 310 .can_dump_fw = true, 311 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 312 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 313 .can_ext_scan = true, 314 }; 315 316 struct mwifiex_evt_buf_desc { 317 u64 paddr; 318 u16 len; 319 u16 flags; 320 } __packed; 321 322 struct mwifiex_pcie_buf_desc { 323 u64 paddr; 324 u16 len; 325 u16 flags; 326 } __packed; 327 328 struct mwifiex_pfu_buf_desc { 329 u16 flags; 330 u16 offset; 331 u16 frag_len; 332 u16 len; 333 u64 paddr; 334 u32 reserved; 335 } __packed; 336 337 #define MWIFIEX_NUM_MSIX_VECTORS 4 338 339 struct mwifiex_msix_context { 340 struct pci_dev *dev; 341 u16 msg_id; 342 }; 343 344 struct pcie_service_card { 345 struct pci_dev *dev; 346 struct mwifiex_adapter *adapter; 347 struct mwifiex_pcie_device pcie; 348 349 u8 txbd_flush; 350 u32 txbd_wrptr; 351 u32 txbd_rdptr; 352 u32 txbd_ring_size; 353 u8 *txbd_ring_vbase; 354 dma_addr_t txbd_ring_pbase; 355 void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; 356 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; 357 358 u32 rxbd_wrptr; 359 u32 rxbd_rdptr; 360 u32 rxbd_ring_size; 361 u8 *rxbd_ring_vbase; 362 dma_addr_t rxbd_ring_pbase; 363 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; 364 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; 365 366 u32 evtbd_wrptr; 367 u32 evtbd_rdptr; 368 u32 evtbd_ring_size; 369 u8 *evtbd_ring_vbase; 370 dma_addr_t evtbd_ring_pbase; 371 void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; 372 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; 373 374 struct sk_buff *cmd_buf; 375 struct sk_buff *cmdrsp_buf; 376 u8 *sleep_cookie_vbase; 377 dma_addr_t sleep_cookie_pbase; 378 void __iomem *pci_mmap; 379 void __iomem *pci_mmap1; 380 int msi_enable; 381 int msix_enable; 382 #ifdef CONFIG_PCI 383 struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS]; 384 #endif 385 struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS]; 386 struct mwifiex_msix_context share_irq_ctx; 387 }; 388 389 static inline int 390 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) 391 { 392 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 393 394 switch (card->dev->device) { 395 case PCIE_DEVICE_ID_MARVELL_88W8766P: 396 if (((card->txbd_wrptr & reg->tx_mask) == 397 (rdptr & reg->tx_mask)) && 398 ((card->txbd_wrptr & reg->tx_rollover_ind) != 399 (rdptr & reg->tx_rollover_ind))) 400 return 1; 401 break; 402 case PCIE_DEVICE_ID_MARVELL_88W8897: 403 case PCIE_DEVICE_ID_MARVELL_88W8997: 404 if (((card->txbd_wrptr & reg->tx_mask) == 405 (rdptr & reg->tx_mask)) && 406 ((card->txbd_wrptr & reg->tx_rollover_ind) == 407 (rdptr & reg->tx_rollover_ind))) 408 return 1; 409 break; 410 } 411 412 return 0; 413 } 414 415 static inline int 416 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) 417 { 418 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 419 420 switch (card->dev->device) { 421 case PCIE_DEVICE_ID_MARVELL_88W8766P: 422 if (((card->txbd_wrptr & reg->tx_mask) != 423 (card->txbd_rdptr & reg->tx_mask)) || 424 ((card->txbd_wrptr & reg->tx_rollover_ind) != 425 (card->txbd_rdptr & reg->tx_rollover_ind))) 426 return 1; 427 break; 428 case PCIE_DEVICE_ID_MARVELL_88W8897: 429 case PCIE_DEVICE_ID_MARVELL_88W8997: 430 if (((card->txbd_wrptr & reg->tx_mask) != 431 (card->txbd_rdptr & reg->tx_mask)) || 432 ((card->txbd_wrptr & reg->tx_rollover_ind) == 433 (card->txbd_rdptr & reg->tx_rollover_ind))) 434 return 1; 435 break; 436 } 437 438 return 0; 439 } 440 441 #endif /* _MWIFIEX_PCIE_H */ 442