1 /* @file mwifiex_pcie.h 2 * 3 * @brief This file contains definitions for PCI-E interface. 4 * driver. 5 * 6 * Copyright (C) 2011-2014, Marvell International Ltd. 7 * 8 * This software file (the "File") is distributed by Marvell International 9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 10 * (the "License"). You may use, redistribute and/or modify this File in 11 * accordance with the terms and conditions of the License, a copy of which 12 * is available by writing to the Free Software Foundation, Inc., 13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 15 * 16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 19 * this warranty disclaimer. 20 */ 21 22 #ifndef _MWIFIEX_PCIE_H 23 #define _MWIFIEX_PCIE_H 24 25 #include <linux/pci.h> 26 #include <linux/pcieport_if.h> 27 #include <linux/interrupt.h> 28 29 #include "main.h" 30 31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" 32 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" 33 #define PCIE8997_DEFAULT_FW_NAME "mrvl/pcie8997_uapsta.bin" 34 35 #define PCIE_VENDOR_ID_MARVELL (0x11ab) 36 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) 37 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) 38 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42) 39 40 /* Constants for Buffer Descriptor (BD) rings */ 41 #define MWIFIEX_MAX_TXRX_BD 0x20 42 #define MWIFIEX_TXBD_MASK 0x3F 43 #define MWIFIEX_RXBD_MASK 0x3F 44 45 #define MWIFIEX_MAX_EVT_BD 0x08 46 #define MWIFIEX_EVTBD_MASK 0x0f 47 48 /* PCIE INTERNAL REGISTERS */ 49 #define PCIE_SCRATCH_0_REG 0xC10 50 #define PCIE_SCRATCH_1_REG 0xC14 51 #define PCIE_CPU_INT_EVENT 0xC18 52 #define PCIE_CPU_INT_STATUS 0xC1C 53 #define PCIE_HOST_INT_STATUS 0xC30 54 #define PCIE_HOST_INT_MASK 0xC34 55 #define PCIE_HOST_INT_STATUS_MASK 0xC3C 56 #define PCIE_SCRATCH_2_REG 0xC40 57 #define PCIE_SCRATCH_3_REG 0xC44 58 #define PCIE_SCRATCH_4_REG 0xCD0 59 #define PCIE_SCRATCH_5_REG 0xCD4 60 #define PCIE_SCRATCH_6_REG 0xCD8 61 #define PCIE_SCRATCH_7_REG 0xCDC 62 #define PCIE_SCRATCH_8_REG 0xCE0 63 #define PCIE_SCRATCH_9_REG 0xCE4 64 #define PCIE_SCRATCH_10_REG 0xCE8 65 #define PCIE_SCRATCH_11_REG 0xCEC 66 #define PCIE_SCRATCH_12_REG 0xCF0 67 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C 68 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C 69 70 #define CPU_INTR_DNLD_RDY BIT(0) 71 #define CPU_INTR_DOOR_BELL BIT(1) 72 #define CPU_INTR_SLEEP_CFM_DONE BIT(2) 73 #define CPU_INTR_RESET BIT(3) 74 #define CPU_INTR_EVENT_DONE BIT(5) 75 76 #define HOST_INTR_DNLD_DONE BIT(0) 77 #define HOST_INTR_UPLD_RDY BIT(1) 78 #define HOST_INTR_CMD_DONE BIT(2) 79 #define HOST_INTR_EVENT_RDY BIT(3) 80 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ 81 HOST_INTR_UPLD_RDY | \ 82 HOST_INTR_CMD_DONE | \ 83 HOST_INTR_EVENT_RDY) 84 85 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) 86 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) 87 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) 88 #define MWIFIEX_BD_FLAG_SOP BIT(0) 89 #define MWIFIEX_BD_FLAG_EOP BIT(1) 90 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) 91 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) 92 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) 93 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) 94 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) 95 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) 96 97 /* Max retry number of command write */ 98 #define MAX_WRITE_IOMEM_RETRY 2 99 /* Define PCIE block size for firmware download */ 100 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 101 /* FW awake cookie after FW ready */ 102 #define FW_AWAKE_COOKIE (0xAA55AA55) 103 #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF 104 #define MWIFIEX_MAX_DELAY_COUNT 5 105 106 struct mwifiex_pcie_card_reg { 107 u16 cmd_addr_lo; 108 u16 cmd_addr_hi; 109 u16 fw_status; 110 u16 cmd_size; 111 u16 cmdrsp_addr_lo; 112 u16 cmdrsp_addr_hi; 113 u16 tx_rdptr; 114 u16 tx_wrptr; 115 u16 rx_rdptr; 116 u16 rx_wrptr; 117 u16 evt_rdptr; 118 u16 evt_wrptr; 119 u16 drv_rdy; 120 u16 tx_start_ptr; 121 u32 tx_mask; 122 u32 tx_wrap_mask; 123 u32 rx_mask; 124 u32 rx_wrap_mask; 125 u32 tx_rollover_ind; 126 u32 rx_rollover_ind; 127 u32 evt_rollover_ind; 128 u8 ring_flag_sop; 129 u8 ring_flag_eop; 130 u8 ring_flag_xs_sop; 131 u8 ring_flag_xs_eop; 132 u32 ring_tx_start_ptr; 133 u8 pfu_enabled; 134 u8 sleep_cookie; 135 u16 fw_dump_ctrl; 136 u16 fw_dump_start; 137 u16 fw_dump_end; 138 }; 139 140 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 141 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 142 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 143 .cmd_size = PCIE_SCRATCH_2_REG, 144 .fw_status = PCIE_SCRATCH_3_REG, 145 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 146 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 147 .tx_rdptr = PCIE_SCRATCH_6_REG, 148 .tx_wrptr = PCIE_SCRATCH_7_REG, 149 .rx_rdptr = PCIE_SCRATCH_8_REG, 150 .rx_wrptr = PCIE_SCRATCH_9_REG, 151 .evt_rdptr = PCIE_SCRATCH_10_REG, 152 .evt_wrptr = PCIE_SCRATCH_11_REG, 153 .drv_rdy = PCIE_SCRATCH_12_REG, 154 .tx_start_ptr = 0, 155 .tx_mask = MWIFIEX_TXBD_MASK, 156 .tx_wrap_mask = 0, 157 .rx_mask = MWIFIEX_RXBD_MASK, 158 .rx_wrap_mask = 0, 159 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 160 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 161 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 162 .ring_flag_sop = 0, 163 .ring_flag_eop = 0, 164 .ring_flag_xs_sop = 0, 165 .ring_flag_xs_eop = 0, 166 .ring_tx_start_ptr = 0, 167 .pfu_enabled = 0, 168 .sleep_cookie = 1, 169 }; 170 171 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 172 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 173 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 174 .cmd_size = PCIE_SCRATCH_2_REG, 175 .fw_status = PCIE_SCRATCH_3_REG, 176 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 177 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 178 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 179 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 180 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 181 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 182 .evt_rdptr = PCIE_SCRATCH_10_REG, 183 .evt_wrptr = PCIE_SCRATCH_11_REG, 184 .drv_rdy = PCIE_SCRATCH_12_REG, 185 .tx_start_ptr = 16, 186 .tx_mask = 0x03FF0000, 187 .tx_wrap_mask = 0x07FF0000, 188 .rx_mask = 0x000003FF, 189 .rx_wrap_mask = 0x000007FF, 190 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 191 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 192 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 193 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 194 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 195 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 196 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 197 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 198 .pfu_enabled = 1, 199 .sleep_cookie = 0, 200 .fw_dump_ctrl = 0xcf4, 201 .fw_dump_start = 0xcf8, 202 .fw_dump_end = 0xcff, 203 }; 204 205 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 206 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 207 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 208 .cmd_size = PCIE_SCRATCH_2_REG, 209 .fw_status = PCIE_SCRATCH_3_REG, 210 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 211 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 212 .tx_rdptr = 0xC1A4, 213 .tx_wrptr = 0xC174, 214 .rx_rdptr = 0xC174, 215 .rx_wrptr = 0xC1A4, 216 .evt_rdptr = PCIE_SCRATCH_10_REG, 217 .evt_wrptr = PCIE_SCRATCH_11_REG, 218 .drv_rdy = PCIE_SCRATCH_12_REG, 219 .tx_start_ptr = 16, 220 .tx_mask = 0x0FFF0000, 221 .tx_wrap_mask = 0x1FFF0000, 222 .rx_mask = 0x00000FFF, 223 .rx_wrap_mask = 0x00001FFF, 224 .tx_rollover_ind = BIT(28), 225 .rx_rollover_ind = BIT(12), 226 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 227 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 228 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 229 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 230 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 231 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 232 .pfu_enabled = 1, 233 .sleep_cookie = 0, 234 }; 235 236 struct mwifiex_pcie_device { 237 const char *firmware; 238 const struct mwifiex_pcie_card_reg *reg; 239 u16 blksz_fw_dl; 240 u16 tx_buf_size; 241 bool can_dump_fw; 242 bool can_ext_scan; 243 }; 244 245 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 246 .firmware = PCIE8766_DEFAULT_FW_NAME, 247 .reg = &mwifiex_reg_8766, 248 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 249 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 250 .can_dump_fw = false, 251 .can_ext_scan = true, 252 }; 253 254 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 255 .firmware = PCIE8897_DEFAULT_FW_NAME, 256 .reg = &mwifiex_reg_8897, 257 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 258 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 259 .can_dump_fw = true, 260 .can_ext_scan = true, 261 }; 262 263 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 264 .firmware = PCIE8997_DEFAULT_FW_NAME, 265 .reg = &mwifiex_reg_8997, 266 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 267 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 268 .can_dump_fw = false, 269 .can_ext_scan = true, 270 }; 271 272 struct mwifiex_evt_buf_desc { 273 u64 paddr; 274 u16 len; 275 u16 flags; 276 } __packed; 277 278 struct mwifiex_pcie_buf_desc { 279 u64 paddr; 280 u16 len; 281 u16 flags; 282 } __packed; 283 284 struct mwifiex_pfu_buf_desc { 285 u16 flags; 286 u16 offset; 287 u16 frag_len; 288 u16 len; 289 u64 paddr; 290 u32 reserved; 291 } __packed; 292 293 struct pcie_service_card { 294 struct pci_dev *dev; 295 struct mwifiex_adapter *adapter; 296 struct mwifiex_pcie_device pcie; 297 298 u8 txbd_flush; 299 u32 txbd_wrptr; 300 u32 txbd_rdptr; 301 u32 txbd_ring_size; 302 u8 *txbd_ring_vbase; 303 dma_addr_t txbd_ring_pbase; 304 void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; 305 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; 306 307 u32 rxbd_wrptr; 308 u32 rxbd_rdptr; 309 u32 rxbd_ring_size; 310 u8 *rxbd_ring_vbase; 311 dma_addr_t rxbd_ring_pbase; 312 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; 313 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; 314 315 u32 evtbd_wrptr; 316 u32 evtbd_rdptr; 317 u32 evtbd_ring_size; 318 u8 *evtbd_ring_vbase; 319 dma_addr_t evtbd_ring_pbase; 320 void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; 321 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; 322 323 struct sk_buff *cmd_buf; 324 struct sk_buff *cmdrsp_buf; 325 u8 *sleep_cookie_vbase; 326 dma_addr_t sleep_cookie_pbase; 327 void __iomem *pci_mmap; 328 void __iomem *pci_mmap1; 329 int msi_enable; 330 }; 331 332 static inline int 333 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) 334 { 335 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 336 337 switch (card->dev->device) { 338 case PCIE_DEVICE_ID_MARVELL_88W8766P: 339 if (((card->txbd_wrptr & reg->tx_mask) == 340 (rdptr & reg->tx_mask)) && 341 ((card->txbd_wrptr & reg->tx_rollover_ind) != 342 (rdptr & reg->tx_rollover_ind))) 343 return 1; 344 break; 345 case PCIE_DEVICE_ID_MARVELL_88W8897: 346 case PCIE_DEVICE_ID_MARVELL_88W8997: 347 if (((card->txbd_wrptr & reg->tx_mask) == 348 (rdptr & reg->tx_mask)) && 349 ((card->txbd_wrptr & reg->tx_rollover_ind) == 350 (rdptr & reg->tx_rollover_ind))) 351 return 1; 352 break; 353 } 354 355 return 0; 356 } 357 358 static inline int 359 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) 360 { 361 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 362 363 switch (card->dev->device) { 364 case PCIE_DEVICE_ID_MARVELL_88W8766P: 365 if (((card->txbd_wrptr & reg->tx_mask) != 366 (card->txbd_rdptr & reg->tx_mask)) || 367 ((card->txbd_wrptr & reg->tx_rollover_ind) != 368 (card->txbd_rdptr & reg->tx_rollover_ind))) 369 return 1; 370 break; 371 case PCIE_DEVICE_ID_MARVELL_88W8897: 372 case PCIE_DEVICE_ID_MARVELL_88W8997: 373 if (((card->txbd_wrptr & reg->tx_mask) != 374 (card->txbd_rdptr & reg->tx_mask)) || 375 ((card->txbd_wrptr & reg->tx_rollover_ind) == 376 (card->txbd_rdptr & reg->tx_rollover_ind))) 377 return 1; 378 break; 379 } 380 381 return 0; 382 } 383 384 #endif /* _MWIFIEX_PCIE_H */ 385