1 /* 2 * NXP Wireless LAN device driver: PCIE specific handling 3 * 4 * Copyright 2011-2020 NXP 5 * 6 * This software file (the "File") is distributed by NXP 7 * under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #include <linux/firmware.h> 21 22 #include "decl.h" 23 #include "ioctl.h" 24 #include "util.h" 25 #include "fw.h" 26 #include "main.h" 27 #include "wmm.h" 28 #include "11n.h" 29 #include "pcie.h" 30 31 #define PCIE_VERSION "1.0" 32 #define DRV_NAME "Marvell mwifiex PCIe" 33 34 static struct mwifiex_if_ops pcie_ops; 35 36 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 37 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 38 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 39 .cmd_size = PCIE_SCRATCH_2_REG, 40 .fw_status = PCIE_SCRATCH_3_REG, 41 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 42 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 43 .tx_rdptr = PCIE_SCRATCH_6_REG, 44 .tx_wrptr = PCIE_SCRATCH_7_REG, 45 .rx_rdptr = PCIE_SCRATCH_8_REG, 46 .rx_wrptr = PCIE_SCRATCH_9_REG, 47 .evt_rdptr = PCIE_SCRATCH_10_REG, 48 .evt_wrptr = PCIE_SCRATCH_11_REG, 49 .drv_rdy = PCIE_SCRATCH_12_REG, 50 .tx_start_ptr = 0, 51 .tx_mask = MWIFIEX_TXBD_MASK, 52 .tx_wrap_mask = 0, 53 .rx_mask = MWIFIEX_RXBD_MASK, 54 .rx_wrap_mask = 0, 55 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 56 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 57 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 58 .ring_flag_sop = 0, 59 .ring_flag_eop = 0, 60 .ring_flag_xs_sop = 0, 61 .ring_flag_xs_eop = 0, 62 .ring_tx_start_ptr = 0, 63 .pfu_enabled = 0, 64 .sleep_cookie = 1, 65 .msix_support = 0, 66 }; 67 68 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 69 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 70 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 71 .cmd_size = PCIE_SCRATCH_2_REG, 72 .fw_status = PCIE_SCRATCH_3_REG, 73 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 74 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 75 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 76 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 77 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 78 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 79 .evt_rdptr = PCIE_SCRATCH_10_REG, 80 .evt_wrptr = PCIE_SCRATCH_11_REG, 81 .drv_rdy = PCIE_SCRATCH_12_REG, 82 .tx_start_ptr = 16, 83 .tx_mask = 0x03FF0000, 84 .tx_wrap_mask = 0x07FF0000, 85 .rx_mask = 0x000003FF, 86 .rx_wrap_mask = 0x000007FF, 87 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 88 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 89 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 90 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 91 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 92 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 93 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 94 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 95 .pfu_enabled = 1, 96 .sleep_cookie = 0, 97 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 98 .fw_dump_start = PCIE_SCRATCH_14_REG, 99 .fw_dump_end = 0xcff, 100 .fw_dump_host_ready = 0xee, 101 .fw_dump_read_done = 0xfe, 102 .msix_support = 0, 103 }; 104 105 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 106 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 107 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 108 .cmd_size = PCIE_SCRATCH_2_REG, 109 .fw_status = PCIE_SCRATCH_3_REG, 110 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 111 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 112 .tx_rdptr = 0xC1A4, 113 .tx_wrptr = 0xC174, 114 .rx_rdptr = 0xC174, 115 .rx_wrptr = 0xC1A4, 116 .evt_rdptr = PCIE_SCRATCH_10_REG, 117 .evt_wrptr = PCIE_SCRATCH_11_REG, 118 .drv_rdy = PCIE_SCRATCH_12_REG, 119 .tx_start_ptr = 16, 120 .tx_mask = 0x0FFF0000, 121 .tx_wrap_mask = 0x1FFF0000, 122 .rx_mask = 0x00000FFF, 123 .rx_wrap_mask = 0x00001FFF, 124 .tx_rollover_ind = BIT(28), 125 .rx_rollover_ind = BIT(12), 126 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 127 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 128 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 129 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 130 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 131 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 132 .pfu_enabled = 1, 133 .sleep_cookie = 0, 134 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 135 .fw_dump_start = PCIE_SCRATCH_14_REG, 136 .fw_dump_end = 0xcff, 137 .fw_dump_host_ready = 0xcc, 138 .fw_dump_read_done = 0xdd, 139 .msix_support = 0, 140 }; 141 142 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 143 {"ITCM", NULL, 0, 0xF0}, 144 {"DTCM", NULL, 0, 0xF1}, 145 {"SQRAM", NULL, 0, 0xF2}, 146 {"IRAM", NULL, 0, 0xF3}, 147 {"APU", NULL, 0, 0xF4}, 148 {"CIU", NULL, 0, 0xF5}, 149 {"ICU", NULL, 0, 0xF6}, 150 {"MAC", NULL, 0, 0xF7}, 151 }; 152 153 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 154 {"DUMP", NULL, 0, 0xDD}, 155 }; 156 157 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 158 .reg = &mwifiex_reg_8766, 159 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 160 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 161 .can_dump_fw = false, 162 .can_ext_scan = true, 163 }; 164 165 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 166 .reg = &mwifiex_reg_8897, 167 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 168 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 169 .can_dump_fw = true, 170 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 171 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 172 .can_ext_scan = true, 173 }; 174 175 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 176 .reg = &mwifiex_reg_8997, 177 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 178 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 179 .can_dump_fw = true, 180 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 181 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 182 .can_ext_scan = true, 183 }; 184 185 static const struct of_device_id mwifiex_pcie_of_match_table[] = { 186 { .compatible = "pci11ab,2b42" }, 187 { .compatible = "pci1b4b,2b42" }, 188 { } 189 }; 190 191 static int mwifiex_pcie_probe_of(struct device *dev) 192 { 193 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) { 194 dev_err(dev, "required compatible string missing\n"); 195 return -EINVAL; 196 } 197 198 return 0; 199 } 200 201 static void mwifiex_pcie_work(struct work_struct *work); 202 203 static int 204 mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, 205 size_t size, int flags) 206 { 207 struct pcie_service_card *card = adapter->card; 208 struct mwifiex_dma_mapping mapping; 209 210 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); 211 if (dma_mapping_error(&card->dev->dev, mapping.addr)) { 212 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); 213 return -1; 214 } 215 mapping.len = size; 216 mwifiex_store_mapping(skb, &mapping); 217 return 0; 218 } 219 220 static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, 221 struct sk_buff *skb, int flags) 222 { 223 struct pcie_service_card *card = adapter->card; 224 struct mwifiex_dma_mapping mapping; 225 226 mwifiex_get_mapping(skb, &mapping); 227 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); 228 } 229 230 /* 231 * This function writes data into PCIE card register. 232 */ 233 static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) 234 { 235 struct pcie_service_card *card = adapter->card; 236 237 iowrite32(data, card->pci_mmap1 + reg); 238 239 return 0; 240 } 241 242 /* This function reads data from PCIE card register. 243 */ 244 static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) 245 { 246 struct pcie_service_card *card = adapter->card; 247 248 *data = ioread32(card->pci_mmap1 + reg); 249 if (*data == 0xffffffff) 250 return 0xffffffff; 251 252 return 0; 253 } 254 255 /* This function reads u8 data from PCIE card register. */ 256 static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter, 257 int reg, u8 *data) 258 { 259 struct pcie_service_card *card = adapter->card; 260 261 *data = ioread8(card->pci_mmap1 + reg); 262 263 return 0; 264 } 265 266 /* 267 * This function reads sleep cookie and checks if FW is ready 268 */ 269 static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) 270 { 271 u32 cookie_value; 272 struct pcie_service_card *card = adapter->card; 273 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 274 275 if (!reg->sleep_cookie) 276 return true; 277 278 if (card->sleep_cookie_vbase) { 279 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase); 280 mwifiex_dbg(adapter, INFO, 281 "info: ACCESS_HW: sleep cookie=0x%x\n", 282 cookie_value); 283 if (cookie_value == FW_AWAKE_COOKIE) 284 return true; 285 } 286 287 return false; 288 } 289 290 #ifdef CONFIG_PM_SLEEP 291 /* 292 * Kernel needs to suspend all functions separately. Therefore all 293 * registered functions must have drivers with suspend and resume 294 * methods. Failing that the kernel simply removes the whole card. 295 * 296 * If already not suspended, this function allocates and sends a host 297 * sleep activate request to the firmware and turns off the traffic. 298 */ 299 static int mwifiex_pcie_suspend(struct device *dev) 300 { 301 struct mwifiex_adapter *adapter; 302 struct pcie_service_card *card = dev_get_drvdata(dev); 303 304 305 /* Might still be loading firmware */ 306 wait_for_completion(&card->fw_done); 307 308 adapter = card->adapter; 309 if (!adapter) { 310 dev_err(dev, "adapter is not valid\n"); 311 return 0; 312 } 313 314 mwifiex_enable_wake(adapter); 315 316 /* Enable the Host Sleep */ 317 if (!mwifiex_enable_hs(adapter)) { 318 mwifiex_dbg(adapter, ERROR, 319 "cmd: failed to suspend\n"); 320 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 321 mwifiex_disable_wake(adapter); 322 return -EFAULT; 323 } 324 325 flush_workqueue(adapter->workqueue); 326 327 /* Indicate device suspended */ 328 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 329 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 330 331 return 0; 332 } 333 334 /* 335 * Kernel needs to suspend all functions separately. Therefore all 336 * registered functions must have drivers with suspend and resume 337 * methods. Failing that the kernel simply removes the whole card. 338 * 339 * If already not resumed, this function turns on the traffic and 340 * sends a host sleep cancel request to the firmware. 341 */ 342 static int mwifiex_pcie_resume(struct device *dev) 343 { 344 struct mwifiex_adapter *adapter; 345 struct pcie_service_card *card = dev_get_drvdata(dev); 346 347 348 if (!card->adapter) { 349 dev_err(dev, "adapter structure is not valid\n"); 350 return 0; 351 } 352 353 adapter = card->adapter; 354 355 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) { 356 mwifiex_dbg(adapter, WARN, 357 "Device already resumed\n"); 358 return 0; 359 } 360 361 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 362 363 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), 364 MWIFIEX_ASYNC_CMD); 365 mwifiex_disable_wake(adapter); 366 367 return 0; 368 } 369 #endif 370 371 /* 372 * This function probes an mwifiex device and registers it. It allocates 373 * the card structure, enables PCIE function number and initiates the 374 * device registration and initialization procedure by adding a logical 375 * interface. 376 */ 377 static int mwifiex_pcie_probe(struct pci_dev *pdev, 378 const struct pci_device_id *ent) 379 { 380 struct pcie_service_card *card; 381 int ret; 382 383 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 384 pdev->vendor, pdev->device, pdev->revision); 385 386 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 387 if (!card) 388 return -ENOMEM; 389 390 init_completion(&card->fw_done); 391 392 card->dev = pdev; 393 394 if (ent->driver_data) { 395 struct mwifiex_pcie_device *data = (void *)ent->driver_data; 396 card->pcie.reg = data->reg; 397 card->pcie.blksz_fw_dl = data->blksz_fw_dl; 398 card->pcie.tx_buf_size = data->tx_buf_size; 399 card->pcie.can_dump_fw = data->can_dump_fw; 400 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl; 401 card->pcie.num_mem_types = data->num_mem_types; 402 card->pcie.can_ext_scan = data->can_ext_scan; 403 INIT_WORK(&card->work, mwifiex_pcie_work); 404 } 405 406 /* device tree node parsing and platform specific configuration*/ 407 if (pdev->dev.of_node) { 408 ret = mwifiex_pcie_probe_of(&pdev->dev); 409 if (ret) 410 return ret; 411 } 412 413 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops, 414 MWIFIEX_PCIE, &pdev->dev)) { 415 pr_err("%s failed\n", __func__); 416 return -1; 417 } 418 419 return 0; 420 } 421 422 /* 423 * This function removes the interface and frees up the card structure. 424 */ 425 static void mwifiex_pcie_remove(struct pci_dev *pdev) 426 { 427 struct pcie_service_card *card; 428 struct mwifiex_adapter *adapter; 429 struct mwifiex_private *priv; 430 const struct mwifiex_pcie_card_reg *reg; 431 u32 fw_status; 432 int ret; 433 434 card = pci_get_drvdata(pdev); 435 436 wait_for_completion(&card->fw_done); 437 438 adapter = card->adapter; 439 if (!adapter || !adapter->priv_num) 440 return; 441 442 reg = card->pcie.reg; 443 if (reg) 444 ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 445 else 446 fw_status = -1; 447 448 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) { 449 mwifiex_deauthenticate_all(adapter); 450 451 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); 452 453 mwifiex_disable_auto_ds(priv); 454 455 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); 456 } 457 458 mwifiex_remove_card(adapter); 459 } 460 461 static void mwifiex_pcie_shutdown(struct pci_dev *pdev) 462 { 463 mwifiex_pcie_remove(pdev); 464 465 return; 466 } 467 468 static void mwifiex_pcie_coredump(struct device *dev) 469 { 470 struct pci_dev *pdev; 471 struct pcie_service_card *card; 472 473 pdev = container_of(dev, struct pci_dev, dev); 474 card = pci_get_drvdata(pdev); 475 476 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 477 &card->work_flags)) 478 schedule_work(&card->work); 479 } 480 481 static const struct pci_device_id mwifiex_ids[] = { 482 { 483 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, 484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 485 .driver_data = (unsigned long)&mwifiex_pcie8766, 486 }, 487 { 488 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, 489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 490 .driver_data = (unsigned long)&mwifiex_pcie8897, 491 }, 492 { 493 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 495 .driver_data = (unsigned long)&mwifiex_pcie8997, 496 }, 497 { 498 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 500 .driver_data = (unsigned long)&mwifiex_pcie8997, 501 }, 502 {}, 503 }; 504 505 MODULE_DEVICE_TABLE(pci, mwifiex_ids); 506 507 /* 508 * Cleanup all software without cleaning anything related to PCIe and HW. 509 */ 510 static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev) 511 { 512 struct pcie_service_card *card = pci_get_drvdata(pdev); 513 struct mwifiex_adapter *adapter = card->adapter; 514 515 if (!adapter) { 516 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 517 __func__); 518 return; 519 } 520 521 mwifiex_dbg(adapter, INFO, 522 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", 523 __func__, pdev->vendor, pdev->device, pdev->revision); 524 525 mwifiex_shutdown_sw(adapter); 526 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags); 527 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags); 528 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 529 } 530 531 /* 532 * Kernel stores and restores PCIe function context before and after performing 533 * FLR respectively. Reconfigure the software and firmware including firmware 534 * redownload. 535 */ 536 static void mwifiex_pcie_reset_done(struct pci_dev *pdev) 537 { 538 struct pcie_service_card *card = pci_get_drvdata(pdev); 539 struct mwifiex_adapter *adapter = card->adapter; 540 int ret; 541 542 if (!adapter) { 543 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 544 __func__); 545 return; 546 } 547 548 mwifiex_dbg(adapter, INFO, 549 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", 550 __func__, pdev->vendor, pdev->device, pdev->revision); 551 552 ret = mwifiex_reinit_sw(adapter); 553 if (ret) 554 dev_err(&pdev->dev, "reinit failed: %d\n", ret); 555 else 556 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 557 } 558 559 static const struct pci_error_handlers mwifiex_pcie_err_handler = { 560 .reset_prepare = mwifiex_pcie_reset_prepare, 561 .reset_done = mwifiex_pcie_reset_done, 562 }; 563 564 #ifdef CONFIG_PM_SLEEP 565 /* Power Management Hooks */ 566 static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, 567 mwifiex_pcie_resume); 568 #endif 569 570 /* PCI Device Driver */ 571 static struct pci_driver __refdata mwifiex_pcie = { 572 .name = "mwifiex_pcie", 573 .id_table = mwifiex_ids, 574 .probe = mwifiex_pcie_probe, 575 .remove = mwifiex_pcie_remove, 576 .driver = { 577 .coredump = mwifiex_pcie_coredump, 578 #ifdef CONFIG_PM_SLEEP 579 .pm = &mwifiex_pcie_pm_ops, 580 #endif 581 }, 582 .shutdown = mwifiex_pcie_shutdown, 583 .err_handler = &mwifiex_pcie_err_handler, 584 }; 585 586 /* 587 * This function adds delay loop to ensure FW is awake before proceeding. 588 */ 589 static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) 590 { 591 int i = 0; 592 593 while (mwifiex_pcie_ok_to_access_hw(adapter)) { 594 i++; 595 usleep_range(10, 20); 596 /* 50ms max wait */ 597 if (i == 5000) 598 break; 599 } 600 601 return; 602 } 603 604 static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, 605 u32 max_delay_loop_cnt) 606 { 607 struct pcie_service_card *card = adapter->card; 608 u8 *buffer; 609 u32 sleep_cookie, count; 610 struct sk_buff *cmdrsp = card->cmdrsp_buf; 611 612 for (count = 0; count < max_delay_loop_cnt; count++) { 613 dma_sync_single_for_cpu(&card->dev->dev, 614 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 615 sizeof(sleep_cookie), DMA_FROM_DEVICE); 616 buffer = cmdrsp->data; 617 sleep_cookie = get_unaligned_le32(buffer); 618 619 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { 620 mwifiex_dbg(adapter, INFO, 621 "sleep cookie found at count %d\n", count); 622 break; 623 } 624 dma_sync_single_for_device(&card->dev->dev, 625 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 626 sizeof(sleep_cookie), 627 DMA_FROM_DEVICE); 628 usleep_range(20, 30); 629 } 630 631 if (count >= max_delay_loop_cnt) 632 mwifiex_dbg(adapter, INFO, 633 "max count reached while accessing sleep cookie\n"); 634 } 635 636 /* This function wakes up the card by reading fw_status register. */ 637 static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) 638 { 639 struct pcie_service_card *card = adapter->card; 640 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 641 642 mwifiex_dbg(adapter, EVENT, 643 "event: Wakeup device...\n"); 644 645 if (reg->sleep_cookie) 646 mwifiex_pcie_dev_wakeup_delay(adapter); 647 648 /* Accessing fw_status register will wakeup device */ 649 if (mwifiex_write_reg(adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 650 mwifiex_dbg(adapter, ERROR, 651 "Writing fw_status register failed\n"); 652 return -1; 653 } 654 655 if (reg->sleep_cookie) { 656 mwifiex_pcie_dev_wakeup_delay(adapter); 657 mwifiex_dbg(adapter, INFO, 658 "PCIE wakeup: Setting PS_STATE_AWAKE\n"); 659 adapter->ps_state = PS_STATE_AWAKE; 660 } 661 662 return 0; 663 } 664 665 /* 666 * This function is called after the card has woken up. 667 * 668 * The card configuration register is reset. 669 */ 670 static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) 671 { 672 mwifiex_dbg(adapter, CMD, 673 "cmd: Wakeup device completed\n"); 674 675 return 0; 676 } 677 678 /* 679 * This function disables the host interrupt. 680 * 681 * The host interrupt mask is read, the disable bit is reset and 682 * written back to the card host interrupt mask register. 683 */ 684 static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) 685 { 686 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 687 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 688 0x00000000)) { 689 mwifiex_dbg(adapter, ERROR, 690 "Disable host interrupt failed\n"); 691 return -1; 692 } 693 } 694 695 atomic_set(&adapter->tx_hw_pending, 0); 696 return 0; 697 } 698 699 static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter) 700 { 701 WARN_ON(mwifiex_pcie_disable_host_int(adapter)); 702 } 703 704 /* 705 * This function enables the host interrupt. 706 * 707 * The host interrupt enable mask is written to the card 708 * host interrupt mask register. 709 */ 710 static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) 711 { 712 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 713 /* Simply write the mask to the register */ 714 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 715 HOST_INTR_MASK)) { 716 mwifiex_dbg(adapter, ERROR, 717 "Enable host interrupt failed\n"); 718 return -1; 719 } 720 } 721 722 return 0; 723 } 724 725 /* 726 * This function initializes TX buffer ring descriptors 727 */ 728 static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) 729 { 730 struct pcie_service_card *card = adapter->card; 731 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 732 struct mwifiex_pcie_buf_desc *desc; 733 struct mwifiex_pfu_buf_desc *desc2; 734 int i; 735 736 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 737 card->tx_buf_list[i] = NULL; 738 if (reg->pfu_enabled) { 739 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 740 (sizeof(*desc2) * i); 741 desc2 = card->txbd_ring[i]; 742 memset(desc2, 0, sizeof(*desc2)); 743 } else { 744 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 745 (sizeof(*desc) * i); 746 desc = card->txbd_ring[i]; 747 memset(desc, 0, sizeof(*desc)); 748 } 749 } 750 751 return 0; 752 } 753 754 /* This function initializes RX buffer ring descriptors. Each SKB is allocated 755 * here and after mapping PCI memory, its physical address is assigned to 756 * PCIE Rx buffer descriptor's physical address. 757 */ 758 static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) 759 { 760 struct pcie_service_card *card = adapter->card; 761 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 762 struct sk_buff *skb; 763 struct mwifiex_pcie_buf_desc *desc; 764 struct mwifiex_pfu_buf_desc *desc2; 765 dma_addr_t buf_pa; 766 int i; 767 768 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 769 /* Allocate skb here so that firmware can DMA data from it */ 770 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 771 GFP_KERNEL); 772 if (!skb) { 773 mwifiex_dbg(adapter, ERROR, 774 "Unable to allocate skb for RX ring.\n"); 775 kfree(card->rxbd_ring_vbase); 776 return -ENOMEM; 777 } 778 779 if (mwifiex_map_pci_memory(adapter, skb, 780 MWIFIEX_RX_DATA_BUF_SIZE, 781 DMA_FROM_DEVICE)) 782 return -1; 783 784 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 785 786 mwifiex_dbg(adapter, INFO, 787 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 788 skb, skb->len, skb->data, (u32)buf_pa, 789 (u32)((u64)buf_pa >> 32)); 790 791 card->rx_buf_list[i] = skb; 792 if (reg->pfu_enabled) { 793 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + 794 (sizeof(*desc2) * i); 795 desc2 = card->rxbd_ring[i]; 796 desc2->paddr = buf_pa; 797 desc2->len = (u16)skb->len; 798 desc2->frag_len = (u16)skb->len; 799 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; 800 desc2->offset = 0; 801 } else { 802 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + 803 (sizeof(*desc) * i)); 804 desc = card->rxbd_ring[i]; 805 desc->paddr = buf_pa; 806 desc->len = (u16)skb->len; 807 desc->flags = 0; 808 } 809 } 810 811 return 0; 812 } 813 814 /* This function initializes event buffer ring descriptors. Each SKB is 815 * allocated here and after mapping PCI memory, its physical address is assigned 816 * to PCIE Rx buffer descriptor's physical address 817 */ 818 static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) 819 { 820 struct pcie_service_card *card = adapter->card; 821 struct mwifiex_evt_buf_desc *desc; 822 struct sk_buff *skb; 823 dma_addr_t buf_pa; 824 int i; 825 826 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 827 /* Allocate skb here so that firmware can DMA data from it */ 828 skb = dev_alloc_skb(MAX_EVENT_SIZE); 829 if (!skb) { 830 mwifiex_dbg(adapter, ERROR, 831 "Unable to allocate skb for EVENT buf.\n"); 832 kfree(card->evtbd_ring_vbase); 833 return -ENOMEM; 834 } 835 skb_put(skb, MAX_EVENT_SIZE); 836 837 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, 838 DMA_FROM_DEVICE)) { 839 kfree_skb(skb); 840 kfree(card->evtbd_ring_vbase); 841 return -1; 842 } 843 844 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 845 846 mwifiex_dbg(adapter, EVENT, 847 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 848 skb, skb->len, skb->data, (u32)buf_pa, 849 (u32)((u64)buf_pa >> 32)); 850 851 card->evt_buf_list[i] = skb; 852 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + 853 (sizeof(*desc) * i)); 854 desc = card->evtbd_ring[i]; 855 desc->paddr = buf_pa; 856 desc->len = (u16)skb->len; 857 desc->flags = 0; 858 } 859 860 return 0; 861 } 862 863 /* This function cleans up TX buffer rings. If any of the buffer list has valid 864 * SKB address, associated SKB is freed. 865 */ 866 static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) 867 { 868 struct pcie_service_card *card = adapter->card; 869 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 870 struct sk_buff *skb; 871 struct mwifiex_pcie_buf_desc *desc; 872 struct mwifiex_pfu_buf_desc *desc2; 873 int i; 874 875 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 876 if (reg->pfu_enabled) { 877 desc2 = card->txbd_ring[i]; 878 if (card->tx_buf_list[i]) { 879 skb = card->tx_buf_list[i]; 880 mwifiex_unmap_pci_memory(adapter, skb, 881 DMA_TO_DEVICE); 882 dev_kfree_skb_any(skb); 883 } 884 memset(desc2, 0, sizeof(*desc2)); 885 } else { 886 desc = card->txbd_ring[i]; 887 if (card->tx_buf_list[i]) { 888 skb = card->tx_buf_list[i]; 889 mwifiex_unmap_pci_memory(adapter, skb, 890 DMA_TO_DEVICE); 891 dev_kfree_skb_any(skb); 892 } 893 memset(desc, 0, sizeof(*desc)); 894 } 895 card->tx_buf_list[i] = NULL; 896 } 897 898 atomic_set(&adapter->tx_hw_pending, 0); 899 return; 900 } 901 902 /* This function cleans up RX buffer rings. If any of the buffer list has valid 903 * SKB address, associated SKB is freed. 904 */ 905 static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) 906 { 907 struct pcie_service_card *card = adapter->card; 908 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 909 struct mwifiex_pcie_buf_desc *desc; 910 struct mwifiex_pfu_buf_desc *desc2; 911 struct sk_buff *skb; 912 int i; 913 914 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 915 if (reg->pfu_enabled) { 916 desc2 = card->rxbd_ring[i]; 917 if (card->rx_buf_list[i]) { 918 skb = card->rx_buf_list[i]; 919 mwifiex_unmap_pci_memory(adapter, skb, 920 DMA_FROM_DEVICE); 921 dev_kfree_skb_any(skb); 922 } 923 memset(desc2, 0, sizeof(*desc2)); 924 } else { 925 desc = card->rxbd_ring[i]; 926 if (card->rx_buf_list[i]) { 927 skb = card->rx_buf_list[i]; 928 mwifiex_unmap_pci_memory(adapter, skb, 929 DMA_FROM_DEVICE); 930 dev_kfree_skb_any(skb); 931 } 932 memset(desc, 0, sizeof(*desc)); 933 } 934 card->rx_buf_list[i] = NULL; 935 } 936 937 return; 938 } 939 940 /* This function cleans up event buffer rings. If any of the buffer list has 941 * valid SKB address, associated SKB is freed. 942 */ 943 static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) 944 { 945 struct pcie_service_card *card = adapter->card; 946 struct mwifiex_evt_buf_desc *desc; 947 struct sk_buff *skb; 948 int i; 949 950 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 951 desc = card->evtbd_ring[i]; 952 if (card->evt_buf_list[i]) { 953 skb = card->evt_buf_list[i]; 954 mwifiex_unmap_pci_memory(adapter, skb, 955 DMA_FROM_DEVICE); 956 dev_kfree_skb_any(skb); 957 } 958 card->evt_buf_list[i] = NULL; 959 memset(desc, 0, sizeof(*desc)); 960 } 961 962 return; 963 } 964 965 /* This function creates buffer descriptor ring for TX 966 */ 967 static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) 968 { 969 struct pcie_service_card *card = adapter->card; 970 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 971 972 /* 973 * driver maintaines the write pointer and firmware maintaines the read 974 * pointer. The write pointer starts at 0 (zero) while the read pointer 975 * starts at zero with rollover bit set 976 */ 977 card->txbd_wrptr = 0; 978 979 if (reg->pfu_enabled) 980 card->txbd_rdptr = 0; 981 else 982 card->txbd_rdptr |= reg->tx_rollover_ind; 983 984 /* allocate shared memory for the BD ring and divide the same in to 985 several descriptors */ 986 if (reg->pfu_enabled) 987 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 988 MWIFIEX_MAX_TXRX_BD; 989 else 990 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 991 MWIFIEX_MAX_TXRX_BD; 992 993 mwifiex_dbg(adapter, INFO, 994 "info: txbd_ring: Allocating %d bytes\n", 995 card->txbd_ring_size); 996 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 997 card->txbd_ring_size, 998 &card->txbd_ring_pbase, 999 GFP_KERNEL); 1000 if (!card->txbd_ring_vbase) { 1001 mwifiex_dbg(adapter, ERROR, 1002 "allocate coherent memory (%d bytes) failed!\n", 1003 card->txbd_ring_size); 1004 return -ENOMEM; 1005 } 1006 1007 mwifiex_dbg(adapter, DATA, 1008 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1009 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase, 1010 (u32)((u64)card->txbd_ring_pbase >> 32), 1011 card->txbd_ring_size); 1012 1013 return mwifiex_init_txq_ring(adapter); 1014 } 1015 1016 static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) 1017 { 1018 struct pcie_service_card *card = adapter->card; 1019 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1020 1021 mwifiex_cleanup_txq_ring(adapter); 1022 1023 if (card->txbd_ring_vbase) 1024 dma_free_coherent(&card->dev->dev, card->txbd_ring_size, 1025 card->txbd_ring_vbase, 1026 card->txbd_ring_pbase); 1027 card->txbd_ring_size = 0; 1028 card->txbd_wrptr = 0; 1029 card->txbd_rdptr = 0 | reg->tx_rollover_ind; 1030 card->txbd_ring_vbase = NULL; 1031 card->txbd_ring_pbase = 0; 1032 1033 return 0; 1034 } 1035 1036 /* 1037 * This function creates buffer descriptor ring for RX 1038 */ 1039 static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) 1040 { 1041 struct pcie_service_card *card = adapter->card; 1042 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1043 1044 /* 1045 * driver maintaines the read pointer and firmware maintaines the write 1046 * pointer. The write pointer starts at 0 (zero) while the read pointer 1047 * starts at zero with rollover bit set 1048 */ 1049 card->rxbd_wrptr = 0; 1050 card->rxbd_rdptr = reg->rx_rollover_ind; 1051 1052 if (reg->pfu_enabled) 1053 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 1054 MWIFIEX_MAX_TXRX_BD; 1055 else 1056 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1057 MWIFIEX_MAX_TXRX_BD; 1058 1059 mwifiex_dbg(adapter, INFO, 1060 "info: rxbd_ring: Allocating %d bytes\n", 1061 card->rxbd_ring_size); 1062 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1063 card->rxbd_ring_size, 1064 &card->rxbd_ring_pbase, 1065 GFP_KERNEL); 1066 if (!card->rxbd_ring_vbase) { 1067 mwifiex_dbg(adapter, ERROR, 1068 "allocate coherent memory (%d bytes) failed!\n", 1069 card->rxbd_ring_size); 1070 return -ENOMEM; 1071 } 1072 1073 mwifiex_dbg(adapter, DATA, 1074 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1075 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, 1076 (u32)((u64)card->rxbd_ring_pbase >> 32), 1077 card->rxbd_ring_size); 1078 1079 return mwifiex_init_rxq_ring(adapter); 1080 } 1081 1082 /* 1083 * This function deletes Buffer descriptor ring for RX 1084 */ 1085 static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) 1086 { 1087 struct pcie_service_card *card = adapter->card; 1088 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1089 1090 mwifiex_cleanup_rxq_ring(adapter); 1091 1092 if (card->rxbd_ring_vbase) 1093 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, 1094 card->rxbd_ring_vbase, 1095 card->rxbd_ring_pbase); 1096 card->rxbd_ring_size = 0; 1097 card->rxbd_wrptr = 0; 1098 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; 1099 card->rxbd_ring_vbase = NULL; 1100 card->rxbd_ring_pbase = 0; 1101 1102 return 0; 1103 } 1104 1105 /* 1106 * This function creates buffer descriptor ring for Events 1107 */ 1108 static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) 1109 { 1110 struct pcie_service_card *card = adapter->card; 1111 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1112 1113 /* 1114 * driver maintaines the read pointer and firmware maintaines the write 1115 * pointer. The write pointer starts at 0 (zero) while the read pointer 1116 * starts at zero with rollover bit set 1117 */ 1118 card->evtbd_wrptr = 0; 1119 card->evtbd_rdptr = reg->evt_rollover_ind; 1120 1121 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * 1122 MWIFIEX_MAX_EVT_BD; 1123 1124 mwifiex_dbg(adapter, INFO, 1125 "info: evtbd_ring: Allocating %d bytes\n", 1126 card->evtbd_ring_size); 1127 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1128 card->evtbd_ring_size, 1129 &card->evtbd_ring_pbase, 1130 GFP_KERNEL); 1131 if (!card->evtbd_ring_vbase) { 1132 mwifiex_dbg(adapter, ERROR, 1133 "allocate coherent memory (%d bytes) failed!\n", 1134 card->evtbd_ring_size); 1135 return -ENOMEM; 1136 } 1137 1138 mwifiex_dbg(adapter, EVENT, 1139 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", 1140 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, 1141 (u32)((u64)card->evtbd_ring_pbase >> 32), 1142 card->evtbd_ring_size); 1143 1144 return mwifiex_pcie_init_evt_ring(adapter); 1145 } 1146 1147 /* 1148 * This function deletes Buffer descriptor ring for Events 1149 */ 1150 static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) 1151 { 1152 struct pcie_service_card *card = adapter->card; 1153 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1154 1155 mwifiex_cleanup_evt_ring(adapter); 1156 1157 if (card->evtbd_ring_vbase) 1158 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, 1159 card->evtbd_ring_vbase, 1160 card->evtbd_ring_pbase); 1161 card->evtbd_wrptr = 0; 1162 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; 1163 card->evtbd_ring_size = 0; 1164 card->evtbd_ring_vbase = NULL; 1165 card->evtbd_ring_pbase = 0; 1166 1167 return 0; 1168 } 1169 1170 /* 1171 * This function allocates a buffer for CMDRSP 1172 */ 1173 static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) 1174 { 1175 struct pcie_service_card *card = adapter->card; 1176 struct sk_buff *skb; 1177 1178 /* Allocate memory for receiving command response data */ 1179 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 1180 if (!skb) { 1181 mwifiex_dbg(adapter, ERROR, 1182 "Unable to allocate skb for command response data.\n"); 1183 return -ENOMEM; 1184 } 1185 skb_put(skb, MWIFIEX_UPLD_SIZE); 1186 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1187 DMA_FROM_DEVICE)) { 1188 kfree_skb(skb); 1189 return -1; 1190 } 1191 1192 card->cmdrsp_buf = skb; 1193 1194 return 0; 1195 } 1196 1197 /* 1198 * This function deletes a buffer for CMDRSP 1199 */ 1200 static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) 1201 { 1202 struct pcie_service_card *card; 1203 1204 if (!adapter) 1205 return 0; 1206 1207 card = adapter->card; 1208 1209 if (card && card->cmdrsp_buf) { 1210 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, 1211 DMA_FROM_DEVICE); 1212 dev_kfree_skb_any(card->cmdrsp_buf); 1213 card->cmdrsp_buf = NULL; 1214 } 1215 1216 if (card && card->cmd_buf) { 1217 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1218 DMA_TO_DEVICE); 1219 dev_kfree_skb_any(card->cmd_buf); 1220 card->cmd_buf = NULL; 1221 } 1222 return 0; 1223 } 1224 1225 /* 1226 * This function allocates a buffer for sleep cookie 1227 */ 1228 static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1229 { 1230 struct pcie_service_card *card = adapter->card; 1231 u32 tmp; 1232 1233 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, 1234 sizeof(u32), 1235 &card->sleep_cookie_pbase, 1236 GFP_KERNEL); 1237 if (!card->sleep_cookie_vbase) { 1238 mwifiex_dbg(adapter, ERROR, 1239 "dma_alloc_coherent failed!\n"); 1240 return -ENOMEM; 1241 } 1242 /* Init val of Sleep Cookie */ 1243 tmp = FW_AWAKE_COOKIE; 1244 put_unaligned(tmp, card->sleep_cookie_vbase); 1245 1246 mwifiex_dbg(adapter, INFO, 1247 "alloc_scook: sleep cookie=0x%x\n", 1248 get_unaligned(card->sleep_cookie_vbase)); 1249 1250 return 0; 1251 } 1252 1253 /* 1254 * This function deletes buffer for sleep cookie 1255 */ 1256 static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1257 { 1258 struct pcie_service_card *card; 1259 1260 if (!adapter) 1261 return 0; 1262 1263 card = adapter->card; 1264 1265 if (card && card->sleep_cookie_vbase) { 1266 dma_free_coherent(&card->dev->dev, sizeof(u32), 1267 card->sleep_cookie_vbase, 1268 card->sleep_cookie_pbase); 1269 card->sleep_cookie_vbase = NULL; 1270 } 1271 1272 return 0; 1273 } 1274 1275 /* This function flushes the TX buffer descriptor ring 1276 * This function defined as handler is also called while cleaning TXRX 1277 * during disconnect/ bss stop. 1278 */ 1279 static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) 1280 { 1281 struct pcie_service_card *card = adapter->card; 1282 1283 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { 1284 card->txbd_flush = 1; 1285 /* write pointer already set at last send 1286 * send dnld-rdy intr again, wait for completion. 1287 */ 1288 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1289 CPU_INTR_DNLD_RDY)) { 1290 mwifiex_dbg(adapter, ERROR, 1291 "failed to assert dnld-rdy interrupt.\n"); 1292 return -1; 1293 } 1294 } 1295 return 0; 1296 } 1297 1298 /* 1299 * This function unmaps and frees downloaded data buffer 1300 */ 1301 static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) 1302 { 1303 struct sk_buff *skb; 1304 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; 1305 struct mwifiex_pcie_buf_desc *desc; 1306 struct mwifiex_pfu_buf_desc *desc2; 1307 struct pcie_service_card *card = adapter->card; 1308 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1309 1310 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1311 mwifiex_pm_wakeup_card(adapter); 1312 1313 /* Read the TX ring read pointer set by firmware */ 1314 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { 1315 mwifiex_dbg(adapter, ERROR, 1316 "SEND COMP: failed to read reg->tx_rdptr\n"); 1317 return -1; 1318 } 1319 1320 mwifiex_dbg(adapter, DATA, 1321 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", 1322 card->txbd_rdptr, rdptr); 1323 1324 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1325 /* free from previous txbd_rdptr to current txbd_rdptr */ 1326 while (((card->txbd_rdptr & reg->tx_mask) != 1327 (rdptr & reg->tx_mask)) || 1328 ((card->txbd_rdptr & reg->tx_rollover_ind) != 1329 (rdptr & reg->tx_rollover_ind))) { 1330 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> 1331 reg->tx_start_ptr; 1332 1333 skb = card->tx_buf_list[wrdoneidx]; 1334 1335 if (skb) { 1336 mwifiex_dbg(adapter, DATA, 1337 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", 1338 skb, wrdoneidx); 1339 mwifiex_unmap_pci_memory(adapter, skb, 1340 DMA_TO_DEVICE); 1341 1342 unmap_count++; 1343 1344 if (card->txbd_flush) 1345 mwifiex_write_data_complete(adapter, skb, 0, 1346 -1); 1347 else 1348 mwifiex_write_data_complete(adapter, skb, 0, 0); 1349 atomic_dec(&adapter->tx_hw_pending); 1350 } 1351 1352 card->tx_buf_list[wrdoneidx] = NULL; 1353 1354 if (reg->pfu_enabled) { 1355 desc2 = card->txbd_ring[wrdoneidx]; 1356 memset(desc2, 0, sizeof(*desc2)); 1357 } else { 1358 desc = card->txbd_ring[wrdoneidx]; 1359 memset(desc, 0, sizeof(*desc)); 1360 } 1361 switch (card->dev->device) { 1362 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1363 card->txbd_rdptr++; 1364 break; 1365 case PCIE_DEVICE_ID_MARVELL_88W8897: 1366 case PCIE_DEVICE_ID_MARVELL_88W8997: 1367 card->txbd_rdptr += reg->ring_tx_start_ptr; 1368 break; 1369 } 1370 1371 1372 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) 1373 card->txbd_rdptr = ((card->txbd_rdptr & 1374 reg->tx_rollover_ind) ^ 1375 reg->tx_rollover_ind); 1376 } 1377 1378 if (unmap_count) 1379 adapter->data_sent = false; 1380 1381 if (card->txbd_flush) { 1382 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) 1383 card->txbd_flush = 0; 1384 else 1385 mwifiex_clean_pcie_ring_buf(adapter); 1386 } 1387 1388 return 0; 1389 } 1390 1391 /* This function sends data buffer to device. First 4 bytes of payload 1392 * are filled with payload length and payload type. Then this payload 1393 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. 1394 * Download ready interrupt to FW is deffered if Tx ring is not full and 1395 * additional payload can be accomodated. 1396 * Caller must ensure tx_param parameter to this function is not NULL. 1397 */ 1398 static int 1399 mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, 1400 struct mwifiex_tx_param *tx_param) 1401 { 1402 struct pcie_service_card *card = adapter->card; 1403 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1404 u32 wrindx, num_tx_buffs, rx_val; 1405 int ret; 1406 dma_addr_t buf_pa; 1407 struct mwifiex_pcie_buf_desc *desc = NULL; 1408 struct mwifiex_pfu_buf_desc *desc2 = NULL; 1409 1410 if (!(skb->data && skb->len)) { 1411 mwifiex_dbg(adapter, ERROR, 1412 "%s(): invalid parameter <%p, %#x>\n", 1413 __func__, skb->data, skb->len); 1414 return -1; 1415 } 1416 1417 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1418 mwifiex_pm_wakeup_card(adapter); 1419 1420 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1421 mwifiex_dbg(adapter, DATA, 1422 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", 1423 card->txbd_rdptr, card->txbd_wrptr); 1424 if (mwifiex_pcie_txbd_not_full(card)) { 1425 u8 *payload; 1426 1427 adapter->data_sent = true; 1428 payload = skb->data; 1429 put_unaligned_le16((u16)skb->len, payload + 0); 1430 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); 1431 1432 if (mwifiex_map_pci_memory(adapter, skb, skb->len, 1433 DMA_TO_DEVICE)) 1434 return -1; 1435 1436 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; 1437 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1438 card->tx_buf_list[wrindx] = skb; 1439 atomic_inc(&adapter->tx_hw_pending); 1440 1441 if (reg->pfu_enabled) { 1442 desc2 = card->txbd_ring[wrindx]; 1443 desc2->paddr = buf_pa; 1444 desc2->len = (u16)skb->len; 1445 desc2->frag_len = (u16)skb->len; 1446 desc2->offset = 0; 1447 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1448 MWIFIEX_BD_FLAG_LAST_DESC; 1449 } else { 1450 desc = card->txbd_ring[wrindx]; 1451 desc->paddr = buf_pa; 1452 desc->len = (u16)skb->len; 1453 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1454 MWIFIEX_BD_FLAG_LAST_DESC; 1455 } 1456 1457 switch (card->dev->device) { 1458 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1459 card->txbd_wrptr++; 1460 break; 1461 case PCIE_DEVICE_ID_MARVELL_88W8897: 1462 case PCIE_DEVICE_ID_MARVELL_88W8997: 1463 card->txbd_wrptr += reg->ring_tx_start_ptr; 1464 break; 1465 } 1466 1467 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) 1468 card->txbd_wrptr = ((card->txbd_wrptr & 1469 reg->tx_rollover_ind) ^ 1470 reg->tx_rollover_ind); 1471 1472 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; 1473 /* Write the TX ring write pointer in to reg->tx_wrptr */ 1474 if (mwifiex_write_reg(adapter, reg->tx_wrptr, 1475 card->txbd_wrptr | rx_val)) { 1476 mwifiex_dbg(adapter, ERROR, 1477 "SEND DATA: failed to write reg->tx_wrptr\n"); 1478 ret = -1; 1479 goto done_unmap; 1480 } 1481 if ((mwifiex_pcie_txbd_not_full(card)) && 1482 tx_param->next_pkt_len) { 1483 /* have more packets and TxBD still can hold more */ 1484 mwifiex_dbg(adapter, DATA, 1485 "SEND DATA: delay dnld-rdy interrupt.\n"); 1486 adapter->data_sent = false; 1487 } else { 1488 /* Send the TX ready interrupt */ 1489 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1490 CPU_INTR_DNLD_RDY)) { 1491 mwifiex_dbg(adapter, ERROR, 1492 "SEND DATA: failed to assert dnld-rdy interrupt.\n"); 1493 ret = -1; 1494 goto done_unmap; 1495 } 1496 } 1497 mwifiex_dbg(adapter, DATA, 1498 "info: SEND DATA: Updated <Rd: %#x, Wr:\t" 1499 "%#x> and sent packet to firmware successfully\n", 1500 card->txbd_rdptr, card->txbd_wrptr); 1501 } else { 1502 mwifiex_dbg(adapter, DATA, 1503 "info: TX Ring full, can't send packets to fw\n"); 1504 adapter->data_sent = true; 1505 /* Send the TX ready interrupt */ 1506 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1507 CPU_INTR_DNLD_RDY)) 1508 mwifiex_dbg(adapter, ERROR, 1509 "SEND DATA: failed to assert door-bell intr\n"); 1510 return -EBUSY; 1511 } 1512 1513 return -EINPROGRESS; 1514 done_unmap: 1515 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1516 card->tx_buf_list[wrindx] = NULL; 1517 atomic_dec(&adapter->tx_hw_pending); 1518 if (reg->pfu_enabled) 1519 memset(desc2, 0, sizeof(*desc2)); 1520 else 1521 memset(desc, 0, sizeof(*desc)); 1522 1523 return ret; 1524 } 1525 1526 /* 1527 * This function handles received buffer ring and 1528 * dispatches packets to upper 1529 */ 1530 static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) 1531 { 1532 struct pcie_service_card *card = adapter->card; 1533 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1534 u32 wrptr, rd_index, tx_val; 1535 dma_addr_t buf_pa; 1536 int ret = 0; 1537 struct sk_buff *skb_tmp = NULL; 1538 struct mwifiex_pcie_buf_desc *desc; 1539 struct mwifiex_pfu_buf_desc *desc2; 1540 1541 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1542 mwifiex_pm_wakeup_card(adapter); 1543 1544 /* Read the RX ring Write pointer set by firmware */ 1545 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1546 mwifiex_dbg(adapter, ERROR, 1547 "RECV DATA: failed to read reg->rx_wrptr\n"); 1548 ret = -1; 1549 goto done; 1550 } 1551 card->rxbd_wrptr = wrptr; 1552 1553 while (((wrptr & reg->rx_mask) != 1554 (card->rxbd_rdptr & reg->rx_mask)) || 1555 ((wrptr & reg->rx_rollover_ind) == 1556 (card->rxbd_rdptr & reg->rx_rollover_ind))) { 1557 struct sk_buff *skb_data; 1558 u16 rx_len; 1559 1560 rd_index = card->rxbd_rdptr & reg->rx_mask; 1561 skb_data = card->rx_buf_list[rd_index]; 1562 1563 /* If skb allocation was failed earlier for Rx packet, 1564 * rx_buf_list[rd_index] would have been left with a NULL. 1565 */ 1566 if (!skb_data) 1567 return -ENOMEM; 1568 1569 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); 1570 card->rx_buf_list[rd_index] = NULL; 1571 1572 /* Get data length from interface header - 1573 * first 2 bytes for len, next 2 bytes is for type 1574 */ 1575 rx_len = get_unaligned_le16(skb_data->data); 1576 if (WARN_ON(rx_len <= adapter->intf_hdr_len || 1577 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) { 1578 mwifiex_dbg(adapter, ERROR, 1579 "Invalid RX len %d, Rd=%#x, Wr=%#x\n", 1580 rx_len, card->rxbd_rdptr, wrptr); 1581 dev_kfree_skb_any(skb_data); 1582 } else { 1583 skb_put(skb_data, rx_len); 1584 mwifiex_dbg(adapter, DATA, 1585 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", 1586 card->rxbd_rdptr, wrptr, rx_len); 1587 skb_pull(skb_data, adapter->intf_hdr_len); 1588 if (adapter->rx_work_enabled) { 1589 skb_queue_tail(&adapter->rx_data_q, skb_data); 1590 adapter->data_received = true; 1591 atomic_inc(&adapter->rx_pending); 1592 } else { 1593 mwifiex_handle_rx_packet(adapter, skb_data); 1594 } 1595 } 1596 1597 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 1598 GFP_KERNEL); 1599 if (!skb_tmp) { 1600 mwifiex_dbg(adapter, ERROR, 1601 "Unable to allocate skb.\n"); 1602 return -ENOMEM; 1603 } 1604 1605 if (mwifiex_map_pci_memory(adapter, skb_tmp, 1606 MWIFIEX_RX_DATA_BUF_SIZE, 1607 DMA_FROM_DEVICE)) 1608 return -1; 1609 1610 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); 1611 1612 mwifiex_dbg(adapter, INFO, 1613 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", 1614 skb_tmp, rd_index); 1615 card->rx_buf_list[rd_index] = skb_tmp; 1616 1617 if (reg->pfu_enabled) { 1618 desc2 = card->rxbd_ring[rd_index]; 1619 desc2->paddr = buf_pa; 1620 desc2->len = skb_tmp->len; 1621 desc2->frag_len = skb_tmp->len; 1622 desc2->offset = 0; 1623 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; 1624 } else { 1625 desc = card->rxbd_ring[rd_index]; 1626 desc->paddr = buf_pa; 1627 desc->len = skb_tmp->len; 1628 desc->flags = 0; 1629 } 1630 1631 if ((++card->rxbd_rdptr & reg->rx_mask) == 1632 MWIFIEX_MAX_TXRX_BD) { 1633 card->rxbd_rdptr = ((card->rxbd_rdptr & 1634 reg->rx_rollover_ind) ^ 1635 reg->rx_rollover_ind); 1636 } 1637 mwifiex_dbg(adapter, DATA, 1638 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", 1639 card->rxbd_rdptr, wrptr); 1640 1641 tx_val = card->txbd_wrptr & reg->tx_wrap_mask; 1642 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1643 if (mwifiex_write_reg(adapter, reg->rx_rdptr, 1644 card->rxbd_rdptr | tx_val)) { 1645 mwifiex_dbg(adapter, DATA, 1646 "RECV DATA: failed to write reg->rx_rdptr\n"); 1647 ret = -1; 1648 goto done; 1649 } 1650 1651 /* Read the RX ring Write pointer set by firmware */ 1652 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1653 mwifiex_dbg(adapter, ERROR, 1654 "RECV DATA: failed to read reg->rx_wrptr\n"); 1655 ret = -1; 1656 goto done; 1657 } 1658 mwifiex_dbg(adapter, DATA, 1659 "info: RECV DATA: Rcvd packet from fw successfully\n"); 1660 card->rxbd_wrptr = wrptr; 1661 } 1662 1663 done: 1664 return ret; 1665 } 1666 1667 /* 1668 * This function downloads the boot command to device 1669 */ 1670 static int 1671 mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1672 { 1673 dma_addr_t buf_pa; 1674 struct pcie_service_card *card = adapter->card; 1675 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1676 1677 if (!(skb->data && skb->len)) { 1678 mwifiex_dbg(adapter, ERROR, 1679 "Invalid parameter in %s <%p. len %d>\n", 1680 __func__, skb->data, skb->len); 1681 return -1; 1682 } 1683 1684 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1685 return -1; 1686 1687 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1688 1689 /* Write the lower 32bits of the physical address to low command 1690 * address scratch register 1691 */ 1692 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { 1693 mwifiex_dbg(adapter, ERROR, 1694 "%s: failed to write download command to boot code.\n", 1695 __func__); 1696 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1697 return -1; 1698 } 1699 1700 /* Write the upper 32bits of the physical address to high command 1701 * address scratch register 1702 */ 1703 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1704 (u32)((u64)buf_pa >> 32))) { 1705 mwifiex_dbg(adapter, ERROR, 1706 "%s: failed to write download command to boot code.\n", 1707 __func__); 1708 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1709 return -1; 1710 } 1711 1712 /* Write the command length to cmd_size scratch register */ 1713 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { 1714 mwifiex_dbg(adapter, ERROR, 1715 "%s: failed to write command len to cmd_size scratch reg\n", 1716 __func__); 1717 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1718 return -1; 1719 } 1720 1721 /* Ring the door bell */ 1722 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1723 CPU_INTR_DOOR_BELL)) { 1724 mwifiex_dbg(adapter, ERROR, 1725 "%s: failed to assert door-bell intr\n", __func__); 1726 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1727 return -1; 1728 } 1729 1730 return 0; 1731 } 1732 1733 /* This function init rx port in firmware which in turn enables to receive data 1734 * from device before transmitting any packet. 1735 */ 1736 static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) 1737 { 1738 struct pcie_service_card *card = adapter->card; 1739 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1740 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; 1741 1742 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1743 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | 1744 tx_wrap)) { 1745 mwifiex_dbg(adapter, ERROR, 1746 "RECV DATA: failed to write reg->rx_rdptr\n"); 1747 return -1; 1748 } 1749 return 0; 1750 } 1751 1752 /* This function downloads commands to the device 1753 */ 1754 static int 1755 mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1756 { 1757 struct pcie_service_card *card = adapter->card; 1758 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1759 int ret = 0; 1760 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; 1761 u8 *payload = (u8 *)skb->data; 1762 1763 if (!(skb->data && skb->len)) { 1764 mwifiex_dbg(adapter, ERROR, 1765 "Invalid parameter in %s <%p, %#x>\n", 1766 __func__, skb->data, skb->len); 1767 return -1; 1768 } 1769 1770 /* Make sure a command response buffer is available */ 1771 if (!card->cmdrsp_buf) { 1772 mwifiex_dbg(adapter, ERROR, 1773 "No response buffer available, send command failed\n"); 1774 return -EBUSY; 1775 } 1776 1777 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1778 mwifiex_pm_wakeup_card(adapter); 1779 1780 adapter->cmd_sent = true; 1781 1782 put_unaligned_le16((u16)skb->len, &payload[0]); 1783 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); 1784 1785 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1786 return -1; 1787 1788 card->cmd_buf = skb; 1789 /* 1790 * Need to keep a reference, since core driver might free up this 1791 * buffer before we've unmapped it. 1792 */ 1793 skb_get(skb); 1794 1795 /* To send a command, the driver will: 1796 1. Write the 64bit physical address of the data buffer to 1797 cmd response address low + cmd response address high 1798 2. Ring the door bell (i.e. set the door bell interrupt) 1799 1800 In response to door bell interrupt, the firmware will perform 1801 the DMA of the command packet (first header to obtain the total 1802 length and then rest of the command). 1803 */ 1804 1805 if (card->cmdrsp_buf) { 1806 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); 1807 /* Write the lower 32bits of the cmdrsp buffer physical 1808 address */ 1809 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 1810 (u32)cmdrsp_buf_pa)) { 1811 mwifiex_dbg(adapter, ERROR, 1812 "Failed to write download cmd to boot code.\n"); 1813 ret = -1; 1814 goto done; 1815 } 1816 /* Write the upper 32bits of the cmdrsp buffer physical 1817 address */ 1818 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 1819 (u32)((u64)cmdrsp_buf_pa >> 32))) { 1820 mwifiex_dbg(adapter, ERROR, 1821 "Failed to write download cmd to boot code.\n"); 1822 ret = -1; 1823 goto done; 1824 } 1825 } 1826 1827 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); 1828 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ 1829 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, 1830 (u32)cmd_buf_pa)) { 1831 mwifiex_dbg(adapter, ERROR, 1832 "Failed to write download cmd to boot code.\n"); 1833 ret = -1; 1834 goto done; 1835 } 1836 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ 1837 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1838 (u32)((u64)cmd_buf_pa >> 32))) { 1839 mwifiex_dbg(adapter, ERROR, 1840 "Failed to write download cmd to boot code.\n"); 1841 ret = -1; 1842 goto done; 1843 } 1844 1845 /* Write the command length to reg->cmd_size */ 1846 if (mwifiex_write_reg(adapter, reg->cmd_size, 1847 card->cmd_buf->len)) { 1848 mwifiex_dbg(adapter, ERROR, 1849 "Failed to write cmd len to reg->cmd_size\n"); 1850 ret = -1; 1851 goto done; 1852 } 1853 1854 /* Ring the door bell */ 1855 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1856 CPU_INTR_DOOR_BELL)) { 1857 mwifiex_dbg(adapter, ERROR, 1858 "Failed to assert door-bell intr\n"); 1859 ret = -1; 1860 goto done; 1861 } 1862 1863 done: 1864 if (ret) 1865 adapter->cmd_sent = false; 1866 1867 return 0; 1868 } 1869 1870 /* 1871 * This function handles command complete interrupt 1872 */ 1873 static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) 1874 { 1875 struct pcie_service_card *card = adapter->card; 1876 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1877 struct sk_buff *skb = card->cmdrsp_buf; 1878 int count = 0; 1879 u16 rx_len; 1880 1881 mwifiex_dbg(adapter, CMD, 1882 "info: Rx CMD Response\n"); 1883 1884 if (adapter->curr_cmd) 1885 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); 1886 else 1887 dma_sync_single_for_cpu(&card->dev->dev, 1888 MWIFIEX_SKB_DMA_ADDR(skb), 1889 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); 1890 1891 /* Unmap the command as a response has been received. */ 1892 if (card->cmd_buf) { 1893 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1894 DMA_TO_DEVICE); 1895 dev_kfree_skb_any(card->cmd_buf); 1896 card->cmd_buf = NULL; 1897 } 1898 1899 rx_len = get_unaligned_le16(skb->data); 1900 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 1901 skb_trim(skb, rx_len); 1902 1903 if (!adapter->curr_cmd) { 1904 if (adapter->ps_state == PS_STATE_SLEEP_CFM) { 1905 dma_sync_single_for_device(&card->dev->dev, 1906 MWIFIEX_SKB_DMA_ADDR(skb), 1907 MWIFIEX_SLEEP_COOKIE_SIZE, 1908 DMA_FROM_DEVICE); 1909 if (mwifiex_write_reg(adapter, 1910 PCIE_CPU_INT_EVENT, 1911 CPU_INTR_SLEEP_CFM_DONE)) { 1912 mwifiex_dbg(adapter, ERROR, 1913 "Write register failed\n"); 1914 return -1; 1915 } 1916 mwifiex_delay_for_sleep_cookie(adapter, 1917 MWIFIEX_MAX_DELAY_COUNT); 1918 mwifiex_unmap_pci_memory(adapter, skb, 1919 DMA_FROM_DEVICE); 1920 skb_pull(skb, adapter->intf_hdr_len); 1921 while (reg->sleep_cookie && (count++ < 10) && 1922 mwifiex_pcie_ok_to_access_hw(adapter)) 1923 usleep_range(50, 60); 1924 mwifiex_pcie_enable_host_int(adapter); 1925 mwifiex_process_sleep_confirm_resp(adapter, skb->data, 1926 skb->len); 1927 } else { 1928 mwifiex_dbg(adapter, ERROR, 1929 "There is no command but got cmdrsp\n"); 1930 } 1931 memcpy(adapter->upld_buf, skb->data, 1932 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); 1933 skb_push(skb, adapter->intf_hdr_len); 1934 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1935 DMA_FROM_DEVICE)) 1936 return -1; 1937 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { 1938 skb_pull(skb, adapter->intf_hdr_len); 1939 adapter->curr_cmd->resp_skb = skb; 1940 adapter->cmd_resp_received = true; 1941 /* Take the pointer and set it to CMD node and will 1942 return in the response complete callback */ 1943 card->cmdrsp_buf = NULL; 1944 1945 /* Clear the cmd-rsp buffer address in scratch registers. This 1946 will prevent firmware from writing to the same response 1947 buffer again. */ 1948 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { 1949 mwifiex_dbg(adapter, ERROR, 1950 "cmd_done: failed to clear cmd_rsp_addr_lo\n"); 1951 return -1; 1952 } 1953 /* Write the upper 32bits of the cmdrsp buffer physical 1954 address */ 1955 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { 1956 mwifiex_dbg(adapter, ERROR, 1957 "cmd_done: failed to clear cmd_rsp_addr_hi\n"); 1958 return -1; 1959 } 1960 } 1961 1962 return 0; 1963 } 1964 1965 /* 1966 * Command Response processing complete handler 1967 */ 1968 static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, 1969 struct sk_buff *skb) 1970 { 1971 struct pcie_service_card *card = adapter->card; 1972 1973 if (skb) { 1974 card->cmdrsp_buf = skb; 1975 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); 1976 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1977 DMA_FROM_DEVICE)) 1978 return -1; 1979 } 1980 1981 return 0; 1982 } 1983 1984 /* 1985 * This function handles firmware event ready interrupt 1986 */ 1987 static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) 1988 { 1989 struct pcie_service_card *card = adapter->card; 1990 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1991 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 1992 u32 wrptr, event; 1993 struct mwifiex_evt_buf_desc *desc; 1994 1995 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1996 mwifiex_pm_wakeup_card(adapter); 1997 1998 if (adapter->event_received) { 1999 mwifiex_dbg(adapter, EVENT, 2000 "info: Event being processed,\t" 2001 "do not process this interrupt just yet\n"); 2002 return 0; 2003 } 2004 2005 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2006 mwifiex_dbg(adapter, ERROR, 2007 "info: Invalid read pointer...\n"); 2008 return -1; 2009 } 2010 2011 /* Read the event ring write pointer set by firmware */ 2012 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2013 mwifiex_dbg(adapter, ERROR, 2014 "EventReady: failed to read reg->evt_wrptr\n"); 2015 return -1; 2016 } 2017 2018 mwifiex_dbg(adapter, EVENT, 2019 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", 2020 card->evtbd_rdptr, wrptr); 2021 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr 2022 & MWIFIEX_EVTBD_MASK)) || 2023 ((wrptr & reg->evt_rollover_ind) == 2024 (card->evtbd_rdptr & reg->evt_rollover_ind))) { 2025 struct sk_buff *skb_cmd; 2026 __le16 data_len = 0; 2027 u16 evt_len; 2028 2029 mwifiex_dbg(adapter, INFO, 2030 "info: Read Index: %d\n", rdptr); 2031 skb_cmd = card->evt_buf_list[rdptr]; 2032 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); 2033 2034 /* Take the pointer and set it to event pointer in adapter 2035 and will return back after event handling callback */ 2036 card->evt_buf_list[rdptr] = NULL; 2037 desc = card->evtbd_ring[rdptr]; 2038 memset(desc, 0, sizeof(*desc)); 2039 2040 event = get_unaligned_le32( 2041 &skb_cmd->data[adapter->intf_hdr_len]); 2042 adapter->event_cause = event; 2043 /* The first 4bytes will be the event transfer header 2044 len is 2 bytes followed by type which is 2 bytes */ 2045 memcpy(&data_len, skb_cmd->data, sizeof(__le16)); 2046 evt_len = le16_to_cpu(data_len); 2047 skb_trim(skb_cmd, evt_len); 2048 skb_pull(skb_cmd, adapter->intf_hdr_len); 2049 mwifiex_dbg(adapter, EVENT, 2050 "info: Event length: %d\n", evt_len); 2051 2052 if (evt_len > MWIFIEX_EVENT_HEADER_LEN && 2053 evt_len < MAX_EVENT_SIZE) 2054 memcpy(adapter->event_body, skb_cmd->data + 2055 MWIFIEX_EVENT_HEADER_LEN, evt_len - 2056 MWIFIEX_EVENT_HEADER_LEN); 2057 2058 adapter->event_received = true; 2059 adapter->event_skb = skb_cmd; 2060 2061 /* Do not update the event read pointer here, wait till the 2062 buffer is released. This is just to make things simpler, 2063 we need to find a better method of managing these buffers. 2064 */ 2065 } else { 2066 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 2067 CPU_INTR_EVENT_DONE)) { 2068 mwifiex_dbg(adapter, ERROR, 2069 "Write register failed\n"); 2070 return -1; 2071 } 2072 } 2073 2074 return 0; 2075 } 2076 2077 /* 2078 * Event processing complete handler 2079 */ 2080 static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, 2081 struct sk_buff *skb) 2082 { 2083 struct pcie_service_card *card = adapter->card; 2084 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2085 int ret = 0; 2086 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 2087 u32 wrptr; 2088 struct mwifiex_evt_buf_desc *desc; 2089 2090 if (!skb) 2091 return 0; 2092 2093 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2094 mwifiex_dbg(adapter, ERROR, 2095 "event_complete: Invalid rdptr 0x%x\n", 2096 rdptr); 2097 return -EINVAL; 2098 } 2099 2100 /* Read the event ring write pointer set by firmware */ 2101 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2102 mwifiex_dbg(adapter, ERROR, 2103 "event_complete: failed to read reg->evt_wrptr\n"); 2104 return -1; 2105 } 2106 2107 if (!card->evt_buf_list[rdptr]) { 2108 skb_push(skb, adapter->intf_hdr_len); 2109 skb_put(skb, MAX_EVENT_SIZE - skb->len); 2110 if (mwifiex_map_pci_memory(adapter, skb, 2111 MAX_EVENT_SIZE, 2112 DMA_FROM_DEVICE)) 2113 return -1; 2114 card->evt_buf_list[rdptr] = skb; 2115 desc = card->evtbd_ring[rdptr]; 2116 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); 2117 desc->len = (u16)skb->len; 2118 desc->flags = 0; 2119 skb = NULL; 2120 } else { 2121 mwifiex_dbg(adapter, ERROR, 2122 "info: ERROR: buf still valid at index %d, <%p, %p>\n", 2123 rdptr, card->evt_buf_list[rdptr], skb); 2124 } 2125 2126 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { 2127 card->evtbd_rdptr = ((card->evtbd_rdptr & 2128 reg->evt_rollover_ind) ^ 2129 reg->evt_rollover_ind); 2130 } 2131 2132 mwifiex_dbg(adapter, EVENT, 2133 "info: Updated <Rd: 0x%x, Wr: 0x%x>", 2134 card->evtbd_rdptr, wrptr); 2135 2136 /* Write the event ring read pointer in to reg->evt_rdptr */ 2137 if (mwifiex_write_reg(adapter, reg->evt_rdptr, 2138 card->evtbd_rdptr)) { 2139 mwifiex_dbg(adapter, ERROR, 2140 "event_complete: failed to read reg->evt_rdptr\n"); 2141 return -1; 2142 } 2143 2144 mwifiex_dbg(adapter, EVENT, 2145 "info: Check Events Again\n"); 2146 ret = mwifiex_pcie_process_event_ready(adapter); 2147 2148 return ret; 2149 } 2150 2151 /* Combo firmware image is a combination of 2152 * (1) combo crc heaer, start with CMD5 2153 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1. 2154 * (3) wifi image. 2155 * 2156 * This function bypass the header and bluetooth part, return 2157 * the offset of tail wifi-only part. If the image is already wifi-only, 2158 * that is start with CMD1, return 0. 2159 */ 2160 2161 static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter, 2162 const void *firmware, u32 firmware_len) { 2163 const struct mwifiex_fw_data *fwdata; 2164 u32 offset = 0, data_len, dnld_cmd; 2165 int ret = 0; 2166 bool cmd7_before = false, first_cmd = false; 2167 2168 while (1) { 2169 /* Check for integer and buffer overflow */ 2170 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) || 2171 offset + sizeof(fwdata->header) >= firmware_len) { 2172 mwifiex_dbg(adapter, ERROR, 2173 "extract wifi-only fw failure!\n"); 2174 ret = -1; 2175 goto done; 2176 } 2177 2178 fwdata = firmware + offset; 2179 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd); 2180 data_len = le32_to_cpu(fwdata->header.data_length); 2181 2182 /* Skip past header */ 2183 offset += sizeof(fwdata->header); 2184 2185 switch (dnld_cmd) { 2186 case MWIFIEX_FW_DNLD_CMD_1: 2187 if (offset + data_len < data_len) { 2188 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2189 ret = -1; 2190 goto done; 2191 } 2192 2193 /* Image start with cmd1, already wifi-only firmware */ 2194 if (!first_cmd) { 2195 mwifiex_dbg(adapter, MSG, 2196 "input wifi-only firmware\n"); 2197 return 0; 2198 } 2199 2200 if (!cmd7_before) { 2201 mwifiex_dbg(adapter, ERROR, 2202 "no cmd7 before cmd1!\n"); 2203 ret = -1; 2204 goto done; 2205 } 2206 offset += data_len; 2207 break; 2208 case MWIFIEX_FW_DNLD_CMD_5: 2209 first_cmd = true; 2210 /* Check for integer overflow */ 2211 if (offset + data_len < data_len) { 2212 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2213 ret = -1; 2214 goto done; 2215 } 2216 offset += data_len; 2217 break; 2218 case MWIFIEX_FW_DNLD_CMD_6: 2219 first_cmd = true; 2220 /* Check for integer overflow */ 2221 if (offset + data_len < data_len) { 2222 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2223 ret = -1; 2224 goto done; 2225 } 2226 offset += data_len; 2227 if (offset >= firmware_len) { 2228 mwifiex_dbg(adapter, ERROR, 2229 "extract wifi-only fw failure!\n"); 2230 ret = -1; 2231 } else { 2232 ret = offset; 2233 } 2234 goto done; 2235 case MWIFIEX_FW_DNLD_CMD_7: 2236 first_cmd = true; 2237 cmd7_before = true; 2238 break; 2239 default: 2240 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n", 2241 dnld_cmd); 2242 ret = -1; 2243 goto done; 2244 } 2245 } 2246 2247 done: 2248 return ret; 2249 } 2250 2251 /* 2252 * This function downloads the firmware to the card. 2253 * 2254 * Firmware is downloaded to the card in blocks. Every block download 2255 * is tested for CRC errors, and retried a number of times before 2256 * returning failure. 2257 */ 2258 static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, 2259 struct mwifiex_fw_image *fw) 2260 { 2261 int ret; 2262 u8 *firmware = fw->fw_buf; 2263 u32 firmware_len = fw->fw_len; 2264 u32 offset = 0; 2265 struct sk_buff *skb; 2266 u32 txlen, tx_blocks = 0, tries, len, val; 2267 u32 block_retry_cnt = 0; 2268 struct pcie_service_card *card = adapter->card; 2269 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2270 2271 if (!firmware || !firmware_len) { 2272 mwifiex_dbg(adapter, ERROR, 2273 "No firmware image found! Terminating download\n"); 2274 return -1; 2275 } 2276 2277 mwifiex_dbg(adapter, INFO, 2278 "info: Downloading FW image (%d bytes)\n", 2279 firmware_len); 2280 2281 if (mwifiex_pcie_disable_host_int(adapter)) { 2282 mwifiex_dbg(adapter, ERROR, 2283 "%s: Disabling interrupts failed.\n", __func__); 2284 return -1; 2285 } 2286 2287 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 2288 if (!skb) { 2289 ret = -ENOMEM; 2290 goto done; 2291 } 2292 2293 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val); 2294 if (ret) { 2295 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n"); 2296 goto done; 2297 } 2298 2299 /* PCIE FLR case: extract wifi part from combo firmware*/ 2300 if (val == MWIFIEX_PCIE_FLR_HAPPENS) { 2301 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len); 2302 if (ret < 0) { 2303 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n"); 2304 goto done; 2305 } 2306 offset = ret; 2307 mwifiex_dbg(adapter, MSG, 2308 "info: dnld wifi firmware from %d bytes\n", offset); 2309 } 2310 2311 /* Perform firmware data transfer */ 2312 do { 2313 u32 ireg_intr = 0; 2314 2315 /* More data? */ 2316 if (offset >= firmware_len) 2317 break; 2318 2319 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2320 ret = mwifiex_read_reg(adapter, reg->cmd_size, 2321 &len); 2322 if (ret) { 2323 mwifiex_dbg(adapter, FATAL, 2324 "Failed reading len from boot code\n"); 2325 goto done; 2326 } 2327 if (len) 2328 break; 2329 usleep_range(10, 20); 2330 } 2331 2332 if (!len) { 2333 break; 2334 } else if (len > MWIFIEX_UPLD_SIZE) { 2335 mwifiex_dbg(adapter, ERROR, 2336 "FW download failure @ %d, invalid length %d\n", 2337 offset, len); 2338 ret = -1; 2339 goto done; 2340 } 2341 2342 txlen = len; 2343 2344 if (len & BIT(0)) { 2345 block_retry_cnt++; 2346 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { 2347 mwifiex_dbg(adapter, ERROR, 2348 "FW download failure @ %d, over max\t" 2349 "retry count\n", offset); 2350 ret = -1; 2351 goto done; 2352 } 2353 mwifiex_dbg(adapter, ERROR, 2354 "FW CRC error indicated by the\t" 2355 "helper: len = 0x%04X, txlen = %d\n", 2356 len, txlen); 2357 len &= ~BIT(0); 2358 /* Setting this to 0 to resend from same offset */ 2359 txlen = 0; 2360 } else { 2361 block_retry_cnt = 0; 2362 /* Set blocksize to transfer - checking for 2363 last block */ 2364 if (firmware_len - offset < txlen) 2365 txlen = firmware_len - offset; 2366 2367 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / 2368 card->pcie.blksz_fw_dl; 2369 2370 /* Copy payload to buffer */ 2371 memmove(skb->data, &firmware[offset], txlen); 2372 } 2373 2374 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 2375 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); 2376 2377 /* Send the boot command to device */ 2378 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { 2379 mwifiex_dbg(adapter, ERROR, 2380 "Failed to send firmware download command\n"); 2381 ret = -1; 2382 goto done; 2383 } 2384 2385 /* Wait for the command done interrupt */ 2386 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2387 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, 2388 &ireg_intr)) { 2389 mwifiex_dbg(adapter, ERROR, 2390 "%s: Failed to read\t" 2391 "interrupt status during fw dnld.\n", 2392 __func__); 2393 mwifiex_unmap_pci_memory(adapter, skb, 2394 DMA_TO_DEVICE); 2395 ret = -1; 2396 goto done; 2397 } 2398 if (!(ireg_intr & CPU_INTR_DOOR_BELL)) 2399 break; 2400 usleep_range(10, 20); 2401 } 2402 if (ireg_intr & CPU_INTR_DOOR_BELL) { 2403 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", 2404 __func__); 2405 mwifiex_unmap_pci_memory(adapter, skb, 2406 DMA_TO_DEVICE); 2407 ret = -1; 2408 goto done; 2409 } 2410 2411 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 2412 2413 offset += txlen; 2414 } while (true); 2415 2416 mwifiex_dbg(adapter, MSG, 2417 "info: FW download over, size %d bytes\n", offset); 2418 2419 ret = 0; 2420 2421 done: 2422 dev_kfree_skb_any(skb); 2423 return ret; 2424 } 2425 2426 /* 2427 * This function checks the firmware status in card. 2428 */ 2429 static int 2430 mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) 2431 { 2432 int ret = 0; 2433 u32 firmware_stat; 2434 struct pcie_service_card *card = adapter->card; 2435 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2436 u32 tries; 2437 2438 /* Mask spurios interrupts */ 2439 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, 2440 HOST_INTR_MASK)) { 2441 mwifiex_dbg(adapter, ERROR, 2442 "Write register failed\n"); 2443 return -1; 2444 } 2445 2446 mwifiex_dbg(adapter, INFO, 2447 "Setting driver ready signature\n"); 2448 if (mwifiex_write_reg(adapter, reg->drv_rdy, 2449 FIRMWARE_READY_PCIE)) { 2450 mwifiex_dbg(adapter, ERROR, 2451 "Failed to write driver ready signature\n"); 2452 return -1; 2453 } 2454 2455 /* Wait for firmware initialization event */ 2456 for (tries = 0; tries < poll_num; tries++) { 2457 if (mwifiex_read_reg(adapter, reg->fw_status, 2458 &firmware_stat)) 2459 ret = -1; 2460 else 2461 ret = 0; 2462 2463 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>", 2464 tries, ret, firmware_stat); 2465 2466 if (ret) 2467 continue; 2468 if (firmware_stat == FIRMWARE_READY_PCIE) { 2469 ret = 0; 2470 break; 2471 } else { 2472 msleep(100); 2473 ret = -1; 2474 } 2475 } 2476 2477 return ret; 2478 } 2479 2480 /* This function checks if WLAN is the winner. 2481 */ 2482 static int 2483 mwifiex_check_winner_status(struct mwifiex_adapter *adapter) 2484 { 2485 u32 winner = 0; 2486 int ret = 0; 2487 struct pcie_service_card *card = adapter->card; 2488 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2489 2490 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) { 2491 ret = -1; 2492 } else if (!winner) { 2493 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n"); 2494 adapter->winner = 1; 2495 } else { 2496 mwifiex_dbg(adapter, ERROR, 2497 "PCI-E is not the winner <%#x>", winner); 2498 } 2499 2500 return ret; 2501 } 2502 2503 /* 2504 * This function reads the interrupt status from card. 2505 */ 2506 static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter, 2507 int msg_id) 2508 { 2509 u32 pcie_ireg; 2510 unsigned long flags; 2511 struct pcie_service_card *card = adapter->card; 2512 2513 if (card->msi_enable) { 2514 spin_lock_irqsave(&adapter->int_lock, flags); 2515 adapter->int_status = 1; 2516 spin_unlock_irqrestore(&adapter->int_lock, flags); 2517 return; 2518 } 2519 2520 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 2521 return; 2522 2523 if (card->msix_enable && msg_id >= 0) { 2524 pcie_ireg = BIT(msg_id); 2525 } else { 2526 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2527 &pcie_ireg)) { 2528 mwifiex_dbg(adapter, ERROR, "Read register failed\n"); 2529 return; 2530 } 2531 2532 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) 2533 return; 2534 2535 2536 mwifiex_pcie_disable_host_int(adapter); 2537 2538 /* Clear the pending interrupts */ 2539 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, 2540 ~pcie_ireg)) { 2541 mwifiex_dbg(adapter, ERROR, 2542 "Write register failed\n"); 2543 return; 2544 } 2545 } 2546 2547 if (!adapter->pps_uapsd_mode && 2548 adapter->ps_state == PS_STATE_SLEEP && 2549 mwifiex_pcie_ok_to_access_hw(adapter)) { 2550 /* Potentially for PCIe we could get other 2551 * interrupts like shared. Don't change power 2552 * state until cookie is set 2553 */ 2554 adapter->ps_state = PS_STATE_AWAKE; 2555 adapter->pm_wakeup_fw_try = false; 2556 del_timer(&adapter->wakeup_timer); 2557 } 2558 2559 spin_lock_irqsave(&adapter->int_lock, flags); 2560 adapter->int_status |= pcie_ireg; 2561 spin_unlock_irqrestore(&adapter->int_lock, flags); 2562 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); 2563 } 2564 2565 /* 2566 * Interrupt handler for PCIe root port 2567 * 2568 * This function reads the interrupt status from firmware and assigns 2569 * the main process in workqueue which will handle the interrupt. 2570 */ 2571 static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) 2572 { 2573 struct mwifiex_msix_context *ctx = context; 2574 struct pci_dev *pdev = ctx->dev; 2575 struct pcie_service_card *card; 2576 struct mwifiex_adapter *adapter; 2577 2578 card = pci_get_drvdata(pdev); 2579 2580 if (!card->adapter) { 2581 pr_err("info: %s: card=%p adapter=%p\n", __func__, card, 2582 card ? card->adapter : NULL); 2583 goto exit; 2584 } 2585 adapter = card->adapter; 2586 2587 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags)) 2588 goto exit; 2589 2590 if (card->msix_enable) 2591 mwifiex_interrupt_status(adapter, ctx->msg_id); 2592 else 2593 mwifiex_interrupt_status(adapter, -1); 2594 2595 mwifiex_queue_main_work(adapter); 2596 2597 exit: 2598 return IRQ_HANDLED; 2599 } 2600 2601 /* 2602 * This function checks the current interrupt status. 2603 * 2604 * The following interrupts are checked and handled by this function - 2605 * - Data sent 2606 * - Command sent 2607 * - Command received 2608 * - Packets received 2609 * - Events received 2610 * 2611 * In case of Rx packets received, the packets are uploaded from card to 2612 * host and processed accordingly. 2613 */ 2614 static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) 2615 { 2616 int ret; 2617 u32 pcie_ireg = 0; 2618 unsigned long flags; 2619 struct pcie_service_card *card = adapter->card; 2620 2621 spin_lock_irqsave(&adapter->int_lock, flags); 2622 if (!card->msi_enable) { 2623 /* Clear out unused interrupts */ 2624 pcie_ireg = adapter->int_status; 2625 } 2626 adapter->int_status = 0; 2627 spin_unlock_irqrestore(&adapter->int_lock, flags); 2628 2629 if (card->msi_enable) { 2630 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 2631 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2632 &pcie_ireg)) { 2633 mwifiex_dbg(adapter, ERROR, 2634 "Read register failed\n"); 2635 return -1; 2636 } 2637 2638 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { 2639 if (mwifiex_write_reg(adapter, 2640 PCIE_HOST_INT_STATUS, 2641 ~pcie_ireg)) { 2642 mwifiex_dbg(adapter, ERROR, 2643 "Write register failed\n"); 2644 return -1; 2645 } 2646 if (!adapter->pps_uapsd_mode && 2647 adapter->ps_state == PS_STATE_SLEEP) { 2648 adapter->ps_state = PS_STATE_AWAKE; 2649 adapter->pm_wakeup_fw_try = false; 2650 del_timer(&adapter->wakeup_timer); 2651 } 2652 } 2653 } 2654 } 2655 2656 if (pcie_ireg & HOST_INTR_DNLD_DONE) { 2657 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n"); 2658 ret = mwifiex_pcie_send_data_complete(adapter); 2659 if (ret) 2660 return ret; 2661 } 2662 if (pcie_ireg & HOST_INTR_UPLD_RDY) { 2663 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n"); 2664 ret = mwifiex_pcie_process_recv_data(adapter); 2665 if (ret) 2666 return ret; 2667 } 2668 if (pcie_ireg & HOST_INTR_EVENT_RDY) { 2669 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n"); 2670 ret = mwifiex_pcie_process_event_ready(adapter); 2671 if (ret) 2672 return ret; 2673 } 2674 if (pcie_ireg & HOST_INTR_CMD_DONE) { 2675 if (adapter->cmd_sent) { 2676 mwifiex_dbg(adapter, INTR, 2677 "info: CMD sent Interrupt\n"); 2678 adapter->cmd_sent = false; 2679 } 2680 /* Handle command response */ 2681 ret = mwifiex_pcie_process_cmd_complete(adapter); 2682 if (ret) 2683 return ret; 2684 } 2685 2686 mwifiex_dbg(adapter, INTR, 2687 "info: cmd_sent=%d data_sent=%d\n", 2688 adapter->cmd_sent, adapter->data_sent); 2689 if (!card->msi_enable && !card->msix_enable && 2690 adapter->ps_state != PS_STATE_SLEEP) 2691 mwifiex_pcie_enable_host_int(adapter); 2692 2693 return 0; 2694 } 2695 2696 /* 2697 * This function downloads data from driver to card. 2698 * 2699 * Both commands and data packets are transferred to the card by this 2700 * function. 2701 * 2702 * This function adds the PCIE specific header to the front of the buffer 2703 * before transferring. The header contains the length of the packet and 2704 * the type. The firmware handles the packets based upon this set type. 2705 */ 2706 static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, 2707 struct sk_buff *skb, 2708 struct mwifiex_tx_param *tx_param) 2709 { 2710 if (!skb) { 2711 mwifiex_dbg(adapter, ERROR, 2712 "Passed NULL skb to %s\n", __func__); 2713 return -1; 2714 } 2715 2716 if (type == MWIFIEX_TYPE_DATA) 2717 return mwifiex_pcie_send_data(adapter, skb, tx_param); 2718 else if (type == MWIFIEX_TYPE_CMD) 2719 return mwifiex_pcie_send_cmd(adapter, skb); 2720 2721 return 0; 2722 } 2723 2724 /* Function to dump PCIE scratch registers in case of FW crash 2725 */ 2726 static int 2727 mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf) 2728 { 2729 char *p = drv_buf; 2730 char buf[256], *ptr; 2731 int i; 2732 u32 value; 2733 struct pcie_service_card *card = adapter->card; 2734 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2735 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG, 2736 PCIE_SCRATCH_14_REG, 2737 PCIE_SCRATCH_15_REG}; 2738 2739 if (!p) 2740 return 0; 2741 2742 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n"); 2743 2744 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) { 2745 mwifiex_dbg(adapter, ERROR, "failed to read firmware status"); 2746 return 0; 2747 } 2748 2749 ptr = buf; 2750 mwifiex_dbg(adapter, MSG, "pcie scratch register:"); 2751 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { 2752 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value); 2753 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", 2754 pcie_scratch_reg[i], value); 2755 } 2756 2757 mwifiex_dbg(adapter, MSG, "%s\n", buf); 2758 p += sprintf(p, "%s\n", buf); 2759 2760 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n"); 2761 2762 return p - drv_buf; 2763 } 2764 2765 /* This function read/write firmware */ 2766 static enum rdwr_status 2767 mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag) 2768 { 2769 int ret, tries; 2770 u8 ctrl_data; 2771 u32 fw_status; 2772 struct pcie_service_card *card = adapter->card; 2773 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2774 2775 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) 2776 return RDWR_STATUS_FAILURE; 2777 2778 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2779 reg->fw_dump_host_ready); 2780 if (ret) { 2781 mwifiex_dbg(adapter, ERROR, 2782 "PCIE write err\n"); 2783 return RDWR_STATUS_FAILURE; 2784 } 2785 2786 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2787 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data); 2788 if (ctrl_data == FW_DUMP_DONE) 2789 return RDWR_STATUS_SUCCESS; 2790 if (doneflag && ctrl_data == doneflag) 2791 return RDWR_STATUS_DONE; 2792 if (ctrl_data != reg->fw_dump_host_ready) { 2793 mwifiex_dbg(adapter, WARN, 2794 "The ctrl reg was changed, re-try again!\n"); 2795 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2796 reg->fw_dump_host_ready); 2797 if (ret) { 2798 mwifiex_dbg(adapter, ERROR, 2799 "PCIE write err\n"); 2800 return RDWR_STATUS_FAILURE; 2801 } 2802 } 2803 usleep_range(100, 200); 2804 } 2805 2806 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n"); 2807 return RDWR_STATUS_FAILURE; 2808 } 2809 2810 /* This function dump firmware memory to file */ 2811 static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter) 2812 { 2813 struct pcie_service_card *card = adapter->card; 2814 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; 2815 unsigned int reg, reg_start, reg_end; 2816 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num; 2817 u8 idx, i, read_reg, doneflag = 0; 2818 enum rdwr_status stat; 2819 u32 memory_size; 2820 int ret; 2821 2822 if (!card->pcie.can_dump_fw) 2823 return; 2824 2825 for (idx = 0; idx < adapter->num_mem_types; idx++) { 2826 struct memory_type_mapping *entry = 2827 &adapter->mem_type_mapping_tbl[idx]; 2828 2829 if (entry->mem_ptr) { 2830 vfree(entry->mem_ptr); 2831 entry->mem_ptr = NULL; 2832 } 2833 entry->mem_size = 0; 2834 } 2835 2836 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n"); 2837 2838 /* Read the number of the memories which will dump */ 2839 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2840 if (stat == RDWR_STATUS_FAILURE) 2841 return; 2842 2843 reg = creg->fw_dump_start; 2844 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num); 2845 2846 /* W8997 chipset firmware dump will be restore in single region*/ 2847 if (fw_dump_num == 0) 2848 dump_num = 1; 2849 else 2850 dump_num = fw_dump_num; 2851 2852 /* Read the length of every memory which will dump */ 2853 for (idx = 0; idx < dump_num; idx++) { 2854 struct memory_type_mapping *entry = 2855 &adapter->mem_type_mapping_tbl[idx]; 2856 memory_size = 0; 2857 if (fw_dump_num != 0) { 2858 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2859 if (stat == RDWR_STATUS_FAILURE) 2860 return; 2861 2862 reg = creg->fw_dump_start; 2863 for (i = 0; i < 4; i++) { 2864 mwifiex_read_reg_byte(adapter, reg, &read_reg); 2865 memory_size |= (read_reg << (i * 8)); 2866 reg++; 2867 } 2868 } else { 2869 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE; 2870 } 2871 2872 if (memory_size == 0) { 2873 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n"); 2874 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl, 2875 creg->fw_dump_read_done); 2876 if (ret) { 2877 mwifiex_dbg(adapter, ERROR, "PCIE write err\n"); 2878 return; 2879 } 2880 break; 2881 } 2882 2883 mwifiex_dbg(adapter, DUMP, 2884 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); 2885 entry->mem_ptr = vmalloc(memory_size + 1); 2886 entry->mem_size = memory_size; 2887 if (!entry->mem_ptr) { 2888 mwifiex_dbg(adapter, ERROR, 2889 "Vmalloc %s failed\n", entry->mem_name); 2890 return; 2891 } 2892 dbg_ptr = entry->mem_ptr; 2893 end_ptr = dbg_ptr + memory_size; 2894 2895 doneflag = entry->done_flag; 2896 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n", 2897 entry->mem_name); 2898 2899 do { 2900 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2901 if (RDWR_STATUS_FAILURE == stat) 2902 return; 2903 2904 reg_start = creg->fw_dump_start; 2905 reg_end = creg->fw_dump_end; 2906 for (reg = reg_start; reg <= reg_end; reg++) { 2907 mwifiex_read_reg_byte(adapter, reg, dbg_ptr); 2908 if (dbg_ptr < end_ptr) { 2909 dbg_ptr++; 2910 continue; 2911 } 2912 mwifiex_dbg(adapter, ERROR, 2913 "pre-allocated buf not enough\n"); 2914 tmp_ptr = 2915 vzalloc(memory_size + MWIFIEX_SIZE_4K); 2916 if (!tmp_ptr) 2917 return; 2918 memcpy(tmp_ptr, entry->mem_ptr, memory_size); 2919 vfree(entry->mem_ptr); 2920 entry->mem_ptr = tmp_ptr; 2921 tmp_ptr = NULL; 2922 dbg_ptr = entry->mem_ptr + memory_size; 2923 memory_size += MWIFIEX_SIZE_4K; 2924 end_ptr = entry->mem_ptr + memory_size; 2925 } 2926 2927 if (stat != RDWR_STATUS_DONE) 2928 continue; 2929 2930 mwifiex_dbg(adapter, DUMP, 2931 "%s done: size=0x%tx\n", 2932 entry->mem_name, dbg_ptr - entry->mem_ptr); 2933 break; 2934 } while (true); 2935 } 2936 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n"); 2937 } 2938 2939 static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter) 2940 { 2941 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE); 2942 if (!adapter->devdump_data) { 2943 mwifiex_dbg(adapter, ERROR, 2944 "vzalloc devdump data failure!\n"); 2945 return; 2946 } 2947 2948 mwifiex_drv_info_dump(adapter); 2949 mwifiex_pcie_fw_dump(adapter); 2950 mwifiex_prepare_fw_dump_info(adapter); 2951 mwifiex_upload_device_dump(adapter); 2952 } 2953 2954 static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter) 2955 { 2956 struct pcie_service_card *card = adapter->card; 2957 2958 /* We can't afford to wait here; remove() might be waiting on us. If we 2959 * can't grab the device lock, maybe we'll get another chance later. 2960 */ 2961 pci_try_reset_function(card->dev); 2962 } 2963 2964 static void mwifiex_pcie_work(struct work_struct *work) 2965 { 2966 struct pcie_service_card *card = 2967 container_of(work, struct pcie_service_card, work); 2968 2969 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2970 &card->work_flags)) 2971 mwifiex_pcie_device_dump_work(card->adapter); 2972 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, 2973 &card->work_flags)) 2974 mwifiex_pcie_card_reset_work(card->adapter); 2975 } 2976 2977 /* This function dumps FW information */ 2978 static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter) 2979 { 2980 struct pcie_service_card *card = adapter->card; 2981 2982 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2983 &card->work_flags)) 2984 schedule_work(&card->work); 2985 } 2986 2987 static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter) 2988 { 2989 struct pcie_service_card *card = adapter->card; 2990 2991 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags)) 2992 schedule_work(&card->work); 2993 } 2994 2995 static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter) 2996 { 2997 struct pcie_service_card *card = adapter->card; 2998 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2999 int ret; 3000 3001 card->cmdrsp_buf = NULL; 3002 ret = mwifiex_pcie_create_txbd_ring(adapter); 3003 if (ret) { 3004 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n"); 3005 goto err_cre_txbd; 3006 } 3007 3008 ret = mwifiex_pcie_create_rxbd_ring(adapter); 3009 if (ret) { 3010 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n"); 3011 goto err_cre_rxbd; 3012 } 3013 3014 ret = mwifiex_pcie_create_evtbd_ring(adapter); 3015 if (ret) { 3016 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n"); 3017 goto err_cre_evtbd; 3018 } 3019 3020 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); 3021 if (ret) { 3022 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n"); 3023 goto err_alloc_cmdbuf; 3024 } 3025 3026 if (reg->sleep_cookie) { 3027 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); 3028 if (ret) { 3029 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n"); 3030 goto err_alloc_cookie; 3031 } 3032 } else { 3033 card->sleep_cookie_vbase = NULL; 3034 } 3035 3036 return 0; 3037 3038 err_alloc_cookie: 3039 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3040 err_alloc_cmdbuf: 3041 mwifiex_pcie_delete_evtbd_ring(adapter); 3042 err_cre_evtbd: 3043 mwifiex_pcie_delete_rxbd_ring(adapter); 3044 err_cre_rxbd: 3045 mwifiex_pcie_delete_txbd_ring(adapter); 3046 err_cre_txbd: 3047 return ret; 3048 } 3049 3050 static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter) 3051 { 3052 struct pcie_service_card *card = adapter->card; 3053 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3054 3055 if (reg->sleep_cookie) 3056 mwifiex_pcie_delete_sleep_cookie_buf(adapter); 3057 3058 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3059 mwifiex_pcie_delete_evtbd_ring(adapter); 3060 mwifiex_pcie_delete_rxbd_ring(adapter); 3061 mwifiex_pcie_delete_txbd_ring(adapter); 3062 } 3063 3064 /* 3065 * This function initializes the PCI-E host memory space, WCB rings, etc. 3066 */ 3067 static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) 3068 { 3069 struct pcie_service_card *card = adapter->card; 3070 int ret; 3071 struct pci_dev *pdev = card->dev; 3072 3073 pci_set_drvdata(pdev, card); 3074 3075 ret = pci_enable_device(pdev); 3076 if (ret) 3077 goto err_enable_dev; 3078 3079 pci_set_master(pdev); 3080 3081 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3082 if (ret) { 3083 pr_err("dma_set_mask(32) failed: %d\n", ret); 3084 goto err_set_dma_mask; 3085 } 3086 3087 ret = pci_request_region(pdev, 0, DRV_NAME); 3088 if (ret) { 3089 pr_err("req_reg(0) error\n"); 3090 goto err_req_region0; 3091 } 3092 card->pci_mmap = pci_iomap(pdev, 0, 0); 3093 if (!card->pci_mmap) { 3094 pr_err("iomap(0) error\n"); 3095 ret = -EIO; 3096 goto err_iomap0; 3097 } 3098 ret = pci_request_region(pdev, 2, DRV_NAME); 3099 if (ret) { 3100 pr_err("req_reg(2) error\n"); 3101 goto err_req_region2; 3102 } 3103 card->pci_mmap1 = pci_iomap(pdev, 2, 0); 3104 if (!card->pci_mmap1) { 3105 pr_err("iomap(2) error\n"); 3106 ret = -EIO; 3107 goto err_iomap2; 3108 } 3109 3110 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n", 3111 card->pci_mmap, card->pci_mmap1); 3112 3113 ret = mwifiex_pcie_alloc_buffers(adapter); 3114 if (ret) 3115 goto err_alloc_buffers; 3116 3117 return 0; 3118 3119 err_alloc_buffers: 3120 pci_iounmap(pdev, card->pci_mmap1); 3121 err_iomap2: 3122 pci_release_region(pdev, 2); 3123 err_req_region2: 3124 pci_iounmap(pdev, card->pci_mmap); 3125 err_iomap0: 3126 pci_release_region(pdev, 0); 3127 err_req_region0: 3128 err_set_dma_mask: 3129 pci_disable_device(pdev); 3130 err_enable_dev: 3131 return ret; 3132 } 3133 3134 /* 3135 * This function cleans up the allocated card buffers. 3136 */ 3137 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter) 3138 { 3139 struct pcie_service_card *card = adapter->card; 3140 struct pci_dev *pdev = card->dev; 3141 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3142 int ret; 3143 u32 fw_status; 3144 3145 cancel_work_sync(&card->work); 3146 3147 ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 3148 if (fw_status == FIRMWARE_READY_PCIE) { 3149 mwifiex_dbg(adapter, INFO, 3150 "Clearing driver ready signature\n"); 3151 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3152 mwifiex_dbg(adapter, ERROR, 3153 "Failed to write driver not-ready signature\n"); 3154 } 3155 3156 pci_disable_device(pdev); 3157 3158 pci_iounmap(pdev, card->pci_mmap); 3159 pci_iounmap(pdev, card->pci_mmap1); 3160 pci_release_region(pdev, 2); 3161 pci_release_region(pdev, 0); 3162 3163 mwifiex_pcie_free_buffers(adapter); 3164 } 3165 3166 static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter) 3167 { 3168 int ret, i, j; 3169 struct pcie_service_card *card = adapter->card; 3170 struct pci_dev *pdev = card->dev; 3171 3172 if (card->pcie.reg->msix_support) { 3173 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3174 card->msix_entries[i].entry = i; 3175 ret = pci_enable_msix_exact(pdev, card->msix_entries, 3176 MWIFIEX_NUM_MSIX_VECTORS); 3177 if (!ret) { 3178 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { 3179 card->msix_ctx[i].dev = pdev; 3180 card->msix_ctx[i].msg_id = i; 3181 3182 ret = request_irq(card->msix_entries[i].vector, 3183 mwifiex_pcie_interrupt, 0, 3184 "MWIFIEX_PCIE_MSIX", 3185 &card->msix_ctx[i]); 3186 if (ret) 3187 break; 3188 } 3189 3190 if (ret) { 3191 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n", 3192 ret); 3193 for (j = 0; j < i; j++) 3194 free_irq(card->msix_entries[j].vector, 3195 &card->msix_ctx[i]); 3196 pci_disable_msix(pdev); 3197 } else { 3198 mwifiex_dbg(adapter, MSG, "MSIx enabled!"); 3199 card->msix_enable = 1; 3200 return 0; 3201 } 3202 } 3203 } 3204 3205 if (pci_enable_msi(pdev) != 0) 3206 pci_disable_msi(pdev); 3207 else 3208 card->msi_enable = 1; 3209 3210 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable); 3211 3212 card->share_irq_ctx.dev = pdev; 3213 card->share_irq_ctx.msg_id = -1; 3214 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, 3215 "MRVL_PCIE", &card->share_irq_ctx); 3216 if (ret) { 3217 pr_err("request_irq failed: ret=%d\n", ret); 3218 return -1; 3219 } 3220 3221 return 0; 3222 } 3223 3224 /* 3225 * This function gets the firmware name for downloading by revision id 3226 * 3227 * Read revision id register to get revision id 3228 */ 3229 static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter) 3230 { 3231 int revision_id = 0; 3232 int version, magic; 3233 struct pcie_service_card *card = adapter->card; 3234 3235 switch (card->dev->device) { 3236 case PCIE_DEVICE_ID_MARVELL_88W8766P: 3237 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME); 3238 break; 3239 case PCIE_DEVICE_ID_MARVELL_88W8897: 3240 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); 3241 mwifiex_read_reg(adapter, 0x0c58, &revision_id); 3242 revision_id &= 0xff00; 3243 switch (revision_id) { 3244 case PCIE8897_A0: 3245 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME); 3246 break; 3247 case PCIE8897_B0: 3248 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME); 3249 break; 3250 default: 3251 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME); 3252 3253 break; 3254 } 3255 break; 3256 case PCIE_DEVICE_ID_MARVELL_88W8997: 3257 mwifiex_read_reg(adapter, 0x8, &revision_id); 3258 mwifiex_read_reg(adapter, 0x0cd0, &version); 3259 mwifiex_read_reg(adapter, 0x0cd4, &magic); 3260 revision_id &= 0xff; 3261 version &= 0x7; 3262 magic &= 0xff; 3263 if (revision_id == PCIE8997_A1 && 3264 magic == CHIP_MAGIC_VALUE && 3265 version == CHIP_VER_PCIEUART) 3266 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4); 3267 else 3268 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4); 3269 break; 3270 default: 3271 break; 3272 } 3273 } 3274 3275 /* 3276 * This function registers the PCIE device. 3277 * 3278 * PCIE IRQ is claimed, block size is set and driver data is initialized. 3279 */ 3280 static int mwifiex_register_dev(struct mwifiex_adapter *adapter) 3281 { 3282 struct pcie_service_card *card = adapter->card; 3283 3284 /* save adapter pointer in card */ 3285 card->adapter = adapter; 3286 3287 if (mwifiex_pcie_request_irq(adapter)) 3288 return -1; 3289 3290 adapter->tx_buf_size = card->pcie.tx_buf_size; 3291 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl; 3292 adapter->num_mem_types = card->pcie.num_mem_types; 3293 adapter->ext_scan = card->pcie.can_ext_scan; 3294 mwifiex_pcie_get_fw_name(adapter); 3295 3296 return 0; 3297 } 3298 3299 /* 3300 * This function unregisters the PCIE device. 3301 * 3302 * The PCIE IRQ is released, the function is disabled and driver 3303 * data is set to null. 3304 */ 3305 static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) 3306 { 3307 struct pcie_service_card *card = adapter->card; 3308 struct pci_dev *pdev = card->dev; 3309 int i; 3310 3311 if (card->msix_enable) { 3312 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3313 synchronize_irq(card->msix_entries[i].vector); 3314 3315 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3316 free_irq(card->msix_entries[i].vector, 3317 &card->msix_ctx[i]); 3318 3319 card->msix_enable = 0; 3320 pci_disable_msix(pdev); 3321 } else { 3322 mwifiex_dbg(adapter, INFO, 3323 "%s(): calling free_irq()\n", __func__); 3324 free_irq(card->dev->irq, &card->share_irq_ctx); 3325 3326 if (card->msi_enable) 3327 pci_disable_msi(pdev); 3328 } 3329 card->adapter = NULL; 3330 } 3331 3332 /* 3333 * This function initializes the PCI-E host memory space, WCB rings, etc., 3334 * similar to mwifiex_init_pcie(), but without resetting PCI-E state. 3335 */ 3336 static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter) 3337 { 3338 struct pcie_service_card *card = adapter->card; 3339 struct pci_dev *pdev = card->dev; 3340 3341 /* tx_buf_size might be changed to 3584 by firmware during 3342 * data transfer, we should reset it to default size. 3343 */ 3344 adapter->tx_buf_size = card->pcie.tx_buf_size; 3345 3346 mwifiex_pcie_alloc_buffers(adapter); 3347 3348 pci_set_master(pdev); 3349 } 3350 3351 /* This function cleans up the PCI-E host memory space. */ 3352 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter) 3353 { 3354 struct pcie_service_card *card = adapter->card; 3355 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3356 struct pci_dev *pdev = card->dev; 3357 3358 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3359 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n"); 3360 3361 pci_clear_master(pdev); 3362 3363 adapter->seq_num = 0; 3364 3365 mwifiex_pcie_free_buffers(adapter); 3366 } 3367 3368 static struct mwifiex_if_ops pcie_ops = { 3369 .init_if = mwifiex_init_pcie, 3370 .cleanup_if = mwifiex_cleanup_pcie, 3371 .check_fw_status = mwifiex_check_fw_status, 3372 .check_winner_status = mwifiex_check_winner_status, 3373 .prog_fw = mwifiex_prog_fw_w_helper, 3374 .register_dev = mwifiex_register_dev, 3375 .unregister_dev = mwifiex_unregister_dev, 3376 .enable_int = mwifiex_pcie_enable_host_int, 3377 .disable_int = mwifiex_pcie_disable_host_int_noerr, 3378 .process_int_status = mwifiex_process_int_status, 3379 .host_to_card = mwifiex_pcie_host_to_card, 3380 .wakeup = mwifiex_pm_wakeup_card, 3381 .wakeup_complete = mwifiex_pm_wakeup_card_complete, 3382 3383 /* PCIE specific */ 3384 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, 3385 .event_complete = mwifiex_pcie_event_complete, 3386 .update_mp_end_port = NULL, 3387 .cleanup_mpa_buf = NULL, 3388 .init_fw_port = mwifiex_pcie_init_fw_port, 3389 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, 3390 .card_reset = mwifiex_pcie_card_reset, 3391 .reg_dump = mwifiex_pcie_reg_dump, 3392 .device_dump = mwifiex_pcie_device_dump, 3393 .down_dev = mwifiex_pcie_down_dev, 3394 .up_dev = mwifiex_pcie_up_dev, 3395 }; 3396 3397 module_pci_driver(mwifiex_pcie); 3398 3399 MODULE_AUTHOR("Marvell International Ltd."); 3400 MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); 3401 MODULE_VERSION(PCIE_VERSION); 3402 MODULE_LICENSE("GPL v2"); 3403