1 /* 2 * NXP Wireless LAN device driver: PCIE specific handling 3 * 4 * Copyright 2011-2020 NXP 5 * 6 * This software file (the "File") is distributed by NXP 7 * under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #include <linux/iopoll.h> 21 #include <linux/firmware.h> 22 23 #include "decl.h" 24 #include "ioctl.h" 25 #include "util.h" 26 #include "fw.h" 27 #include "main.h" 28 #include "wmm.h" 29 #include "11n.h" 30 #include "pcie.h" 31 #include "pcie_quirks.h" 32 33 #define PCIE_VERSION "1.0" 34 #define DRV_NAME "Marvell mwifiex PCIe" 35 36 static struct mwifiex_if_ops pcie_ops; 37 38 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 39 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 40 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 41 .cmd_size = PCIE_SCRATCH_2_REG, 42 .fw_status = PCIE_SCRATCH_3_REG, 43 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 44 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 45 .tx_rdptr = PCIE_SCRATCH_6_REG, 46 .tx_wrptr = PCIE_SCRATCH_7_REG, 47 .rx_rdptr = PCIE_SCRATCH_8_REG, 48 .rx_wrptr = PCIE_SCRATCH_9_REG, 49 .evt_rdptr = PCIE_SCRATCH_10_REG, 50 .evt_wrptr = PCIE_SCRATCH_11_REG, 51 .drv_rdy = PCIE_SCRATCH_12_REG, 52 .tx_start_ptr = 0, 53 .tx_mask = MWIFIEX_TXBD_MASK, 54 .tx_wrap_mask = 0, 55 .rx_mask = MWIFIEX_RXBD_MASK, 56 .rx_wrap_mask = 0, 57 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 58 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 59 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 60 .ring_flag_sop = 0, 61 .ring_flag_eop = 0, 62 .ring_flag_xs_sop = 0, 63 .ring_flag_xs_eop = 0, 64 .ring_tx_start_ptr = 0, 65 .pfu_enabled = 0, 66 .sleep_cookie = 1, 67 .msix_support = 0, 68 }; 69 70 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 71 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 72 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 73 .cmd_size = PCIE_SCRATCH_2_REG, 74 .fw_status = PCIE_SCRATCH_3_REG, 75 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 76 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 77 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 78 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 79 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 80 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 81 .evt_rdptr = PCIE_SCRATCH_10_REG, 82 .evt_wrptr = PCIE_SCRATCH_11_REG, 83 .drv_rdy = PCIE_SCRATCH_12_REG, 84 .tx_start_ptr = 16, 85 .tx_mask = 0x03FF0000, 86 .tx_wrap_mask = 0x07FF0000, 87 .rx_mask = 0x000003FF, 88 .rx_wrap_mask = 0x000007FF, 89 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 90 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 91 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 92 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 93 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 94 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 95 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 96 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 97 .pfu_enabled = 1, 98 .sleep_cookie = 0, 99 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 100 .fw_dump_start = PCIE_SCRATCH_14_REG, 101 .fw_dump_end = 0xcff, 102 .fw_dump_host_ready = 0xee, 103 .fw_dump_read_done = 0xfe, 104 .msix_support = 0, 105 }; 106 107 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 108 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 109 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 110 .cmd_size = PCIE_SCRATCH_2_REG, 111 .fw_status = PCIE_SCRATCH_3_REG, 112 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 113 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 114 .tx_rdptr = 0xC1A4, 115 .tx_wrptr = 0xC174, 116 .rx_rdptr = 0xC174, 117 .rx_wrptr = 0xC1A4, 118 .evt_rdptr = PCIE_SCRATCH_10_REG, 119 .evt_wrptr = PCIE_SCRATCH_11_REG, 120 .drv_rdy = PCIE_SCRATCH_12_REG, 121 .tx_start_ptr = 16, 122 .tx_mask = 0x0FFF0000, 123 .tx_wrap_mask = 0x1FFF0000, 124 .rx_mask = 0x00000FFF, 125 .rx_wrap_mask = 0x00001FFF, 126 .tx_rollover_ind = BIT(28), 127 .rx_rollover_ind = BIT(12), 128 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 129 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 130 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 131 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 132 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 133 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 134 .pfu_enabled = 1, 135 .sleep_cookie = 0, 136 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 137 .fw_dump_start = PCIE_SCRATCH_14_REG, 138 .fw_dump_end = 0xcff, 139 .fw_dump_host_ready = 0xcc, 140 .fw_dump_read_done = 0xdd, 141 .msix_support = 0, 142 }; 143 144 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 145 {"ITCM", NULL, 0, 0xF0}, 146 {"DTCM", NULL, 0, 0xF1}, 147 {"SQRAM", NULL, 0, 0xF2}, 148 {"IRAM", NULL, 0, 0xF3}, 149 {"APU", NULL, 0, 0xF4}, 150 {"CIU", NULL, 0, 0xF5}, 151 {"ICU", NULL, 0, 0xF6}, 152 {"MAC", NULL, 0, 0xF7}, 153 }; 154 155 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 156 {"DUMP", NULL, 0, 0xDD}, 157 }; 158 159 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 160 .reg = &mwifiex_reg_8766, 161 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 162 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 163 .can_dump_fw = false, 164 .can_ext_scan = true, 165 }; 166 167 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 168 .reg = &mwifiex_reg_8897, 169 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 170 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 171 .can_dump_fw = true, 172 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 173 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 174 .can_ext_scan = true, 175 }; 176 177 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 178 .reg = &mwifiex_reg_8997, 179 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 180 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 181 .can_dump_fw = true, 182 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 183 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 184 .can_ext_scan = true, 185 }; 186 187 static const struct of_device_id mwifiex_pcie_of_match_table[] = { 188 { .compatible = "pci11ab,2b42" }, 189 { .compatible = "pci1b4b,2b42" }, 190 { } 191 }; 192 193 static int mwifiex_pcie_probe_of(struct device *dev) 194 { 195 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) { 196 dev_err(dev, "required compatible string missing\n"); 197 return -EINVAL; 198 } 199 200 return 0; 201 } 202 203 static void mwifiex_pcie_work(struct work_struct *work); 204 205 static int 206 mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, 207 size_t size, int flags) 208 { 209 struct pcie_service_card *card = adapter->card; 210 struct mwifiex_dma_mapping mapping; 211 212 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); 213 if (dma_mapping_error(&card->dev->dev, mapping.addr)) { 214 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); 215 return -1; 216 } 217 mapping.len = size; 218 mwifiex_store_mapping(skb, &mapping); 219 return 0; 220 } 221 222 static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, 223 struct sk_buff *skb, int flags) 224 { 225 struct pcie_service_card *card = adapter->card; 226 struct mwifiex_dma_mapping mapping; 227 228 mwifiex_get_mapping(skb, &mapping); 229 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); 230 } 231 232 /* 233 * This function writes data into PCIE card register. 234 */ 235 static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) 236 { 237 struct pcie_service_card *card = adapter->card; 238 239 iowrite32(data, card->pci_mmap1 + reg); 240 241 return 0; 242 } 243 244 /* This function reads data from PCIE card register. 245 */ 246 static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) 247 { 248 struct pcie_service_card *card = adapter->card; 249 250 *data = ioread32(card->pci_mmap1 + reg); 251 if (*data == 0xffffffff) 252 return 0xffffffff; 253 254 return 0; 255 } 256 257 /* This function reads u8 data from PCIE card register. */ 258 static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter, 259 int reg, u8 *data) 260 { 261 struct pcie_service_card *card = adapter->card; 262 263 *data = ioread8(card->pci_mmap1 + reg); 264 265 return 0; 266 } 267 268 /* 269 * This function reads sleep cookie and checks if FW is ready 270 */ 271 static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) 272 { 273 u32 cookie_value; 274 struct pcie_service_card *card = adapter->card; 275 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 276 277 if (!reg->sleep_cookie) 278 return true; 279 280 if (card->sleep_cookie_vbase) { 281 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase); 282 mwifiex_dbg(adapter, INFO, 283 "info: ACCESS_HW: sleep cookie=0x%x\n", 284 cookie_value); 285 if (cookie_value == FW_AWAKE_COOKIE) 286 return true; 287 } 288 289 return false; 290 } 291 292 #ifdef CONFIG_PM_SLEEP 293 /* 294 * Kernel needs to suspend all functions separately. Therefore all 295 * registered functions must have drivers with suspend and resume 296 * methods. Failing that the kernel simply removes the whole card. 297 * 298 * If already not suspended, this function allocates and sends a host 299 * sleep activate request to the firmware and turns off the traffic. 300 */ 301 static int mwifiex_pcie_suspend(struct device *dev) 302 { 303 struct mwifiex_adapter *adapter; 304 struct pcie_service_card *card = dev_get_drvdata(dev); 305 306 307 /* Might still be loading firmware */ 308 wait_for_completion(&card->fw_done); 309 310 adapter = card->adapter; 311 if (!adapter) { 312 dev_err(dev, "adapter is not valid\n"); 313 return 0; 314 } 315 316 mwifiex_enable_wake(adapter); 317 318 /* Enable the Host Sleep */ 319 if (!mwifiex_enable_hs(adapter)) { 320 mwifiex_dbg(adapter, ERROR, 321 "cmd: failed to suspend\n"); 322 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 323 mwifiex_disable_wake(adapter); 324 return -EFAULT; 325 } 326 327 flush_workqueue(adapter->workqueue); 328 329 /* Indicate device suspended */ 330 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 331 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 332 333 return 0; 334 } 335 336 /* 337 * Kernel needs to suspend all functions separately. Therefore all 338 * registered functions must have drivers with suspend and resume 339 * methods. Failing that the kernel simply removes the whole card. 340 * 341 * If already not resumed, this function turns on the traffic and 342 * sends a host sleep cancel request to the firmware. 343 */ 344 static int mwifiex_pcie_resume(struct device *dev) 345 { 346 struct mwifiex_adapter *adapter; 347 struct pcie_service_card *card = dev_get_drvdata(dev); 348 349 350 if (!card->adapter) { 351 dev_err(dev, "adapter structure is not valid\n"); 352 return 0; 353 } 354 355 adapter = card->adapter; 356 357 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) { 358 mwifiex_dbg(adapter, WARN, 359 "Device already resumed\n"); 360 return 0; 361 } 362 363 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 364 365 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), 366 MWIFIEX_ASYNC_CMD); 367 mwifiex_disable_wake(adapter); 368 369 return 0; 370 } 371 #endif 372 373 /* 374 * This function probes an mwifiex device and registers it. It allocates 375 * the card structure, enables PCIE function number and initiates the 376 * device registration and initialization procedure by adding a logical 377 * interface. 378 */ 379 static int mwifiex_pcie_probe(struct pci_dev *pdev, 380 const struct pci_device_id *ent) 381 { 382 struct pcie_service_card *card; 383 int ret; 384 385 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 386 pdev->vendor, pdev->device, pdev->revision); 387 388 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 389 if (!card) 390 return -ENOMEM; 391 392 init_completion(&card->fw_done); 393 394 card->dev = pdev; 395 396 if (ent->driver_data) { 397 struct mwifiex_pcie_device *data = (void *)ent->driver_data; 398 card->pcie.reg = data->reg; 399 card->pcie.blksz_fw_dl = data->blksz_fw_dl; 400 card->pcie.tx_buf_size = data->tx_buf_size; 401 card->pcie.can_dump_fw = data->can_dump_fw; 402 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl; 403 card->pcie.num_mem_types = data->num_mem_types; 404 card->pcie.can_ext_scan = data->can_ext_scan; 405 INIT_WORK(&card->work, mwifiex_pcie_work); 406 } 407 408 /* device tree node parsing and platform specific configuration*/ 409 if (pdev->dev.of_node) { 410 ret = mwifiex_pcie_probe_of(&pdev->dev); 411 if (ret) 412 return ret; 413 } 414 415 /* check quirks */ 416 mwifiex_initialize_quirks(card); 417 418 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops, 419 MWIFIEX_PCIE, &pdev->dev)) { 420 pr_err("%s failed\n", __func__); 421 return -1; 422 } 423 424 return 0; 425 } 426 427 /* 428 * This function removes the interface and frees up the card structure. 429 */ 430 static void mwifiex_pcie_remove(struct pci_dev *pdev) 431 { 432 struct pcie_service_card *card; 433 struct mwifiex_adapter *adapter; 434 struct mwifiex_private *priv; 435 const struct mwifiex_pcie_card_reg *reg; 436 u32 fw_status; 437 438 card = pci_get_drvdata(pdev); 439 440 wait_for_completion(&card->fw_done); 441 442 adapter = card->adapter; 443 if (!adapter || !adapter->priv_num) 444 return; 445 446 reg = card->pcie.reg; 447 if (reg) 448 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 449 else 450 fw_status = -1; 451 452 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) { 453 mwifiex_deauthenticate_all(adapter); 454 455 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); 456 457 mwifiex_disable_auto_ds(priv); 458 459 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); 460 } 461 462 mwifiex_remove_card(adapter); 463 } 464 465 static void mwifiex_pcie_shutdown(struct pci_dev *pdev) 466 { 467 mwifiex_pcie_remove(pdev); 468 469 return; 470 } 471 472 static void mwifiex_pcie_coredump(struct device *dev) 473 { 474 struct pci_dev *pdev; 475 struct pcie_service_card *card; 476 477 pdev = container_of(dev, struct pci_dev, dev); 478 card = pci_get_drvdata(pdev); 479 480 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 481 &card->work_flags)) 482 schedule_work(&card->work); 483 } 484 485 static const struct pci_device_id mwifiex_ids[] = { 486 { 487 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, 488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 489 .driver_data = (unsigned long)&mwifiex_pcie8766, 490 }, 491 { 492 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, 493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 494 .driver_data = (unsigned long)&mwifiex_pcie8897, 495 }, 496 { 497 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 499 .driver_data = (unsigned long)&mwifiex_pcie8997, 500 }, 501 { 502 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 504 .driver_data = (unsigned long)&mwifiex_pcie8997, 505 }, 506 {}, 507 }; 508 509 MODULE_DEVICE_TABLE(pci, mwifiex_ids); 510 511 /* 512 * Cleanup all software without cleaning anything related to PCIe and HW. 513 */ 514 static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev) 515 { 516 struct pcie_service_card *card = pci_get_drvdata(pdev); 517 struct mwifiex_adapter *adapter = card->adapter; 518 519 if (!adapter) { 520 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 521 __func__); 522 return; 523 } 524 525 mwifiex_dbg(adapter, INFO, 526 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", 527 __func__, pdev->vendor, pdev->device, pdev->revision); 528 529 mwifiex_shutdown_sw(adapter); 530 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags); 531 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags); 532 533 /* On MS Surface gen4+ devices FLR isn't effective to recover from 534 * hangups, so we power-cycle the card instead. 535 */ 536 if (card->quirks & QUIRK_FW_RST_D3COLD) 537 mwifiex_pcie_reset_d3cold_quirk(pdev); 538 539 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 540 541 card->pci_reset_ongoing = true; 542 } 543 544 /* 545 * Kernel stores and restores PCIe function context before and after performing 546 * FLR respectively. Reconfigure the software and firmware including firmware 547 * redownload. 548 */ 549 static void mwifiex_pcie_reset_done(struct pci_dev *pdev) 550 { 551 struct pcie_service_card *card = pci_get_drvdata(pdev); 552 struct mwifiex_adapter *adapter = card->adapter; 553 int ret; 554 555 if (!adapter) { 556 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 557 __func__); 558 return; 559 } 560 561 mwifiex_dbg(adapter, INFO, 562 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", 563 __func__, pdev->vendor, pdev->device, pdev->revision); 564 565 ret = mwifiex_reinit_sw(adapter); 566 if (ret) 567 dev_err(&pdev->dev, "reinit failed: %d\n", ret); 568 else 569 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 570 571 card->pci_reset_ongoing = false; 572 } 573 574 static const struct pci_error_handlers mwifiex_pcie_err_handler = { 575 .reset_prepare = mwifiex_pcie_reset_prepare, 576 .reset_done = mwifiex_pcie_reset_done, 577 }; 578 579 #ifdef CONFIG_PM_SLEEP 580 /* Power Management Hooks */ 581 static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, 582 mwifiex_pcie_resume); 583 #endif 584 585 /* PCI Device Driver */ 586 static struct pci_driver mwifiex_pcie = { 587 .name = "mwifiex_pcie", 588 .id_table = mwifiex_ids, 589 .probe = mwifiex_pcie_probe, 590 .remove = mwifiex_pcie_remove, 591 .driver = { 592 .coredump = mwifiex_pcie_coredump, 593 #ifdef CONFIG_PM_SLEEP 594 .pm = &mwifiex_pcie_pm_ops, 595 #endif 596 }, 597 .shutdown = mwifiex_pcie_shutdown, 598 .err_handler = &mwifiex_pcie_err_handler, 599 }; 600 601 /* 602 * This function adds delay loop to ensure FW is awake before proceeding. 603 */ 604 static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) 605 { 606 int i = 0; 607 608 while (mwifiex_pcie_ok_to_access_hw(adapter)) { 609 i++; 610 usleep_range(10, 20); 611 /* 50ms max wait */ 612 if (i == 5000) 613 break; 614 } 615 616 return; 617 } 618 619 static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, 620 u32 max_delay_loop_cnt) 621 { 622 struct pcie_service_card *card = adapter->card; 623 u8 *buffer; 624 u32 sleep_cookie, count; 625 struct sk_buff *cmdrsp = card->cmdrsp_buf; 626 627 for (count = 0; count < max_delay_loop_cnt; count++) { 628 dma_sync_single_for_cpu(&card->dev->dev, 629 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 630 sizeof(sleep_cookie), DMA_FROM_DEVICE); 631 buffer = cmdrsp->data; 632 sleep_cookie = get_unaligned_le32(buffer); 633 634 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { 635 mwifiex_dbg(adapter, INFO, 636 "sleep cookie found at count %d\n", count); 637 break; 638 } 639 dma_sync_single_for_device(&card->dev->dev, 640 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 641 sizeof(sleep_cookie), 642 DMA_FROM_DEVICE); 643 usleep_range(20, 30); 644 } 645 646 if (count >= max_delay_loop_cnt) 647 mwifiex_dbg(adapter, INFO, 648 "max count reached while accessing sleep cookie\n"); 649 } 650 651 #define N_WAKEUP_TRIES_SHORT_INTERVAL 15 652 #define N_WAKEUP_TRIES_LONG_INTERVAL 35 653 654 /* This function wakes up the card by reading fw_status register. */ 655 static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) 656 { 657 struct pcie_service_card *card = adapter->card; 658 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 659 int retval; 660 661 mwifiex_dbg(adapter, EVENT, 662 "event: Wakeup device...\n"); 663 664 if (reg->sleep_cookie) 665 mwifiex_pcie_dev_wakeup_delay(adapter); 666 667 /* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes 668 * appears to ignore or miss our wakeup request, so we continue trying 669 * until we receive an interrupt from the card. 670 */ 671 if (read_poll_timeout(mwifiex_write_reg, retval, 672 READ_ONCE(adapter->int_status) != 0, 673 500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL, 674 false, 675 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 676 if (read_poll_timeout(mwifiex_write_reg, retval, 677 READ_ONCE(adapter->int_status) != 0, 678 10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL, 679 false, 680 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 681 mwifiex_dbg(adapter, ERROR, 682 "Firmware didn't wake up\n"); 683 return -EIO; 684 } 685 } 686 687 if (reg->sleep_cookie) { 688 mwifiex_pcie_dev_wakeup_delay(adapter); 689 mwifiex_dbg(adapter, INFO, 690 "PCIE wakeup: Setting PS_STATE_AWAKE\n"); 691 adapter->ps_state = PS_STATE_AWAKE; 692 } 693 694 return 0; 695 } 696 697 /* 698 * This function is called after the card has woken up. 699 * 700 * The card configuration register is reset. 701 */ 702 static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) 703 { 704 mwifiex_dbg(adapter, CMD, 705 "cmd: Wakeup device completed\n"); 706 707 return 0; 708 } 709 710 /* 711 * This function disables the host interrupt. 712 * 713 * The host interrupt mask is read, the disable bit is reset and 714 * written back to the card host interrupt mask register. 715 */ 716 static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) 717 { 718 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 719 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 720 0x00000000)) { 721 mwifiex_dbg(adapter, ERROR, 722 "Disable host interrupt failed\n"); 723 return -1; 724 } 725 } 726 727 atomic_set(&adapter->tx_hw_pending, 0); 728 return 0; 729 } 730 731 static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter) 732 { 733 WARN_ON(mwifiex_pcie_disable_host_int(adapter)); 734 } 735 736 /* 737 * This function enables the host interrupt. 738 * 739 * The host interrupt enable mask is written to the card 740 * host interrupt mask register. 741 */ 742 static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) 743 { 744 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 745 /* Simply write the mask to the register */ 746 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 747 HOST_INTR_MASK)) { 748 mwifiex_dbg(adapter, ERROR, 749 "Enable host interrupt failed\n"); 750 return -1; 751 } 752 } 753 754 return 0; 755 } 756 757 /* 758 * This function initializes TX buffer ring descriptors 759 */ 760 static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) 761 { 762 struct pcie_service_card *card = adapter->card; 763 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 764 struct mwifiex_pcie_buf_desc *desc; 765 struct mwifiex_pfu_buf_desc *desc2; 766 int i; 767 768 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 769 card->tx_buf_list[i] = NULL; 770 if (reg->pfu_enabled) { 771 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 772 (sizeof(*desc2) * i); 773 desc2 = card->txbd_ring[i]; 774 memset(desc2, 0, sizeof(*desc2)); 775 } else { 776 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 777 (sizeof(*desc) * i); 778 desc = card->txbd_ring[i]; 779 memset(desc, 0, sizeof(*desc)); 780 } 781 } 782 783 return 0; 784 } 785 786 /* This function initializes RX buffer ring descriptors. Each SKB is allocated 787 * here and after mapping PCI memory, its physical address is assigned to 788 * PCIE Rx buffer descriptor's physical address. 789 */ 790 static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) 791 { 792 struct pcie_service_card *card = adapter->card; 793 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 794 struct sk_buff *skb; 795 struct mwifiex_pcie_buf_desc *desc; 796 struct mwifiex_pfu_buf_desc *desc2; 797 dma_addr_t buf_pa; 798 int i; 799 800 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 801 /* Allocate skb here so that firmware can DMA data from it */ 802 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 803 GFP_KERNEL); 804 if (!skb) { 805 mwifiex_dbg(adapter, ERROR, 806 "Unable to allocate skb for RX ring.\n"); 807 kfree(card->rxbd_ring_vbase); 808 return -ENOMEM; 809 } 810 811 if (mwifiex_map_pci_memory(adapter, skb, 812 MWIFIEX_RX_DATA_BUF_SIZE, 813 DMA_FROM_DEVICE)) 814 return -1; 815 816 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 817 818 mwifiex_dbg(adapter, INFO, 819 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 820 skb, skb->len, skb->data, (u32)buf_pa, 821 (u32)((u64)buf_pa >> 32)); 822 823 card->rx_buf_list[i] = skb; 824 if (reg->pfu_enabled) { 825 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + 826 (sizeof(*desc2) * i); 827 desc2 = card->rxbd_ring[i]; 828 desc2->paddr = buf_pa; 829 desc2->len = (u16)skb->len; 830 desc2->frag_len = (u16)skb->len; 831 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; 832 desc2->offset = 0; 833 } else { 834 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + 835 (sizeof(*desc) * i)); 836 desc = card->rxbd_ring[i]; 837 desc->paddr = buf_pa; 838 desc->len = (u16)skb->len; 839 desc->flags = 0; 840 } 841 } 842 843 return 0; 844 } 845 846 /* This function initializes event buffer ring descriptors. Each SKB is 847 * allocated here and after mapping PCI memory, its physical address is assigned 848 * to PCIE Rx buffer descriptor's physical address 849 */ 850 static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) 851 { 852 struct pcie_service_card *card = adapter->card; 853 struct mwifiex_evt_buf_desc *desc; 854 struct sk_buff *skb; 855 dma_addr_t buf_pa; 856 int i; 857 858 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 859 /* Allocate skb here so that firmware can DMA data from it */ 860 skb = dev_alloc_skb(MAX_EVENT_SIZE); 861 if (!skb) { 862 mwifiex_dbg(adapter, ERROR, 863 "Unable to allocate skb for EVENT buf.\n"); 864 kfree(card->evtbd_ring_vbase); 865 return -ENOMEM; 866 } 867 skb_put(skb, MAX_EVENT_SIZE); 868 869 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, 870 DMA_FROM_DEVICE)) { 871 kfree_skb(skb); 872 kfree(card->evtbd_ring_vbase); 873 return -1; 874 } 875 876 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 877 878 mwifiex_dbg(adapter, EVENT, 879 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 880 skb, skb->len, skb->data, (u32)buf_pa, 881 (u32)((u64)buf_pa >> 32)); 882 883 card->evt_buf_list[i] = skb; 884 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + 885 (sizeof(*desc) * i)); 886 desc = card->evtbd_ring[i]; 887 desc->paddr = buf_pa; 888 desc->len = (u16)skb->len; 889 desc->flags = 0; 890 } 891 892 return 0; 893 } 894 895 /* This function cleans up TX buffer rings. If any of the buffer list has valid 896 * SKB address, associated SKB is freed. 897 */ 898 static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) 899 { 900 struct pcie_service_card *card = adapter->card; 901 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 902 struct sk_buff *skb; 903 struct mwifiex_pcie_buf_desc *desc; 904 struct mwifiex_pfu_buf_desc *desc2; 905 int i; 906 907 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 908 if (reg->pfu_enabled) { 909 desc2 = card->txbd_ring[i]; 910 if (card->tx_buf_list[i]) { 911 skb = card->tx_buf_list[i]; 912 mwifiex_unmap_pci_memory(adapter, skb, 913 DMA_TO_DEVICE); 914 dev_kfree_skb_any(skb); 915 } 916 memset(desc2, 0, sizeof(*desc2)); 917 } else { 918 desc = card->txbd_ring[i]; 919 if (card->tx_buf_list[i]) { 920 skb = card->tx_buf_list[i]; 921 mwifiex_unmap_pci_memory(adapter, skb, 922 DMA_TO_DEVICE); 923 dev_kfree_skb_any(skb); 924 } 925 memset(desc, 0, sizeof(*desc)); 926 } 927 card->tx_buf_list[i] = NULL; 928 } 929 930 atomic_set(&adapter->tx_hw_pending, 0); 931 return; 932 } 933 934 /* This function cleans up RX buffer rings. If any of the buffer list has valid 935 * SKB address, associated SKB is freed. 936 */ 937 static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) 938 { 939 struct pcie_service_card *card = adapter->card; 940 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 941 struct mwifiex_pcie_buf_desc *desc; 942 struct mwifiex_pfu_buf_desc *desc2; 943 struct sk_buff *skb; 944 int i; 945 946 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 947 if (reg->pfu_enabled) { 948 desc2 = card->rxbd_ring[i]; 949 if (card->rx_buf_list[i]) { 950 skb = card->rx_buf_list[i]; 951 mwifiex_unmap_pci_memory(adapter, skb, 952 DMA_FROM_DEVICE); 953 dev_kfree_skb_any(skb); 954 } 955 memset(desc2, 0, sizeof(*desc2)); 956 } else { 957 desc = card->rxbd_ring[i]; 958 if (card->rx_buf_list[i]) { 959 skb = card->rx_buf_list[i]; 960 mwifiex_unmap_pci_memory(adapter, skb, 961 DMA_FROM_DEVICE); 962 dev_kfree_skb_any(skb); 963 } 964 memset(desc, 0, sizeof(*desc)); 965 } 966 card->rx_buf_list[i] = NULL; 967 } 968 969 return; 970 } 971 972 /* This function cleans up event buffer rings. If any of the buffer list has 973 * valid SKB address, associated SKB is freed. 974 */ 975 static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) 976 { 977 struct pcie_service_card *card = adapter->card; 978 struct mwifiex_evt_buf_desc *desc; 979 struct sk_buff *skb; 980 int i; 981 982 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 983 desc = card->evtbd_ring[i]; 984 if (card->evt_buf_list[i]) { 985 skb = card->evt_buf_list[i]; 986 mwifiex_unmap_pci_memory(adapter, skb, 987 DMA_FROM_DEVICE); 988 dev_kfree_skb_any(skb); 989 } 990 card->evt_buf_list[i] = NULL; 991 memset(desc, 0, sizeof(*desc)); 992 } 993 994 return; 995 } 996 997 /* This function creates buffer descriptor ring for TX 998 */ 999 static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) 1000 { 1001 struct pcie_service_card *card = adapter->card; 1002 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1003 1004 /* 1005 * driver maintaines the write pointer and firmware maintaines the read 1006 * pointer. The write pointer starts at 0 (zero) while the read pointer 1007 * starts at zero with rollover bit set 1008 */ 1009 card->txbd_wrptr = 0; 1010 1011 if (reg->pfu_enabled) 1012 card->txbd_rdptr = 0; 1013 else 1014 card->txbd_rdptr |= reg->tx_rollover_ind; 1015 1016 /* allocate shared memory for the BD ring and divide the same in to 1017 several descriptors */ 1018 if (reg->pfu_enabled) 1019 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 1020 MWIFIEX_MAX_TXRX_BD; 1021 else 1022 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1023 MWIFIEX_MAX_TXRX_BD; 1024 1025 mwifiex_dbg(adapter, INFO, 1026 "info: txbd_ring: Allocating %d bytes\n", 1027 card->txbd_ring_size); 1028 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1029 card->txbd_ring_size, 1030 &card->txbd_ring_pbase, 1031 GFP_KERNEL); 1032 if (!card->txbd_ring_vbase) { 1033 mwifiex_dbg(adapter, ERROR, 1034 "allocate coherent memory (%d bytes) failed!\n", 1035 card->txbd_ring_size); 1036 return -ENOMEM; 1037 } 1038 1039 mwifiex_dbg(adapter, DATA, 1040 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1041 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase, 1042 (u32)((u64)card->txbd_ring_pbase >> 32), 1043 card->txbd_ring_size); 1044 1045 return mwifiex_init_txq_ring(adapter); 1046 } 1047 1048 static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) 1049 { 1050 struct pcie_service_card *card = adapter->card; 1051 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1052 1053 mwifiex_cleanup_txq_ring(adapter); 1054 1055 if (card->txbd_ring_vbase) 1056 dma_free_coherent(&card->dev->dev, card->txbd_ring_size, 1057 card->txbd_ring_vbase, 1058 card->txbd_ring_pbase); 1059 card->txbd_ring_size = 0; 1060 card->txbd_wrptr = 0; 1061 card->txbd_rdptr = 0 | reg->tx_rollover_ind; 1062 card->txbd_ring_vbase = NULL; 1063 card->txbd_ring_pbase = 0; 1064 1065 return 0; 1066 } 1067 1068 /* 1069 * This function creates buffer descriptor ring for RX 1070 */ 1071 static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) 1072 { 1073 struct pcie_service_card *card = adapter->card; 1074 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1075 1076 /* 1077 * driver maintaines the read pointer and firmware maintaines the write 1078 * pointer. The write pointer starts at 0 (zero) while the read pointer 1079 * starts at zero with rollover bit set 1080 */ 1081 card->rxbd_wrptr = 0; 1082 card->rxbd_rdptr = reg->rx_rollover_ind; 1083 1084 if (reg->pfu_enabled) 1085 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 1086 MWIFIEX_MAX_TXRX_BD; 1087 else 1088 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1089 MWIFIEX_MAX_TXRX_BD; 1090 1091 mwifiex_dbg(adapter, INFO, 1092 "info: rxbd_ring: Allocating %d bytes\n", 1093 card->rxbd_ring_size); 1094 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1095 card->rxbd_ring_size, 1096 &card->rxbd_ring_pbase, 1097 GFP_KERNEL); 1098 if (!card->rxbd_ring_vbase) { 1099 mwifiex_dbg(adapter, ERROR, 1100 "allocate coherent memory (%d bytes) failed!\n", 1101 card->rxbd_ring_size); 1102 return -ENOMEM; 1103 } 1104 1105 mwifiex_dbg(adapter, DATA, 1106 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1107 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, 1108 (u32)((u64)card->rxbd_ring_pbase >> 32), 1109 card->rxbd_ring_size); 1110 1111 return mwifiex_init_rxq_ring(adapter); 1112 } 1113 1114 /* 1115 * This function deletes Buffer descriptor ring for RX 1116 */ 1117 static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) 1118 { 1119 struct pcie_service_card *card = adapter->card; 1120 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1121 1122 mwifiex_cleanup_rxq_ring(adapter); 1123 1124 if (card->rxbd_ring_vbase) 1125 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, 1126 card->rxbd_ring_vbase, 1127 card->rxbd_ring_pbase); 1128 card->rxbd_ring_size = 0; 1129 card->rxbd_wrptr = 0; 1130 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; 1131 card->rxbd_ring_vbase = NULL; 1132 card->rxbd_ring_pbase = 0; 1133 1134 return 0; 1135 } 1136 1137 /* 1138 * This function creates buffer descriptor ring for Events 1139 */ 1140 static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) 1141 { 1142 struct pcie_service_card *card = adapter->card; 1143 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1144 1145 /* 1146 * driver maintaines the read pointer and firmware maintaines the write 1147 * pointer. The write pointer starts at 0 (zero) while the read pointer 1148 * starts at zero with rollover bit set 1149 */ 1150 card->evtbd_wrptr = 0; 1151 card->evtbd_rdptr = reg->evt_rollover_ind; 1152 1153 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * 1154 MWIFIEX_MAX_EVT_BD; 1155 1156 mwifiex_dbg(adapter, INFO, 1157 "info: evtbd_ring: Allocating %d bytes\n", 1158 card->evtbd_ring_size); 1159 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1160 card->evtbd_ring_size, 1161 &card->evtbd_ring_pbase, 1162 GFP_KERNEL); 1163 if (!card->evtbd_ring_vbase) { 1164 mwifiex_dbg(adapter, ERROR, 1165 "allocate coherent memory (%d bytes) failed!\n", 1166 card->evtbd_ring_size); 1167 return -ENOMEM; 1168 } 1169 1170 mwifiex_dbg(adapter, EVENT, 1171 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", 1172 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, 1173 (u32)((u64)card->evtbd_ring_pbase >> 32), 1174 card->evtbd_ring_size); 1175 1176 return mwifiex_pcie_init_evt_ring(adapter); 1177 } 1178 1179 /* 1180 * This function deletes Buffer descriptor ring for Events 1181 */ 1182 static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) 1183 { 1184 struct pcie_service_card *card = adapter->card; 1185 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1186 1187 mwifiex_cleanup_evt_ring(adapter); 1188 1189 if (card->evtbd_ring_vbase) 1190 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, 1191 card->evtbd_ring_vbase, 1192 card->evtbd_ring_pbase); 1193 card->evtbd_wrptr = 0; 1194 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; 1195 card->evtbd_ring_size = 0; 1196 card->evtbd_ring_vbase = NULL; 1197 card->evtbd_ring_pbase = 0; 1198 1199 return 0; 1200 } 1201 1202 /* 1203 * This function allocates a buffer for CMDRSP 1204 */ 1205 static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) 1206 { 1207 struct pcie_service_card *card = adapter->card; 1208 struct sk_buff *skb; 1209 1210 /* Allocate memory for receiving command response data */ 1211 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 1212 if (!skb) { 1213 mwifiex_dbg(adapter, ERROR, 1214 "Unable to allocate skb for command response data.\n"); 1215 return -ENOMEM; 1216 } 1217 skb_put(skb, MWIFIEX_UPLD_SIZE); 1218 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1219 DMA_FROM_DEVICE)) { 1220 kfree_skb(skb); 1221 return -1; 1222 } 1223 1224 card->cmdrsp_buf = skb; 1225 1226 return 0; 1227 } 1228 1229 /* 1230 * This function deletes a buffer for CMDRSP 1231 */ 1232 static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) 1233 { 1234 struct pcie_service_card *card; 1235 1236 if (!adapter) 1237 return 0; 1238 1239 card = adapter->card; 1240 1241 if (card && card->cmdrsp_buf) { 1242 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, 1243 DMA_FROM_DEVICE); 1244 dev_kfree_skb_any(card->cmdrsp_buf); 1245 card->cmdrsp_buf = NULL; 1246 } 1247 1248 if (card && card->cmd_buf) { 1249 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1250 DMA_TO_DEVICE); 1251 dev_kfree_skb_any(card->cmd_buf); 1252 card->cmd_buf = NULL; 1253 } 1254 return 0; 1255 } 1256 1257 /* 1258 * This function allocates a buffer for sleep cookie 1259 */ 1260 static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1261 { 1262 struct pcie_service_card *card = adapter->card; 1263 u32 *cookie; 1264 1265 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, 1266 sizeof(u32), 1267 &card->sleep_cookie_pbase, 1268 GFP_KERNEL); 1269 if (!card->sleep_cookie_vbase) { 1270 mwifiex_dbg(adapter, ERROR, 1271 "dma_alloc_coherent failed!\n"); 1272 return -ENOMEM; 1273 } 1274 cookie = (u32 *)card->sleep_cookie_vbase; 1275 /* Init val of Sleep Cookie */ 1276 *cookie = FW_AWAKE_COOKIE; 1277 1278 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie); 1279 1280 return 0; 1281 } 1282 1283 /* 1284 * This function deletes buffer for sleep cookie 1285 */ 1286 static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1287 { 1288 struct pcie_service_card *card; 1289 1290 if (!adapter) 1291 return 0; 1292 1293 card = adapter->card; 1294 1295 if (card && card->sleep_cookie_vbase) { 1296 dma_free_coherent(&card->dev->dev, sizeof(u32), 1297 card->sleep_cookie_vbase, 1298 card->sleep_cookie_pbase); 1299 card->sleep_cookie_vbase = NULL; 1300 } 1301 1302 return 0; 1303 } 1304 1305 /* This function flushes the TX buffer descriptor ring 1306 * This function defined as handler is also called while cleaning TXRX 1307 * during disconnect/ bss stop. 1308 */ 1309 static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) 1310 { 1311 struct pcie_service_card *card = adapter->card; 1312 1313 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { 1314 card->txbd_flush = 1; 1315 /* write pointer already set at last send 1316 * send dnld-rdy intr again, wait for completion. 1317 */ 1318 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1319 CPU_INTR_DNLD_RDY)) { 1320 mwifiex_dbg(adapter, ERROR, 1321 "failed to assert dnld-rdy interrupt.\n"); 1322 return -1; 1323 } 1324 } 1325 return 0; 1326 } 1327 1328 /* 1329 * This function unmaps and frees downloaded data buffer 1330 */ 1331 static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) 1332 { 1333 struct sk_buff *skb; 1334 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; 1335 struct mwifiex_pcie_buf_desc *desc; 1336 struct mwifiex_pfu_buf_desc *desc2; 1337 struct pcie_service_card *card = adapter->card; 1338 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1339 1340 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1341 mwifiex_pm_wakeup_card(adapter); 1342 1343 /* Read the TX ring read pointer set by firmware */ 1344 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { 1345 mwifiex_dbg(adapter, ERROR, 1346 "SEND COMP: failed to read reg->tx_rdptr\n"); 1347 return -1; 1348 } 1349 1350 mwifiex_dbg(adapter, DATA, 1351 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", 1352 card->txbd_rdptr, rdptr); 1353 1354 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1355 /* free from previous txbd_rdptr to current txbd_rdptr */ 1356 while (((card->txbd_rdptr & reg->tx_mask) != 1357 (rdptr & reg->tx_mask)) || 1358 ((card->txbd_rdptr & reg->tx_rollover_ind) != 1359 (rdptr & reg->tx_rollover_ind))) { 1360 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> 1361 reg->tx_start_ptr; 1362 1363 skb = card->tx_buf_list[wrdoneidx]; 1364 1365 if (skb) { 1366 mwifiex_dbg(adapter, DATA, 1367 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", 1368 skb, wrdoneidx); 1369 mwifiex_unmap_pci_memory(adapter, skb, 1370 DMA_TO_DEVICE); 1371 1372 unmap_count++; 1373 1374 if (card->txbd_flush) 1375 mwifiex_write_data_complete(adapter, skb, 0, 1376 -1); 1377 else 1378 mwifiex_write_data_complete(adapter, skb, 0, 0); 1379 atomic_dec(&adapter->tx_hw_pending); 1380 } 1381 1382 card->tx_buf_list[wrdoneidx] = NULL; 1383 1384 if (reg->pfu_enabled) { 1385 desc2 = card->txbd_ring[wrdoneidx]; 1386 memset(desc2, 0, sizeof(*desc2)); 1387 } else { 1388 desc = card->txbd_ring[wrdoneidx]; 1389 memset(desc, 0, sizeof(*desc)); 1390 } 1391 switch (card->dev->device) { 1392 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1393 card->txbd_rdptr++; 1394 break; 1395 case PCIE_DEVICE_ID_MARVELL_88W8897: 1396 case PCIE_DEVICE_ID_MARVELL_88W8997: 1397 card->txbd_rdptr += reg->ring_tx_start_ptr; 1398 break; 1399 } 1400 1401 1402 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) 1403 card->txbd_rdptr = ((card->txbd_rdptr & 1404 reg->tx_rollover_ind) ^ 1405 reg->tx_rollover_ind); 1406 } 1407 1408 if (unmap_count) 1409 adapter->data_sent = false; 1410 1411 if (card->txbd_flush) { 1412 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) 1413 card->txbd_flush = 0; 1414 else 1415 mwifiex_clean_pcie_ring_buf(adapter); 1416 } 1417 1418 return 0; 1419 } 1420 1421 /* This function sends data buffer to device. First 4 bytes of payload 1422 * are filled with payload length and payload type. Then this payload 1423 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. 1424 * Download ready interrupt to FW is deffered if Tx ring is not full and 1425 * additional payload can be accomodated. 1426 * Caller must ensure tx_param parameter to this function is not NULL. 1427 */ 1428 static int 1429 mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, 1430 struct mwifiex_tx_param *tx_param) 1431 { 1432 struct pcie_service_card *card = adapter->card; 1433 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1434 u32 wrindx, num_tx_buffs, rx_val; 1435 int ret; 1436 dma_addr_t buf_pa; 1437 struct mwifiex_pcie_buf_desc *desc = NULL; 1438 struct mwifiex_pfu_buf_desc *desc2 = NULL; 1439 1440 if (!(skb->data && skb->len)) { 1441 mwifiex_dbg(adapter, ERROR, 1442 "%s(): invalid parameter <%p, %#x>\n", 1443 __func__, skb->data, skb->len); 1444 return -1; 1445 } 1446 1447 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1448 mwifiex_pm_wakeup_card(adapter); 1449 1450 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1451 mwifiex_dbg(adapter, DATA, 1452 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", 1453 card->txbd_rdptr, card->txbd_wrptr); 1454 if (mwifiex_pcie_txbd_not_full(card)) { 1455 u8 *payload; 1456 1457 adapter->data_sent = true; 1458 payload = skb->data; 1459 put_unaligned_le16((u16)skb->len, payload + 0); 1460 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); 1461 1462 if (mwifiex_map_pci_memory(adapter, skb, skb->len, 1463 DMA_TO_DEVICE)) 1464 return -1; 1465 1466 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; 1467 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1468 card->tx_buf_list[wrindx] = skb; 1469 atomic_inc(&adapter->tx_hw_pending); 1470 1471 if (reg->pfu_enabled) { 1472 desc2 = card->txbd_ring[wrindx]; 1473 desc2->paddr = buf_pa; 1474 desc2->len = (u16)skb->len; 1475 desc2->frag_len = (u16)skb->len; 1476 desc2->offset = 0; 1477 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1478 MWIFIEX_BD_FLAG_LAST_DESC; 1479 } else { 1480 desc = card->txbd_ring[wrindx]; 1481 desc->paddr = buf_pa; 1482 desc->len = (u16)skb->len; 1483 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1484 MWIFIEX_BD_FLAG_LAST_DESC; 1485 } 1486 1487 switch (card->dev->device) { 1488 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1489 card->txbd_wrptr++; 1490 break; 1491 case PCIE_DEVICE_ID_MARVELL_88W8897: 1492 case PCIE_DEVICE_ID_MARVELL_88W8997: 1493 card->txbd_wrptr += reg->ring_tx_start_ptr; 1494 break; 1495 } 1496 1497 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) 1498 card->txbd_wrptr = ((card->txbd_wrptr & 1499 reg->tx_rollover_ind) ^ 1500 reg->tx_rollover_ind); 1501 1502 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; 1503 /* Write the TX ring write pointer in to reg->tx_wrptr */ 1504 if (mwifiex_write_reg(adapter, reg->tx_wrptr, 1505 card->txbd_wrptr | rx_val)) { 1506 mwifiex_dbg(adapter, ERROR, 1507 "SEND DATA: failed to write reg->tx_wrptr\n"); 1508 ret = -1; 1509 goto done_unmap; 1510 } 1511 1512 /* The firmware (latest version 15.68.19.p21) of the 88W8897 PCIe+USB card 1513 * seems to crash randomly after setting the TX ring write pointer when 1514 * ASPM powersaving is enabled. A workaround seems to be keeping the bus 1515 * busy by reading a random register afterwards. 1516 */ 1517 mwifiex_read_reg(adapter, PCI_VENDOR_ID, &rx_val); 1518 1519 if ((mwifiex_pcie_txbd_not_full(card)) && 1520 tx_param->next_pkt_len) { 1521 /* have more packets and TxBD still can hold more */ 1522 mwifiex_dbg(adapter, DATA, 1523 "SEND DATA: delay dnld-rdy interrupt.\n"); 1524 adapter->data_sent = false; 1525 } else { 1526 /* Send the TX ready interrupt */ 1527 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1528 CPU_INTR_DNLD_RDY)) { 1529 mwifiex_dbg(adapter, ERROR, 1530 "SEND DATA: failed to assert dnld-rdy interrupt.\n"); 1531 ret = -1; 1532 goto done_unmap; 1533 } 1534 } 1535 mwifiex_dbg(adapter, DATA, 1536 "info: SEND DATA: Updated <Rd: %#x, Wr:\t" 1537 "%#x> and sent packet to firmware successfully\n", 1538 card->txbd_rdptr, card->txbd_wrptr); 1539 } else { 1540 mwifiex_dbg(adapter, DATA, 1541 "info: TX Ring full, can't send packets to fw\n"); 1542 adapter->data_sent = true; 1543 /* Send the TX ready interrupt */ 1544 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1545 CPU_INTR_DNLD_RDY)) 1546 mwifiex_dbg(adapter, ERROR, 1547 "SEND DATA: failed to assert door-bell intr\n"); 1548 return -EBUSY; 1549 } 1550 1551 return -EINPROGRESS; 1552 done_unmap: 1553 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1554 card->tx_buf_list[wrindx] = NULL; 1555 atomic_dec(&adapter->tx_hw_pending); 1556 if (reg->pfu_enabled) 1557 memset(desc2, 0, sizeof(*desc2)); 1558 else 1559 memset(desc, 0, sizeof(*desc)); 1560 1561 return ret; 1562 } 1563 1564 /* 1565 * This function handles received buffer ring and 1566 * dispatches packets to upper 1567 */ 1568 static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) 1569 { 1570 struct pcie_service_card *card = adapter->card; 1571 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1572 u32 wrptr, rd_index, tx_val; 1573 dma_addr_t buf_pa; 1574 int ret = 0; 1575 struct sk_buff *skb_tmp = NULL; 1576 struct mwifiex_pcie_buf_desc *desc; 1577 struct mwifiex_pfu_buf_desc *desc2; 1578 1579 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1580 mwifiex_pm_wakeup_card(adapter); 1581 1582 /* Read the RX ring Write pointer set by firmware */ 1583 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1584 mwifiex_dbg(adapter, ERROR, 1585 "RECV DATA: failed to read reg->rx_wrptr\n"); 1586 ret = -1; 1587 goto done; 1588 } 1589 card->rxbd_wrptr = wrptr; 1590 1591 while (((wrptr & reg->rx_mask) != 1592 (card->rxbd_rdptr & reg->rx_mask)) || 1593 ((wrptr & reg->rx_rollover_ind) == 1594 (card->rxbd_rdptr & reg->rx_rollover_ind))) { 1595 struct sk_buff *skb_data; 1596 u16 rx_len; 1597 1598 rd_index = card->rxbd_rdptr & reg->rx_mask; 1599 skb_data = card->rx_buf_list[rd_index]; 1600 1601 /* If skb allocation was failed earlier for Rx packet, 1602 * rx_buf_list[rd_index] would have been left with a NULL. 1603 */ 1604 if (!skb_data) 1605 return -ENOMEM; 1606 1607 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); 1608 card->rx_buf_list[rd_index] = NULL; 1609 1610 /* Get data length from interface header - 1611 * first 2 bytes for len, next 2 bytes is for type 1612 */ 1613 rx_len = get_unaligned_le16(skb_data->data); 1614 if (WARN_ON(rx_len <= adapter->intf_hdr_len || 1615 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) { 1616 mwifiex_dbg(adapter, ERROR, 1617 "Invalid RX len %d, Rd=%#x, Wr=%#x\n", 1618 rx_len, card->rxbd_rdptr, wrptr); 1619 dev_kfree_skb_any(skb_data); 1620 } else { 1621 skb_put(skb_data, rx_len); 1622 mwifiex_dbg(adapter, DATA, 1623 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", 1624 card->rxbd_rdptr, wrptr, rx_len); 1625 skb_pull(skb_data, adapter->intf_hdr_len); 1626 if (adapter->rx_work_enabled) { 1627 skb_queue_tail(&adapter->rx_data_q, skb_data); 1628 adapter->data_received = true; 1629 atomic_inc(&adapter->rx_pending); 1630 } else { 1631 mwifiex_handle_rx_packet(adapter, skb_data); 1632 } 1633 } 1634 1635 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 1636 GFP_KERNEL); 1637 if (!skb_tmp) { 1638 mwifiex_dbg(adapter, ERROR, 1639 "Unable to allocate skb.\n"); 1640 return -ENOMEM; 1641 } 1642 1643 if (mwifiex_map_pci_memory(adapter, skb_tmp, 1644 MWIFIEX_RX_DATA_BUF_SIZE, 1645 DMA_FROM_DEVICE)) 1646 return -1; 1647 1648 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); 1649 1650 mwifiex_dbg(adapter, INFO, 1651 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", 1652 skb_tmp, rd_index); 1653 card->rx_buf_list[rd_index] = skb_tmp; 1654 1655 if (reg->pfu_enabled) { 1656 desc2 = card->rxbd_ring[rd_index]; 1657 desc2->paddr = buf_pa; 1658 desc2->len = skb_tmp->len; 1659 desc2->frag_len = skb_tmp->len; 1660 desc2->offset = 0; 1661 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; 1662 } else { 1663 desc = card->rxbd_ring[rd_index]; 1664 desc->paddr = buf_pa; 1665 desc->len = skb_tmp->len; 1666 desc->flags = 0; 1667 } 1668 1669 if ((++card->rxbd_rdptr & reg->rx_mask) == 1670 MWIFIEX_MAX_TXRX_BD) { 1671 card->rxbd_rdptr = ((card->rxbd_rdptr & 1672 reg->rx_rollover_ind) ^ 1673 reg->rx_rollover_ind); 1674 } 1675 mwifiex_dbg(adapter, DATA, 1676 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", 1677 card->rxbd_rdptr, wrptr); 1678 1679 tx_val = card->txbd_wrptr & reg->tx_wrap_mask; 1680 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1681 if (mwifiex_write_reg(adapter, reg->rx_rdptr, 1682 card->rxbd_rdptr | tx_val)) { 1683 mwifiex_dbg(adapter, DATA, 1684 "RECV DATA: failed to write reg->rx_rdptr\n"); 1685 ret = -1; 1686 goto done; 1687 } 1688 1689 /* Read the RX ring Write pointer set by firmware */ 1690 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1691 mwifiex_dbg(adapter, ERROR, 1692 "RECV DATA: failed to read reg->rx_wrptr\n"); 1693 ret = -1; 1694 goto done; 1695 } 1696 mwifiex_dbg(adapter, DATA, 1697 "info: RECV DATA: Rcvd packet from fw successfully\n"); 1698 card->rxbd_wrptr = wrptr; 1699 } 1700 1701 done: 1702 return ret; 1703 } 1704 1705 /* 1706 * This function downloads the boot command to device 1707 */ 1708 static int 1709 mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1710 { 1711 dma_addr_t buf_pa; 1712 struct pcie_service_card *card = adapter->card; 1713 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1714 1715 if (!(skb->data && skb->len)) { 1716 mwifiex_dbg(adapter, ERROR, 1717 "Invalid parameter in %s <%p. len %d>\n", 1718 __func__, skb->data, skb->len); 1719 return -1; 1720 } 1721 1722 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1723 return -1; 1724 1725 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1726 1727 /* Write the lower 32bits of the physical address to low command 1728 * address scratch register 1729 */ 1730 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { 1731 mwifiex_dbg(adapter, ERROR, 1732 "%s: failed to write download command to boot code.\n", 1733 __func__); 1734 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1735 return -1; 1736 } 1737 1738 /* Write the upper 32bits of the physical address to high command 1739 * address scratch register 1740 */ 1741 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1742 (u32)((u64)buf_pa >> 32))) { 1743 mwifiex_dbg(adapter, ERROR, 1744 "%s: failed to write download command to boot code.\n", 1745 __func__); 1746 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1747 return -1; 1748 } 1749 1750 /* Write the command length to cmd_size scratch register */ 1751 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { 1752 mwifiex_dbg(adapter, ERROR, 1753 "%s: failed to write command len to cmd_size scratch reg\n", 1754 __func__); 1755 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1756 return -1; 1757 } 1758 1759 /* Ring the door bell */ 1760 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1761 CPU_INTR_DOOR_BELL)) { 1762 mwifiex_dbg(adapter, ERROR, 1763 "%s: failed to assert door-bell intr\n", __func__); 1764 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1765 return -1; 1766 } 1767 1768 return 0; 1769 } 1770 1771 /* This function init rx port in firmware which in turn enables to receive data 1772 * from device before transmitting any packet. 1773 */ 1774 static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) 1775 { 1776 struct pcie_service_card *card = adapter->card; 1777 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1778 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; 1779 1780 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1781 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | 1782 tx_wrap)) { 1783 mwifiex_dbg(adapter, ERROR, 1784 "RECV DATA: failed to write reg->rx_rdptr\n"); 1785 return -1; 1786 } 1787 return 0; 1788 } 1789 1790 /* This function downloads commands to the device 1791 */ 1792 static int 1793 mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1794 { 1795 struct pcie_service_card *card = adapter->card; 1796 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1797 int ret = 0; 1798 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; 1799 u8 *payload = (u8 *)skb->data; 1800 1801 if (!(skb->data && skb->len)) { 1802 mwifiex_dbg(adapter, ERROR, 1803 "Invalid parameter in %s <%p, %#x>\n", 1804 __func__, skb->data, skb->len); 1805 return -1; 1806 } 1807 1808 /* Make sure a command response buffer is available */ 1809 if (!card->cmdrsp_buf) { 1810 mwifiex_dbg(adapter, ERROR, 1811 "No response buffer available, send command failed\n"); 1812 return -EBUSY; 1813 } 1814 1815 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1816 mwifiex_pm_wakeup_card(adapter); 1817 1818 adapter->cmd_sent = true; 1819 1820 put_unaligned_le16((u16)skb->len, &payload[0]); 1821 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); 1822 1823 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1824 return -1; 1825 1826 card->cmd_buf = skb; 1827 /* 1828 * Need to keep a reference, since core driver might free up this 1829 * buffer before we've unmapped it. 1830 */ 1831 skb_get(skb); 1832 1833 /* To send a command, the driver will: 1834 1. Write the 64bit physical address of the data buffer to 1835 cmd response address low + cmd response address high 1836 2. Ring the door bell (i.e. set the door bell interrupt) 1837 1838 In response to door bell interrupt, the firmware will perform 1839 the DMA of the command packet (first header to obtain the total 1840 length and then rest of the command). 1841 */ 1842 1843 if (card->cmdrsp_buf) { 1844 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); 1845 /* Write the lower 32bits of the cmdrsp buffer physical 1846 address */ 1847 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 1848 (u32)cmdrsp_buf_pa)) { 1849 mwifiex_dbg(adapter, ERROR, 1850 "Failed to write download cmd to boot code.\n"); 1851 ret = -1; 1852 goto done; 1853 } 1854 /* Write the upper 32bits of the cmdrsp buffer physical 1855 address */ 1856 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 1857 (u32)((u64)cmdrsp_buf_pa >> 32))) { 1858 mwifiex_dbg(adapter, ERROR, 1859 "Failed to write download cmd to boot code.\n"); 1860 ret = -1; 1861 goto done; 1862 } 1863 } 1864 1865 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); 1866 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ 1867 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, 1868 (u32)cmd_buf_pa)) { 1869 mwifiex_dbg(adapter, ERROR, 1870 "Failed to write download cmd to boot code.\n"); 1871 ret = -1; 1872 goto done; 1873 } 1874 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ 1875 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1876 (u32)((u64)cmd_buf_pa >> 32))) { 1877 mwifiex_dbg(adapter, ERROR, 1878 "Failed to write download cmd to boot code.\n"); 1879 ret = -1; 1880 goto done; 1881 } 1882 1883 /* Write the command length to reg->cmd_size */ 1884 if (mwifiex_write_reg(adapter, reg->cmd_size, 1885 card->cmd_buf->len)) { 1886 mwifiex_dbg(adapter, ERROR, 1887 "Failed to write cmd len to reg->cmd_size\n"); 1888 ret = -1; 1889 goto done; 1890 } 1891 1892 /* Ring the door bell */ 1893 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1894 CPU_INTR_DOOR_BELL)) { 1895 mwifiex_dbg(adapter, ERROR, 1896 "Failed to assert door-bell intr\n"); 1897 ret = -1; 1898 goto done; 1899 } 1900 1901 done: 1902 if (ret) 1903 adapter->cmd_sent = false; 1904 1905 return 0; 1906 } 1907 1908 /* 1909 * This function handles command complete interrupt 1910 */ 1911 static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) 1912 { 1913 struct pcie_service_card *card = adapter->card; 1914 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1915 struct sk_buff *skb = card->cmdrsp_buf; 1916 int count = 0; 1917 u16 rx_len; 1918 1919 mwifiex_dbg(adapter, CMD, 1920 "info: Rx CMD Response\n"); 1921 1922 if (adapter->curr_cmd) 1923 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); 1924 else 1925 dma_sync_single_for_cpu(&card->dev->dev, 1926 MWIFIEX_SKB_DMA_ADDR(skb), 1927 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); 1928 1929 /* Unmap the command as a response has been received. */ 1930 if (card->cmd_buf) { 1931 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1932 DMA_TO_DEVICE); 1933 dev_kfree_skb_any(card->cmd_buf); 1934 card->cmd_buf = NULL; 1935 } 1936 1937 rx_len = get_unaligned_le16(skb->data); 1938 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 1939 skb_trim(skb, rx_len); 1940 1941 if (!adapter->curr_cmd) { 1942 if (adapter->ps_state == PS_STATE_SLEEP_CFM) { 1943 dma_sync_single_for_device(&card->dev->dev, 1944 MWIFIEX_SKB_DMA_ADDR(skb), 1945 MWIFIEX_SLEEP_COOKIE_SIZE, 1946 DMA_FROM_DEVICE); 1947 if (mwifiex_write_reg(adapter, 1948 PCIE_CPU_INT_EVENT, 1949 CPU_INTR_SLEEP_CFM_DONE)) { 1950 mwifiex_dbg(adapter, ERROR, 1951 "Write register failed\n"); 1952 return -1; 1953 } 1954 mwifiex_delay_for_sleep_cookie(adapter, 1955 MWIFIEX_MAX_DELAY_COUNT); 1956 mwifiex_unmap_pci_memory(adapter, skb, 1957 DMA_FROM_DEVICE); 1958 skb_pull(skb, adapter->intf_hdr_len); 1959 while (reg->sleep_cookie && (count++ < 10) && 1960 mwifiex_pcie_ok_to_access_hw(adapter)) 1961 usleep_range(50, 60); 1962 mwifiex_pcie_enable_host_int(adapter); 1963 mwifiex_process_sleep_confirm_resp(adapter, skb->data, 1964 skb->len); 1965 } else { 1966 mwifiex_dbg(adapter, ERROR, 1967 "There is no command but got cmdrsp\n"); 1968 } 1969 memcpy(adapter->upld_buf, skb->data, 1970 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); 1971 skb_push(skb, adapter->intf_hdr_len); 1972 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1973 DMA_FROM_DEVICE)) 1974 return -1; 1975 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { 1976 skb_pull(skb, adapter->intf_hdr_len); 1977 adapter->curr_cmd->resp_skb = skb; 1978 adapter->cmd_resp_received = true; 1979 /* Take the pointer and set it to CMD node and will 1980 return in the response complete callback */ 1981 card->cmdrsp_buf = NULL; 1982 1983 /* Clear the cmd-rsp buffer address in scratch registers. This 1984 will prevent firmware from writing to the same response 1985 buffer again. */ 1986 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { 1987 mwifiex_dbg(adapter, ERROR, 1988 "cmd_done: failed to clear cmd_rsp_addr_lo\n"); 1989 return -1; 1990 } 1991 /* Write the upper 32bits of the cmdrsp buffer physical 1992 address */ 1993 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { 1994 mwifiex_dbg(adapter, ERROR, 1995 "cmd_done: failed to clear cmd_rsp_addr_hi\n"); 1996 return -1; 1997 } 1998 } 1999 2000 return 0; 2001 } 2002 2003 /* 2004 * Command Response processing complete handler 2005 */ 2006 static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, 2007 struct sk_buff *skb) 2008 { 2009 struct pcie_service_card *card = adapter->card; 2010 2011 if (skb) { 2012 card->cmdrsp_buf = skb; 2013 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); 2014 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 2015 DMA_FROM_DEVICE)) 2016 return -1; 2017 } 2018 2019 return 0; 2020 } 2021 2022 /* 2023 * This function handles firmware event ready interrupt 2024 */ 2025 static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) 2026 { 2027 struct pcie_service_card *card = adapter->card; 2028 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2029 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 2030 u32 wrptr, event; 2031 struct mwifiex_evt_buf_desc *desc; 2032 2033 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 2034 mwifiex_pm_wakeup_card(adapter); 2035 2036 if (adapter->event_received) { 2037 mwifiex_dbg(adapter, EVENT, 2038 "info: Event being processed,\t" 2039 "do not process this interrupt just yet\n"); 2040 return 0; 2041 } 2042 2043 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2044 mwifiex_dbg(adapter, ERROR, 2045 "info: Invalid read pointer...\n"); 2046 return -1; 2047 } 2048 2049 /* Read the event ring write pointer set by firmware */ 2050 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2051 mwifiex_dbg(adapter, ERROR, 2052 "EventReady: failed to read reg->evt_wrptr\n"); 2053 return -1; 2054 } 2055 2056 mwifiex_dbg(adapter, EVENT, 2057 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", 2058 card->evtbd_rdptr, wrptr); 2059 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr 2060 & MWIFIEX_EVTBD_MASK)) || 2061 ((wrptr & reg->evt_rollover_ind) == 2062 (card->evtbd_rdptr & reg->evt_rollover_ind))) { 2063 struct sk_buff *skb_cmd; 2064 __le16 data_len = 0; 2065 u16 evt_len; 2066 2067 mwifiex_dbg(adapter, INFO, 2068 "info: Read Index: %d\n", rdptr); 2069 skb_cmd = card->evt_buf_list[rdptr]; 2070 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); 2071 2072 /* Take the pointer and set it to event pointer in adapter 2073 and will return back after event handling callback */ 2074 card->evt_buf_list[rdptr] = NULL; 2075 desc = card->evtbd_ring[rdptr]; 2076 memset(desc, 0, sizeof(*desc)); 2077 2078 event = get_unaligned_le32( 2079 &skb_cmd->data[adapter->intf_hdr_len]); 2080 adapter->event_cause = event; 2081 /* The first 4bytes will be the event transfer header 2082 len is 2 bytes followed by type which is 2 bytes */ 2083 memcpy(&data_len, skb_cmd->data, sizeof(__le16)); 2084 evt_len = le16_to_cpu(data_len); 2085 skb_trim(skb_cmd, evt_len); 2086 skb_pull(skb_cmd, adapter->intf_hdr_len); 2087 mwifiex_dbg(adapter, EVENT, 2088 "info: Event length: %d\n", evt_len); 2089 2090 if (evt_len > MWIFIEX_EVENT_HEADER_LEN && 2091 evt_len < MAX_EVENT_SIZE) 2092 memcpy(adapter->event_body, skb_cmd->data + 2093 MWIFIEX_EVENT_HEADER_LEN, evt_len - 2094 MWIFIEX_EVENT_HEADER_LEN); 2095 2096 adapter->event_received = true; 2097 adapter->event_skb = skb_cmd; 2098 2099 /* Do not update the event read pointer here, wait till the 2100 buffer is released. This is just to make things simpler, 2101 we need to find a better method of managing these buffers. 2102 */ 2103 } else { 2104 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 2105 CPU_INTR_EVENT_DONE)) { 2106 mwifiex_dbg(adapter, ERROR, 2107 "Write register failed\n"); 2108 return -1; 2109 } 2110 } 2111 2112 return 0; 2113 } 2114 2115 /* 2116 * Event processing complete handler 2117 */ 2118 static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, 2119 struct sk_buff *skb) 2120 { 2121 struct pcie_service_card *card = adapter->card; 2122 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2123 int ret = 0; 2124 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 2125 u32 wrptr; 2126 struct mwifiex_evt_buf_desc *desc; 2127 2128 if (!skb) 2129 return 0; 2130 2131 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2132 mwifiex_dbg(adapter, ERROR, 2133 "event_complete: Invalid rdptr 0x%x\n", 2134 rdptr); 2135 return -EINVAL; 2136 } 2137 2138 /* Read the event ring write pointer set by firmware */ 2139 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2140 mwifiex_dbg(adapter, ERROR, 2141 "event_complete: failed to read reg->evt_wrptr\n"); 2142 return -1; 2143 } 2144 2145 if (!card->evt_buf_list[rdptr]) { 2146 skb_push(skb, adapter->intf_hdr_len); 2147 skb_put(skb, MAX_EVENT_SIZE - skb->len); 2148 if (mwifiex_map_pci_memory(adapter, skb, 2149 MAX_EVENT_SIZE, 2150 DMA_FROM_DEVICE)) 2151 return -1; 2152 card->evt_buf_list[rdptr] = skb; 2153 desc = card->evtbd_ring[rdptr]; 2154 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); 2155 desc->len = (u16)skb->len; 2156 desc->flags = 0; 2157 skb = NULL; 2158 } else { 2159 mwifiex_dbg(adapter, ERROR, 2160 "info: ERROR: buf still valid at index %d, <%p, %p>\n", 2161 rdptr, card->evt_buf_list[rdptr], skb); 2162 } 2163 2164 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { 2165 card->evtbd_rdptr = ((card->evtbd_rdptr & 2166 reg->evt_rollover_ind) ^ 2167 reg->evt_rollover_ind); 2168 } 2169 2170 mwifiex_dbg(adapter, EVENT, 2171 "info: Updated <Rd: 0x%x, Wr: 0x%x>", 2172 card->evtbd_rdptr, wrptr); 2173 2174 /* Write the event ring read pointer in to reg->evt_rdptr */ 2175 if (mwifiex_write_reg(adapter, reg->evt_rdptr, 2176 card->evtbd_rdptr)) { 2177 mwifiex_dbg(adapter, ERROR, 2178 "event_complete: failed to read reg->evt_rdptr\n"); 2179 return -1; 2180 } 2181 2182 mwifiex_dbg(adapter, EVENT, 2183 "info: Check Events Again\n"); 2184 ret = mwifiex_pcie_process_event_ready(adapter); 2185 2186 return ret; 2187 } 2188 2189 /* Combo firmware image is a combination of 2190 * (1) combo crc heaer, start with CMD5 2191 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1. 2192 * (3) wifi image. 2193 * 2194 * This function bypass the header and bluetooth part, return 2195 * the offset of tail wifi-only part. If the image is already wifi-only, 2196 * that is start with CMD1, return 0. 2197 */ 2198 2199 static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter, 2200 const void *firmware, u32 firmware_len) { 2201 const struct mwifiex_fw_data *fwdata; 2202 u32 offset = 0, data_len, dnld_cmd; 2203 int ret = 0; 2204 bool cmd7_before = false, first_cmd = false; 2205 2206 while (1) { 2207 /* Check for integer and buffer overflow */ 2208 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) || 2209 offset + sizeof(fwdata->header) >= firmware_len) { 2210 mwifiex_dbg(adapter, ERROR, 2211 "extract wifi-only fw failure!\n"); 2212 ret = -1; 2213 goto done; 2214 } 2215 2216 fwdata = firmware + offset; 2217 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd); 2218 data_len = le32_to_cpu(fwdata->header.data_length); 2219 2220 /* Skip past header */ 2221 offset += sizeof(fwdata->header); 2222 2223 switch (dnld_cmd) { 2224 case MWIFIEX_FW_DNLD_CMD_1: 2225 if (offset + data_len < data_len) { 2226 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2227 ret = -1; 2228 goto done; 2229 } 2230 2231 /* Image start with cmd1, already wifi-only firmware */ 2232 if (!first_cmd) { 2233 mwifiex_dbg(adapter, MSG, 2234 "input wifi-only firmware\n"); 2235 return 0; 2236 } 2237 2238 if (!cmd7_before) { 2239 mwifiex_dbg(adapter, ERROR, 2240 "no cmd7 before cmd1!\n"); 2241 ret = -1; 2242 goto done; 2243 } 2244 offset += data_len; 2245 break; 2246 case MWIFIEX_FW_DNLD_CMD_5: 2247 first_cmd = true; 2248 /* Check for integer overflow */ 2249 if (offset + data_len < data_len) { 2250 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2251 ret = -1; 2252 goto done; 2253 } 2254 offset += data_len; 2255 break; 2256 case MWIFIEX_FW_DNLD_CMD_6: 2257 first_cmd = true; 2258 /* Check for integer overflow */ 2259 if (offset + data_len < data_len) { 2260 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2261 ret = -1; 2262 goto done; 2263 } 2264 offset += data_len; 2265 if (offset >= firmware_len) { 2266 mwifiex_dbg(adapter, ERROR, 2267 "extract wifi-only fw failure!\n"); 2268 ret = -1; 2269 } else { 2270 ret = offset; 2271 } 2272 goto done; 2273 case MWIFIEX_FW_DNLD_CMD_7: 2274 first_cmd = true; 2275 cmd7_before = true; 2276 break; 2277 default: 2278 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n", 2279 dnld_cmd); 2280 ret = -1; 2281 goto done; 2282 } 2283 } 2284 2285 done: 2286 return ret; 2287 } 2288 2289 /* 2290 * This function downloads the firmware to the card. 2291 * 2292 * Firmware is downloaded to the card in blocks. Every block download 2293 * is tested for CRC errors, and retried a number of times before 2294 * returning failure. 2295 */ 2296 static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, 2297 struct mwifiex_fw_image *fw) 2298 { 2299 int ret; 2300 u8 *firmware = fw->fw_buf; 2301 u32 firmware_len = fw->fw_len; 2302 u32 offset = 0; 2303 struct sk_buff *skb; 2304 u32 txlen, tx_blocks = 0, tries, len, val; 2305 u32 block_retry_cnt = 0; 2306 struct pcie_service_card *card = adapter->card; 2307 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2308 2309 if (!firmware || !firmware_len) { 2310 mwifiex_dbg(adapter, ERROR, 2311 "No firmware image found! Terminating download\n"); 2312 return -1; 2313 } 2314 2315 mwifiex_dbg(adapter, INFO, 2316 "info: Downloading FW image (%d bytes)\n", 2317 firmware_len); 2318 2319 if (mwifiex_pcie_disable_host_int(adapter)) { 2320 mwifiex_dbg(adapter, ERROR, 2321 "%s: Disabling interrupts failed.\n", __func__); 2322 return -1; 2323 } 2324 2325 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 2326 if (!skb) { 2327 ret = -ENOMEM; 2328 goto done; 2329 } 2330 2331 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val); 2332 if (ret) { 2333 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n"); 2334 goto done; 2335 } 2336 2337 /* PCIE FLR case: extract wifi part from combo firmware*/ 2338 if (val == MWIFIEX_PCIE_FLR_HAPPENS) { 2339 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len); 2340 if (ret < 0) { 2341 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n"); 2342 goto done; 2343 } 2344 offset = ret; 2345 mwifiex_dbg(adapter, MSG, 2346 "info: dnld wifi firmware from %d bytes\n", offset); 2347 } 2348 2349 /* Perform firmware data transfer */ 2350 do { 2351 u32 ireg_intr = 0; 2352 2353 /* More data? */ 2354 if (offset >= firmware_len) 2355 break; 2356 2357 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2358 ret = mwifiex_read_reg(adapter, reg->cmd_size, 2359 &len); 2360 if (ret) { 2361 mwifiex_dbg(adapter, FATAL, 2362 "Failed reading len from boot code\n"); 2363 goto done; 2364 } 2365 if (len) 2366 break; 2367 usleep_range(10, 20); 2368 } 2369 2370 if (!len) { 2371 break; 2372 } else if (len > MWIFIEX_UPLD_SIZE) { 2373 mwifiex_dbg(adapter, ERROR, 2374 "FW download failure @ %d, invalid length %d\n", 2375 offset, len); 2376 ret = -1; 2377 goto done; 2378 } 2379 2380 txlen = len; 2381 2382 if (len & BIT(0)) { 2383 block_retry_cnt++; 2384 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { 2385 mwifiex_dbg(adapter, ERROR, 2386 "FW download failure @ %d, over max\t" 2387 "retry count\n", offset); 2388 ret = -1; 2389 goto done; 2390 } 2391 mwifiex_dbg(adapter, ERROR, 2392 "FW CRC error indicated by the\t" 2393 "helper: len = 0x%04X, txlen = %d\n", 2394 len, txlen); 2395 len &= ~BIT(0); 2396 /* Setting this to 0 to resend from same offset */ 2397 txlen = 0; 2398 } else { 2399 block_retry_cnt = 0; 2400 /* Set blocksize to transfer - checking for 2401 last block */ 2402 if (firmware_len - offset < txlen) 2403 txlen = firmware_len - offset; 2404 2405 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / 2406 card->pcie.blksz_fw_dl; 2407 2408 /* Copy payload to buffer */ 2409 memmove(skb->data, &firmware[offset], txlen); 2410 } 2411 2412 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 2413 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); 2414 2415 /* Send the boot command to device */ 2416 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { 2417 mwifiex_dbg(adapter, ERROR, 2418 "Failed to send firmware download command\n"); 2419 ret = -1; 2420 goto done; 2421 } 2422 2423 /* Wait for the command done interrupt */ 2424 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2425 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, 2426 &ireg_intr)) { 2427 mwifiex_dbg(adapter, ERROR, 2428 "%s: Failed to read\t" 2429 "interrupt status during fw dnld.\n", 2430 __func__); 2431 mwifiex_unmap_pci_memory(adapter, skb, 2432 DMA_TO_DEVICE); 2433 ret = -1; 2434 goto done; 2435 } 2436 if (!(ireg_intr & CPU_INTR_DOOR_BELL)) 2437 break; 2438 usleep_range(10, 20); 2439 } 2440 if (ireg_intr & CPU_INTR_DOOR_BELL) { 2441 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", 2442 __func__); 2443 mwifiex_unmap_pci_memory(adapter, skb, 2444 DMA_TO_DEVICE); 2445 ret = -1; 2446 goto done; 2447 } 2448 2449 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 2450 2451 offset += txlen; 2452 } while (true); 2453 2454 mwifiex_dbg(adapter, MSG, 2455 "info: FW download over, size %d bytes\n", offset); 2456 2457 ret = 0; 2458 2459 done: 2460 dev_kfree_skb_any(skb); 2461 return ret; 2462 } 2463 2464 /* 2465 * This function checks the firmware status in card. 2466 */ 2467 static int 2468 mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) 2469 { 2470 int ret = 0; 2471 u32 firmware_stat; 2472 struct pcie_service_card *card = adapter->card; 2473 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2474 u32 tries; 2475 2476 /* Mask spurios interrupts */ 2477 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, 2478 HOST_INTR_MASK)) { 2479 mwifiex_dbg(adapter, ERROR, 2480 "Write register failed\n"); 2481 return -1; 2482 } 2483 2484 mwifiex_dbg(adapter, INFO, 2485 "Setting driver ready signature\n"); 2486 if (mwifiex_write_reg(adapter, reg->drv_rdy, 2487 FIRMWARE_READY_PCIE)) { 2488 mwifiex_dbg(adapter, ERROR, 2489 "Failed to write driver ready signature\n"); 2490 return -1; 2491 } 2492 2493 /* Wait for firmware initialization event */ 2494 for (tries = 0; tries < poll_num; tries++) { 2495 if (mwifiex_read_reg(adapter, reg->fw_status, 2496 &firmware_stat)) 2497 ret = -1; 2498 else 2499 ret = 0; 2500 2501 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>", 2502 tries, ret, firmware_stat); 2503 2504 if (ret) 2505 continue; 2506 if (firmware_stat == FIRMWARE_READY_PCIE) { 2507 ret = 0; 2508 break; 2509 } else { 2510 msleep(100); 2511 ret = -1; 2512 } 2513 } 2514 2515 return ret; 2516 } 2517 2518 /* This function checks if WLAN is the winner. 2519 */ 2520 static int 2521 mwifiex_check_winner_status(struct mwifiex_adapter *adapter) 2522 { 2523 u32 winner = 0; 2524 int ret = 0; 2525 struct pcie_service_card *card = adapter->card; 2526 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2527 2528 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) { 2529 ret = -1; 2530 } else if (!winner) { 2531 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n"); 2532 adapter->winner = 1; 2533 } else { 2534 mwifiex_dbg(adapter, ERROR, 2535 "PCI-E is not the winner <%#x>", winner); 2536 } 2537 2538 return ret; 2539 } 2540 2541 /* 2542 * This function reads the interrupt status from card. 2543 */ 2544 static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter, 2545 int msg_id) 2546 { 2547 u32 pcie_ireg; 2548 unsigned long flags; 2549 struct pcie_service_card *card = adapter->card; 2550 2551 if (card->msi_enable) { 2552 spin_lock_irqsave(&adapter->int_lock, flags); 2553 adapter->int_status = 1; 2554 spin_unlock_irqrestore(&adapter->int_lock, flags); 2555 return; 2556 } 2557 2558 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 2559 return; 2560 2561 if (card->msix_enable && msg_id >= 0) { 2562 pcie_ireg = BIT(msg_id); 2563 } else { 2564 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2565 &pcie_ireg)) { 2566 mwifiex_dbg(adapter, ERROR, "Read register failed\n"); 2567 return; 2568 } 2569 2570 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) 2571 return; 2572 2573 2574 mwifiex_pcie_disable_host_int(adapter); 2575 2576 /* Clear the pending interrupts */ 2577 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, 2578 ~pcie_ireg)) { 2579 mwifiex_dbg(adapter, ERROR, 2580 "Write register failed\n"); 2581 return; 2582 } 2583 } 2584 2585 if (!adapter->pps_uapsd_mode && 2586 adapter->ps_state == PS_STATE_SLEEP && 2587 mwifiex_pcie_ok_to_access_hw(adapter)) { 2588 /* Potentially for PCIe we could get other 2589 * interrupts like shared. Don't change power 2590 * state until cookie is set 2591 */ 2592 adapter->ps_state = PS_STATE_AWAKE; 2593 adapter->pm_wakeup_fw_try = false; 2594 del_timer(&adapter->wakeup_timer); 2595 } 2596 2597 spin_lock_irqsave(&adapter->int_lock, flags); 2598 adapter->int_status |= pcie_ireg; 2599 spin_unlock_irqrestore(&adapter->int_lock, flags); 2600 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); 2601 } 2602 2603 /* 2604 * Interrupt handler for PCIe root port 2605 * 2606 * This function reads the interrupt status from firmware and assigns 2607 * the main process in workqueue which will handle the interrupt. 2608 */ 2609 static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) 2610 { 2611 struct mwifiex_msix_context *ctx = context; 2612 struct pci_dev *pdev = ctx->dev; 2613 struct pcie_service_card *card; 2614 struct mwifiex_adapter *adapter; 2615 2616 card = pci_get_drvdata(pdev); 2617 2618 if (!card->adapter) { 2619 pr_err("info: %s: card=%p adapter=%p\n", __func__, card, 2620 card ? card->adapter : NULL); 2621 goto exit; 2622 } 2623 adapter = card->adapter; 2624 2625 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags)) 2626 goto exit; 2627 2628 if (card->msix_enable) 2629 mwifiex_interrupt_status(adapter, ctx->msg_id); 2630 else 2631 mwifiex_interrupt_status(adapter, -1); 2632 2633 mwifiex_queue_main_work(adapter); 2634 2635 exit: 2636 return IRQ_HANDLED; 2637 } 2638 2639 /* 2640 * This function checks the current interrupt status. 2641 * 2642 * The following interrupts are checked and handled by this function - 2643 * - Data sent 2644 * - Command sent 2645 * - Command received 2646 * - Packets received 2647 * - Events received 2648 * 2649 * In case of Rx packets received, the packets are uploaded from card to 2650 * host and processed accordingly. 2651 */ 2652 static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) 2653 { 2654 int ret; 2655 u32 pcie_ireg = 0; 2656 unsigned long flags; 2657 struct pcie_service_card *card = adapter->card; 2658 2659 spin_lock_irqsave(&adapter->int_lock, flags); 2660 if (!card->msi_enable) { 2661 /* Clear out unused interrupts */ 2662 pcie_ireg = adapter->int_status; 2663 } 2664 adapter->int_status = 0; 2665 spin_unlock_irqrestore(&adapter->int_lock, flags); 2666 2667 if (card->msi_enable) { 2668 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 2669 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2670 &pcie_ireg)) { 2671 mwifiex_dbg(adapter, ERROR, 2672 "Read register failed\n"); 2673 return -1; 2674 } 2675 2676 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { 2677 if (mwifiex_write_reg(adapter, 2678 PCIE_HOST_INT_STATUS, 2679 ~pcie_ireg)) { 2680 mwifiex_dbg(adapter, ERROR, 2681 "Write register failed\n"); 2682 return -1; 2683 } 2684 if (!adapter->pps_uapsd_mode && 2685 adapter->ps_state == PS_STATE_SLEEP) { 2686 adapter->ps_state = PS_STATE_AWAKE; 2687 adapter->pm_wakeup_fw_try = false; 2688 del_timer(&adapter->wakeup_timer); 2689 } 2690 } 2691 } 2692 } 2693 2694 if (pcie_ireg & HOST_INTR_DNLD_DONE) { 2695 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n"); 2696 ret = mwifiex_pcie_send_data_complete(adapter); 2697 if (ret) 2698 return ret; 2699 } 2700 if (pcie_ireg & HOST_INTR_UPLD_RDY) { 2701 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n"); 2702 ret = mwifiex_pcie_process_recv_data(adapter); 2703 if (ret) 2704 return ret; 2705 } 2706 if (pcie_ireg & HOST_INTR_EVENT_RDY) { 2707 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n"); 2708 ret = mwifiex_pcie_process_event_ready(adapter); 2709 if (ret) 2710 return ret; 2711 } 2712 if (pcie_ireg & HOST_INTR_CMD_DONE) { 2713 if (adapter->cmd_sent) { 2714 mwifiex_dbg(adapter, INTR, 2715 "info: CMD sent Interrupt\n"); 2716 adapter->cmd_sent = false; 2717 } 2718 /* Handle command response */ 2719 ret = mwifiex_pcie_process_cmd_complete(adapter); 2720 if (ret) 2721 return ret; 2722 } 2723 2724 mwifiex_dbg(adapter, INTR, 2725 "info: cmd_sent=%d data_sent=%d\n", 2726 adapter->cmd_sent, adapter->data_sent); 2727 if (!card->msi_enable && !card->msix_enable && 2728 adapter->ps_state != PS_STATE_SLEEP) 2729 mwifiex_pcie_enable_host_int(adapter); 2730 2731 return 0; 2732 } 2733 2734 /* 2735 * This function downloads data from driver to card. 2736 * 2737 * Both commands and data packets are transferred to the card by this 2738 * function. 2739 * 2740 * This function adds the PCIE specific header to the front of the buffer 2741 * before transferring. The header contains the length of the packet and 2742 * the type. The firmware handles the packets based upon this set type. 2743 */ 2744 static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, 2745 struct sk_buff *skb, 2746 struct mwifiex_tx_param *tx_param) 2747 { 2748 if (!skb) { 2749 mwifiex_dbg(adapter, ERROR, 2750 "Passed NULL skb to %s\n", __func__); 2751 return -1; 2752 } 2753 2754 if (type == MWIFIEX_TYPE_DATA) 2755 return mwifiex_pcie_send_data(adapter, skb, tx_param); 2756 else if (type == MWIFIEX_TYPE_CMD) 2757 return mwifiex_pcie_send_cmd(adapter, skb); 2758 2759 return 0; 2760 } 2761 2762 /* Function to dump PCIE scratch registers in case of FW crash 2763 */ 2764 static int 2765 mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf) 2766 { 2767 char *p = drv_buf; 2768 char buf[256], *ptr; 2769 int i; 2770 u32 value; 2771 struct pcie_service_card *card = adapter->card; 2772 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2773 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG, 2774 PCIE_SCRATCH_14_REG, 2775 PCIE_SCRATCH_15_REG}; 2776 2777 if (!p) 2778 return 0; 2779 2780 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n"); 2781 2782 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) { 2783 mwifiex_dbg(adapter, ERROR, "failed to read firmware status"); 2784 return 0; 2785 } 2786 2787 ptr = buf; 2788 mwifiex_dbg(adapter, MSG, "pcie scratch register:"); 2789 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { 2790 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value); 2791 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", 2792 pcie_scratch_reg[i], value); 2793 } 2794 2795 mwifiex_dbg(adapter, MSG, "%s\n", buf); 2796 p += sprintf(p, "%s\n", buf); 2797 2798 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n"); 2799 2800 return p - drv_buf; 2801 } 2802 2803 /* This function read/write firmware */ 2804 static enum rdwr_status 2805 mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag) 2806 { 2807 int ret, tries; 2808 u8 ctrl_data; 2809 u32 fw_status; 2810 struct pcie_service_card *card = adapter->card; 2811 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2812 2813 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) 2814 return RDWR_STATUS_FAILURE; 2815 2816 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2817 reg->fw_dump_host_ready); 2818 if (ret) { 2819 mwifiex_dbg(adapter, ERROR, 2820 "PCIE write err\n"); 2821 return RDWR_STATUS_FAILURE; 2822 } 2823 2824 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2825 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data); 2826 if (ctrl_data == FW_DUMP_DONE) 2827 return RDWR_STATUS_SUCCESS; 2828 if (doneflag && ctrl_data == doneflag) 2829 return RDWR_STATUS_DONE; 2830 if (ctrl_data != reg->fw_dump_host_ready) { 2831 mwifiex_dbg(adapter, WARN, 2832 "The ctrl reg was changed, re-try again!\n"); 2833 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2834 reg->fw_dump_host_ready); 2835 if (ret) { 2836 mwifiex_dbg(adapter, ERROR, 2837 "PCIE write err\n"); 2838 return RDWR_STATUS_FAILURE; 2839 } 2840 } 2841 usleep_range(100, 200); 2842 } 2843 2844 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n"); 2845 return RDWR_STATUS_FAILURE; 2846 } 2847 2848 /* This function dump firmware memory to file */ 2849 static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter) 2850 { 2851 struct pcie_service_card *card = adapter->card; 2852 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; 2853 unsigned int reg, reg_start, reg_end; 2854 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num; 2855 u8 idx, i, read_reg, doneflag = 0; 2856 enum rdwr_status stat; 2857 u32 memory_size; 2858 int ret; 2859 2860 if (!card->pcie.can_dump_fw) 2861 return; 2862 2863 for (idx = 0; idx < adapter->num_mem_types; idx++) { 2864 struct memory_type_mapping *entry = 2865 &adapter->mem_type_mapping_tbl[idx]; 2866 2867 if (entry->mem_ptr) { 2868 vfree(entry->mem_ptr); 2869 entry->mem_ptr = NULL; 2870 } 2871 entry->mem_size = 0; 2872 } 2873 2874 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n"); 2875 2876 /* Read the number of the memories which will dump */ 2877 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2878 if (stat == RDWR_STATUS_FAILURE) 2879 return; 2880 2881 reg = creg->fw_dump_start; 2882 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num); 2883 2884 /* W8997 chipset firmware dump will be restore in single region*/ 2885 if (fw_dump_num == 0) 2886 dump_num = 1; 2887 else 2888 dump_num = fw_dump_num; 2889 2890 /* Read the length of every memory which will dump */ 2891 for (idx = 0; idx < dump_num; idx++) { 2892 struct memory_type_mapping *entry = 2893 &adapter->mem_type_mapping_tbl[idx]; 2894 memory_size = 0; 2895 if (fw_dump_num != 0) { 2896 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2897 if (stat == RDWR_STATUS_FAILURE) 2898 return; 2899 2900 reg = creg->fw_dump_start; 2901 for (i = 0; i < 4; i++) { 2902 mwifiex_read_reg_byte(adapter, reg, &read_reg); 2903 memory_size |= (read_reg << (i * 8)); 2904 reg++; 2905 } 2906 } else { 2907 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE; 2908 } 2909 2910 if (memory_size == 0) { 2911 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n"); 2912 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl, 2913 creg->fw_dump_read_done); 2914 if (ret) { 2915 mwifiex_dbg(adapter, ERROR, "PCIE write err\n"); 2916 return; 2917 } 2918 break; 2919 } 2920 2921 mwifiex_dbg(adapter, DUMP, 2922 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); 2923 entry->mem_ptr = vmalloc(memory_size + 1); 2924 entry->mem_size = memory_size; 2925 if (!entry->mem_ptr) { 2926 mwifiex_dbg(adapter, ERROR, 2927 "Vmalloc %s failed\n", entry->mem_name); 2928 return; 2929 } 2930 dbg_ptr = entry->mem_ptr; 2931 end_ptr = dbg_ptr + memory_size; 2932 2933 doneflag = entry->done_flag; 2934 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n", 2935 entry->mem_name); 2936 2937 do { 2938 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2939 if (RDWR_STATUS_FAILURE == stat) 2940 return; 2941 2942 reg_start = creg->fw_dump_start; 2943 reg_end = creg->fw_dump_end; 2944 for (reg = reg_start; reg <= reg_end; reg++) { 2945 mwifiex_read_reg_byte(adapter, reg, dbg_ptr); 2946 if (dbg_ptr < end_ptr) { 2947 dbg_ptr++; 2948 continue; 2949 } 2950 mwifiex_dbg(adapter, ERROR, 2951 "pre-allocated buf not enough\n"); 2952 tmp_ptr = 2953 vzalloc(memory_size + MWIFIEX_SIZE_4K); 2954 if (!tmp_ptr) 2955 return; 2956 memcpy(tmp_ptr, entry->mem_ptr, memory_size); 2957 vfree(entry->mem_ptr); 2958 entry->mem_ptr = tmp_ptr; 2959 tmp_ptr = NULL; 2960 dbg_ptr = entry->mem_ptr + memory_size; 2961 memory_size += MWIFIEX_SIZE_4K; 2962 end_ptr = entry->mem_ptr + memory_size; 2963 } 2964 2965 if (stat != RDWR_STATUS_DONE) 2966 continue; 2967 2968 mwifiex_dbg(adapter, DUMP, 2969 "%s done: size=0x%tx\n", 2970 entry->mem_name, dbg_ptr - entry->mem_ptr); 2971 break; 2972 } while (true); 2973 } 2974 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n"); 2975 } 2976 2977 static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter) 2978 { 2979 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE); 2980 if (!adapter->devdump_data) { 2981 mwifiex_dbg(adapter, ERROR, 2982 "vzalloc devdump data failure!\n"); 2983 return; 2984 } 2985 2986 mwifiex_drv_info_dump(adapter); 2987 mwifiex_pcie_fw_dump(adapter); 2988 mwifiex_prepare_fw_dump_info(adapter); 2989 mwifiex_upload_device_dump(adapter); 2990 } 2991 2992 static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter) 2993 { 2994 struct pcie_service_card *card = adapter->card; 2995 2996 /* We can't afford to wait here; remove() might be waiting on us. If we 2997 * can't grab the device lock, maybe we'll get another chance later. 2998 */ 2999 pci_try_reset_function(card->dev); 3000 } 3001 3002 static void mwifiex_pcie_work(struct work_struct *work) 3003 { 3004 struct pcie_service_card *card = 3005 container_of(work, struct pcie_service_card, work); 3006 3007 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 3008 &card->work_flags)) 3009 mwifiex_pcie_device_dump_work(card->adapter); 3010 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, 3011 &card->work_flags)) 3012 mwifiex_pcie_card_reset_work(card->adapter); 3013 } 3014 3015 /* This function dumps FW information */ 3016 static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter) 3017 { 3018 struct pcie_service_card *card = adapter->card; 3019 3020 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 3021 &card->work_flags)) 3022 schedule_work(&card->work); 3023 } 3024 3025 static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter) 3026 { 3027 struct pcie_service_card *card = adapter->card; 3028 3029 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags)) 3030 schedule_work(&card->work); 3031 } 3032 3033 static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter) 3034 { 3035 struct pcie_service_card *card = adapter->card; 3036 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3037 int ret; 3038 3039 card->cmdrsp_buf = NULL; 3040 ret = mwifiex_pcie_create_txbd_ring(adapter); 3041 if (ret) { 3042 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n"); 3043 goto err_cre_txbd; 3044 } 3045 3046 ret = mwifiex_pcie_create_rxbd_ring(adapter); 3047 if (ret) { 3048 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n"); 3049 goto err_cre_rxbd; 3050 } 3051 3052 ret = mwifiex_pcie_create_evtbd_ring(adapter); 3053 if (ret) { 3054 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n"); 3055 goto err_cre_evtbd; 3056 } 3057 3058 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); 3059 if (ret) { 3060 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n"); 3061 goto err_alloc_cmdbuf; 3062 } 3063 3064 if (reg->sleep_cookie) { 3065 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); 3066 if (ret) { 3067 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n"); 3068 goto err_alloc_cookie; 3069 } 3070 } else { 3071 card->sleep_cookie_vbase = NULL; 3072 } 3073 3074 return 0; 3075 3076 err_alloc_cookie: 3077 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3078 err_alloc_cmdbuf: 3079 mwifiex_pcie_delete_evtbd_ring(adapter); 3080 err_cre_evtbd: 3081 mwifiex_pcie_delete_rxbd_ring(adapter); 3082 err_cre_rxbd: 3083 mwifiex_pcie_delete_txbd_ring(adapter); 3084 err_cre_txbd: 3085 return ret; 3086 } 3087 3088 static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter) 3089 { 3090 struct pcie_service_card *card = adapter->card; 3091 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3092 3093 if (reg->sleep_cookie) 3094 mwifiex_pcie_delete_sleep_cookie_buf(adapter); 3095 3096 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3097 mwifiex_pcie_delete_evtbd_ring(adapter); 3098 mwifiex_pcie_delete_rxbd_ring(adapter); 3099 mwifiex_pcie_delete_txbd_ring(adapter); 3100 } 3101 3102 /* 3103 * This function initializes the PCI-E host memory space, WCB rings, etc. 3104 */ 3105 static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) 3106 { 3107 struct pcie_service_card *card = adapter->card; 3108 int ret; 3109 struct pci_dev *pdev = card->dev; 3110 3111 pci_set_drvdata(pdev, card); 3112 3113 ret = pci_enable_device(pdev); 3114 if (ret) 3115 goto err_enable_dev; 3116 3117 pci_set_master(pdev); 3118 3119 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3120 if (ret) { 3121 pr_err("dma_set_mask(32) failed: %d\n", ret); 3122 goto err_set_dma_mask; 3123 } 3124 3125 ret = pci_request_region(pdev, 0, DRV_NAME); 3126 if (ret) { 3127 pr_err("req_reg(0) error\n"); 3128 goto err_req_region0; 3129 } 3130 card->pci_mmap = pci_iomap(pdev, 0, 0); 3131 if (!card->pci_mmap) { 3132 pr_err("iomap(0) error\n"); 3133 ret = -EIO; 3134 goto err_iomap0; 3135 } 3136 ret = pci_request_region(pdev, 2, DRV_NAME); 3137 if (ret) { 3138 pr_err("req_reg(2) error\n"); 3139 goto err_req_region2; 3140 } 3141 card->pci_mmap1 = pci_iomap(pdev, 2, 0); 3142 if (!card->pci_mmap1) { 3143 pr_err("iomap(2) error\n"); 3144 ret = -EIO; 3145 goto err_iomap2; 3146 } 3147 3148 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n", 3149 card->pci_mmap, card->pci_mmap1); 3150 3151 ret = mwifiex_pcie_alloc_buffers(adapter); 3152 if (ret) 3153 goto err_alloc_buffers; 3154 3155 return 0; 3156 3157 err_alloc_buffers: 3158 pci_iounmap(pdev, card->pci_mmap1); 3159 err_iomap2: 3160 pci_release_region(pdev, 2); 3161 err_req_region2: 3162 pci_iounmap(pdev, card->pci_mmap); 3163 err_iomap0: 3164 pci_release_region(pdev, 0); 3165 err_req_region0: 3166 err_set_dma_mask: 3167 pci_disable_device(pdev); 3168 err_enable_dev: 3169 return ret; 3170 } 3171 3172 /* 3173 * This function cleans up the allocated card buffers. 3174 */ 3175 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter) 3176 { 3177 struct pcie_service_card *card = adapter->card; 3178 struct pci_dev *pdev = card->dev; 3179 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3180 u32 fw_status; 3181 3182 /* Perform the cancel_work_sync() only when we're not resetting 3183 * the card. It's because that function never returns if we're 3184 * in reset path. If we're here when resetting the card, it means 3185 * that we failed to reset the card (reset failure path). 3186 */ 3187 if (!card->pci_reset_ongoing) { 3188 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n"); 3189 cancel_work_sync(&card->work); 3190 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n"); 3191 } else { 3192 mwifiex_dbg(adapter, MSG, 3193 "skipped cancel_work_sync() because we're in card reset failure path\n"); 3194 } 3195 3196 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 3197 if (fw_status == FIRMWARE_READY_PCIE) { 3198 mwifiex_dbg(adapter, INFO, 3199 "Clearing driver ready signature\n"); 3200 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3201 mwifiex_dbg(adapter, ERROR, 3202 "Failed to write driver not-ready signature\n"); 3203 } 3204 3205 pci_disable_device(pdev); 3206 3207 pci_iounmap(pdev, card->pci_mmap); 3208 pci_iounmap(pdev, card->pci_mmap1); 3209 pci_release_region(pdev, 2); 3210 pci_release_region(pdev, 0); 3211 3212 mwifiex_pcie_free_buffers(adapter); 3213 } 3214 3215 static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter) 3216 { 3217 int ret, i, j; 3218 struct pcie_service_card *card = adapter->card; 3219 struct pci_dev *pdev = card->dev; 3220 3221 if (card->pcie.reg->msix_support) { 3222 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3223 card->msix_entries[i].entry = i; 3224 ret = pci_enable_msix_exact(pdev, card->msix_entries, 3225 MWIFIEX_NUM_MSIX_VECTORS); 3226 if (!ret) { 3227 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { 3228 card->msix_ctx[i].dev = pdev; 3229 card->msix_ctx[i].msg_id = i; 3230 3231 ret = request_irq(card->msix_entries[i].vector, 3232 mwifiex_pcie_interrupt, 0, 3233 "MWIFIEX_PCIE_MSIX", 3234 &card->msix_ctx[i]); 3235 if (ret) 3236 break; 3237 } 3238 3239 if (ret) { 3240 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n", 3241 ret); 3242 for (j = 0; j < i; j++) 3243 free_irq(card->msix_entries[j].vector, 3244 &card->msix_ctx[i]); 3245 pci_disable_msix(pdev); 3246 } else { 3247 mwifiex_dbg(adapter, MSG, "MSIx enabled!"); 3248 card->msix_enable = 1; 3249 return 0; 3250 } 3251 } 3252 } 3253 3254 if (pci_enable_msi(pdev) != 0) 3255 pci_disable_msi(pdev); 3256 else 3257 card->msi_enable = 1; 3258 3259 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable); 3260 3261 card->share_irq_ctx.dev = pdev; 3262 card->share_irq_ctx.msg_id = -1; 3263 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, 3264 "MRVL_PCIE", &card->share_irq_ctx); 3265 if (ret) { 3266 pr_err("request_irq failed: ret=%d\n", ret); 3267 return -1; 3268 } 3269 3270 return 0; 3271 } 3272 3273 /* 3274 * This function gets the firmware name for downloading by revision id 3275 * 3276 * Read revision id register to get revision id 3277 */ 3278 static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter) 3279 { 3280 int revision_id = 0; 3281 int version, magic; 3282 struct pcie_service_card *card = adapter->card; 3283 3284 switch (card->dev->device) { 3285 case PCIE_DEVICE_ID_MARVELL_88W8766P: 3286 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME); 3287 break; 3288 case PCIE_DEVICE_ID_MARVELL_88W8897: 3289 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); 3290 mwifiex_read_reg(adapter, 0x0c58, &revision_id); 3291 revision_id &= 0xff00; 3292 switch (revision_id) { 3293 case PCIE8897_A0: 3294 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME); 3295 break; 3296 case PCIE8897_B0: 3297 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME); 3298 break; 3299 default: 3300 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME); 3301 3302 break; 3303 } 3304 break; 3305 case PCIE_DEVICE_ID_MARVELL_88W8997: 3306 mwifiex_read_reg(adapter, 0x8, &revision_id); 3307 mwifiex_read_reg(adapter, 0x0cd0, &version); 3308 mwifiex_read_reg(adapter, 0x0cd4, &magic); 3309 revision_id &= 0xff; 3310 version &= 0x7; 3311 magic &= 0xff; 3312 if (revision_id == PCIE8997_A1 && 3313 magic == CHIP_MAGIC_VALUE && 3314 version == CHIP_VER_PCIEUART) 3315 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4); 3316 else 3317 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4); 3318 break; 3319 default: 3320 break; 3321 } 3322 } 3323 3324 /* 3325 * This function registers the PCIE device. 3326 * 3327 * PCIE IRQ is claimed, block size is set and driver data is initialized. 3328 */ 3329 static int mwifiex_register_dev(struct mwifiex_adapter *adapter) 3330 { 3331 struct pcie_service_card *card = adapter->card; 3332 3333 /* save adapter pointer in card */ 3334 card->adapter = adapter; 3335 3336 if (mwifiex_pcie_request_irq(adapter)) 3337 return -1; 3338 3339 adapter->tx_buf_size = card->pcie.tx_buf_size; 3340 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl; 3341 adapter->num_mem_types = card->pcie.num_mem_types; 3342 adapter->ext_scan = card->pcie.can_ext_scan; 3343 mwifiex_pcie_get_fw_name(adapter); 3344 3345 return 0; 3346 } 3347 3348 /* 3349 * This function unregisters the PCIE device. 3350 * 3351 * The PCIE IRQ is released, the function is disabled and driver 3352 * data is set to null. 3353 */ 3354 static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) 3355 { 3356 struct pcie_service_card *card = adapter->card; 3357 struct pci_dev *pdev = card->dev; 3358 int i; 3359 3360 if (card->msix_enable) { 3361 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3362 synchronize_irq(card->msix_entries[i].vector); 3363 3364 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3365 free_irq(card->msix_entries[i].vector, 3366 &card->msix_ctx[i]); 3367 3368 card->msix_enable = 0; 3369 pci_disable_msix(pdev); 3370 } else { 3371 mwifiex_dbg(adapter, INFO, 3372 "%s(): calling free_irq()\n", __func__); 3373 free_irq(card->dev->irq, &card->share_irq_ctx); 3374 3375 if (card->msi_enable) 3376 pci_disable_msi(pdev); 3377 } 3378 card->adapter = NULL; 3379 } 3380 3381 /* 3382 * This function initializes the PCI-E host memory space, WCB rings, etc., 3383 * similar to mwifiex_init_pcie(), but without resetting PCI-E state. 3384 */ 3385 static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter) 3386 { 3387 struct pcie_service_card *card = adapter->card; 3388 struct pci_dev *pdev = card->dev; 3389 3390 /* tx_buf_size might be changed to 3584 by firmware during 3391 * data transfer, we should reset it to default size. 3392 */ 3393 adapter->tx_buf_size = card->pcie.tx_buf_size; 3394 3395 mwifiex_pcie_alloc_buffers(adapter); 3396 3397 pci_set_master(pdev); 3398 } 3399 3400 /* This function cleans up the PCI-E host memory space. */ 3401 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter) 3402 { 3403 struct pcie_service_card *card = adapter->card; 3404 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3405 struct pci_dev *pdev = card->dev; 3406 3407 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3408 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n"); 3409 3410 pci_clear_master(pdev); 3411 3412 adapter->seq_num = 0; 3413 3414 mwifiex_pcie_free_buffers(adapter); 3415 } 3416 3417 static struct mwifiex_if_ops pcie_ops = { 3418 .init_if = mwifiex_init_pcie, 3419 .cleanup_if = mwifiex_cleanup_pcie, 3420 .check_fw_status = mwifiex_check_fw_status, 3421 .check_winner_status = mwifiex_check_winner_status, 3422 .prog_fw = mwifiex_prog_fw_w_helper, 3423 .register_dev = mwifiex_register_dev, 3424 .unregister_dev = mwifiex_unregister_dev, 3425 .enable_int = mwifiex_pcie_enable_host_int, 3426 .disable_int = mwifiex_pcie_disable_host_int_noerr, 3427 .process_int_status = mwifiex_process_int_status, 3428 .host_to_card = mwifiex_pcie_host_to_card, 3429 .wakeup = mwifiex_pm_wakeup_card, 3430 .wakeup_complete = mwifiex_pm_wakeup_card_complete, 3431 3432 /* PCIE specific */ 3433 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, 3434 .event_complete = mwifiex_pcie_event_complete, 3435 .update_mp_end_port = NULL, 3436 .cleanup_mpa_buf = NULL, 3437 .init_fw_port = mwifiex_pcie_init_fw_port, 3438 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, 3439 .card_reset = mwifiex_pcie_card_reset, 3440 .reg_dump = mwifiex_pcie_reg_dump, 3441 .device_dump = mwifiex_pcie_device_dump, 3442 .down_dev = mwifiex_pcie_down_dev, 3443 .up_dev = mwifiex_pcie_up_dev, 3444 }; 3445 3446 module_pci_driver(mwifiex_pcie); 3447 3448 MODULE_AUTHOR("Marvell International Ltd."); 3449 MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); 3450 MODULE_VERSION(PCIE_VERSION); 3451 MODULE_LICENSE("GPL v2"); 3452