1 /* 2 * NXP Wireless LAN device driver: PCIE specific handling 3 * 4 * Copyright 2011-2020 NXP 5 * 6 * This software file (the "File") is distributed by NXP 7 * under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #include <linux/firmware.h> 21 22 #include "decl.h" 23 #include "ioctl.h" 24 #include "util.h" 25 #include "fw.h" 26 #include "main.h" 27 #include "wmm.h" 28 #include "11n.h" 29 #include "pcie.h" 30 31 #define PCIE_VERSION "1.0" 32 #define DRV_NAME "Marvell mwifiex PCIe" 33 34 static struct mwifiex_if_ops pcie_ops; 35 36 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 37 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 38 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 39 .cmd_size = PCIE_SCRATCH_2_REG, 40 .fw_status = PCIE_SCRATCH_3_REG, 41 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 42 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 43 .tx_rdptr = PCIE_SCRATCH_6_REG, 44 .tx_wrptr = PCIE_SCRATCH_7_REG, 45 .rx_rdptr = PCIE_SCRATCH_8_REG, 46 .rx_wrptr = PCIE_SCRATCH_9_REG, 47 .evt_rdptr = PCIE_SCRATCH_10_REG, 48 .evt_wrptr = PCIE_SCRATCH_11_REG, 49 .drv_rdy = PCIE_SCRATCH_12_REG, 50 .tx_start_ptr = 0, 51 .tx_mask = MWIFIEX_TXBD_MASK, 52 .tx_wrap_mask = 0, 53 .rx_mask = MWIFIEX_RXBD_MASK, 54 .rx_wrap_mask = 0, 55 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 56 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 57 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 58 .ring_flag_sop = 0, 59 .ring_flag_eop = 0, 60 .ring_flag_xs_sop = 0, 61 .ring_flag_xs_eop = 0, 62 .ring_tx_start_ptr = 0, 63 .pfu_enabled = 0, 64 .sleep_cookie = 1, 65 .msix_support = 0, 66 }; 67 68 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 69 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 70 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 71 .cmd_size = PCIE_SCRATCH_2_REG, 72 .fw_status = PCIE_SCRATCH_3_REG, 73 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 74 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 75 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 76 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 77 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 78 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 79 .evt_rdptr = PCIE_SCRATCH_10_REG, 80 .evt_wrptr = PCIE_SCRATCH_11_REG, 81 .drv_rdy = PCIE_SCRATCH_12_REG, 82 .tx_start_ptr = 16, 83 .tx_mask = 0x03FF0000, 84 .tx_wrap_mask = 0x07FF0000, 85 .rx_mask = 0x000003FF, 86 .rx_wrap_mask = 0x000007FF, 87 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 88 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 89 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 90 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 91 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 92 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 93 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 94 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 95 .pfu_enabled = 1, 96 .sleep_cookie = 0, 97 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 98 .fw_dump_start = PCIE_SCRATCH_14_REG, 99 .fw_dump_end = 0xcff, 100 .fw_dump_host_ready = 0xee, 101 .fw_dump_read_done = 0xfe, 102 .msix_support = 0, 103 }; 104 105 static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 106 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 107 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 108 .cmd_size = PCIE_SCRATCH_2_REG, 109 .fw_status = PCIE_SCRATCH_3_REG, 110 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 111 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 112 .tx_rdptr = 0xC1A4, 113 .tx_wrptr = 0xC174, 114 .rx_rdptr = 0xC174, 115 .rx_wrptr = 0xC1A4, 116 .evt_rdptr = PCIE_SCRATCH_10_REG, 117 .evt_wrptr = PCIE_SCRATCH_11_REG, 118 .drv_rdy = PCIE_SCRATCH_12_REG, 119 .tx_start_ptr = 16, 120 .tx_mask = 0x0FFF0000, 121 .tx_wrap_mask = 0x1FFF0000, 122 .rx_mask = 0x00000FFF, 123 .rx_wrap_mask = 0x00001FFF, 124 .tx_rollover_ind = BIT(28), 125 .rx_rollover_ind = BIT(12), 126 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 127 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 128 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 129 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 130 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 131 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 132 .pfu_enabled = 1, 133 .sleep_cookie = 0, 134 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 135 .fw_dump_start = PCIE_SCRATCH_14_REG, 136 .fw_dump_end = 0xcff, 137 .fw_dump_host_ready = 0xcc, 138 .fw_dump_read_done = 0xdd, 139 .msix_support = 0, 140 }; 141 142 static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 143 {"ITCM", NULL, 0, 0xF0}, 144 {"DTCM", NULL, 0, 0xF1}, 145 {"SQRAM", NULL, 0, 0xF2}, 146 {"IRAM", NULL, 0, 0xF3}, 147 {"APU", NULL, 0, 0xF4}, 148 {"CIU", NULL, 0, 0xF5}, 149 {"ICU", NULL, 0, 0xF6}, 150 {"MAC", NULL, 0, 0xF7}, 151 }; 152 153 static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 154 {"DUMP", NULL, 0, 0xDD}, 155 }; 156 157 static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 158 .reg = &mwifiex_reg_8766, 159 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 160 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 161 .can_dump_fw = false, 162 .can_ext_scan = true, 163 }; 164 165 static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 166 .reg = &mwifiex_reg_8897, 167 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 168 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 169 .can_dump_fw = true, 170 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 171 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 172 .can_ext_scan = true, 173 }; 174 175 static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 176 .reg = &mwifiex_reg_8997, 177 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 178 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 179 .can_dump_fw = true, 180 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 181 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 182 .can_ext_scan = true, 183 }; 184 185 static const struct of_device_id mwifiex_pcie_of_match_table[] = { 186 { .compatible = "pci11ab,2b42" }, 187 { .compatible = "pci1b4b,2b42" }, 188 { } 189 }; 190 191 static int mwifiex_pcie_probe_of(struct device *dev) 192 { 193 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) { 194 dev_err(dev, "required compatible string missing\n"); 195 return -EINVAL; 196 } 197 198 return 0; 199 } 200 201 static void mwifiex_pcie_work(struct work_struct *work); 202 203 static int 204 mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, 205 size_t size, int flags) 206 { 207 struct pcie_service_card *card = adapter->card; 208 struct mwifiex_dma_mapping mapping; 209 210 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); 211 if (dma_mapping_error(&card->dev->dev, mapping.addr)) { 212 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); 213 return -1; 214 } 215 mapping.len = size; 216 mwifiex_store_mapping(skb, &mapping); 217 return 0; 218 } 219 220 static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, 221 struct sk_buff *skb, int flags) 222 { 223 struct pcie_service_card *card = adapter->card; 224 struct mwifiex_dma_mapping mapping; 225 226 mwifiex_get_mapping(skb, &mapping); 227 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); 228 } 229 230 /* 231 * This function writes data into PCIE card register. 232 */ 233 static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) 234 { 235 struct pcie_service_card *card = adapter->card; 236 237 iowrite32(data, card->pci_mmap1 + reg); 238 239 return 0; 240 } 241 242 /* This function reads data from PCIE card register. 243 */ 244 static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) 245 { 246 struct pcie_service_card *card = adapter->card; 247 248 *data = ioread32(card->pci_mmap1 + reg); 249 if (*data == 0xffffffff) 250 return 0xffffffff; 251 252 return 0; 253 } 254 255 /* This function reads u8 data from PCIE card register. */ 256 static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter, 257 int reg, u8 *data) 258 { 259 struct pcie_service_card *card = adapter->card; 260 261 *data = ioread8(card->pci_mmap1 + reg); 262 263 return 0; 264 } 265 266 /* 267 * This function reads sleep cookie and checks if FW is ready 268 */ 269 static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) 270 { 271 u32 cookie_value; 272 struct pcie_service_card *card = adapter->card; 273 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 274 275 if (!reg->sleep_cookie) 276 return true; 277 278 if (card->sleep_cookie_vbase) { 279 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase); 280 mwifiex_dbg(adapter, INFO, 281 "info: ACCESS_HW: sleep cookie=0x%x\n", 282 cookie_value); 283 if (cookie_value == FW_AWAKE_COOKIE) 284 return true; 285 } 286 287 return false; 288 } 289 290 #ifdef CONFIG_PM_SLEEP 291 /* 292 * Kernel needs to suspend all functions separately. Therefore all 293 * registered functions must have drivers with suspend and resume 294 * methods. Failing that the kernel simply removes the whole card. 295 * 296 * If already not suspended, this function allocates and sends a host 297 * sleep activate request to the firmware and turns off the traffic. 298 */ 299 static int mwifiex_pcie_suspend(struct device *dev) 300 { 301 struct mwifiex_adapter *adapter; 302 struct pcie_service_card *card = dev_get_drvdata(dev); 303 304 305 /* Might still be loading firmware */ 306 wait_for_completion(&card->fw_done); 307 308 adapter = card->adapter; 309 if (!adapter) { 310 dev_err(dev, "adapter is not valid\n"); 311 return 0; 312 } 313 314 mwifiex_enable_wake(adapter); 315 316 /* Enable the Host Sleep */ 317 if (!mwifiex_enable_hs(adapter)) { 318 mwifiex_dbg(adapter, ERROR, 319 "cmd: failed to suspend\n"); 320 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 321 mwifiex_disable_wake(adapter); 322 return -EFAULT; 323 } 324 325 flush_workqueue(adapter->workqueue); 326 327 /* Indicate device suspended */ 328 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 329 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 330 331 return 0; 332 } 333 334 /* 335 * Kernel needs to suspend all functions separately. Therefore all 336 * registered functions must have drivers with suspend and resume 337 * methods. Failing that the kernel simply removes the whole card. 338 * 339 * If already not resumed, this function turns on the traffic and 340 * sends a host sleep cancel request to the firmware. 341 */ 342 static int mwifiex_pcie_resume(struct device *dev) 343 { 344 struct mwifiex_adapter *adapter; 345 struct pcie_service_card *card = dev_get_drvdata(dev); 346 347 348 if (!card->adapter) { 349 dev_err(dev, "adapter structure is not valid\n"); 350 return 0; 351 } 352 353 adapter = card->adapter; 354 355 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) { 356 mwifiex_dbg(adapter, WARN, 357 "Device already resumed\n"); 358 return 0; 359 } 360 361 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 362 363 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), 364 MWIFIEX_ASYNC_CMD); 365 mwifiex_disable_wake(adapter); 366 367 return 0; 368 } 369 #endif 370 371 /* 372 * This function probes an mwifiex device and registers it. It allocates 373 * the card structure, enables PCIE function number and initiates the 374 * device registration and initialization procedure by adding a logical 375 * interface. 376 */ 377 static int mwifiex_pcie_probe(struct pci_dev *pdev, 378 const struct pci_device_id *ent) 379 { 380 struct pcie_service_card *card; 381 int ret; 382 383 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 384 pdev->vendor, pdev->device, pdev->revision); 385 386 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 387 if (!card) 388 return -ENOMEM; 389 390 init_completion(&card->fw_done); 391 392 card->dev = pdev; 393 394 if (ent->driver_data) { 395 struct mwifiex_pcie_device *data = (void *)ent->driver_data; 396 card->pcie.reg = data->reg; 397 card->pcie.blksz_fw_dl = data->blksz_fw_dl; 398 card->pcie.tx_buf_size = data->tx_buf_size; 399 card->pcie.can_dump_fw = data->can_dump_fw; 400 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl; 401 card->pcie.num_mem_types = data->num_mem_types; 402 card->pcie.can_ext_scan = data->can_ext_scan; 403 INIT_WORK(&card->work, mwifiex_pcie_work); 404 } 405 406 /* device tree node parsing and platform specific configuration*/ 407 if (pdev->dev.of_node) { 408 ret = mwifiex_pcie_probe_of(&pdev->dev); 409 if (ret) 410 return ret; 411 } 412 413 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops, 414 MWIFIEX_PCIE, &pdev->dev)) { 415 pr_err("%s failed\n", __func__); 416 return -1; 417 } 418 419 return 0; 420 } 421 422 /* 423 * This function removes the interface and frees up the card structure. 424 */ 425 static void mwifiex_pcie_remove(struct pci_dev *pdev) 426 { 427 struct pcie_service_card *card; 428 struct mwifiex_adapter *adapter; 429 struct mwifiex_private *priv; 430 const struct mwifiex_pcie_card_reg *reg; 431 u32 fw_status; 432 433 card = pci_get_drvdata(pdev); 434 435 wait_for_completion(&card->fw_done); 436 437 adapter = card->adapter; 438 if (!adapter || !adapter->priv_num) 439 return; 440 441 reg = card->pcie.reg; 442 if (reg) 443 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 444 else 445 fw_status = -1; 446 447 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) { 448 mwifiex_deauthenticate_all(adapter); 449 450 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); 451 452 mwifiex_disable_auto_ds(priv); 453 454 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); 455 } 456 457 mwifiex_remove_card(adapter); 458 } 459 460 static void mwifiex_pcie_shutdown(struct pci_dev *pdev) 461 { 462 mwifiex_pcie_remove(pdev); 463 464 return; 465 } 466 467 static void mwifiex_pcie_coredump(struct device *dev) 468 { 469 struct pci_dev *pdev; 470 struct pcie_service_card *card; 471 472 pdev = container_of(dev, struct pci_dev, dev); 473 card = pci_get_drvdata(pdev); 474 475 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 476 &card->work_flags)) 477 schedule_work(&card->work); 478 } 479 480 static const struct pci_device_id mwifiex_ids[] = { 481 { 482 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, 483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 484 .driver_data = (unsigned long)&mwifiex_pcie8766, 485 }, 486 { 487 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, 488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 489 .driver_data = (unsigned long)&mwifiex_pcie8897, 490 }, 491 { 492 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 494 .driver_data = (unsigned long)&mwifiex_pcie8997, 495 }, 496 { 497 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 499 .driver_data = (unsigned long)&mwifiex_pcie8997, 500 }, 501 {}, 502 }; 503 504 MODULE_DEVICE_TABLE(pci, mwifiex_ids); 505 506 /* 507 * Cleanup all software without cleaning anything related to PCIe and HW. 508 */ 509 static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev) 510 { 511 struct pcie_service_card *card = pci_get_drvdata(pdev); 512 struct mwifiex_adapter *adapter = card->adapter; 513 514 if (!adapter) { 515 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 516 __func__); 517 return; 518 } 519 520 mwifiex_dbg(adapter, INFO, 521 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", 522 __func__, pdev->vendor, pdev->device, pdev->revision); 523 524 mwifiex_shutdown_sw(adapter); 525 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags); 526 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags); 527 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 528 529 card->pci_reset_ongoing = true; 530 } 531 532 /* 533 * Kernel stores and restores PCIe function context before and after performing 534 * FLR respectively. Reconfigure the software and firmware including firmware 535 * redownload. 536 */ 537 static void mwifiex_pcie_reset_done(struct pci_dev *pdev) 538 { 539 struct pcie_service_card *card = pci_get_drvdata(pdev); 540 struct mwifiex_adapter *adapter = card->adapter; 541 int ret; 542 543 if (!adapter) { 544 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 545 __func__); 546 return; 547 } 548 549 mwifiex_dbg(adapter, INFO, 550 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", 551 __func__, pdev->vendor, pdev->device, pdev->revision); 552 553 ret = mwifiex_reinit_sw(adapter); 554 if (ret) 555 dev_err(&pdev->dev, "reinit failed: %d\n", ret); 556 else 557 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 558 559 card->pci_reset_ongoing = false; 560 } 561 562 static const struct pci_error_handlers mwifiex_pcie_err_handler = { 563 .reset_prepare = mwifiex_pcie_reset_prepare, 564 .reset_done = mwifiex_pcie_reset_done, 565 }; 566 567 #ifdef CONFIG_PM_SLEEP 568 /* Power Management Hooks */ 569 static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, 570 mwifiex_pcie_resume); 571 #endif 572 573 /* PCI Device Driver */ 574 static struct pci_driver mwifiex_pcie = { 575 .name = "mwifiex_pcie", 576 .id_table = mwifiex_ids, 577 .probe = mwifiex_pcie_probe, 578 .remove = mwifiex_pcie_remove, 579 .driver = { 580 .coredump = mwifiex_pcie_coredump, 581 #ifdef CONFIG_PM_SLEEP 582 .pm = &mwifiex_pcie_pm_ops, 583 #endif 584 }, 585 .shutdown = mwifiex_pcie_shutdown, 586 .err_handler = &mwifiex_pcie_err_handler, 587 }; 588 589 /* 590 * This function adds delay loop to ensure FW is awake before proceeding. 591 */ 592 static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) 593 { 594 int i = 0; 595 596 while (mwifiex_pcie_ok_to_access_hw(adapter)) { 597 i++; 598 usleep_range(10, 20); 599 /* 50ms max wait */ 600 if (i == 5000) 601 break; 602 } 603 604 return; 605 } 606 607 static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, 608 u32 max_delay_loop_cnt) 609 { 610 struct pcie_service_card *card = adapter->card; 611 u8 *buffer; 612 u32 sleep_cookie, count; 613 struct sk_buff *cmdrsp = card->cmdrsp_buf; 614 615 for (count = 0; count < max_delay_loop_cnt; count++) { 616 dma_sync_single_for_cpu(&card->dev->dev, 617 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 618 sizeof(sleep_cookie), DMA_FROM_DEVICE); 619 buffer = cmdrsp->data; 620 sleep_cookie = get_unaligned_le32(buffer); 621 622 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { 623 mwifiex_dbg(adapter, INFO, 624 "sleep cookie found at count %d\n", count); 625 break; 626 } 627 dma_sync_single_for_device(&card->dev->dev, 628 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 629 sizeof(sleep_cookie), 630 DMA_FROM_DEVICE); 631 usleep_range(20, 30); 632 } 633 634 if (count >= max_delay_loop_cnt) 635 mwifiex_dbg(adapter, INFO, 636 "max count reached while accessing sleep cookie\n"); 637 } 638 639 /* This function wakes up the card by reading fw_status register. */ 640 static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) 641 { 642 struct pcie_service_card *card = adapter->card; 643 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 644 645 mwifiex_dbg(adapter, EVENT, 646 "event: Wakeup device...\n"); 647 648 if (reg->sleep_cookie) 649 mwifiex_pcie_dev_wakeup_delay(adapter); 650 651 /* Accessing fw_status register will wakeup device */ 652 if (mwifiex_write_reg(adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 653 mwifiex_dbg(adapter, ERROR, 654 "Writing fw_status register failed\n"); 655 return -1; 656 } 657 658 if (reg->sleep_cookie) { 659 mwifiex_pcie_dev_wakeup_delay(adapter); 660 mwifiex_dbg(adapter, INFO, 661 "PCIE wakeup: Setting PS_STATE_AWAKE\n"); 662 adapter->ps_state = PS_STATE_AWAKE; 663 } 664 665 return 0; 666 } 667 668 /* 669 * This function is called after the card has woken up. 670 * 671 * The card configuration register is reset. 672 */ 673 static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) 674 { 675 mwifiex_dbg(adapter, CMD, 676 "cmd: Wakeup device completed\n"); 677 678 return 0; 679 } 680 681 /* 682 * This function disables the host interrupt. 683 * 684 * The host interrupt mask is read, the disable bit is reset and 685 * written back to the card host interrupt mask register. 686 */ 687 static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) 688 { 689 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 690 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 691 0x00000000)) { 692 mwifiex_dbg(adapter, ERROR, 693 "Disable host interrupt failed\n"); 694 return -1; 695 } 696 } 697 698 atomic_set(&adapter->tx_hw_pending, 0); 699 return 0; 700 } 701 702 static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter) 703 { 704 WARN_ON(mwifiex_pcie_disable_host_int(adapter)); 705 } 706 707 /* 708 * This function enables the host interrupt. 709 * 710 * The host interrupt enable mask is written to the card 711 * host interrupt mask register. 712 */ 713 static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) 714 { 715 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 716 /* Simply write the mask to the register */ 717 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 718 HOST_INTR_MASK)) { 719 mwifiex_dbg(adapter, ERROR, 720 "Enable host interrupt failed\n"); 721 return -1; 722 } 723 } 724 725 return 0; 726 } 727 728 /* 729 * This function initializes TX buffer ring descriptors 730 */ 731 static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) 732 { 733 struct pcie_service_card *card = adapter->card; 734 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 735 struct mwifiex_pcie_buf_desc *desc; 736 struct mwifiex_pfu_buf_desc *desc2; 737 int i; 738 739 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 740 card->tx_buf_list[i] = NULL; 741 if (reg->pfu_enabled) { 742 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 743 (sizeof(*desc2) * i); 744 desc2 = card->txbd_ring[i]; 745 memset(desc2, 0, sizeof(*desc2)); 746 } else { 747 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 748 (sizeof(*desc) * i); 749 desc = card->txbd_ring[i]; 750 memset(desc, 0, sizeof(*desc)); 751 } 752 } 753 754 return 0; 755 } 756 757 /* This function initializes RX buffer ring descriptors. Each SKB is allocated 758 * here and after mapping PCI memory, its physical address is assigned to 759 * PCIE Rx buffer descriptor's physical address. 760 */ 761 static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) 762 { 763 struct pcie_service_card *card = adapter->card; 764 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 765 struct sk_buff *skb; 766 struct mwifiex_pcie_buf_desc *desc; 767 struct mwifiex_pfu_buf_desc *desc2; 768 dma_addr_t buf_pa; 769 int i; 770 771 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 772 /* Allocate skb here so that firmware can DMA data from it */ 773 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 774 GFP_KERNEL); 775 if (!skb) { 776 mwifiex_dbg(adapter, ERROR, 777 "Unable to allocate skb for RX ring.\n"); 778 kfree(card->rxbd_ring_vbase); 779 return -ENOMEM; 780 } 781 782 if (mwifiex_map_pci_memory(adapter, skb, 783 MWIFIEX_RX_DATA_BUF_SIZE, 784 DMA_FROM_DEVICE)) 785 return -1; 786 787 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 788 789 mwifiex_dbg(adapter, INFO, 790 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 791 skb, skb->len, skb->data, (u32)buf_pa, 792 (u32)((u64)buf_pa >> 32)); 793 794 card->rx_buf_list[i] = skb; 795 if (reg->pfu_enabled) { 796 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + 797 (sizeof(*desc2) * i); 798 desc2 = card->rxbd_ring[i]; 799 desc2->paddr = buf_pa; 800 desc2->len = (u16)skb->len; 801 desc2->frag_len = (u16)skb->len; 802 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; 803 desc2->offset = 0; 804 } else { 805 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + 806 (sizeof(*desc) * i)); 807 desc = card->rxbd_ring[i]; 808 desc->paddr = buf_pa; 809 desc->len = (u16)skb->len; 810 desc->flags = 0; 811 } 812 } 813 814 return 0; 815 } 816 817 /* This function initializes event buffer ring descriptors. Each SKB is 818 * allocated here and after mapping PCI memory, its physical address is assigned 819 * to PCIE Rx buffer descriptor's physical address 820 */ 821 static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) 822 { 823 struct pcie_service_card *card = adapter->card; 824 struct mwifiex_evt_buf_desc *desc; 825 struct sk_buff *skb; 826 dma_addr_t buf_pa; 827 int i; 828 829 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 830 /* Allocate skb here so that firmware can DMA data from it */ 831 skb = dev_alloc_skb(MAX_EVENT_SIZE); 832 if (!skb) { 833 mwifiex_dbg(adapter, ERROR, 834 "Unable to allocate skb for EVENT buf.\n"); 835 kfree(card->evtbd_ring_vbase); 836 return -ENOMEM; 837 } 838 skb_put(skb, MAX_EVENT_SIZE); 839 840 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, 841 DMA_FROM_DEVICE)) { 842 kfree_skb(skb); 843 kfree(card->evtbd_ring_vbase); 844 return -1; 845 } 846 847 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 848 849 mwifiex_dbg(adapter, EVENT, 850 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 851 skb, skb->len, skb->data, (u32)buf_pa, 852 (u32)((u64)buf_pa >> 32)); 853 854 card->evt_buf_list[i] = skb; 855 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + 856 (sizeof(*desc) * i)); 857 desc = card->evtbd_ring[i]; 858 desc->paddr = buf_pa; 859 desc->len = (u16)skb->len; 860 desc->flags = 0; 861 } 862 863 return 0; 864 } 865 866 /* This function cleans up TX buffer rings. If any of the buffer list has valid 867 * SKB address, associated SKB is freed. 868 */ 869 static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) 870 { 871 struct pcie_service_card *card = adapter->card; 872 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 873 struct sk_buff *skb; 874 struct mwifiex_pcie_buf_desc *desc; 875 struct mwifiex_pfu_buf_desc *desc2; 876 int i; 877 878 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 879 if (reg->pfu_enabled) { 880 desc2 = card->txbd_ring[i]; 881 if (card->tx_buf_list[i]) { 882 skb = card->tx_buf_list[i]; 883 mwifiex_unmap_pci_memory(adapter, skb, 884 DMA_TO_DEVICE); 885 dev_kfree_skb_any(skb); 886 } 887 memset(desc2, 0, sizeof(*desc2)); 888 } else { 889 desc = card->txbd_ring[i]; 890 if (card->tx_buf_list[i]) { 891 skb = card->tx_buf_list[i]; 892 mwifiex_unmap_pci_memory(adapter, skb, 893 DMA_TO_DEVICE); 894 dev_kfree_skb_any(skb); 895 } 896 memset(desc, 0, sizeof(*desc)); 897 } 898 card->tx_buf_list[i] = NULL; 899 } 900 901 atomic_set(&adapter->tx_hw_pending, 0); 902 return; 903 } 904 905 /* This function cleans up RX buffer rings. If any of the buffer list has valid 906 * SKB address, associated SKB is freed. 907 */ 908 static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) 909 { 910 struct pcie_service_card *card = adapter->card; 911 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 912 struct mwifiex_pcie_buf_desc *desc; 913 struct mwifiex_pfu_buf_desc *desc2; 914 struct sk_buff *skb; 915 int i; 916 917 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 918 if (reg->pfu_enabled) { 919 desc2 = card->rxbd_ring[i]; 920 if (card->rx_buf_list[i]) { 921 skb = card->rx_buf_list[i]; 922 mwifiex_unmap_pci_memory(adapter, skb, 923 DMA_FROM_DEVICE); 924 dev_kfree_skb_any(skb); 925 } 926 memset(desc2, 0, sizeof(*desc2)); 927 } else { 928 desc = card->rxbd_ring[i]; 929 if (card->rx_buf_list[i]) { 930 skb = card->rx_buf_list[i]; 931 mwifiex_unmap_pci_memory(adapter, skb, 932 DMA_FROM_DEVICE); 933 dev_kfree_skb_any(skb); 934 } 935 memset(desc, 0, sizeof(*desc)); 936 } 937 card->rx_buf_list[i] = NULL; 938 } 939 940 return; 941 } 942 943 /* This function cleans up event buffer rings. If any of the buffer list has 944 * valid SKB address, associated SKB is freed. 945 */ 946 static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) 947 { 948 struct pcie_service_card *card = adapter->card; 949 struct mwifiex_evt_buf_desc *desc; 950 struct sk_buff *skb; 951 int i; 952 953 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 954 desc = card->evtbd_ring[i]; 955 if (card->evt_buf_list[i]) { 956 skb = card->evt_buf_list[i]; 957 mwifiex_unmap_pci_memory(adapter, skb, 958 DMA_FROM_DEVICE); 959 dev_kfree_skb_any(skb); 960 } 961 card->evt_buf_list[i] = NULL; 962 memset(desc, 0, sizeof(*desc)); 963 } 964 965 return; 966 } 967 968 /* This function creates buffer descriptor ring for TX 969 */ 970 static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) 971 { 972 struct pcie_service_card *card = adapter->card; 973 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 974 975 /* 976 * driver maintaines the write pointer and firmware maintaines the read 977 * pointer. The write pointer starts at 0 (zero) while the read pointer 978 * starts at zero with rollover bit set 979 */ 980 card->txbd_wrptr = 0; 981 982 if (reg->pfu_enabled) 983 card->txbd_rdptr = 0; 984 else 985 card->txbd_rdptr |= reg->tx_rollover_ind; 986 987 /* allocate shared memory for the BD ring and divide the same in to 988 several descriptors */ 989 if (reg->pfu_enabled) 990 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 991 MWIFIEX_MAX_TXRX_BD; 992 else 993 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 994 MWIFIEX_MAX_TXRX_BD; 995 996 mwifiex_dbg(adapter, INFO, 997 "info: txbd_ring: Allocating %d bytes\n", 998 card->txbd_ring_size); 999 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1000 card->txbd_ring_size, 1001 &card->txbd_ring_pbase, 1002 GFP_KERNEL); 1003 if (!card->txbd_ring_vbase) { 1004 mwifiex_dbg(adapter, ERROR, 1005 "allocate coherent memory (%d bytes) failed!\n", 1006 card->txbd_ring_size); 1007 return -ENOMEM; 1008 } 1009 1010 mwifiex_dbg(adapter, DATA, 1011 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1012 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase, 1013 (u32)((u64)card->txbd_ring_pbase >> 32), 1014 card->txbd_ring_size); 1015 1016 return mwifiex_init_txq_ring(adapter); 1017 } 1018 1019 static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) 1020 { 1021 struct pcie_service_card *card = adapter->card; 1022 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1023 1024 mwifiex_cleanup_txq_ring(adapter); 1025 1026 if (card->txbd_ring_vbase) 1027 dma_free_coherent(&card->dev->dev, card->txbd_ring_size, 1028 card->txbd_ring_vbase, 1029 card->txbd_ring_pbase); 1030 card->txbd_ring_size = 0; 1031 card->txbd_wrptr = 0; 1032 card->txbd_rdptr = 0 | reg->tx_rollover_ind; 1033 card->txbd_ring_vbase = NULL; 1034 card->txbd_ring_pbase = 0; 1035 1036 return 0; 1037 } 1038 1039 /* 1040 * This function creates buffer descriptor ring for RX 1041 */ 1042 static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) 1043 { 1044 struct pcie_service_card *card = adapter->card; 1045 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1046 1047 /* 1048 * driver maintaines the read pointer and firmware maintaines the write 1049 * pointer. The write pointer starts at 0 (zero) while the read pointer 1050 * starts at zero with rollover bit set 1051 */ 1052 card->rxbd_wrptr = 0; 1053 card->rxbd_rdptr = reg->rx_rollover_ind; 1054 1055 if (reg->pfu_enabled) 1056 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 1057 MWIFIEX_MAX_TXRX_BD; 1058 else 1059 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1060 MWIFIEX_MAX_TXRX_BD; 1061 1062 mwifiex_dbg(adapter, INFO, 1063 "info: rxbd_ring: Allocating %d bytes\n", 1064 card->rxbd_ring_size); 1065 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1066 card->rxbd_ring_size, 1067 &card->rxbd_ring_pbase, 1068 GFP_KERNEL); 1069 if (!card->rxbd_ring_vbase) { 1070 mwifiex_dbg(adapter, ERROR, 1071 "allocate coherent memory (%d bytes) failed!\n", 1072 card->rxbd_ring_size); 1073 return -ENOMEM; 1074 } 1075 1076 mwifiex_dbg(adapter, DATA, 1077 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1078 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, 1079 (u32)((u64)card->rxbd_ring_pbase >> 32), 1080 card->rxbd_ring_size); 1081 1082 return mwifiex_init_rxq_ring(adapter); 1083 } 1084 1085 /* 1086 * This function deletes Buffer descriptor ring for RX 1087 */ 1088 static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) 1089 { 1090 struct pcie_service_card *card = adapter->card; 1091 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1092 1093 mwifiex_cleanup_rxq_ring(adapter); 1094 1095 if (card->rxbd_ring_vbase) 1096 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, 1097 card->rxbd_ring_vbase, 1098 card->rxbd_ring_pbase); 1099 card->rxbd_ring_size = 0; 1100 card->rxbd_wrptr = 0; 1101 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; 1102 card->rxbd_ring_vbase = NULL; 1103 card->rxbd_ring_pbase = 0; 1104 1105 return 0; 1106 } 1107 1108 /* 1109 * This function creates buffer descriptor ring for Events 1110 */ 1111 static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) 1112 { 1113 struct pcie_service_card *card = adapter->card; 1114 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1115 1116 /* 1117 * driver maintaines the read pointer and firmware maintaines the write 1118 * pointer. The write pointer starts at 0 (zero) while the read pointer 1119 * starts at zero with rollover bit set 1120 */ 1121 card->evtbd_wrptr = 0; 1122 card->evtbd_rdptr = reg->evt_rollover_ind; 1123 1124 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * 1125 MWIFIEX_MAX_EVT_BD; 1126 1127 mwifiex_dbg(adapter, INFO, 1128 "info: evtbd_ring: Allocating %d bytes\n", 1129 card->evtbd_ring_size); 1130 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1131 card->evtbd_ring_size, 1132 &card->evtbd_ring_pbase, 1133 GFP_KERNEL); 1134 if (!card->evtbd_ring_vbase) { 1135 mwifiex_dbg(adapter, ERROR, 1136 "allocate coherent memory (%d bytes) failed!\n", 1137 card->evtbd_ring_size); 1138 return -ENOMEM; 1139 } 1140 1141 mwifiex_dbg(adapter, EVENT, 1142 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", 1143 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, 1144 (u32)((u64)card->evtbd_ring_pbase >> 32), 1145 card->evtbd_ring_size); 1146 1147 return mwifiex_pcie_init_evt_ring(adapter); 1148 } 1149 1150 /* 1151 * This function deletes Buffer descriptor ring for Events 1152 */ 1153 static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) 1154 { 1155 struct pcie_service_card *card = adapter->card; 1156 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1157 1158 mwifiex_cleanup_evt_ring(adapter); 1159 1160 if (card->evtbd_ring_vbase) 1161 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, 1162 card->evtbd_ring_vbase, 1163 card->evtbd_ring_pbase); 1164 card->evtbd_wrptr = 0; 1165 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; 1166 card->evtbd_ring_size = 0; 1167 card->evtbd_ring_vbase = NULL; 1168 card->evtbd_ring_pbase = 0; 1169 1170 return 0; 1171 } 1172 1173 /* 1174 * This function allocates a buffer for CMDRSP 1175 */ 1176 static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) 1177 { 1178 struct pcie_service_card *card = adapter->card; 1179 struct sk_buff *skb; 1180 1181 /* Allocate memory for receiving command response data */ 1182 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 1183 if (!skb) { 1184 mwifiex_dbg(adapter, ERROR, 1185 "Unable to allocate skb for command response data.\n"); 1186 return -ENOMEM; 1187 } 1188 skb_put(skb, MWIFIEX_UPLD_SIZE); 1189 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1190 DMA_FROM_DEVICE)) { 1191 kfree_skb(skb); 1192 return -1; 1193 } 1194 1195 card->cmdrsp_buf = skb; 1196 1197 return 0; 1198 } 1199 1200 /* 1201 * This function deletes a buffer for CMDRSP 1202 */ 1203 static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) 1204 { 1205 struct pcie_service_card *card; 1206 1207 if (!adapter) 1208 return 0; 1209 1210 card = adapter->card; 1211 1212 if (card && card->cmdrsp_buf) { 1213 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, 1214 DMA_FROM_DEVICE); 1215 dev_kfree_skb_any(card->cmdrsp_buf); 1216 card->cmdrsp_buf = NULL; 1217 } 1218 1219 if (card && card->cmd_buf) { 1220 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1221 DMA_TO_DEVICE); 1222 dev_kfree_skb_any(card->cmd_buf); 1223 card->cmd_buf = NULL; 1224 } 1225 return 0; 1226 } 1227 1228 /* 1229 * This function allocates a buffer for sleep cookie 1230 */ 1231 static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1232 { 1233 struct pcie_service_card *card = adapter->card; 1234 u32 *cookie; 1235 1236 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, 1237 sizeof(u32), 1238 &card->sleep_cookie_pbase, 1239 GFP_KERNEL); 1240 if (!card->sleep_cookie_vbase) { 1241 mwifiex_dbg(adapter, ERROR, 1242 "dma_alloc_coherent failed!\n"); 1243 return -ENOMEM; 1244 } 1245 cookie = (u32 *)card->sleep_cookie_vbase; 1246 /* Init val of Sleep Cookie */ 1247 *cookie = FW_AWAKE_COOKIE; 1248 1249 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie); 1250 1251 return 0; 1252 } 1253 1254 /* 1255 * This function deletes buffer for sleep cookie 1256 */ 1257 static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1258 { 1259 struct pcie_service_card *card; 1260 1261 if (!adapter) 1262 return 0; 1263 1264 card = adapter->card; 1265 1266 if (card && card->sleep_cookie_vbase) { 1267 dma_free_coherent(&card->dev->dev, sizeof(u32), 1268 card->sleep_cookie_vbase, 1269 card->sleep_cookie_pbase); 1270 card->sleep_cookie_vbase = NULL; 1271 } 1272 1273 return 0; 1274 } 1275 1276 /* This function flushes the TX buffer descriptor ring 1277 * This function defined as handler is also called while cleaning TXRX 1278 * during disconnect/ bss stop. 1279 */ 1280 static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) 1281 { 1282 struct pcie_service_card *card = adapter->card; 1283 1284 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { 1285 card->txbd_flush = 1; 1286 /* write pointer already set at last send 1287 * send dnld-rdy intr again, wait for completion. 1288 */ 1289 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1290 CPU_INTR_DNLD_RDY)) { 1291 mwifiex_dbg(adapter, ERROR, 1292 "failed to assert dnld-rdy interrupt.\n"); 1293 return -1; 1294 } 1295 } 1296 return 0; 1297 } 1298 1299 /* 1300 * This function unmaps and frees downloaded data buffer 1301 */ 1302 static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) 1303 { 1304 struct sk_buff *skb; 1305 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; 1306 struct mwifiex_pcie_buf_desc *desc; 1307 struct mwifiex_pfu_buf_desc *desc2; 1308 struct pcie_service_card *card = adapter->card; 1309 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1310 1311 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1312 mwifiex_pm_wakeup_card(adapter); 1313 1314 /* Read the TX ring read pointer set by firmware */ 1315 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { 1316 mwifiex_dbg(adapter, ERROR, 1317 "SEND COMP: failed to read reg->tx_rdptr\n"); 1318 return -1; 1319 } 1320 1321 mwifiex_dbg(adapter, DATA, 1322 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", 1323 card->txbd_rdptr, rdptr); 1324 1325 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1326 /* free from previous txbd_rdptr to current txbd_rdptr */ 1327 while (((card->txbd_rdptr & reg->tx_mask) != 1328 (rdptr & reg->tx_mask)) || 1329 ((card->txbd_rdptr & reg->tx_rollover_ind) != 1330 (rdptr & reg->tx_rollover_ind))) { 1331 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> 1332 reg->tx_start_ptr; 1333 1334 skb = card->tx_buf_list[wrdoneidx]; 1335 1336 if (skb) { 1337 mwifiex_dbg(adapter, DATA, 1338 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", 1339 skb, wrdoneidx); 1340 mwifiex_unmap_pci_memory(adapter, skb, 1341 DMA_TO_DEVICE); 1342 1343 unmap_count++; 1344 1345 if (card->txbd_flush) 1346 mwifiex_write_data_complete(adapter, skb, 0, 1347 -1); 1348 else 1349 mwifiex_write_data_complete(adapter, skb, 0, 0); 1350 atomic_dec(&adapter->tx_hw_pending); 1351 } 1352 1353 card->tx_buf_list[wrdoneidx] = NULL; 1354 1355 if (reg->pfu_enabled) { 1356 desc2 = card->txbd_ring[wrdoneidx]; 1357 memset(desc2, 0, sizeof(*desc2)); 1358 } else { 1359 desc = card->txbd_ring[wrdoneidx]; 1360 memset(desc, 0, sizeof(*desc)); 1361 } 1362 switch (card->dev->device) { 1363 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1364 card->txbd_rdptr++; 1365 break; 1366 case PCIE_DEVICE_ID_MARVELL_88W8897: 1367 case PCIE_DEVICE_ID_MARVELL_88W8997: 1368 card->txbd_rdptr += reg->ring_tx_start_ptr; 1369 break; 1370 } 1371 1372 1373 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) 1374 card->txbd_rdptr = ((card->txbd_rdptr & 1375 reg->tx_rollover_ind) ^ 1376 reg->tx_rollover_ind); 1377 } 1378 1379 if (unmap_count) 1380 adapter->data_sent = false; 1381 1382 if (card->txbd_flush) { 1383 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) 1384 card->txbd_flush = 0; 1385 else 1386 mwifiex_clean_pcie_ring_buf(adapter); 1387 } 1388 1389 return 0; 1390 } 1391 1392 /* This function sends data buffer to device. First 4 bytes of payload 1393 * are filled with payload length and payload type. Then this payload 1394 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. 1395 * Download ready interrupt to FW is deffered if Tx ring is not full and 1396 * additional payload can be accomodated. 1397 * Caller must ensure tx_param parameter to this function is not NULL. 1398 */ 1399 static int 1400 mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, 1401 struct mwifiex_tx_param *tx_param) 1402 { 1403 struct pcie_service_card *card = adapter->card; 1404 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1405 u32 wrindx, num_tx_buffs, rx_val; 1406 int ret; 1407 dma_addr_t buf_pa; 1408 struct mwifiex_pcie_buf_desc *desc = NULL; 1409 struct mwifiex_pfu_buf_desc *desc2 = NULL; 1410 1411 if (!(skb->data && skb->len)) { 1412 mwifiex_dbg(adapter, ERROR, 1413 "%s(): invalid parameter <%p, %#x>\n", 1414 __func__, skb->data, skb->len); 1415 return -1; 1416 } 1417 1418 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1419 mwifiex_pm_wakeup_card(adapter); 1420 1421 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1422 mwifiex_dbg(adapter, DATA, 1423 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", 1424 card->txbd_rdptr, card->txbd_wrptr); 1425 if (mwifiex_pcie_txbd_not_full(card)) { 1426 u8 *payload; 1427 1428 adapter->data_sent = true; 1429 payload = skb->data; 1430 put_unaligned_le16((u16)skb->len, payload + 0); 1431 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); 1432 1433 if (mwifiex_map_pci_memory(adapter, skb, skb->len, 1434 DMA_TO_DEVICE)) 1435 return -1; 1436 1437 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; 1438 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1439 card->tx_buf_list[wrindx] = skb; 1440 atomic_inc(&adapter->tx_hw_pending); 1441 1442 if (reg->pfu_enabled) { 1443 desc2 = card->txbd_ring[wrindx]; 1444 desc2->paddr = buf_pa; 1445 desc2->len = (u16)skb->len; 1446 desc2->frag_len = (u16)skb->len; 1447 desc2->offset = 0; 1448 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1449 MWIFIEX_BD_FLAG_LAST_DESC; 1450 } else { 1451 desc = card->txbd_ring[wrindx]; 1452 desc->paddr = buf_pa; 1453 desc->len = (u16)skb->len; 1454 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1455 MWIFIEX_BD_FLAG_LAST_DESC; 1456 } 1457 1458 switch (card->dev->device) { 1459 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1460 card->txbd_wrptr++; 1461 break; 1462 case PCIE_DEVICE_ID_MARVELL_88W8897: 1463 case PCIE_DEVICE_ID_MARVELL_88W8997: 1464 card->txbd_wrptr += reg->ring_tx_start_ptr; 1465 break; 1466 } 1467 1468 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) 1469 card->txbd_wrptr = ((card->txbd_wrptr & 1470 reg->tx_rollover_ind) ^ 1471 reg->tx_rollover_ind); 1472 1473 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; 1474 /* Write the TX ring write pointer in to reg->tx_wrptr */ 1475 if (mwifiex_write_reg(adapter, reg->tx_wrptr, 1476 card->txbd_wrptr | rx_val)) { 1477 mwifiex_dbg(adapter, ERROR, 1478 "SEND DATA: failed to write reg->tx_wrptr\n"); 1479 ret = -1; 1480 goto done_unmap; 1481 } 1482 if ((mwifiex_pcie_txbd_not_full(card)) && 1483 tx_param->next_pkt_len) { 1484 /* have more packets and TxBD still can hold more */ 1485 mwifiex_dbg(adapter, DATA, 1486 "SEND DATA: delay dnld-rdy interrupt.\n"); 1487 adapter->data_sent = false; 1488 } else { 1489 /* Send the TX ready interrupt */ 1490 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1491 CPU_INTR_DNLD_RDY)) { 1492 mwifiex_dbg(adapter, ERROR, 1493 "SEND DATA: failed to assert dnld-rdy interrupt.\n"); 1494 ret = -1; 1495 goto done_unmap; 1496 } 1497 } 1498 mwifiex_dbg(adapter, DATA, 1499 "info: SEND DATA: Updated <Rd: %#x, Wr:\t" 1500 "%#x> and sent packet to firmware successfully\n", 1501 card->txbd_rdptr, card->txbd_wrptr); 1502 } else { 1503 mwifiex_dbg(adapter, DATA, 1504 "info: TX Ring full, can't send packets to fw\n"); 1505 adapter->data_sent = true; 1506 /* Send the TX ready interrupt */ 1507 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1508 CPU_INTR_DNLD_RDY)) 1509 mwifiex_dbg(adapter, ERROR, 1510 "SEND DATA: failed to assert door-bell intr\n"); 1511 return -EBUSY; 1512 } 1513 1514 return -EINPROGRESS; 1515 done_unmap: 1516 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1517 card->tx_buf_list[wrindx] = NULL; 1518 atomic_dec(&adapter->tx_hw_pending); 1519 if (reg->pfu_enabled) 1520 memset(desc2, 0, sizeof(*desc2)); 1521 else 1522 memset(desc, 0, sizeof(*desc)); 1523 1524 return ret; 1525 } 1526 1527 /* 1528 * This function handles received buffer ring and 1529 * dispatches packets to upper 1530 */ 1531 static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) 1532 { 1533 struct pcie_service_card *card = adapter->card; 1534 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1535 u32 wrptr, rd_index, tx_val; 1536 dma_addr_t buf_pa; 1537 int ret = 0; 1538 struct sk_buff *skb_tmp = NULL; 1539 struct mwifiex_pcie_buf_desc *desc; 1540 struct mwifiex_pfu_buf_desc *desc2; 1541 1542 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1543 mwifiex_pm_wakeup_card(adapter); 1544 1545 /* Read the RX ring Write pointer set by firmware */ 1546 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1547 mwifiex_dbg(adapter, ERROR, 1548 "RECV DATA: failed to read reg->rx_wrptr\n"); 1549 ret = -1; 1550 goto done; 1551 } 1552 card->rxbd_wrptr = wrptr; 1553 1554 while (((wrptr & reg->rx_mask) != 1555 (card->rxbd_rdptr & reg->rx_mask)) || 1556 ((wrptr & reg->rx_rollover_ind) == 1557 (card->rxbd_rdptr & reg->rx_rollover_ind))) { 1558 struct sk_buff *skb_data; 1559 u16 rx_len; 1560 1561 rd_index = card->rxbd_rdptr & reg->rx_mask; 1562 skb_data = card->rx_buf_list[rd_index]; 1563 1564 /* If skb allocation was failed earlier for Rx packet, 1565 * rx_buf_list[rd_index] would have been left with a NULL. 1566 */ 1567 if (!skb_data) 1568 return -ENOMEM; 1569 1570 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); 1571 card->rx_buf_list[rd_index] = NULL; 1572 1573 /* Get data length from interface header - 1574 * first 2 bytes for len, next 2 bytes is for type 1575 */ 1576 rx_len = get_unaligned_le16(skb_data->data); 1577 if (WARN_ON(rx_len <= adapter->intf_hdr_len || 1578 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) { 1579 mwifiex_dbg(adapter, ERROR, 1580 "Invalid RX len %d, Rd=%#x, Wr=%#x\n", 1581 rx_len, card->rxbd_rdptr, wrptr); 1582 dev_kfree_skb_any(skb_data); 1583 } else { 1584 skb_put(skb_data, rx_len); 1585 mwifiex_dbg(adapter, DATA, 1586 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", 1587 card->rxbd_rdptr, wrptr, rx_len); 1588 skb_pull(skb_data, adapter->intf_hdr_len); 1589 if (adapter->rx_work_enabled) { 1590 skb_queue_tail(&adapter->rx_data_q, skb_data); 1591 adapter->data_received = true; 1592 atomic_inc(&adapter->rx_pending); 1593 } else { 1594 mwifiex_handle_rx_packet(adapter, skb_data); 1595 } 1596 } 1597 1598 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 1599 GFP_KERNEL); 1600 if (!skb_tmp) { 1601 mwifiex_dbg(adapter, ERROR, 1602 "Unable to allocate skb.\n"); 1603 return -ENOMEM; 1604 } 1605 1606 if (mwifiex_map_pci_memory(adapter, skb_tmp, 1607 MWIFIEX_RX_DATA_BUF_SIZE, 1608 DMA_FROM_DEVICE)) 1609 return -1; 1610 1611 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); 1612 1613 mwifiex_dbg(adapter, INFO, 1614 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", 1615 skb_tmp, rd_index); 1616 card->rx_buf_list[rd_index] = skb_tmp; 1617 1618 if (reg->pfu_enabled) { 1619 desc2 = card->rxbd_ring[rd_index]; 1620 desc2->paddr = buf_pa; 1621 desc2->len = skb_tmp->len; 1622 desc2->frag_len = skb_tmp->len; 1623 desc2->offset = 0; 1624 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; 1625 } else { 1626 desc = card->rxbd_ring[rd_index]; 1627 desc->paddr = buf_pa; 1628 desc->len = skb_tmp->len; 1629 desc->flags = 0; 1630 } 1631 1632 if ((++card->rxbd_rdptr & reg->rx_mask) == 1633 MWIFIEX_MAX_TXRX_BD) { 1634 card->rxbd_rdptr = ((card->rxbd_rdptr & 1635 reg->rx_rollover_ind) ^ 1636 reg->rx_rollover_ind); 1637 } 1638 mwifiex_dbg(adapter, DATA, 1639 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", 1640 card->rxbd_rdptr, wrptr); 1641 1642 tx_val = card->txbd_wrptr & reg->tx_wrap_mask; 1643 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1644 if (mwifiex_write_reg(adapter, reg->rx_rdptr, 1645 card->rxbd_rdptr | tx_val)) { 1646 mwifiex_dbg(adapter, DATA, 1647 "RECV DATA: failed to write reg->rx_rdptr\n"); 1648 ret = -1; 1649 goto done; 1650 } 1651 1652 /* Read the RX ring Write pointer set by firmware */ 1653 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1654 mwifiex_dbg(adapter, ERROR, 1655 "RECV DATA: failed to read reg->rx_wrptr\n"); 1656 ret = -1; 1657 goto done; 1658 } 1659 mwifiex_dbg(adapter, DATA, 1660 "info: RECV DATA: Rcvd packet from fw successfully\n"); 1661 card->rxbd_wrptr = wrptr; 1662 } 1663 1664 done: 1665 return ret; 1666 } 1667 1668 /* 1669 * This function downloads the boot command to device 1670 */ 1671 static int 1672 mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1673 { 1674 dma_addr_t buf_pa; 1675 struct pcie_service_card *card = adapter->card; 1676 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1677 1678 if (!(skb->data && skb->len)) { 1679 mwifiex_dbg(adapter, ERROR, 1680 "Invalid parameter in %s <%p. len %d>\n", 1681 __func__, skb->data, skb->len); 1682 return -1; 1683 } 1684 1685 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1686 return -1; 1687 1688 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1689 1690 /* Write the lower 32bits of the physical address to low command 1691 * address scratch register 1692 */ 1693 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { 1694 mwifiex_dbg(adapter, ERROR, 1695 "%s: failed to write download command to boot code.\n", 1696 __func__); 1697 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1698 return -1; 1699 } 1700 1701 /* Write the upper 32bits of the physical address to high command 1702 * address scratch register 1703 */ 1704 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1705 (u32)((u64)buf_pa >> 32))) { 1706 mwifiex_dbg(adapter, ERROR, 1707 "%s: failed to write download command to boot code.\n", 1708 __func__); 1709 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1710 return -1; 1711 } 1712 1713 /* Write the command length to cmd_size scratch register */ 1714 if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { 1715 mwifiex_dbg(adapter, ERROR, 1716 "%s: failed to write command len to cmd_size scratch reg\n", 1717 __func__); 1718 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1719 return -1; 1720 } 1721 1722 /* Ring the door bell */ 1723 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1724 CPU_INTR_DOOR_BELL)) { 1725 mwifiex_dbg(adapter, ERROR, 1726 "%s: failed to assert door-bell intr\n", __func__); 1727 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 1728 return -1; 1729 } 1730 1731 return 0; 1732 } 1733 1734 /* This function init rx port in firmware which in turn enables to receive data 1735 * from device before transmitting any packet. 1736 */ 1737 static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) 1738 { 1739 struct pcie_service_card *card = adapter->card; 1740 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1741 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; 1742 1743 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1744 if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | 1745 tx_wrap)) { 1746 mwifiex_dbg(adapter, ERROR, 1747 "RECV DATA: failed to write reg->rx_rdptr\n"); 1748 return -1; 1749 } 1750 return 0; 1751 } 1752 1753 /* This function downloads commands to the device 1754 */ 1755 static int 1756 mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1757 { 1758 struct pcie_service_card *card = adapter->card; 1759 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1760 int ret = 0; 1761 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; 1762 u8 *payload = (u8 *)skb->data; 1763 1764 if (!(skb->data && skb->len)) { 1765 mwifiex_dbg(adapter, ERROR, 1766 "Invalid parameter in %s <%p, %#x>\n", 1767 __func__, skb->data, skb->len); 1768 return -1; 1769 } 1770 1771 /* Make sure a command response buffer is available */ 1772 if (!card->cmdrsp_buf) { 1773 mwifiex_dbg(adapter, ERROR, 1774 "No response buffer available, send command failed\n"); 1775 return -EBUSY; 1776 } 1777 1778 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1779 mwifiex_pm_wakeup_card(adapter); 1780 1781 adapter->cmd_sent = true; 1782 1783 put_unaligned_le16((u16)skb->len, &payload[0]); 1784 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); 1785 1786 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1787 return -1; 1788 1789 card->cmd_buf = skb; 1790 /* 1791 * Need to keep a reference, since core driver might free up this 1792 * buffer before we've unmapped it. 1793 */ 1794 skb_get(skb); 1795 1796 /* To send a command, the driver will: 1797 1. Write the 64bit physical address of the data buffer to 1798 cmd response address low + cmd response address high 1799 2. Ring the door bell (i.e. set the door bell interrupt) 1800 1801 In response to door bell interrupt, the firmware will perform 1802 the DMA of the command packet (first header to obtain the total 1803 length and then rest of the command). 1804 */ 1805 1806 if (card->cmdrsp_buf) { 1807 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); 1808 /* Write the lower 32bits of the cmdrsp buffer physical 1809 address */ 1810 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 1811 (u32)cmdrsp_buf_pa)) { 1812 mwifiex_dbg(adapter, ERROR, 1813 "Failed to write download cmd to boot code.\n"); 1814 ret = -1; 1815 goto done; 1816 } 1817 /* Write the upper 32bits of the cmdrsp buffer physical 1818 address */ 1819 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 1820 (u32)((u64)cmdrsp_buf_pa >> 32))) { 1821 mwifiex_dbg(adapter, ERROR, 1822 "Failed to write download cmd to boot code.\n"); 1823 ret = -1; 1824 goto done; 1825 } 1826 } 1827 1828 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); 1829 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ 1830 if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, 1831 (u32)cmd_buf_pa)) { 1832 mwifiex_dbg(adapter, ERROR, 1833 "Failed to write download cmd to boot code.\n"); 1834 ret = -1; 1835 goto done; 1836 } 1837 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ 1838 if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1839 (u32)((u64)cmd_buf_pa >> 32))) { 1840 mwifiex_dbg(adapter, ERROR, 1841 "Failed to write download cmd to boot code.\n"); 1842 ret = -1; 1843 goto done; 1844 } 1845 1846 /* Write the command length to reg->cmd_size */ 1847 if (mwifiex_write_reg(adapter, reg->cmd_size, 1848 card->cmd_buf->len)) { 1849 mwifiex_dbg(adapter, ERROR, 1850 "Failed to write cmd len to reg->cmd_size\n"); 1851 ret = -1; 1852 goto done; 1853 } 1854 1855 /* Ring the door bell */ 1856 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1857 CPU_INTR_DOOR_BELL)) { 1858 mwifiex_dbg(adapter, ERROR, 1859 "Failed to assert door-bell intr\n"); 1860 ret = -1; 1861 goto done; 1862 } 1863 1864 done: 1865 if (ret) 1866 adapter->cmd_sent = false; 1867 1868 return 0; 1869 } 1870 1871 /* 1872 * This function handles command complete interrupt 1873 */ 1874 static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) 1875 { 1876 struct pcie_service_card *card = adapter->card; 1877 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1878 struct sk_buff *skb = card->cmdrsp_buf; 1879 int count = 0; 1880 u16 rx_len; 1881 1882 mwifiex_dbg(adapter, CMD, 1883 "info: Rx CMD Response\n"); 1884 1885 if (adapter->curr_cmd) 1886 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); 1887 else 1888 dma_sync_single_for_cpu(&card->dev->dev, 1889 MWIFIEX_SKB_DMA_ADDR(skb), 1890 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); 1891 1892 /* Unmap the command as a response has been received. */ 1893 if (card->cmd_buf) { 1894 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1895 DMA_TO_DEVICE); 1896 dev_kfree_skb_any(card->cmd_buf); 1897 card->cmd_buf = NULL; 1898 } 1899 1900 rx_len = get_unaligned_le16(skb->data); 1901 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 1902 skb_trim(skb, rx_len); 1903 1904 if (!adapter->curr_cmd) { 1905 if (adapter->ps_state == PS_STATE_SLEEP_CFM) { 1906 dma_sync_single_for_device(&card->dev->dev, 1907 MWIFIEX_SKB_DMA_ADDR(skb), 1908 MWIFIEX_SLEEP_COOKIE_SIZE, 1909 DMA_FROM_DEVICE); 1910 if (mwifiex_write_reg(adapter, 1911 PCIE_CPU_INT_EVENT, 1912 CPU_INTR_SLEEP_CFM_DONE)) { 1913 mwifiex_dbg(adapter, ERROR, 1914 "Write register failed\n"); 1915 return -1; 1916 } 1917 mwifiex_delay_for_sleep_cookie(adapter, 1918 MWIFIEX_MAX_DELAY_COUNT); 1919 mwifiex_unmap_pci_memory(adapter, skb, 1920 DMA_FROM_DEVICE); 1921 skb_pull(skb, adapter->intf_hdr_len); 1922 while (reg->sleep_cookie && (count++ < 10) && 1923 mwifiex_pcie_ok_to_access_hw(adapter)) 1924 usleep_range(50, 60); 1925 mwifiex_pcie_enable_host_int(adapter); 1926 mwifiex_process_sleep_confirm_resp(adapter, skb->data, 1927 skb->len); 1928 } else { 1929 mwifiex_dbg(adapter, ERROR, 1930 "There is no command but got cmdrsp\n"); 1931 } 1932 memcpy(adapter->upld_buf, skb->data, 1933 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); 1934 skb_push(skb, adapter->intf_hdr_len); 1935 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1936 DMA_FROM_DEVICE)) 1937 return -1; 1938 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { 1939 skb_pull(skb, adapter->intf_hdr_len); 1940 adapter->curr_cmd->resp_skb = skb; 1941 adapter->cmd_resp_received = true; 1942 /* Take the pointer and set it to CMD node and will 1943 return in the response complete callback */ 1944 card->cmdrsp_buf = NULL; 1945 1946 /* Clear the cmd-rsp buffer address in scratch registers. This 1947 will prevent firmware from writing to the same response 1948 buffer again. */ 1949 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { 1950 mwifiex_dbg(adapter, ERROR, 1951 "cmd_done: failed to clear cmd_rsp_addr_lo\n"); 1952 return -1; 1953 } 1954 /* Write the upper 32bits of the cmdrsp buffer physical 1955 address */ 1956 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { 1957 mwifiex_dbg(adapter, ERROR, 1958 "cmd_done: failed to clear cmd_rsp_addr_hi\n"); 1959 return -1; 1960 } 1961 } 1962 1963 return 0; 1964 } 1965 1966 /* 1967 * Command Response processing complete handler 1968 */ 1969 static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, 1970 struct sk_buff *skb) 1971 { 1972 struct pcie_service_card *card = adapter->card; 1973 1974 if (skb) { 1975 card->cmdrsp_buf = skb; 1976 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); 1977 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1978 DMA_FROM_DEVICE)) 1979 return -1; 1980 } 1981 1982 return 0; 1983 } 1984 1985 /* 1986 * This function handles firmware event ready interrupt 1987 */ 1988 static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) 1989 { 1990 struct pcie_service_card *card = adapter->card; 1991 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1992 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 1993 u32 wrptr, event; 1994 struct mwifiex_evt_buf_desc *desc; 1995 1996 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1997 mwifiex_pm_wakeup_card(adapter); 1998 1999 if (adapter->event_received) { 2000 mwifiex_dbg(adapter, EVENT, 2001 "info: Event being processed,\t" 2002 "do not process this interrupt just yet\n"); 2003 return 0; 2004 } 2005 2006 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2007 mwifiex_dbg(adapter, ERROR, 2008 "info: Invalid read pointer...\n"); 2009 return -1; 2010 } 2011 2012 /* Read the event ring write pointer set by firmware */ 2013 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2014 mwifiex_dbg(adapter, ERROR, 2015 "EventReady: failed to read reg->evt_wrptr\n"); 2016 return -1; 2017 } 2018 2019 mwifiex_dbg(adapter, EVENT, 2020 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", 2021 card->evtbd_rdptr, wrptr); 2022 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr 2023 & MWIFIEX_EVTBD_MASK)) || 2024 ((wrptr & reg->evt_rollover_ind) == 2025 (card->evtbd_rdptr & reg->evt_rollover_ind))) { 2026 struct sk_buff *skb_cmd; 2027 __le16 data_len = 0; 2028 u16 evt_len; 2029 2030 mwifiex_dbg(adapter, INFO, 2031 "info: Read Index: %d\n", rdptr); 2032 skb_cmd = card->evt_buf_list[rdptr]; 2033 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); 2034 2035 /* Take the pointer and set it to event pointer in adapter 2036 and will return back after event handling callback */ 2037 card->evt_buf_list[rdptr] = NULL; 2038 desc = card->evtbd_ring[rdptr]; 2039 memset(desc, 0, sizeof(*desc)); 2040 2041 event = get_unaligned_le32( 2042 &skb_cmd->data[adapter->intf_hdr_len]); 2043 adapter->event_cause = event; 2044 /* The first 4bytes will be the event transfer header 2045 len is 2 bytes followed by type which is 2 bytes */ 2046 memcpy(&data_len, skb_cmd->data, sizeof(__le16)); 2047 evt_len = le16_to_cpu(data_len); 2048 skb_trim(skb_cmd, evt_len); 2049 skb_pull(skb_cmd, adapter->intf_hdr_len); 2050 mwifiex_dbg(adapter, EVENT, 2051 "info: Event length: %d\n", evt_len); 2052 2053 if (evt_len > MWIFIEX_EVENT_HEADER_LEN && 2054 evt_len < MAX_EVENT_SIZE) 2055 memcpy(adapter->event_body, skb_cmd->data + 2056 MWIFIEX_EVENT_HEADER_LEN, evt_len - 2057 MWIFIEX_EVENT_HEADER_LEN); 2058 2059 adapter->event_received = true; 2060 adapter->event_skb = skb_cmd; 2061 2062 /* Do not update the event read pointer here, wait till the 2063 buffer is released. This is just to make things simpler, 2064 we need to find a better method of managing these buffers. 2065 */ 2066 } else { 2067 if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 2068 CPU_INTR_EVENT_DONE)) { 2069 mwifiex_dbg(adapter, ERROR, 2070 "Write register failed\n"); 2071 return -1; 2072 } 2073 } 2074 2075 return 0; 2076 } 2077 2078 /* 2079 * Event processing complete handler 2080 */ 2081 static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, 2082 struct sk_buff *skb) 2083 { 2084 struct pcie_service_card *card = adapter->card; 2085 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2086 int ret = 0; 2087 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 2088 u32 wrptr; 2089 struct mwifiex_evt_buf_desc *desc; 2090 2091 if (!skb) 2092 return 0; 2093 2094 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2095 mwifiex_dbg(adapter, ERROR, 2096 "event_complete: Invalid rdptr 0x%x\n", 2097 rdptr); 2098 return -EINVAL; 2099 } 2100 2101 /* Read the event ring write pointer set by firmware */ 2102 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2103 mwifiex_dbg(adapter, ERROR, 2104 "event_complete: failed to read reg->evt_wrptr\n"); 2105 return -1; 2106 } 2107 2108 if (!card->evt_buf_list[rdptr]) { 2109 skb_push(skb, adapter->intf_hdr_len); 2110 skb_put(skb, MAX_EVENT_SIZE - skb->len); 2111 if (mwifiex_map_pci_memory(adapter, skb, 2112 MAX_EVENT_SIZE, 2113 DMA_FROM_DEVICE)) 2114 return -1; 2115 card->evt_buf_list[rdptr] = skb; 2116 desc = card->evtbd_ring[rdptr]; 2117 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); 2118 desc->len = (u16)skb->len; 2119 desc->flags = 0; 2120 skb = NULL; 2121 } else { 2122 mwifiex_dbg(adapter, ERROR, 2123 "info: ERROR: buf still valid at index %d, <%p, %p>\n", 2124 rdptr, card->evt_buf_list[rdptr], skb); 2125 } 2126 2127 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { 2128 card->evtbd_rdptr = ((card->evtbd_rdptr & 2129 reg->evt_rollover_ind) ^ 2130 reg->evt_rollover_ind); 2131 } 2132 2133 mwifiex_dbg(adapter, EVENT, 2134 "info: Updated <Rd: 0x%x, Wr: 0x%x>", 2135 card->evtbd_rdptr, wrptr); 2136 2137 /* Write the event ring read pointer in to reg->evt_rdptr */ 2138 if (mwifiex_write_reg(adapter, reg->evt_rdptr, 2139 card->evtbd_rdptr)) { 2140 mwifiex_dbg(adapter, ERROR, 2141 "event_complete: failed to read reg->evt_rdptr\n"); 2142 return -1; 2143 } 2144 2145 mwifiex_dbg(adapter, EVENT, 2146 "info: Check Events Again\n"); 2147 ret = mwifiex_pcie_process_event_ready(adapter); 2148 2149 return ret; 2150 } 2151 2152 /* Combo firmware image is a combination of 2153 * (1) combo crc heaer, start with CMD5 2154 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1. 2155 * (3) wifi image. 2156 * 2157 * This function bypass the header and bluetooth part, return 2158 * the offset of tail wifi-only part. If the image is already wifi-only, 2159 * that is start with CMD1, return 0. 2160 */ 2161 2162 static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter, 2163 const void *firmware, u32 firmware_len) { 2164 const struct mwifiex_fw_data *fwdata; 2165 u32 offset = 0, data_len, dnld_cmd; 2166 int ret = 0; 2167 bool cmd7_before = false, first_cmd = false; 2168 2169 while (1) { 2170 /* Check for integer and buffer overflow */ 2171 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) || 2172 offset + sizeof(fwdata->header) >= firmware_len) { 2173 mwifiex_dbg(adapter, ERROR, 2174 "extract wifi-only fw failure!\n"); 2175 ret = -1; 2176 goto done; 2177 } 2178 2179 fwdata = firmware + offset; 2180 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd); 2181 data_len = le32_to_cpu(fwdata->header.data_length); 2182 2183 /* Skip past header */ 2184 offset += sizeof(fwdata->header); 2185 2186 switch (dnld_cmd) { 2187 case MWIFIEX_FW_DNLD_CMD_1: 2188 if (offset + data_len < data_len) { 2189 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2190 ret = -1; 2191 goto done; 2192 } 2193 2194 /* Image start with cmd1, already wifi-only firmware */ 2195 if (!first_cmd) { 2196 mwifiex_dbg(adapter, MSG, 2197 "input wifi-only firmware\n"); 2198 return 0; 2199 } 2200 2201 if (!cmd7_before) { 2202 mwifiex_dbg(adapter, ERROR, 2203 "no cmd7 before cmd1!\n"); 2204 ret = -1; 2205 goto done; 2206 } 2207 offset += data_len; 2208 break; 2209 case MWIFIEX_FW_DNLD_CMD_5: 2210 first_cmd = true; 2211 /* Check for integer overflow */ 2212 if (offset + data_len < data_len) { 2213 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2214 ret = -1; 2215 goto done; 2216 } 2217 offset += data_len; 2218 break; 2219 case MWIFIEX_FW_DNLD_CMD_6: 2220 first_cmd = true; 2221 /* Check for integer overflow */ 2222 if (offset + data_len < data_len) { 2223 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2224 ret = -1; 2225 goto done; 2226 } 2227 offset += data_len; 2228 if (offset >= firmware_len) { 2229 mwifiex_dbg(adapter, ERROR, 2230 "extract wifi-only fw failure!\n"); 2231 ret = -1; 2232 } else { 2233 ret = offset; 2234 } 2235 goto done; 2236 case MWIFIEX_FW_DNLD_CMD_7: 2237 first_cmd = true; 2238 cmd7_before = true; 2239 break; 2240 default: 2241 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n", 2242 dnld_cmd); 2243 ret = -1; 2244 goto done; 2245 } 2246 } 2247 2248 done: 2249 return ret; 2250 } 2251 2252 /* 2253 * This function downloads the firmware to the card. 2254 * 2255 * Firmware is downloaded to the card in blocks. Every block download 2256 * is tested for CRC errors, and retried a number of times before 2257 * returning failure. 2258 */ 2259 static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, 2260 struct mwifiex_fw_image *fw) 2261 { 2262 int ret; 2263 u8 *firmware = fw->fw_buf; 2264 u32 firmware_len = fw->fw_len; 2265 u32 offset = 0; 2266 struct sk_buff *skb; 2267 u32 txlen, tx_blocks = 0, tries, len, val; 2268 u32 block_retry_cnt = 0; 2269 struct pcie_service_card *card = adapter->card; 2270 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2271 2272 if (!firmware || !firmware_len) { 2273 mwifiex_dbg(adapter, ERROR, 2274 "No firmware image found! Terminating download\n"); 2275 return -1; 2276 } 2277 2278 mwifiex_dbg(adapter, INFO, 2279 "info: Downloading FW image (%d bytes)\n", 2280 firmware_len); 2281 2282 if (mwifiex_pcie_disable_host_int(adapter)) { 2283 mwifiex_dbg(adapter, ERROR, 2284 "%s: Disabling interrupts failed.\n", __func__); 2285 return -1; 2286 } 2287 2288 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 2289 if (!skb) { 2290 ret = -ENOMEM; 2291 goto done; 2292 } 2293 2294 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val); 2295 if (ret) { 2296 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n"); 2297 goto done; 2298 } 2299 2300 /* PCIE FLR case: extract wifi part from combo firmware*/ 2301 if (val == MWIFIEX_PCIE_FLR_HAPPENS) { 2302 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len); 2303 if (ret < 0) { 2304 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n"); 2305 goto done; 2306 } 2307 offset = ret; 2308 mwifiex_dbg(adapter, MSG, 2309 "info: dnld wifi firmware from %d bytes\n", offset); 2310 } 2311 2312 /* Perform firmware data transfer */ 2313 do { 2314 u32 ireg_intr = 0; 2315 2316 /* More data? */ 2317 if (offset >= firmware_len) 2318 break; 2319 2320 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2321 ret = mwifiex_read_reg(adapter, reg->cmd_size, 2322 &len); 2323 if (ret) { 2324 mwifiex_dbg(adapter, FATAL, 2325 "Failed reading len from boot code\n"); 2326 goto done; 2327 } 2328 if (len) 2329 break; 2330 usleep_range(10, 20); 2331 } 2332 2333 if (!len) { 2334 break; 2335 } else if (len > MWIFIEX_UPLD_SIZE) { 2336 mwifiex_dbg(adapter, ERROR, 2337 "FW download failure @ %d, invalid length %d\n", 2338 offset, len); 2339 ret = -1; 2340 goto done; 2341 } 2342 2343 txlen = len; 2344 2345 if (len & BIT(0)) { 2346 block_retry_cnt++; 2347 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { 2348 mwifiex_dbg(adapter, ERROR, 2349 "FW download failure @ %d, over max\t" 2350 "retry count\n", offset); 2351 ret = -1; 2352 goto done; 2353 } 2354 mwifiex_dbg(adapter, ERROR, 2355 "FW CRC error indicated by the\t" 2356 "helper: len = 0x%04X, txlen = %d\n", 2357 len, txlen); 2358 len &= ~BIT(0); 2359 /* Setting this to 0 to resend from same offset */ 2360 txlen = 0; 2361 } else { 2362 block_retry_cnt = 0; 2363 /* Set blocksize to transfer - checking for 2364 last block */ 2365 if (firmware_len - offset < txlen) 2366 txlen = firmware_len - offset; 2367 2368 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / 2369 card->pcie.blksz_fw_dl; 2370 2371 /* Copy payload to buffer */ 2372 memmove(skb->data, &firmware[offset], txlen); 2373 } 2374 2375 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 2376 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); 2377 2378 /* Send the boot command to device */ 2379 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { 2380 mwifiex_dbg(adapter, ERROR, 2381 "Failed to send firmware download command\n"); 2382 ret = -1; 2383 goto done; 2384 } 2385 2386 /* Wait for the command done interrupt */ 2387 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2388 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, 2389 &ireg_intr)) { 2390 mwifiex_dbg(adapter, ERROR, 2391 "%s: Failed to read\t" 2392 "interrupt status during fw dnld.\n", 2393 __func__); 2394 mwifiex_unmap_pci_memory(adapter, skb, 2395 DMA_TO_DEVICE); 2396 ret = -1; 2397 goto done; 2398 } 2399 if (!(ireg_intr & CPU_INTR_DOOR_BELL)) 2400 break; 2401 usleep_range(10, 20); 2402 } 2403 if (ireg_intr & CPU_INTR_DOOR_BELL) { 2404 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", 2405 __func__); 2406 mwifiex_unmap_pci_memory(adapter, skb, 2407 DMA_TO_DEVICE); 2408 ret = -1; 2409 goto done; 2410 } 2411 2412 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 2413 2414 offset += txlen; 2415 } while (true); 2416 2417 mwifiex_dbg(adapter, MSG, 2418 "info: FW download over, size %d bytes\n", offset); 2419 2420 ret = 0; 2421 2422 done: 2423 dev_kfree_skb_any(skb); 2424 return ret; 2425 } 2426 2427 /* 2428 * This function checks the firmware status in card. 2429 */ 2430 static int 2431 mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) 2432 { 2433 int ret = 0; 2434 u32 firmware_stat; 2435 struct pcie_service_card *card = adapter->card; 2436 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2437 u32 tries; 2438 2439 /* Mask spurios interrupts */ 2440 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, 2441 HOST_INTR_MASK)) { 2442 mwifiex_dbg(adapter, ERROR, 2443 "Write register failed\n"); 2444 return -1; 2445 } 2446 2447 mwifiex_dbg(adapter, INFO, 2448 "Setting driver ready signature\n"); 2449 if (mwifiex_write_reg(adapter, reg->drv_rdy, 2450 FIRMWARE_READY_PCIE)) { 2451 mwifiex_dbg(adapter, ERROR, 2452 "Failed to write driver ready signature\n"); 2453 return -1; 2454 } 2455 2456 /* Wait for firmware initialization event */ 2457 for (tries = 0; tries < poll_num; tries++) { 2458 if (mwifiex_read_reg(adapter, reg->fw_status, 2459 &firmware_stat)) 2460 ret = -1; 2461 else 2462 ret = 0; 2463 2464 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>", 2465 tries, ret, firmware_stat); 2466 2467 if (ret) 2468 continue; 2469 if (firmware_stat == FIRMWARE_READY_PCIE) { 2470 ret = 0; 2471 break; 2472 } else { 2473 msleep(100); 2474 ret = -1; 2475 } 2476 } 2477 2478 return ret; 2479 } 2480 2481 /* This function checks if WLAN is the winner. 2482 */ 2483 static int 2484 mwifiex_check_winner_status(struct mwifiex_adapter *adapter) 2485 { 2486 u32 winner = 0; 2487 int ret = 0; 2488 struct pcie_service_card *card = adapter->card; 2489 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2490 2491 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) { 2492 ret = -1; 2493 } else if (!winner) { 2494 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n"); 2495 adapter->winner = 1; 2496 } else { 2497 mwifiex_dbg(adapter, ERROR, 2498 "PCI-E is not the winner <%#x>", winner); 2499 } 2500 2501 return ret; 2502 } 2503 2504 /* 2505 * This function reads the interrupt status from card. 2506 */ 2507 static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter, 2508 int msg_id) 2509 { 2510 u32 pcie_ireg; 2511 unsigned long flags; 2512 struct pcie_service_card *card = adapter->card; 2513 2514 if (card->msi_enable) { 2515 spin_lock_irqsave(&adapter->int_lock, flags); 2516 adapter->int_status = 1; 2517 spin_unlock_irqrestore(&adapter->int_lock, flags); 2518 return; 2519 } 2520 2521 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 2522 return; 2523 2524 if (card->msix_enable && msg_id >= 0) { 2525 pcie_ireg = BIT(msg_id); 2526 } else { 2527 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2528 &pcie_ireg)) { 2529 mwifiex_dbg(adapter, ERROR, "Read register failed\n"); 2530 return; 2531 } 2532 2533 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) 2534 return; 2535 2536 2537 mwifiex_pcie_disable_host_int(adapter); 2538 2539 /* Clear the pending interrupts */ 2540 if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, 2541 ~pcie_ireg)) { 2542 mwifiex_dbg(adapter, ERROR, 2543 "Write register failed\n"); 2544 return; 2545 } 2546 } 2547 2548 if (!adapter->pps_uapsd_mode && 2549 adapter->ps_state == PS_STATE_SLEEP && 2550 mwifiex_pcie_ok_to_access_hw(adapter)) { 2551 /* Potentially for PCIe we could get other 2552 * interrupts like shared. Don't change power 2553 * state until cookie is set 2554 */ 2555 adapter->ps_state = PS_STATE_AWAKE; 2556 adapter->pm_wakeup_fw_try = false; 2557 del_timer(&adapter->wakeup_timer); 2558 } 2559 2560 spin_lock_irqsave(&adapter->int_lock, flags); 2561 adapter->int_status |= pcie_ireg; 2562 spin_unlock_irqrestore(&adapter->int_lock, flags); 2563 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); 2564 } 2565 2566 /* 2567 * Interrupt handler for PCIe root port 2568 * 2569 * This function reads the interrupt status from firmware and assigns 2570 * the main process in workqueue which will handle the interrupt. 2571 */ 2572 static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) 2573 { 2574 struct mwifiex_msix_context *ctx = context; 2575 struct pci_dev *pdev = ctx->dev; 2576 struct pcie_service_card *card; 2577 struct mwifiex_adapter *adapter; 2578 2579 card = pci_get_drvdata(pdev); 2580 2581 if (!card->adapter) { 2582 pr_err("info: %s: card=%p adapter=%p\n", __func__, card, 2583 card ? card->adapter : NULL); 2584 goto exit; 2585 } 2586 adapter = card->adapter; 2587 2588 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags)) 2589 goto exit; 2590 2591 if (card->msix_enable) 2592 mwifiex_interrupt_status(adapter, ctx->msg_id); 2593 else 2594 mwifiex_interrupt_status(adapter, -1); 2595 2596 mwifiex_queue_main_work(adapter); 2597 2598 exit: 2599 return IRQ_HANDLED; 2600 } 2601 2602 /* 2603 * This function checks the current interrupt status. 2604 * 2605 * The following interrupts are checked and handled by this function - 2606 * - Data sent 2607 * - Command sent 2608 * - Command received 2609 * - Packets received 2610 * - Events received 2611 * 2612 * In case of Rx packets received, the packets are uploaded from card to 2613 * host and processed accordingly. 2614 */ 2615 static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) 2616 { 2617 int ret; 2618 u32 pcie_ireg = 0; 2619 unsigned long flags; 2620 struct pcie_service_card *card = adapter->card; 2621 2622 spin_lock_irqsave(&adapter->int_lock, flags); 2623 if (!card->msi_enable) { 2624 /* Clear out unused interrupts */ 2625 pcie_ireg = adapter->int_status; 2626 } 2627 adapter->int_status = 0; 2628 spin_unlock_irqrestore(&adapter->int_lock, flags); 2629 2630 if (card->msi_enable) { 2631 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 2632 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2633 &pcie_ireg)) { 2634 mwifiex_dbg(adapter, ERROR, 2635 "Read register failed\n"); 2636 return -1; 2637 } 2638 2639 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { 2640 if (mwifiex_write_reg(adapter, 2641 PCIE_HOST_INT_STATUS, 2642 ~pcie_ireg)) { 2643 mwifiex_dbg(adapter, ERROR, 2644 "Write register failed\n"); 2645 return -1; 2646 } 2647 if (!adapter->pps_uapsd_mode && 2648 adapter->ps_state == PS_STATE_SLEEP) { 2649 adapter->ps_state = PS_STATE_AWAKE; 2650 adapter->pm_wakeup_fw_try = false; 2651 del_timer(&adapter->wakeup_timer); 2652 } 2653 } 2654 } 2655 } 2656 2657 if (pcie_ireg & HOST_INTR_DNLD_DONE) { 2658 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n"); 2659 ret = mwifiex_pcie_send_data_complete(adapter); 2660 if (ret) 2661 return ret; 2662 } 2663 if (pcie_ireg & HOST_INTR_UPLD_RDY) { 2664 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n"); 2665 ret = mwifiex_pcie_process_recv_data(adapter); 2666 if (ret) 2667 return ret; 2668 } 2669 if (pcie_ireg & HOST_INTR_EVENT_RDY) { 2670 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n"); 2671 ret = mwifiex_pcie_process_event_ready(adapter); 2672 if (ret) 2673 return ret; 2674 } 2675 if (pcie_ireg & HOST_INTR_CMD_DONE) { 2676 if (adapter->cmd_sent) { 2677 mwifiex_dbg(adapter, INTR, 2678 "info: CMD sent Interrupt\n"); 2679 adapter->cmd_sent = false; 2680 } 2681 /* Handle command response */ 2682 ret = mwifiex_pcie_process_cmd_complete(adapter); 2683 if (ret) 2684 return ret; 2685 } 2686 2687 mwifiex_dbg(adapter, INTR, 2688 "info: cmd_sent=%d data_sent=%d\n", 2689 adapter->cmd_sent, adapter->data_sent); 2690 if (!card->msi_enable && !card->msix_enable && 2691 adapter->ps_state != PS_STATE_SLEEP) 2692 mwifiex_pcie_enable_host_int(adapter); 2693 2694 return 0; 2695 } 2696 2697 /* 2698 * This function downloads data from driver to card. 2699 * 2700 * Both commands and data packets are transferred to the card by this 2701 * function. 2702 * 2703 * This function adds the PCIE specific header to the front of the buffer 2704 * before transferring. The header contains the length of the packet and 2705 * the type. The firmware handles the packets based upon this set type. 2706 */ 2707 static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, 2708 struct sk_buff *skb, 2709 struct mwifiex_tx_param *tx_param) 2710 { 2711 if (!skb) { 2712 mwifiex_dbg(adapter, ERROR, 2713 "Passed NULL skb to %s\n", __func__); 2714 return -1; 2715 } 2716 2717 if (type == MWIFIEX_TYPE_DATA) 2718 return mwifiex_pcie_send_data(adapter, skb, tx_param); 2719 else if (type == MWIFIEX_TYPE_CMD) 2720 return mwifiex_pcie_send_cmd(adapter, skb); 2721 2722 return 0; 2723 } 2724 2725 /* Function to dump PCIE scratch registers in case of FW crash 2726 */ 2727 static int 2728 mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf) 2729 { 2730 char *p = drv_buf; 2731 char buf[256], *ptr; 2732 int i; 2733 u32 value; 2734 struct pcie_service_card *card = adapter->card; 2735 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2736 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG, 2737 PCIE_SCRATCH_14_REG, 2738 PCIE_SCRATCH_15_REG}; 2739 2740 if (!p) 2741 return 0; 2742 2743 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n"); 2744 2745 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) { 2746 mwifiex_dbg(adapter, ERROR, "failed to read firmware status"); 2747 return 0; 2748 } 2749 2750 ptr = buf; 2751 mwifiex_dbg(adapter, MSG, "pcie scratch register:"); 2752 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { 2753 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value); 2754 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", 2755 pcie_scratch_reg[i], value); 2756 } 2757 2758 mwifiex_dbg(adapter, MSG, "%s\n", buf); 2759 p += sprintf(p, "%s\n", buf); 2760 2761 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n"); 2762 2763 return p - drv_buf; 2764 } 2765 2766 /* This function read/write firmware */ 2767 static enum rdwr_status 2768 mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag) 2769 { 2770 int ret, tries; 2771 u8 ctrl_data; 2772 u32 fw_status; 2773 struct pcie_service_card *card = adapter->card; 2774 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2775 2776 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) 2777 return RDWR_STATUS_FAILURE; 2778 2779 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2780 reg->fw_dump_host_ready); 2781 if (ret) { 2782 mwifiex_dbg(adapter, ERROR, 2783 "PCIE write err\n"); 2784 return RDWR_STATUS_FAILURE; 2785 } 2786 2787 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2788 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data); 2789 if (ctrl_data == FW_DUMP_DONE) 2790 return RDWR_STATUS_SUCCESS; 2791 if (doneflag && ctrl_data == doneflag) 2792 return RDWR_STATUS_DONE; 2793 if (ctrl_data != reg->fw_dump_host_ready) { 2794 mwifiex_dbg(adapter, WARN, 2795 "The ctrl reg was changed, re-try again!\n"); 2796 ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2797 reg->fw_dump_host_ready); 2798 if (ret) { 2799 mwifiex_dbg(adapter, ERROR, 2800 "PCIE write err\n"); 2801 return RDWR_STATUS_FAILURE; 2802 } 2803 } 2804 usleep_range(100, 200); 2805 } 2806 2807 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n"); 2808 return RDWR_STATUS_FAILURE; 2809 } 2810 2811 /* This function dump firmware memory to file */ 2812 static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter) 2813 { 2814 struct pcie_service_card *card = adapter->card; 2815 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; 2816 unsigned int reg, reg_start, reg_end; 2817 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num; 2818 u8 idx, i, read_reg, doneflag = 0; 2819 enum rdwr_status stat; 2820 u32 memory_size; 2821 int ret; 2822 2823 if (!card->pcie.can_dump_fw) 2824 return; 2825 2826 for (idx = 0; idx < adapter->num_mem_types; idx++) { 2827 struct memory_type_mapping *entry = 2828 &adapter->mem_type_mapping_tbl[idx]; 2829 2830 if (entry->mem_ptr) { 2831 vfree(entry->mem_ptr); 2832 entry->mem_ptr = NULL; 2833 } 2834 entry->mem_size = 0; 2835 } 2836 2837 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n"); 2838 2839 /* Read the number of the memories which will dump */ 2840 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2841 if (stat == RDWR_STATUS_FAILURE) 2842 return; 2843 2844 reg = creg->fw_dump_start; 2845 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num); 2846 2847 /* W8997 chipset firmware dump will be restore in single region*/ 2848 if (fw_dump_num == 0) 2849 dump_num = 1; 2850 else 2851 dump_num = fw_dump_num; 2852 2853 /* Read the length of every memory which will dump */ 2854 for (idx = 0; idx < dump_num; idx++) { 2855 struct memory_type_mapping *entry = 2856 &adapter->mem_type_mapping_tbl[idx]; 2857 memory_size = 0; 2858 if (fw_dump_num != 0) { 2859 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2860 if (stat == RDWR_STATUS_FAILURE) 2861 return; 2862 2863 reg = creg->fw_dump_start; 2864 for (i = 0; i < 4; i++) { 2865 mwifiex_read_reg_byte(adapter, reg, &read_reg); 2866 memory_size |= (read_reg << (i * 8)); 2867 reg++; 2868 } 2869 } else { 2870 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE; 2871 } 2872 2873 if (memory_size == 0) { 2874 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n"); 2875 ret = mwifiex_write_reg(adapter, creg->fw_dump_ctrl, 2876 creg->fw_dump_read_done); 2877 if (ret) { 2878 mwifiex_dbg(adapter, ERROR, "PCIE write err\n"); 2879 return; 2880 } 2881 break; 2882 } 2883 2884 mwifiex_dbg(adapter, DUMP, 2885 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); 2886 entry->mem_ptr = vmalloc(memory_size + 1); 2887 entry->mem_size = memory_size; 2888 if (!entry->mem_ptr) { 2889 mwifiex_dbg(adapter, ERROR, 2890 "Vmalloc %s failed\n", entry->mem_name); 2891 return; 2892 } 2893 dbg_ptr = entry->mem_ptr; 2894 end_ptr = dbg_ptr + memory_size; 2895 2896 doneflag = entry->done_flag; 2897 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n", 2898 entry->mem_name); 2899 2900 do { 2901 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2902 if (RDWR_STATUS_FAILURE == stat) 2903 return; 2904 2905 reg_start = creg->fw_dump_start; 2906 reg_end = creg->fw_dump_end; 2907 for (reg = reg_start; reg <= reg_end; reg++) { 2908 mwifiex_read_reg_byte(adapter, reg, dbg_ptr); 2909 if (dbg_ptr < end_ptr) { 2910 dbg_ptr++; 2911 continue; 2912 } 2913 mwifiex_dbg(adapter, ERROR, 2914 "pre-allocated buf not enough\n"); 2915 tmp_ptr = 2916 vzalloc(memory_size + MWIFIEX_SIZE_4K); 2917 if (!tmp_ptr) 2918 return; 2919 memcpy(tmp_ptr, entry->mem_ptr, memory_size); 2920 vfree(entry->mem_ptr); 2921 entry->mem_ptr = tmp_ptr; 2922 tmp_ptr = NULL; 2923 dbg_ptr = entry->mem_ptr + memory_size; 2924 memory_size += MWIFIEX_SIZE_4K; 2925 end_ptr = entry->mem_ptr + memory_size; 2926 } 2927 2928 if (stat != RDWR_STATUS_DONE) 2929 continue; 2930 2931 mwifiex_dbg(adapter, DUMP, 2932 "%s done: size=0x%tx\n", 2933 entry->mem_name, dbg_ptr - entry->mem_ptr); 2934 break; 2935 } while (true); 2936 } 2937 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n"); 2938 } 2939 2940 static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter) 2941 { 2942 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE); 2943 if (!adapter->devdump_data) { 2944 mwifiex_dbg(adapter, ERROR, 2945 "vzalloc devdump data failure!\n"); 2946 return; 2947 } 2948 2949 mwifiex_drv_info_dump(adapter); 2950 mwifiex_pcie_fw_dump(adapter); 2951 mwifiex_prepare_fw_dump_info(adapter); 2952 mwifiex_upload_device_dump(adapter); 2953 } 2954 2955 static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter) 2956 { 2957 struct pcie_service_card *card = adapter->card; 2958 2959 /* We can't afford to wait here; remove() might be waiting on us. If we 2960 * can't grab the device lock, maybe we'll get another chance later. 2961 */ 2962 pci_try_reset_function(card->dev); 2963 } 2964 2965 static void mwifiex_pcie_work(struct work_struct *work) 2966 { 2967 struct pcie_service_card *card = 2968 container_of(work, struct pcie_service_card, work); 2969 2970 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2971 &card->work_flags)) 2972 mwifiex_pcie_device_dump_work(card->adapter); 2973 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, 2974 &card->work_flags)) 2975 mwifiex_pcie_card_reset_work(card->adapter); 2976 } 2977 2978 /* This function dumps FW information */ 2979 static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter) 2980 { 2981 struct pcie_service_card *card = adapter->card; 2982 2983 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2984 &card->work_flags)) 2985 schedule_work(&card->work); 2986 } 2987 2988 static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter) 2989 { 2990 struct pcie_service_card *card = adapter->card; 2991 2992 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags)) 2993 schedule_work(&card->work); 2994 } 2995 2996 static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter) 2997 { 2998 struct pcie_service_card *card = adapter->card; 2999 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3000 int ret; 3001 3002 card->cmdrsp_buf = NULL; 3003 ret = mwifiex_pcie_create_txbd_ring(adapter); 3004 if (ret) { 3005 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n"); 3006 goto err_cre_txbd; 3007 } 3008 3009 ret = mwifiex_pcie_create_rxbd_ring(adapter); 3010 if (ret) { 3011 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n"); 3012 goto err_cre_rxbd; 3013 } 3014 3015 ret = mwifiex_pcie_create_evtbd_ring(adapter); 3016 if (ret) { 3017 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n"); 3018 goto err_cre_evtbd; 3019 } 3020 3021 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); 3022 if (ret) { 3023 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n"); 3024 goto err_alloc_cmdbuf; 3025 } 3026 3027 if (reg->sleep_cookie) { 3028 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); 3029 if (ret) { 3030 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n"); 3031 goto err_alloc_cookie; 3032 } 3033 } else { 3034 card->sleep_cookie_vbase = NULL; 3035 } 3036 3037 return 0; 3038 3039 err_alloc_cookie: 3040 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3041 err_alloc_cmdbuf: 3042 mwifiex_pcie_delete_evtbd_ring(adapter); 3043 err_cre_evtbd: 3044 mwifiex_pcie_delete_rxbd_ring(adapter); 3045 err_cre_rxbd: 3046 mwifiex_pcie_delete_txbd_ring(adapter); 3047 err_cre_txbd: 3048 return ret; 3049 } 3050 3051 static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter) 3052 { 3053 struct pcie_service_card *card = adapter->card; 3054 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3055 3056 if (reg->sleep_cookie) 3057 mwifiex_pcie_delete_sleep_cookie_buf(adapter); 3058 3059 mwifiex_pcie_delete_cmdrsp_buf(adapter); 3060 mwifiex_pcie_delete_evtbd_ring(adapter); 3061 mwifiex_pcie_delete_rxbd_ring(adapter); 3062 mwifiex_pcie_delete_txbd_ring(adapter); 3063 } 3064 3065 /* 3066 * This function initializes the PCI-E host memory space, WCB rings, etc. 3067 */ 3068 static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) 3069 { 3070 struct pcie_service_card *card = adapter->card; 3071 int ret; 3072 struct pci_dev *pdev = card->dev; 3073 3074 pci_set_drvdata(pdev, card); 3075 3076 ret = pci_enable_device(pdev); 3077 if (ret) 3078 goto err_enable_dev; 3079 3080 pci_set_master(pdev); 3081 3082 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3083 if (ret) { 3084 pr_err("dma_set_mask(32) failed: %d\n", ret); 3085 goto err_set_dma_mask; 3086 } 3087 3088 ret = pci_request_region(pdev, 0, DRV_NAME); 3089 if (ret) { 3090 pr_err("req_reg(0) error\n"); 3091 goto err_req_region0; 3092 } 3093 card->pci_mmap = pci_iomap(pdev, 0, 0); 3094 if (!card->pci_mmap) { 3095 pr_err("iomap(0) error\n"); 3096 ret = -EIO; 3097 goto err_iomap0; 3098 } 3099 ret = pci_request_region(pdev, 2, DRV_NAME); 3100 if (ret) { 3101 pr_err("req_reg(2) error\n"); 3102 goto err_req_region2; 3103 } 3104 card->pci_mmap1 = pci_iomap(pdev, 2, 0); 3105 if (!card->pci_mmap1) { 3106 pr_err("iomap(2) error\n"); 3107 ret = -EIO; 3108 goto err_iomap2; 3109 } 3110 3111 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n", 3112 card->pci_mmap, card->pci_mmap1); 3113 3114 ret = mwifiex_pcie_alloc_buffers(adapter); 3115 if (ret) 3116 goto err_alloc_buffers; 3117 3118 return 0; 3119 3120 err_alloc_buffers: 3121 pci_iounmap(pdev, card->pci_mmap1); 3122 err_iomap2: 3123 pci_release_region(pdev, 2); 3124 err_req_region2: 3125 pci_iounmap(pdev, card->pci_mmap); 3126 err_iomap0: 3127 pci_release_region(pdev, 0); 3128 err_req_region0: 3129 err_set_dma_mask: 3130 pci_disable_device(pdev); 3131 err_enable_dev: 3132 return ret; 3133 } 3134 3135 /* 3136 * This function cleans up the allocated card buffers. 3137 */ 3138 static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter) 3139 { 3140 struct pcie_service_card *card = adapter->card; 3141 struct pci_dev *pdev = card->dev; 3142 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3143 u32 fw_status; 3144 3145 /* Perform the cancel_work_sync() only when we're not resetting 3146 * the card. It's because that function never returns if we're 3147 * in reset path. If we're here when resetting the card, it means 3148 * that we failed to reset the card (reset failure path). 3149 */ 3150 if (!card->pci_reset_ongoing) { 3151 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n"); 3152 cancel_work_sync(&card->work); 3153 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n"); 3154 } else { 3155 mwifiex_dbg(adapter, MSG, 3156 "skipped cancel_work_sync() because we're in card reset failure path\n"); 3157 } 3158 3159 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 3160 if (fw_status == FIRMWARE_READY_PCIE) { 3161 mwifiex_dbg(adapter, INFO, 3162 "Clearing driver ready signature\n"); 3163 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3164 mwifiex_dbg(adapter, ERROR, 3165 "Failed to write driver not-ready signature\n"); 3166 } 3167 3168 pci_disable_device(pdev); 3169 3170 pci_iounmap(pdev, card->pci_mmap); 3171 pci_iounmap(pdev, card->pci_mmap1); 3172 pci_release_region(pdev, 2); 3173 pci_release_region(pdev, 0); 3174 3175 mwifiex_pcie_free_buffers(adapter); 3176 } 3177 3178 static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter) 3179 { 3180 int ret, i, j; 3181 struct pcie_service_card *card = adapter->card; 3182 struct pci_dev *pdev = card->dev; 3183 3184 if (card->pcie.reg->msix_support) { 3185 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3186 card->msix_entries[i].entry = i; 3187 ret = pci_enable_msix_exact(pdev, card->msix_entries, 3188 MWIFIEX_NUM_MSIX_VECTORS); 3189 if (!ret) { 3190 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { 3191 card->msix_ctx[i].dev = pdev; 3192 card->msix_ctx[i].msg_id = i; 3193 3194 ret = request_irq(card->msix_entries[i].vector, 3195 mwifiex_pcie_interrupt, 0, 3196 "MWIFIEX_PCIE_MSIX", 3197 &card->msix_ctx[i]); 3198 if (ret) 3199 break; 3200 } 3201 3202 if (ret) { 3203 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n", 3204 ret); 3205 for (j = 0; j < i; j++) 3206 free_irq(card->msix_entries[j].vector, 3207 &card->msix_ctx[i]); 3208 pci_disable_msix(pdev); 3209 } else { 3210 mwifiex_dbg(adapter, MSG, "MSIx enabled!"); 3211 card->msix_enable = 1; 3212 return 0; 3213 } 3214 } 3215 } 3216 3217 if (pci_enable_msi(pdev) != 0) 3218 pci_disable_msi(pdev); 3219 else 3220 card->msi_enable = 1; 3221 3222 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable); 3223 3224 card->share_irq_ctx.dev = pdev; 3225 card->share_irq_ctx.msg_id = -1; 3226 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, 3227 "MRVL_PCIE", &card->share_irq_ctx); 3228 if (ret) { 3229 pr_err("request_irq failed: ret=%d\n", ret); 3230 return -1; 3231 } 3232 3233 return 0; 3234 } 3235 3236 /* 3237 * This function gets the firmware name for downloading by revision id 3238 * 3239 * Read revision id register to get revision id 3240 */ 3241 static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter) 3242 { 3243 int revision_id = 0; 3244 int version, magic; 3245 struct pcie_service_card *card = adapter->card; 3246 3247 switch (card->dev->device) { 3248 case PCIE_DEVICE_ID_MARVELL_88W8766P: 3249 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME); 3250 break; 3251 case PCIE_DEVICE_ID_MARVELL_88W8897: 3252 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); 3253 mwifiex_read_reg(adapter, 0x0c58, &revision_id); 3254 revision_id &= 0xff00; 3255 switch (revision_id) { 3256 case PCIE8897_A0: 3257 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME); 3258 break; 3259 case PCIE8897_B0: 3260 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME); 3261 break; 3262 default: 3263 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME); 3264 3265 break; 3266 } 3267 break; 3268 case PCIE_DEVICE_ID_MARVELL_88W8997: 3269 mwifiex_read_reg(adapter, 0x8, &revision_id); 3270 mwifiex_read_reg(adapter, 0x0cd0, &version); 3271 mwifiex_read_reg(adapter, 0x0cd4, &magic); 3272 revision_id &= 0xff; 3273 version &= 0x7; 3274 magic &= 0xff; 3275 if (revision_id == PCIE8997_A1 && 3276 magic == CHIP_MAGIC_VALUE && 3277 version == CHIP_VER_PCIEUART) 3278 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4); 3279 else 3280 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4); 3281 break; 3282 default: 3283 break; 3284 } 3285 } 3286 3287 /* 3288 * This function registers the PCIE device. 3289 * 3290 * PCIE IRQ is claimed, block size is set and driver data is initialized. 3291 */ 3292 static int mwifiex_register_dev(struct mwifiex_adapter *adapter) 3293 { 3294 struct pcie_service_card *card = adapter->card; 3295 3296 /* save adapter pointer in card */ 3297 card->adapter = adapter; 3298 3299 if (mwifiex_pcie_request_irq(adapter)) 3300 return -1; 3301 3302 adapter->tx_buf_size = card->pcie.tx_buf_size; 3303 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl; 3304 adapter->num_mem_types = card->pcie.num_mem_types; 3305 adapter->ext_scan = card->pcie.can_ext_scan; 3306 mwifiex_pcie_get_fw_name(adapter); 3307 3308 return 0; 3309 } 3310 3311 /* 3312 * This function unregisters the PCIE device. 3313 * 3314 * The PCIE IRQ is released, the function is disabled and driver 3315 * data is set to null. 3316 */ 3317 static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) 3318 { 3319 struct pcie_service_card *card = adapter->card; 3320 struct pci_dev *pdev = card->dev; 3321 int i; 3322 3323 if (card->msix_enable) { 3324 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3325 synchronize_irq(card->msix_entries[i].vector); 3326 3327 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3328 free_irq(card->msix_entries[i].vector, 3329 &card->msix_ctx[i]); 3330 3331 card->msix_enable = 0; 3332 pci_disable_msix(pdev); 3333 } else { 3334 mwifiex_dbg(adapter, INFO, 3335 "%s(): calling free_irq()\n", __func__); 3336 free_irq(card->dev->irq, &card->share_irq_ctx); 3337 3338 if (card->msi_enable) 3339 pci_disable_msi(pdev); 3340 } 3341 card->adapter = NULL; 3342 } 3343 3344 /* 3345 * This function initializes the PCI-E host memory space, WCB rings, etc., 3346 * similar to mwifiex_init_pcie(), but without resetting PCI-E state. 3347 */ 3348 static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter) 3349 { 3350 struct pcie_service_card *card = adapter->card; 3351 struct pci_dev *pdev = card->dev; 3352 3353 /* tx_buf_size might be changed to 3584 by firmware during 3354 * data transfer, we should reset it to default size. 3355 */ 3356 adapter->tx_buf_size = card->pcie.tx_buf_size; 3357 3358 mwifiex_pcie_alloc_buffers(adapter); 3359 3360 pci_set_master(pdev); 3361 } 3362 3363 /* This function cleans up the PCI-E host memory space. */ 3364 static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter) 3365 { 3366 struct pcie_service_card *card = adapter->card; 3367 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3368 struct pci_dev *pdev = card->dev; 3369 3370 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) 3371 mwifiex_dbg(adapter, ERROR, "Failed to write driver not-ready signature\n"); 3372 3373 pci_clear_master(pdev); 3374 3375 adapter->seq_num = 0; 3376 3377 mwifiex_pcie_free_buffers(adapter); 3378 } 3379 3380 static struct mwifiex_if_ops pcie_ops = { 3381 .init_if = mwifiex_init_pcie, 3382 .cleanup_if = mwifiex_cleanup_pcie, 3383 .check_fw_status = mwifiex_check_fw_status, 3384 .check_winner_status = mwifiex_check_winner_status, 3385 .prog_fw = mwifiex_prog_fw_w_helper, 3386 .register_dev = mwifiex_register_dev, 3387 .unregister_dev = mwifiex_unregister_dev, 3388 .enable_int = mwifiex_pcie_enable_host_int, 3389 .disable_int = mwifiex_pcie_disable_host_int_noerr, 3390 .process_int_status = mwifiex_process_int_status, 3391 .host_to_card = mwifiex_pcie_host_to_card, 3392 .wakeup = mwifiex_pm_wakeup_card, 3393 .wakeup_complete = mwifiex_pm_wakeup_card_complete, 3394 3395 /* PCIE specific */ 3396 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, 3397 .event_complete = mwifiex_pcie_event_complete, 3398 .update_mp_end_port = NULL, 3399 .cleanup_mpa_buf = NULL, 3400 .init_fw_port = mwifiex_pcie_init_fw_port, 3401 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, 3402 .card_reset = mwifiex_pcie_card_reset, 3403 .reg_dump = mwifiex_pcie_reg_dump, 3404 .device_dump = mwifiex_pcie_device_dump, 3405 .down_dev = mwifiex_pcie_down_dev, 3406 .up_dev = mwifiex_pcie_up_dev, 3407 }; 3408 3409 module_pci_driver(mwifiex_pcie); 3410 3411 MODULE_AUTHOR("Marvell International Ltd."); 3412 MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); 3413 MODULE_VERSION(PCIE_VERSION); 3414 MODULE_LICENSE("GPL v2"); 3415