1 /*
2  *	linux/drivers/net/wireless/libertas/if_spi.c
3  *
4  *	Driver for Marvell SPI WLAN cards.
5  *
6  *	Copyright 2008 Analog Devices Inc.
7  *
8  *	Authors:
9  *	Andrey Yurovsky <andrey@cozybit.com>
10  *	Colin McCabe <colin@cozybit.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or (at
15  * your option) any later version.
16  */
17 
18 #ifndef _LBS_IF_SPI_H_
19 #define _LBS_IF_SPI_H_
20 
21 #define IPFIELD_ALIGN_OFFSET 2
22 #define IF_SPI_CMD_BUF_SIZE 2400
23 
24 /***************** Firmware *****************/
25 
26 #define IF_SPI_FW_NAME_MAX 30
27 
28 #define MAX_MAIN_FW_LOAD_CRC_ERR 10
29 
30 /* Chunk size when loading the helper firmware */
31 #define HELPER_FW_LOAD_CHUNK_SZ 64
32 
33 /* Value to write to indicate end of helper firmware dnld */
34 #define FIRMWARE_DNLD_OK 0x0000
35 
36 /* Value to check once the main firmware is downloaded */
37 #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888
38 
39 /***************** SPI Interface Unit *****************/
40 /* Masks used in SPI register read/write operations */
41 #define IF_SPI_READ_OPERATION_MASK 0x0
42 #define IF_SPI_WRITE_OPERATION_MASK 0x8000
43 
44 /* SPI register offsets. 4-byte aligned. */
45 #define IF_SPI_DEVICEID_CTRL_REG 0x00	/* DeviceID controller reg */
46 #define IF_SPI_IO_READBASE_REG 0x04 	/* Read I/O base reg */
47 #define IF_SPI_IO_WRITEBASE_REG 0x08	/* Write I/O base reg */
48 #define IF_SPI_IO_RDWRPORT_REG 0x0C	/* Read/Write I/O port reg */
49 
50 #define IF_SPI_CMD_READBASE_REG 0x10	/* Read command base reg */
51 #define IF_SPI_CMD_WRITEBASE_REG 0x14	/* Write command base reg */
52 #define IF_SPI_CMD_RDWRPORT_REG 0x18	/* Read/Write command port reg */
53 
54 #define IF_SPI_DATA_READBASE_REG 0x1C	/* Read data base reg */
55 #define IF_SPI_DATA_WRITEBASE_REG 0x20	/* Write data base reg */
56 #define IF_SPI_DATA_RDWRPORT_REG 0x24	/* Read/Write data port reg */
57 
58 #define IF_SPI_SCRATCH_1_REG 0x28	/* Scratch reg 1 */
59 #define IF_SPI_SCRATCH_2_REG 0x2C	/* Scratch reg 2 */
60 #define IF_SPI_SCRATCH_3_REG 0x30	/* Scratch reg 3 */
61 #define IF_SPI_SCRATCH_4_REG 0x34	/* Scratch reg 4 */
62 
63 #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */
64 #define IF_SPI_TX_FRAME_STATUS_REG 0x3C	/* Tx frame status reg */
65 
66 #define IF_SPI_HOST_INT_CTRL_REG 0x40	/* Host interrupt controller reg */
67 
68 #define IF_SPI_CARD_INT_CAUSE_REG 0x44	/* Card interrupt cause reg */
69 #define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */
70 #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */
71 #define IF_SPI_CARD_INT_STATUS_MASK_REG	0x50 /* Card interrupt status mask */
72 
73 #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */
74 
75 #define IF_SPI_HOST_INT_CAUSE_REG 0x58	/* Host interrupt cause reg */
76 #define IF_SPI_HOST_INT_STATUS_REG 0x5C	/* Host interrupt status reg */
77 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */
78 #define IF_SPI_HOST_INT_STATUS_MASK_REG	0x64 /* Host interrupt status mask */
79 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */
80 
81 #define IF_SPI_DELAY_READ_REG 0x6C	/* Delay read reg */
82 #define IF_SPI_SPU_BUS_MODE_REG 0x70	/* SPU BUS mode reg */
83 
84 /***************** IF_SPI_DEVICEID_CTRL_REG *****************/
85 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
86 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
87 
88 /***************** IF_SPI_HOST_INT_CTRL_REG *****************/
89 /* Host Interrupt Control bit : Wake up */
90 #define IF_SPI_HICT_WAKE_UP				(1<<0)
91 /* Host Interrupt Control bit : WLAN ready */
92 #define IF_SPI_HICT_WLAN_READY				(1<<1)
93 /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY		(1<<2) */
94 /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY		(1<<3) */
95 /*#define IF_SPI_HICT_IRQSRC_WLAN			(1<<4) */
96 /* Host Interrupt Control bit : Tx auto download */
97 #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO		(1<<5)
98 /* Host Interrupt Control bit : Rx auto upload */
99 #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO			(1<<6)
100 /* Host Interrupt Control bit : Command auto download */
101 #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO		(1<<7)
102 /* Host Interrupt Control bit : Command auto upload */
103 #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO		(1<<8)
104 
105 /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/
106 /* Card Interrupt Case bit : Tx download over */
107 #define IF_SPI_CIC_TX_DOWNLOAD_OVER			(1<<0)
108 /* Card Interrupt Case bit : Rx upload over */
109 #define IF_SPI_CIC_RX_UPLOAD_OVER			(1<<1)
110 /* Card Interrupt Case bit : Command download over */
111 #define IF_SPI_CIC_CMD_DOWNLOAD_OVER			(1<<2)
112 /* Card Interrupt Case bit : Host event */
113 #define IF_SPI_CIC_HOST_EVENT				(1<<3)
114 /* Card Interrupt Case bit : Command upload over */
115 #define IF_SPI_CIC_CMD_UPLOAD_OVER			(1<<4)
116 /* Card Interrupt Case bit : Power down */
117 #define IF_SPI_CIC_POWER_DOWN				(1<<5)
118 
119 /***************** IF_SPI_CARD_INT_STATUS_REG *****************/
120 #define IF_SPI_CIS_TX_DOWNLOAD_OVER			(1<<0)
121 #define IF_SPI_CIS_RX_UPLOAD_OVER			(1<<1)
122 #define IF_SPI_CIS_CMD_DOWNLOAD_OVER			(1<<2)
123 #define IF_SPI_CIS_HOST_EVENT				(1<<3)
124 #define IF_SPI_CIS_CMD_UPLOAD_OVER			(1<<4)
125 #define IF_SPI_CIS_POWER_DOWN				(1<<5)
126 
127 /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/
128 #define IF_SPI_HICU_TX_DOWNLOAD_RDY			(1<<0)
129 #define IF_SPI_HICU_RX_UPLOAD_RDY			(1<<1)
130 #define IF_SPI_HICU_CMD_DOWNLOAD_RDY			(1<<2)
131 #define IF_SPI_HICU_CARD_EVENT				(1<<3)
132 #define IF_SPI_HICU_CMD_UPLOAD_RDY			(1<<4)
133 #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW			(1<<5)
134 #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW		(1<<6)
135 #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW		(1<<7)
136 #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW		(1<<8)
137 #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW		(1<<9)
138 #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW		(1<<10)
139 
140 /***************** IF_SPI_HOST_INT_STATUS_REG *****************/
141 /* Host Interrupt Status bit : Tx download ready */
142 #define IF_SPI_HIST_TX_DOWNLOAD_RDY			(1<<0)
143 /* Host Interrupt Status bit : Rx upload ready */
144 #define IF_SPI_HIST_RX_UPLOAD_RDY			(1<<1)
145 /* Host Interrupt Status bit : Command download ready */
146 #define IF_SPI_HIST_CMD_DOWNLOAD_RDY			(1<<2)
147 /* Host Interrupt Status bit : Card event */
148 #define IF_SPI_HIST_CARD_EVENT				(1<<3)
149 /* Host Interrupt Status bit : Command upload ready */
150 #define IF_SPI_HIST_CMD_UPLOAD_RDY			(1<<4)
151 /* Host Interrupt Status bit : I/O write FIFO overflow */
152 #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW			(1<<5)
153 /* Host Interrupt Status bit : I/O read FIFO underflow */
154 #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW			(1<<6)
155 /* Host Interrupt Status bit : Data write FIFO overflow */
156 #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW		(1<<7)
157 /* Host Interrupt Status bit : Data read FIFO underflow */
158 #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW		(1<<8)
159 /* Host Interrupt Status bit : Command write FIFO overflow */
160 #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW		(1<<9)
161 /* Host Interrupt Status bit : Command read FIFO underflow */
162 #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW		(1<<10)
163 
164 /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/
165 /* Host Interrupt Status Mask bit : Tx download ready */
166 #define IF_SPI_HISM_TX_DOWNLOAD_RDY			(1<<0)
167 /* Host Interrupt Status Mask bit : Rx upload ready */
168 #define IF_SPI_HISM_RX_UPLOAD_RDY			(1<<1)
169 /* Host Interrupt Status Mask bit : Command download ready */
170 #define IF_SPI_HISM_CMD_DOWNLOAD_RDY			(1<<2)
171 /* Host Interrupt Status Mask bit : Card event */
172 #define IF_SPI_HISM_CARDEVENT				(1<<3)
173 /* Host Interrupt Status Mask bit : Command upload ready */
174 #define IF_SPI_HISM_CMD_UPLOAD_RDY			(1<<4)
175 /* Host Interrupt Status Mask bit : I/O write FIFO overflow */
176 #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW			(1<<5)
177 /* Host Interrupt Status Mask bit : I/O read FIFO underflow */
178 #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW		(1<<6)
179 /* Host Interrupt Status Mask bit : Data write FIFO overflow */
180 #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW		(1<<7)
181 /* Host Interrupt Status Mask bit : Data write FIFO underflow */
182 #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW		(1<<8)
183 /* Host Interrupt Status Mask bit : Command write FIFO overflow */
184 #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW		(1<<9)
185 /* Host Interrupt Status Mask bit : Command write FIFO underflow */
186 #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW		(1<<10)
187 
188 /***************** IF_SPI_SPU_BUS_MODE_REG *****************/
189 /* SCK edge on which the WLAN module outputs data on MISO */
190 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8
191 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0
192 
193 /* In a SPU read operation, there is a delay between writing the SPU
194  * register name and getting back data from the WLAN module.
195  * This can be specified in terms of nanoseconds or in terms of dummy
196  * clock cycles which the master must output before receiving a response. */
197 #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4
198 #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0
199 
200 /* Some different modes of SPI operation */
201 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00
202 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01
203 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02
204 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03
205 
206 #endif
207