1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2d3466830SKalle Valo #ifndef P54PCI_H
3d3466830SKalle Valo #define P54PCI_H
4d3466830SKalle Valo #include <linux/interrupt.h>
5d3466830SKalle Valo 
6d3466830SKalle Valo /*
7d3466830SKalle Valo  * Defines for PCI based mac80211 Prism54 driver
8d3466830SKalle Valo  *
9d3466830SKalle Valo  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
10d3466830SKalle Valo  *
11d3466830SKalle Valo  * Based on the islsm (softmac prism54) driver, which is:
12d3466830SKalle Valo  * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
13d3466830SKalle Valo  */
14d3466830SKalle Valo 
15d3466830SKalle Valo /* Device Interrupt register bits */
16d3466830SKalle Valo #define ISL38XX_DEV_INT_RESET                   0x0001
17d3466830SKalle Valo #define ISL38XX_DEV_INT_UPDATE                  0x0002
18d3466830SKalle Valo #define ISL38XX_DEV_INT_WAKEUP                  0x0008
19d3466830SKalle Valo #define ISL38XX_DEV_INT_SLEEP                   0x0010
20d3466830SKalle Valo #define ISL38XX_DEV_INT_ABORT                   0x0020
21d3466830SKalle Valo /* these two only used in USB */
22d3466830SKalle Valo #define ISL38XX_DEV_INT_DATA                    0x0040
23d3466830SKalle Valo #define ISL38XX_DEV_INT_MGMT                    0x0080
24d3466830SKalle Valo 
25d3466830SKalle Valo #define ISL38XX_DEV_INT_PCIUART_CTS             0x4000
26d3466830SKalle Valo #define ISL38XX_DEV_INT_PCIUART_DR              0x8000
27d3466830SKalle Valo 
28d3466830SKalle Valo /* Interrupt Identification/Acknowledge/Enable register bits */
29d3466830SKalle Valo #define ISL38XX_INT_IDENT_UPDATE		0x0002
30d3466830SKalle Valo #define ISL38XX_INT_IDENT_INIT			0x0004
31d3466830SKalle Valo #define ISL38XX_INT_IDENT_WAKEUP		0x0008
32d3466830SKalle Valo #define ISL38XX_INT_IDENT_SLEEP			0x0010
33d3466830SKalle Valo #define ISL38XX_INT_IDENT_PCIUART_CTS		0x4000
34d3466830SKalle Valo #define ISL38XX_INT_IDENT_PCIUART_DR		0x8000
35d3466830SKalle Valo 
36d3466830SKalle Valo /* Control/Status register bits */
37d3466830SKalle Valo #define ISL38XX_CTRL_STAT_SLEEPMODE		0x00000200
38d3466830SKalle Valo #define ISL38XX_CTRL_STAT_CLKRUN		0x00800000
39d3466830SKalle Valo #define ISL38XX_CTRL_STAT_RESET			0x10000000
40d3466830SKalle Valo #define ISL38XX_CTRL_STAT_RAMBOOT		0x20000000
41d3466830SKalle Valo #define ISL38XX_CTRL_STAT_STARTHALTED		0x40000000
42d3466830SKalle Valo #define ISL38XX_CTRL_STAT_HOST_OVERRIDE		0x80000000
43d3466830SKalle Valo 
44d3466830SKalle Valo struct p54p_csr {
45d3466830SKalle Valo 	__le32 dev_int;
46d3466830SKalle Valo 	u8 unused_1[12];
47d3466830SKalle Valo 	__le32 int_ident;
48d3466830SKalle Valo 	__le32 int_ack;
49d3466830SKalle Valo 	__le32 int_enable;
50d3466830SKalle Valo 	u8 unused_2[4];
51d3466830SKalle Valo 	union {
52d3466830SKalle Valo 		__le32 ring_control_base;
53d3466830SKalle Valo 		__le32 gen_purp_com[2];
54d3466830SKalle Valo 	};
55d3466830SKalle Valo 	u8 unused_3[8];
56d3466830SKalle Valo 	__le32 direct_mem_base;
57d3466830SKalle Valo 	u8 unused_4[44];
58d3466830SKalle Valo 	__le32 dma_addr;
59d3466830SKalle Valo 	__le32 dma_len;
60d3466830SKalle Valo 	__le32 dma_ctrl;
61d3466830SKalle Valo 	u8 unused_5[12];
62d3466830SKalle Valo 	__le32 ctrl_stat;
63d3466830SKalle Valo 	u8 unused_6[1924];
64d3466830SKalle Valo 	u8 cardbus_cis[0x800];
65d3466830SKalle Valo 	u8 direct_mem_win[0x1000];
66d3466830SKalle Valo } __packed;
67d3466830SKalle Valo 
68d3466830SKalle Valo /* usb backend only needs the register defines above */
69d3466830SKalle Valo #ifndef P54USB_H
70d3466830SKalle Valo struct p54p_desc {
71d3466830SKalle Valo 	__le32 host_addr;
72d3466830SKalle Valo 	__le32 device_addr;
73d3466830SKalle Valo 	__le16 len;
74d3466830SKalle Valo 	__le16 flags;
75d3466830SKalle Valo } __packed;
76d3466830SKalle Valo 
77d3466830SKalle Valo struct p54p_ring_control {
78d3466830SKalle Valo 	__le32 host_idx[4];
79d3466830SKalle Valo 	__le32 device_idx[4];
80d3466830SKalle Valo 	struct p54p_desc rx_data[8];
81d3466830SKalle Valo 	struct p54p_desc tx_data[32];
82d3466830SKalle Valo 	struct p54p_desc rx_mgmt[4];
83d3466830SKalle Valo 	struct p54p_desc tx_mgmt[4];
84d3466830SKalle Valo } __packed;
85d3466830SKalle Valo 
86d3466830SKalle Valo #define P54P_READ(r) (__force __le32)__raw_readl(&priv->map->r)
87d3466830SKalle Valo #define P54P_WRITE(r, val) __raw_writel((__force u32)(__le32)(val), &priv->map->r)
88d3466830SKalle Valo 
89d3466830SKalle Valo struct p54p_priv {
90d3466830SKalle Valo 	struct p54_common common;
91d3466830SKalle Valo 	struct pci_dev *pdev;
92d3466830SKalle Valo 	struct p54p_csr __iomem *map;
93d3466830SKalle Valo 	struct tasklet_struct tasklet;
94d3466830SKalle Valo 	const struct firmware *firmware;
95d3466830SKalle Valo 	spinlock_t lock;
96d3466830SKalle Valo 	struct p54p_ring_control *ring_control;
97d3466830SKalle Valo 	dma_addr_t ring_control_dma;
98d3466830SKalle Valo 	u32 rx_idx_data, tx_idx_data;
99d3466830SKalle Valo 	u32 rx_idx_mgmt, tx_idx_mgmt;
100d3466830SKalle Valo 	struct sk_buff *rx_buf_data[8];
101d3466830SKalle Valo 	struct sk_buff *rx_buf_mgmt[4];
102d3466830SKalle Valo 	struct sk_buff *tx_buf_data[32];
103d3466830SKalle Valo 	struct sk_buff *tx_buf_mgmt[4];
104d3466830SKalle Valo 	struct completion boot_comp;
105d3466830SKalle Valo 	struct completion fw_loaded;
106d3466830SKalle Valo };
107d3466830SKalle Valo 
108d3466830SKalle Valo #endif /* P54USB_H */
109d3466830SKalle Valo #endif /* P54PCI_H */
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