1d3466830SKalle Valo /*
2d3466830SKalle Valo  * LMAC Interface specific definitions for mac80211 Prism54 drivers
3d3466830SKalle Valo  *
4d3466830SKalle Valo  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5d3466830SKalle Valo  * Copyright (c) 2007 - 2009, Christian Lamparter <chunkeey@web.de>
6d3466830SKalle Valo  *
7d3466830SKalle Valo  * Based on:
8d3466830SKalle Valo  * - the islsm (softmac prism54) driver, which is:
9d3466830SKalle Valo  *   Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10d3466830SKalle Valo  *
11d3466830SKalle Valo  * - LMAC API interface header file for STLC4560 (lmac_longbow.h)
12d3466830SKalle Valo  *   Copyright (C) 2007 Conexant Systems, Inc.
13d3466830SKalle Valo  *
14d3466830SKalle Valo  * This program is free software; you can redistribute it and/or modify
15d3466830SKalle Valo  * it under the terms of the GNU General Public License version 2 as
16d3466830SKalle Valo  * published by the Free Software Foundation.
17d3466830SKalle Valo  */
18d3466830SKalle Valo 
19d3466830SKalle Valo #ifndef LMAC_H
20d3466830SKalle Valo #define LMAC_H
21d3466830SKalle Valo 
22d3466830SKalle Valo enum p54_control_frame_types {
23d3466830SKalle Valo 	P54_CONTROL_TYPE_SETUP = 0,
24d3466830SKalle Valo 	P54_CONTROL_TYPE_SCAN,
25d3466830SKalle Valo 	P54_CONTROL_TYPE_TRAP,
26d3466830SKalle Valo 	P54_CONTROL_TYPE_DCFINIT,
27d3466830SKalle Valo 	P54_CONTROL_TYPE_RX_KEYCACHE,
28d3466830SKalle Valo 	P54_CONTROL_TYPE_TIM,
29d3466830SKalle Valo 	P54_CONTROL_TYPE_PSM,
30d3466830SKalle Valo 	P54_CONTROL_TYPE_TXCANCEL,
31d3466830SKalle Valo 	P54_CONTROL_TYPE_TXDONE,
32d3466830SKalle Valo 	P54_CONTROL_TYPE_BURST,
33d3466830SKalle Valo 	P54_CONTROL_TYPE_STAT_READBACK,
34d3466830SKalle Valo 	P54_CONTROL_TYPE_BBP,
35d3466830SKalle Valo 	P54_CONTROL_TYPE_EEPROM_READBACK,
36d3466830SKalle Valo 	P54_CONTROL_TYPE_LED,
37d3466830SKalle Valo 	P54_CONTROL_TYPE_GPIO,
38d3466830SKalle Valo 	P54_CONTROL_TYPE_TIMER,
39d3466830SKalle Valo 	P54_CONTROL_TYPE_MODULATION,
40d3466830SKalle Valo 	P54_CONTROL_TYPE_SYNTH_CONFIG,
41d3466830SKalle Valo 	P54_CONTROL_TYPE_DETECTOR_VALUE,
42d3466830SKalle Valo 	P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
43d3466830SKalle Valo 	P54_CONTROL_TYPE_CCE_QUIET,
44d3466830SKalle Valo 	P54_CONTROL_TYPE_PSM_STA_UNLOCK,
45d3466830SKalle Valo 	P54_CONTROL_TYPE_PCS,
46d3466830SKalle Valo 	P54_CONTROL_TYPE_BT_BALANCER = 28,
47d3466830SKalle Valo 	P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE = 30,
48d3466830SKalle Valo 	P54_CONTROL_TYPE_ARPTABLE = 31,
49d3466830SKalle Valo 	P54_CONTROL_TYPE_BT_OPTIONS = 35,
50d3466830SKalle Valo };
51d3466830SKalle Valo 
52d3466830SKalle Valo #define P54_HDR_FLAG_CONTROL		BIT(15)
53d3466830SKalle Valo #define P54_HDR_FLAG_CONTROL_OPSET	(BIT(15) + BIT(0))
54d3466830SKalle Valo #define P54_HDR_FLAG_DATA_ALIGN		BIT(14)
55d3466830SKalle Valo 
56d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_PROMISC		BIT(0)
57d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP		BIT(1)
58d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_SEQNR		BIT(2)
59d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_BIT3		BIT(3)
60d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_BURST		BIT(4)
61d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_NOCANCEL		BIT(5)
62d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_CLEARTIM		BIT(6)
63d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE		BIT(7)
64d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_COMPRESS		BIT(8)
65d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_CONCAT		BIT(9)
66d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT	BIT(10)
67d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_WAITEOSP		BIT(11)
68d3466830SKalle Valo 
69d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_FCS_GOOD		BIT(0)
70d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MATCH_MAC		BIT(1)
71d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MCBC		BIT(2)
72d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BEACON		BIT(3)
73d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MATCH_BSS		BIT(4)
74d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BCAST_BSS		BIT(5)
75d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_DATA		BIT(6)
76d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_TRUNCATED		BIT(7)
77d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BIT8		BIT(8)
78d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_TRANSPARENT	BIT(9)
79d3466830SKalle Valo 
80d3466830SKalle Valo struct p54_hdr {
81d3466830SKalle Valo 	__le16 flags;
82d3466830SKalle Valo 	__le16 len;
83d3466830SKalle Valo 	__le32 req_id;
84d3466830SKalle Valo 	__le16 type;	/* enum p54_control_frame_types */
85d3466830SKalle Valo 	u8 rts_tries;
86d3466830SKalle Valo 	u8 tries;
87d3466830SKalle Valo 	u8 data[0];
88d3466830SKalle Valo } __packed;
89d3466830SKalle Valo 
90d3466830SKalle Valo #define GET_REQ_ID(skb)							\
91d3466830SKalle Valo 	(((struct p54_hdr *) ((struct sk_buff *) skb)->data)->req_id)	\
92d3466830SKalle Valo 
93d3466830SKalle Valo #define FREE_AFTER_TX(skb)						\
94d3466830SKalle Valo 	((((struct p54_hdr *) ((struct sk_buff *) skb)->data)->		\
95d3466830SKalle Valo 	flags) == cpu_to_le16(P54_HDR_FLAG_CONTROL_OPSET))
96d3466830SKalle Valo 
97d3466830SKalle Valo #define IS_DATA_FRAME(skb)						\
98d3466830SKalle Valo 	(!((((struct p54_hdr *) ((struct sk_buff *) skb)->data)->	\
99d3466830SKalle Valo 	flags) & cpu_to_le16(P54_HDR_FLAG_CONTROL)))
100d3466830SKalle Valo 
101d3466830SKalle Valo #define GET_HW_QUEUE(skb)						\
102d3466830SKalle Valo 	(((struct p54_tx_data *)((struct p54_hdr *)			\
103d3466830SKalle Valo 	skb->data)->data)->hw_queue)
104d3466830SKalle Valo 
105d3466830SKalle Valo /*
106d3466830SKalle Valo  * shared interface ID definitions
107d3466830SKalle Valo  * The interface ID is a unique identification of a specific interface.
108d3466830SKalle Valo  * The following values are reserved: 0x0000, 0x0002, 0x0012, 0x0014, 0x0015
109d3466830SKalle Valo  */
110d3466830SKalle Valo #define IF_ID_ISL36356A			0x0001	/* ISL36356A <-> Firmware */
111d3466830SKalle Valo #define IF_ID_MVC			0x0003	/* MAC Virtual Coprocessor */
112d3466830SKalle Valo #define IF_ID_DEBUG			0x0008	/* PolDebug Interface */
113d3466830SKalle Valo #define IF_ID_PRODUCT			0x0009
114d3466830SKalle Valo #define IF_ID_OEM			0x000a
115d3466830SKalle Valo #define IF_ID_PCI3877			0x000b	/* 3877 <-> Host PCI */
116d3466830SKalle Valo #define IF_ID_ISL37704C			0x000c	/* ISL37704C <-> Fw */
117d3466830SKalle Valo #define IF_ID_ISL39000			0x000f	/* ISL39000 <-> Fw */
118d3466830SKalle Valo #define IF_ID_ISL39300A			0x0010	/* ISL39300A <-> Fw */
119d3466830SKalle Valo #define IF_ID_ISL37700_UAP		0x0016	/* ISL37700 uAP Fw <-> Fw */
120d3466830SKalle Valo #define IF_ID_ISL39000_UAP		0x0017	/* ISL39000 uAP Fw <-> Fw */
121d3466830SKalle Valo #define IF_ID_LMAC			0x001a	/* Interface exposed by LMAC */
122d3466830SKalle Valo 
123d3466830SKalle Valo struct exp_if {
124d3466830SKalle Valo 	__le16 role;
125d3466830SKalle Valo 	__le16 if_id;
126d3466830SKalle Valo 	__le16 variant;
127d3466830SKalle Valo 	__le16 btm_compat;
128d3466830SKalle Valo 	__le16 top_compat;
129d3466830SKalle Valo } __packed;
130d3466830SKalle Valo 
131d3466830SKalle Valo struct dep_if {
132d3466830SKalle Valo 	__le16 role;
133d3466830SKalle Valo 	__le16 if_id;
134d3466830SKalle Valo 	__le16 variant;
135d3466830SKalle Valo } __packed;
136d3466830SKalle Valo 
137d3466830SKalle Valo /* driver <-> lmac definitions */
138d3466830SKalle Valo struct p54_eeprom_lm86 {
139d3466830SKalle Valo 	union {
140d3466830SKalle Valo 		struct {
141d3466830SKalle Valo 			__le16 offset;
142d3466830SKalle Valo 			__le16 len;
143d3466830SKalle Valo 			u8 data[0];
144d3466830SKalle Valo 		} __packed v1;
145d3466830SKalle Valo 		struct {
146d3466830SKalle Valo 			__le32 offset;
147d3466830SKalle Valo 			__le16 len;
148d3466830SKalle Valo 			u8 magic2;
149d3466830SKalle Valo 			u8 pad;
150d3466830SKalle Valo 			u8 magic[4];
151d3466830SKalle Valo 			u8 data[0];
152d3466830SKalle Valo 		} __packed v2;
153d3466830SKalle Valo 	}  __packed;
154d3466830SKalle Valo } __packed;
155d3466830SKalle Valo 
156d3466830SKalle Valo enum p54_rx_decrypt_status {
157d3466830SKalle Valo 	P54_DECRYPT_NONE = 0,
158d3466830SKalle Valo 	P54_DECRYPT_OK,
159d3466830SKalle Valo 	P54_DECRYPT_NOKEY,
160d3466830SKalle Valo 	P54_DECRYPT_NOMICHAEL,
161d3466830SKalle Valo 	P54_DECRYPT_NOCKIPMIC,
162d3466830SKalle Valo 	P54_DECRYPT_FAIL_WEP,
163d3466830SKalle Valo 	P54_DECRYPT_FAIL_TKIP,
164d3466830SKalle Valo 	P54_DECRYPT_FAIL_MICHAEL,
165d3466830SKalle Valo 	P54_DECRYPT_FAIL_CKIPKP,
166d3466830SKalle Valo 	P54_DECRYPT_FAIL_CKIPMIC,
167d3466830SKalle Valo 	P54_DECRYPT_FAIL_AESCCMP
168d3466830SKalle Valo };
169d3466830SKalle Valo 
170d3466830SKalle Valo struct p54_rx_data {
171d3466830SKalle Valo 	__le16 flags;
172d3466830SKalle Valo 	__le16 len;
173d3466830SKalle Valo 	__le16 freq;
174d3466830SKalle Valo 	u8 antenna;
175d3466830SKalle Valo 	u8 rate;
176d3466830SKalle Valo 	u8 rssi;
177d3466830SKalle Valo 	u8 quality;
178d3466830SKalle Valo 	u8 decrypt_status;
179d3466830SKalle Valo 	u8 rssi_raw;
180d3466830SKalle Valo 	__le32 tsf32;
181d3466830SKalle Valo 	__le32 unalloc0;
182d3466830SKalle Valo 	u8 align[0];
183d3466830SKalle Valo } __packed;
184d3466830SKalle Valo 
185d3466830SKalle Valo enum p54_trap_type {
186d3466830SKalle Valo 	P54_TRAP_SCAN = 0,
187d3466830SKalle Valo 	P54_TRAP_TIMER,
188d3466830SKalle Valo 	P54_TRAP_BEACON_TX,
189d3466830SKalle Valo 	P54_TRAP_FAA_RADIO_ON,
190d3466830SKalle Valo 	P54_TRAP_FAA_RADIO_OFF,
191d3466830SKalle Valo 	P54_TRAP_RADAR,
192d3466830SKalle Valo 	P54_TRAP_NO_BEACON,
193d3466830SKalle Valo 	P54_TRAP_TBTT,
194d3466830SKalle Valo 	P54_TRAP_SCO_ENTER,
195d3466830SKalle Valo 	P54_TRAP_SCO_EXIT
196d3466830SKalle Valo };
197d3466830SKalle Valo 
198d3466830SKalle Valo struct p54_trap {
199d3466830SKalle Valo 	__le16 event;
200d3466830SKalle Valo 	__le16 frequency;
201d3466830SKalle Valo } __packed;
202d3466830SKalle Valo 
203d3466830SKalle Valo enum p54_frame_sent_status {
204d3466830SKalle Valo 	P54_TX_OK = 0,
205d3466830SKalle Valo 	P54_TX_FAILED,
206d3466830SKalle Valo 	P54_TX_PSM,
207d3466830SKalle Valo 	P54_TX_PSM_CANCELLED = 4
208d3466830SKalle Valo };
209d3466830SKalle Valo 
210d3466830SKalle Valo struct p54_frame_sent {
211d3466830SKalle Valo 	u8 status;
212d3466830SKalle Valo 	u8 tries;
213d3466830SKalle Valo 	u8 ack_rssi;
214d3466830SKalle Valo 	u8 quality;
215d3466830SKalle Valo 	__le16 seq;
216d3466830SKalle Valo 	u8 antenna;
217d3466830SKalle Valo 	u8 padding;
218d3466830SKalle Valo } __packed;
219d3466830SKalle Valo 
220d3466830SKalle Valo enum p54_tx_data_crypt {
221d3466830SKalle Valo 	P54_CRYPTO_NONE = 0,
222d3466830SKalle Valo 	P54_CRYPTO_WEP,
223d3466830SKalle Valo 	P54_CRYPTO_TKIP,
224d3466830SKalle Valo 	P54_CRYPTO_TKIPMICHAEL,
225d3466830SKalle Valo 	P54_CRYPTO_CCX_WEPMIC,
226d3466830SKalle Valo 	P54_CRYPTO_CCX_KPMIC,
227d3466830SKalle Valo 	P54_CRYPTO_CCX_KP,
228d3466830SKalle Valo 	P54_CRYPTO_AESCCMP
229d3466830SKalle Valo };
230d3466830SKalle Valo 
231d3466830SKalle Valo enum p54_tx_data_queue {
232d3466830SKalle Valo 	P54_QUEUE_BEACON	= 0,
233d3466830SKalle Valo 	P54_QUEUE_FWSCAN	= 1,
234d3466830SKalle Valo 	P54_QUEUE_MGMT		= 2,
235d3466830SKalle Valo 	P54_QUEUE_CAB		= 3,
236d3466830SKalle Valo 	P54_QUEUE_DATA		= 4,
237d3466830SKalle Valo 
238d3466830SKalle Valo 	P54_QUEUE_AC_NUM	= 4,
239d3466830SKalle Valo 	P54_QUEUE_AC_VO		= 4,
240d3466830SKalle Valo 	P54_QUEUE_AC_VI		= 5,
241d3466830SKalle Valo 	P54_QUEUE_AC_BE		= 6,
242d3466830SKalle Valo 	P54_QUEUE_AC_BK		= 7,
243d3466830SKalle Valo 
244d3466830SKalle Valo 	/* keep last */
245d3466830SKalle Valo 	P54_QUEUE_NUM		= 8,
246d3466830SKalle Valo };
247d3466830SKalle Valo 
248d3466830SKalle Valo #define IS_QOS_QUEUE(n)	(n >= P54_QUEUE_DATA)
249d3466830SKalle Valo 
250d3466830SKalle Valo struct p54_tx_data {
251d3466830SKalle Valo 	u8 rateset[8];
252d3466830SKalle Valo 	u8 rts_rate_idx;
253d3466830SKalle Valo 	u8 crypt_offset;
254d3466830SKalle Valo 	u8 key_type;
255d3466830SKalle Valo 	u8 key_len;
256d3466830SKalle Valo 	u8 key[16];
257d3466830SKalle Valo 	u8 hw_queue;
258d3466830SKalle Valo 	u8 backlog;
259d3466830SKalle Valo 	__le16 durations[4];
260d3466830SKalle Valo 	u8 tx_antenna;
261d3466830SKalle Valo 	union {
262d3466830SKalle Valo 		struct {
263d3466830SKalle Valo 			u8 cts_rate;
264d3466830SKalle Valo 			__le16 output_power;
265d3466830SKalle Valo 		} __packed longbow;
266d3466830SKalle Valo 		struct {
267d3466830SKalle Valo 			u8 output_power;
268d3466830SKalle Valo 			u8 cts_rate;
269d3466830SKalle Valo 			u8 unalloc;
270d3466830SKalle Valo 		} __packed normal;
271d3466830SKalle Valo 	} __packed;
272d3466830SKalle Valo 	u8 unalloc2[2];
273d3466830SKalle Valo 	u8 align[0];
274d3466830SKalle Valo } __packed;
275d3466830SKalle Valo 
276d3466830SKalle Valo /* unit is ms */
277d3466830SKalle Valo #define P54_TX_FRAME_LIFETIME 2000
278d3466830SKalle Valo #define P54_TX_TIMEOUT 4000
279d3466830SKalle Valo #define P54_STATISTICS_UPDATE 5000
280d3466830SKalle Valo 
281d3466830SKalle Valo #define P54_FILTER_TYPE_NONE		0
282d3466830SKalle Valo #define P54_FILTER_TYPE_STATION		BIT(0)
283d3466830SKalle Valo #define P54_FILTER_TYPE_IBSS		BIT(1)
284d3466830SKalle Valo #define P54_FILTER_TYPE_AP		BIT(2)
285d3466830SKalle Valo #define P54_FILTER_TYPE_TRANSPARENT	BIT(3)
286d3466830SKalle Valo #define P54_FILTER_TYPE_PROMISCUOUS	BIT(4)
287d3466830SKalle Valo #define P54_FILTER_TYPE_HIBERNATE	BIT(5)
288d3466830SKalle Valo #define P54_FILTER_TYPE_NOACK		BIT(6)
289d3466830SKalle Valo #define P54_FILTER_TYPE_RX_DISABLED	BIT(7)
290d3466830SKalle Valo 
291d3466830SKalle Valo struct p54_setup_mac {
292d3466830SKalle Valo 	__le16 mac_mode;
293d3466830SKalle Valo 	u8 mac_addr[ETH_ALEN];
294d3466830SKalle Valo 	u8 bssid[ETH_ALEN];
295d3466830SKalle Valo 	u8 rx_antenna;
296d3466830SKalle Valo 	u8 rx_align;
297d3466830SKalle Valo 	union {
298d3466830SKalle Valo 		struct {
299d3466830SKalle Valo 			__le32 basic_rate_mask;
300d3466830SKalle Valo 			u8 rts_rates[8];
301d3466830SKalle Valo 			__le32 rx_addr;
302d3466830SKalle Valo 			__le16 max_rx;
303d3466830SKalle Valo 			__le16 rxhw;
304d3466830SKalle Valo 			__le16 wakeup_timer;
305d3466830SKalle Valo 			__le16 unalloc0;
306d3466830SKalle Valo 		} __packed v1;
307d3466830SKalle Valo 		struct {
308d3466830SKalle Valo 			__le32 rx_addr;
309d3466830SKalle Valo 			__le16 max_rx;
310d3466830SKalle Valo 			__le16 rxhw;
311d3466830SKalle Valo 			__le16 timer;
312d3466830SKalle Valo 			__le16 truncate;
313d3466830SKalle Valo 			__le32 basic_rate_mask;
314d3466830SKalle Valo 			u8 sbss_offset;
315d3466830SKalle Valo 			u8 mcast_window;
316d3466830SKalle Valo 			u8 rx_rssi_threshold;
317d3466830SKalle Valo 			u8 rx_ed_threshold;
318d3466830SKalle Valo 			__le32 ref_clock;
319d3466830SKalle Valo 			__le16 lpf_bandwidth;
320d3466830SKalle Valo 			__le16 osc_start_delay;
321d3466830SKalle Valo 		} __packed v2;
322d3466830SKalle Valo 	} __packed;
323d3466830SKalle Valo } __packed;
324d3466830SKalle Valo 
325d3466830SKalle Valo #define P54_SETUP_V1_LEN 40
326d3466830SKalle Valo #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac))
327d3466830SKalle Valo 
328d3466830SKalle Valo #define P54_SCAN_EXIT	BIT(0)
329d3466830SKalle Valo #define P54_SCAN_TRAP	BIT(1)
330d3466830SKalle Valo #define P54_SCAN_ACTIVE BIT(2)
331d3466830SKalle Valo #define P54_SCAN_FILTER BIT(3)
332d3466830SKalle Valo 
333d3466830SKalle Valo struct p54_scan_head {
334d3466830SKalle Valo 	__le16 mode;
335d3466830SKalle Valo 	__le16 dwell;
336d3466830SKalle Valo 	u8 scan_params[20];
337d3466830SKalle Valo 	__le16 freq;
338d3466830SKalle Valo } __packed;
339d3466830SKalle Valo 
340d3466830SKalle Valo struct p54_pa_curve_data_sample {
341d3466830SKalle Valo 	u8 rf_power;
342d3466830SKalle Valo 	u8 pa_detector;
343d3466830SKalle Valo 	u8 data_barker;
344d3466830SKalle Valo 	u8 data_bpsk;
345d3466830SKalle Valo 	u8 data_qpsk;
346d3466830SKalle Valo 	u8 data_16qam;
347d3466830SKalle Valo 	u8 data_64qam;
348d3466830SKalle Valo 	u8 padding;
349d3466830SKalle Valo } __packed;
350d3466830SKalle Valo 
351d3466830SKalle Valo struct p54_scan_body {
352d3466830SKalle Valo 	u8 pa_points_per_curve;
353d3466830SKalle Valo 	u8 val_barker;
354d3466830SKalle Valo 	u8 val_bpsk;
355d3466830SKalle Valo 	u8 val_qpsk;
356d3466830SKalle Valo 	u8 val_16qam;
357d3466830SKalle Valo 	u8 val_64qam;
358d3466830SKalle Valo 	struct p54_pa_curve_data_sample curve_data[8];
359d3466830SKalle Valo 	u8 dup_bpsk;
360d3466830SKalle Valo 	u8 dup_qpsk;
361d3466830SKalle Valo 	u8 dup_16qam;
362d3466830SKalle Valo 	u8 dup_64qam;
363d3466830SKalle Valo } __packed;
364d3466830SKalle Valo 
365d3466830SKalle Valo /*
366d3466830SKalle Valo  * Warning: Longbow's structures are bogus.
367d3466830SKalle Valo  */
368d3466830SKalle Valo struct p54_channel_output_limit_longbow {
369d3466830SKalle Valo 	__le16 rf_power_points[12];
370d3466830SKalle Valo } __packed;
371d3466830SKalle Valo 
372d3466830SKalle Valo struct p54_pa_curve_data_sample_longbow {
373d3466830SKalle Valo 	__le16 rf_power;
374d3466830SKalle Valo 	__le16 pa_detector;
375d3466830SKalle Valo 	struct {
376d3466830SKalle Valo 		__le16 data[4];
377d3466830SKalle Valo 	} points[3] __packed;
378d3466830SKalle Valo } __packed;
379d3466830SKalle Valo 
380d3466830SKalle Valo struct p54_scan_body_longbow {
381d3466830SKalle Valo 	struct p54_channel_output_limit_longbow power_limits;
382d3466830SKalle Valo 	struct p54_pa_curve_data_sample_longbow curve_data[8];
383d3466830SKalle Valo 	__le16 unkn[6];		/* maybe more power_limits or rate_mask */
384d3466830SKalle Valo } __packed;
385d3466830SKalle Valo 
386d3466830SKalle Valo union p54_scan_body_union {
387d3466830SKalle Valo 	struct p54_scan_body normal;
388d3466830SKalle Valo 	struct p54_scan_body_longbow longbow;
389d3466830SKalle Valo } __packed;
390d3466830SKalle Valo 
391d3466830SKalle Valo struct p54_scan_tail_rate {
392d3466830SKalle Valo 	__le32 basic_rate_mask;
393d3466830SKalle Valo 	u8 rts_rates[8];
394d3466830SKalle Valo } __packed;
395d3466830SKalle Valo 
396d3466830SKalle Valo struct p54_led {
397d3466830SKalle Valo 	__le16 flags;
398d3466830SKalle Valo 	__le16 mask[2];
399d3466830SKalle Valo 	__le16 delay[2];
400d3466830SKalle Valo } __packed;
401d3466830SKalle Valo 
402d3466830SKalle Valo struct p54_edcf {
403d3466830SKalle Valo 	u8 flags;
404d3466830SKalle Valo 	u8 slottime;
405d3466830SKalle Valo 	u8 sifs;
406d3466830SKalle Valo 	u8 eofpad;
407d3466830SKalle Valo 	struct p54_edcf_queue_param queue[8];
408d3466830SKalle Valo 	u8 mapping[4];
409d3466830SKalle Valo 	__le16 frameburst;
410d3466830SKalle Valo 	__le16 round_trip_delay;
411d3466830SKalle Valo } __packed;
412d3466830SKalle Valo 
413d3466830SKalle Valo struct p54_statistics {
414d3466830SKalle Valo 	__le32 rx_success;
415d3466830SKalle Valo 	__le32 rx_bad_fcs;
416d3466830SKalle Valo 	__le32 rx_abort;
417d3466830SKalle Valo 	__le32 rx_abort_phy;
418d3466830SKalle Valo 	__le32 rts_success;
419d3466830SKalle Valo 	__le32 rts_fail;
420d3466830SKalle Valo 	__le32 tsf32;
421d3466830SKalle Valo 	__le32 airtime;
422d3466830SKalle Valo 	__le32 noise;
423d3466830SKalle Valo 	__le32 sample_noise[8];
424d3466830SKalle Valo 	__le32 sample_cca;
425d3466830SKalle Valo 	__le32 sample_tx;
426d3466830SKalle Valo } __packed;
427d3466830SKalle Valo 
428d3466830SKalle Valo struct p54_xbow_synth {
429d3466830SKalle Valo 	__le16 magic1;
430d3466830SKalle Valo 	__le16 magic2;
431d3466830SKalle Valo 	__le16 freq;
432d3466830SKalle Valo 	u32 padding[5];
433d3466830SKalle Valo } __packed;
434d3466830SKalle Valo 
435d3466830SKalle Valo struct p54_timer {
436d3466830SKalle Valo 	__le32 interval;
437d3466830SKalle Valo } __packed;
438d3466830SKalle Valo 
439d3466830SKalle Valo struct p54_keycache {
440d3466830SKalle Valo 	u8 entry;
441d3466830SKalle Valo 	u8 key_id;
442d3466830SKalle Valo 	u8 mac[ETH_ALEN];
443d3466830SKalle Valo 	u8 padding[2];
444d3466830SKalle Valo 	u8 key_type;
445d3466830SKalle Valo 	u8 key_len;
446d3466830SKalle Valo 	u8 key[24];
447d3466830SKalle Valo } __packed;
448d3466830SKalle Valo 
449d3466830SKalle Valo struct p54_burst {
450d3466830SKalle Valo 	u8 flags;
451d3466830SKalle Valo 	u8 queue;
452d3466830SKalle Valo 	u8 backlog;
453d3466830SKalle Valo 	u8 pad;
454d3466830SKalle Valo 	__le16 durations[32];
455d3466830SKalle Valo } __packed;
456d3466830SKalle Valo 
457d3466830SKalle Valo struct p54_psm_interval {
458d3466830SKalle Valo 	__le16 interval;
459d3466830SKalle Valo 	__le16 periods;
460d3466830SKalle Valo } __packed;
461d3466830SKalle Valo 
462d3466830SKalle Valo #define P54_PSM_CAM			0
463d3466830SKalle Valo #define P54_PSM				BIT(0)
464d3466830SKalle Valo #define P54_PSM_DTIM			BIT(1)
465d3466830SKalle Valo #define P54_PSM_MCBC			BIT(2)
466d3466830SKalle Valo #define P54_PSM_CHECKSUM		BIT(3)
467d3466830SKalle Valo #define P54_PSM_SKIP_MORE_DATA		BIT(4)
468d3466830SKalle Valo #define P54_PSM_BEACON_TIMEOUT		BIT(5)
469d3466830SKalle Valo #define P54_PSM_HFOSLEEP		BIT(6)
470d3466830SKalle Valo #define P54_PSM_AUTOSWITCH_SLEEP	BIT(7)
471d3466830SKalle Valo #define P54_PSM_LPIT			BIT(8)
472d3466830SKalle Valo #define P54_PSM_BF_UCAST_SKIP		BIT(9)
473d3466830SKalle Valo #define P54_PSM_BF_MCAST_SKIP		BIT(10)
474d3466830SKalle Valo 
475d3466830SKalle Valo struct p54_psm {
476d3466830SKalle Valo 	__le16 mode;
477d3466830SKalle Valo 	__le16 aid;
478d3466830SKalle Valo 	struct p54_psm_interval intervals[4];
479d3466830SKalle Valo 	u8 beacon_rssi_skip_max;
480d3466830SKalle Valo 	u8 rssi_delta_threshold;
481d3466830SKalle Valo 	u8 nr;
482d3466830SKalle Valo 	u8 exclude[1];
483d3466830SKalle Valo } __packed;
484d3466830SKalle Valo 
485d3466830SKalle Valo #define MC_FILTER_ADDRESS_NUM 4
486d3466830SKalle Valo 
487d3466830SKalle Valo struct p54_group_address_table {
488d3466830SKalle Valo 	__le16 filter_enable;
489d3466830SKalle Valo 	__le16 num_address;
490d3466830SKalle Valo 	u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN];
491d3466830SKalle Valo } __packed;
492d3466830SKalle Valo 
493d3466830SKalle Valo struct p54_txcancel {
494d3466830SKalle Valo 	__le32 req_id;
495d3466830SKalle Valo } __packed;
496d3466830SKalle Valo 
497d3466830SKalle Valo struct p54_sta_unlock {
498d3466830SKalle Valo 	u8 addr[ETH_ALEN];
499d3466830SKalle Valo 	u16 padding;
500d3466830SKalle Valo } __packed;
501d3466830SKalle Valo 
502d3466830SKalle Valo #define P54_TIM_CLEAR BIT(15)
503d3466830SKalle Valo struct p54_tim {
504d3466830SKalle Valo 	u8 count;
505d3466830SKalle Valo 	u8 padding[3];
506d3466830SKalle Valo 	__le16 entry[8];
507d3466830SKalle Valo } __packed;
508d3466830SKalle Valo 
509d3466830SKalle Valo struct p54_cce_quiet {
510d3466830SKalle Valo 	__le32 period;
511d3466830SKalle Valo } __packed;
512d3466830SKalle Valo 
513d3466830SKalle Valo struct p54_bt_balancer {
514d3466830SKalle Valo 	__le16 prio_thresh;
515d3466830SKalle Valo 	__le16 acl_thresh;
516d3466830SKalle Valo } __packed;
517d3466830SKalle Valo 
518d3466830SKalle Valo struct p54_arp_table {
519d3466830SKalle Valo 	__le16 filter_enable;
520d3466830SKalle Valo 	u8 ipv4_addr[4];
521d3466830SKalle Valo } __packed;
522d3466830SKalle Valo 
523d3466830SKalle Valo /* LED control */
524d3466830SKalle Valo int p54_set_leds(struct p54_common *priv);
525d3466830SKalle Valo int p54_init_leds(struct p54_common *priv);
526d3466830SKalle Valo void p54_unregister_leds(struct p54_common *priv);
527d3466830SKalle Valo 
528d3466830SKalle Valo /* xmit functions */
529d3466830SKalle Valo void p54_tx_80211(struct ieee80211_hw *dev,
530d3466830SKalle Valo 		  struct ieee80211_tx_control *control,
531d3466830SKalle Valo 		  struct sk_buff *skb);
532d3466830SKalle Valo int p54_tx_cancel(struct p54_common *priv, __le32 req_id);
533d3466830SKalle Valo void p54_tx(struct p54_common *priv, struct sk_buff *skb);
534d3466830SKalle Valo 
535d3466830SKalle Valo /* synth/phy configuration */
536d3466830SKalle Valo int p54_init_xbow_synth(struct p54_common *priv);
537d3466830SKalle Valo int p54_scan(struct p54_common *priv, u16 mode, u16 dwell);
538d3466830SKalle Valo 
539d3466830SKalle Valo /* MAC */
540d3466830SKalle Valo int p54_sta_unlock(struct p54_common *priv, u8 *addr);
541d3466830SKalle Valo int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set);
542d3466830SKalle Valo int p54_setup_mac(struct p54_common *priv);
543d3466830SKalle Valo int p54_set_ps(struct p54_common *priv);
544d3466830SKalle Valo int p54_fetch_statistics(struct p54_common *priv);
545d3466830SKalle Valo int p54_set_groupfilter(struct p54_common *priv);
546d3466830SKalle Valo 
547d3466830SKalle Valo /* e/v DCF setup */
548d3466830SKalle Valo int p54_set_edcf(struct p54_common *priv);
549d3466830SKalle Valo 
550d3466830SKalle Valo /* cryptographic engine */
551d3466830SKalle Valo int p54_upload_key(struct p54_common *priv, u8 algo, int slot,
552d3466830SKalle Valo 		   u8 idx, u8 len, u8 *addr, u8* key);
553d3466830SKalle Valo 
554d3466830SKalle Valo /* eeprom */
555d3466830SKalle Valo int p54_download_eeprom(struct p54_common *priv, void *buf,
556d3466830SKalle Valo 			u16 offset, u16 len);
557d3466830SKalle Valo struct p54_rssi_db_entry *p54_rssi_find(struct p54_common *p, const u16 freq);
558d3466830SKalle Valo 
559d3466830SKalle Valo /* utility */
560d3466830SKalle Valo u8 *p54_find_ie(struct sk_buff *skb, u8 ie);
561d3466830SKalle Valo 
562d3466830SKalle Valo #endif /* LMAC_H */
563