1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d3466830SKalle Valo /* 3d3466830SKalle Valo * LMAC Interface specific definitions for mac80211 Prism54 drivers 4d3466830SKalle Valo * 5d3466830SKalle Valo * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> 6d3466830SKalle Valo * Copyright (c) 2007 - 2009, Christian Lamparter <chunkeey@web.de> 7d3466830SKalle Valo * 8d3466830SKalle Valo * Based on: 9d3466830SKalle Valo * - the islsm (softmac prism54) driver, which is: 10d3466830SKalle Valo * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al. 11d3466830SKalle Valo * 12d3466830SKalle Valo * - LMAC API interface header file for STLC4560 (lmac_longbow.h) 13d3466830SKalle Valo * Copyright (C) 2007 Conexant Systems, Inc. 14d3466830SKalle Valo */ 15d3466830SKalle Valo 16d3466830SKalle Valo #ifndef LMAC_H 17d3466830SKalle Valo #define LMAC_H 18d3466830SKalle Valo 19d3466830SKalle Valo enum p54_control_frame_types { 20d3466830SKalle Valo P54_CONTROL_TYPE_SETUP = 0, 21d3466830SKalle Valo P54_CONTROL_TYPE_SCAN, 22d3466830SKalle Valo P54_CONTROL_TYPE_TRAP, 23d3466830SKalle Valo P54_CONTROL_TYPE_DCFINIT, 24d3466830SKalle Valo P54_CONTROL_TYPE_RX_KEYCACHE, 25d3466830SKalle Valo P54_CONTROL_TYPE_TIM, 26d3466830SKalle Valo P54_CONTROL_TYPE_PSM, 27d3466830SKalle Valo P54_CONTROL_TYPE_TXCANCEL, 28d3466830SKalle Valo P54_CONTROL_TYPE_TXDONE, 29d3466830SKalle Valo P54_CONTROL_TYPE_BURST, 30d3466830SKalle Valo P54_CONTROL_TYPE_STAT_READBACK, 31d3466830SKalle Valo P54_CONTROL_TYPE_BBP, 32d3466830SKalle Valo P54_CONTROL_TYPE_EEPROM_READBACK, 33d3466830SKalle Valo P54_CONTROL_TYPE_LED, 34d3466830SKalle Valo P54_CONTROL_TYPE_GPIO, 35d3466830SKalle Valo P54_CONTROL_TYPE_TIMER, 36d3466830SKalle Valo P54_CONTROL_TYPE_MODULATION, 37d3466830SKalle Valo P54_CONTROL_TYPE_SYNTH_CONFIG, 38d3466830SKalle Valo P54_CONTROL_TYPE_DETECTOR_VALUE, 39d3466830SKalle Valo P54_CONTROL_TYPE_XBOW_SYNTH_CFG, 40d3466830SKalle Valo P54_CONTROL_TYPE_CCE_QUIET, 41d3466830SKalle Valo P54_CONTROL_TYPE_PSM_STA_UNLOCK, 42d3466830SKalle Valo P54_CONTROL_TYPE_PCS, 43d3466830SKalle Valo P54_CONTROL_TYPE_BT_BALANCER = 28, 44d3466830SKalle Valo P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE = 30, 45d3466830SKalle Valo P54_CONTROL_TYPE_ARPTABLE = 31, 46d3466830SKalle Valo P54_CONTROL_TYPE_BT_OPTIONS = 35, 47d3466830SKalle Valo }; 48d3466830SKalle Valo 49d3466830SKalle Valo #define P54_HDR_FLAG_CONTROL BIT(15) 50d3466830SKalle Valo #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0)) 51d3466830SKalle Valo #define P54_HDR_FLAG_DATA_ALIGN BIT(14) 52d3466830SKalle Valo 53d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0) 54d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1) 55d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2) 56d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3) 57d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4) 58d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5) 59d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6) 60d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7) 61d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8) 62d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9) 63d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10) 64d3466830SKalle Valo #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11) 65d3466830SKalle Valo 66d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0) 67d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1) 68d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2) 69d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3) 70d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4) 71d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5) 72d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_DATA BIT(6) 73d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7) 74d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8) 75d3466830SKalle Valo #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9) 76d3466830SKalle Valo 77d3466830SKalle Valo struct p54_hdr { 78d3466830SKalle Valo __le16 flags; 79d3466830SKalle Valo __le16 len; 80d3466830SKalle Valo __le32 req_id; 81d3466830SKalle Valo __le16 type; /* enum p54_control_frame_types */ 82d3466830SKalle Valo u8 rts_tries; 83d3466830SKalle Valo u8 tries; 847b930713SGustavo A. R. Silva u8 data[]; 85d3466830SKalle Valo } __packed; 86d3466830SKalle Valo 87d3466830SKalle Valo #define GET_REQ_ID(skb) \ 88d3466830SKalle Valo (((struct p54_hdr *) ((struct sk_buff *) skb)->data)->req_id) \ 89d3466830SKalle Valo 90d3466830SKalle Valo #define FREE_AFTER_TX(skb) \ 91d3466830SKalle Valo ((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \ 92d3466830SKalle Valo flags) == cpu_to_le16(P54_HDR_FLAG_CONTROL_OPSET)) 93d3466830SKalle Valo 94d3466830SKalle Valo #define IS_DATA_FRAME(skb) \ 95d3466830SKalle Valo (!((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \ 96d3466830SKalle Valo flags) & cpu_to_le16(P54_HDR_FLAG_CONTROL))) 97d3466830SKalle Valo 98d3466830SKalle Valo #define GET_HW_QUEUE(skb) \ 99d3466830SKalle Valo (((struct p54_tx_data *)((struct p54_hdr *) \ 100d3466830SKalle Valo skb->data)->data)->hw_queue) 101d3466830SKalle Valo 102d3466830SKalle Valo /* 103d3466830SKalle Valo * shared interface ID definitions 104d3466830SKalle Valo * The interface ID is a unique identification of a specific interface. 105d3466830SKalle Valo * The following values are reserved: 0x0000, 0x0002, 0x0012, 0x0014, 0x0015 106d3466830SKalle Valo */ 107d3466830SKalle Valo #define IF_ID_ISL36356A 0x0001 /* ISL36356A <-> Firmware */ 108d3466830SKalle Valo #define IF_ID_MVC 0x0003 /* MAC Virtual Coprocessor */ 109d3466830SKalle Valo #define IF_ID_DEBUG 0x0008 /* PolDebug Interface */ 110d3466830SKalle Valo #define IF_ID_PRODUCT 0x0009 111d3466830SKalle Valo #define IF_ID_OEM 0x000a 112d3466830SKalle Valo #define IF_ID_PCI3877 0x000b /* 3877 <-> Host PCI */ 113d3466830SKalle Valo #define IF_ID_ISL37704C 0x000c /* ISL37704C <-> Fw */ 114d3466830SKalle Valo #define IF_ID_ISL39000 0x000f /* ISL39000 <-> Fw */ 115d3466830SKalle Valo #define IF_ID_ISL39300A 0x0010 /* ISL39300A <-> Fw */ 116d3466830SKalle Valo #define IF_ID_ISL37700_UAP 0x0016 /* ISL37700 uAP Fw <-> Fw */ 117d3466830SKalle Valo #define IF_ID_ISL39000_UAP 0x0017 /* ISL39000 uAP Fw <-> Fw */ 118d3466830SKalle Valo #define IF_ID_LMAC 0x001a /* Interface exposed by LMAC */ 119d3466830SKalle Valo 120d3466830SKalle Valo struct exp_if { 121d3466830SKalle Valo __le16 role; 122d3466830SKalle Valo __le16 if_id; 123d3466830SKalle Valo __le16 variant; 124d3466830SKalle Valo __le16 btm_compat; 125d3466830SKalle Valo __le16 top_compat; 126d3466830SKalle Valo } __packed; 127d3466830SKalle Valo 128d3466830SKalle Valo struct dep_if { 129d3466830SKalle Valo __le16 role; 130d3466830SKalle Valo __le16 if_id; 131d3466830SKalle Valo __le16 variant; 132d3466830SKalle Valo } __packed; 133d3466830SKalle Valo 134d3466830SKalle Valo /* driver <-> lmac definitions */ 135d3466830SKalle Valo struct p54_eeprom_lm86 { 136d3466830SKalle Valo union { 137d3466830SKalle Valo struct { 138d3466830SKalle Valo __le16 offset; 139d3466830SKalle Valo __le16 len; 140d3466830SKalle Valo u8 data[0]; 141d3466830SKalle Valo } __packed v1; 142d3466830SKalle Valo struct { 143d3466830SKalle Valo __le32 offset; 144d3466830SKalle Valo __le16 len; 145d3466830SKalle Valo u8 magic2; 146d3466830SKalle Valo u8 pad; 147d3466830SKalle Valo u8 magic[4]; 148d3466830SKalle Valo u8 data[0]; 149d3466830SKalle Valo } __packed v2; 150d3466830SKalle Valo } __packed; 151d3466830SKalle Valo } __packed; 152d3466830SKalle Valo 153d3466830SKalle Valo enum p54_rx_decrypt_status { 154d3466830SKalle Valo P54_DECRYPT_NONE = 0, 155d3466830SKalle Valo P54_DECRYPT_OK, 156d3466830SKalle Valo P54_DECRYPT_NOKEY, 157d3466830SKalle Valo P54_DECRYPT_NOMICHAEL, 158d3466830SKalle Valo P54_DECRYPT_NOCKIPMIC, 159d3466830SKalle Valo P54_DECRYPT_FAIL_WEP, 160d3466830SKalle Valo P54_DECRYPT_FAIL_TKIP, 161d3466830SKalle Valo P54_DECRYPT_FAIL_MICHAEL, 162d3466830SKalle Valo P54_DECRYPT_FAIL_CKIPKP, 163d3466830SKalle Valo P54_DECRYPT_FAIL_CKIPMIC, 164d3466830SKalle Valo P54_DECRYPT_FAIL_AESCCMP 165d3466830SKalle Valo }; 166d3466830SKalle Valo 167d3466830SKalle Valo struct p54_rx_data { 168d3466830SKalle Valo __le16 flags; 169d3466830SKalle Valo __le16 len; 170d3466830SKalle Valo __le16 freq; 171d3466830SKalle Valo u8 antenna; 172d3466830SKalle Valo u8 rate; 173d3466830SKalle Valo u8 rssi; 174d3466830SKalle Valo u8 quality; 175d3466830SKalle Valo u8 decrypt_status; 176d3466830SKalle Valo u8 rssi_raw; 177d3466830SKalle Valo __le32 tsf32; 178d3466830SKalle Valo __le32 unalloc0; 1797b930713SGustavo A. R. Silva u8 align[]; 180d3466830SKalle Valo } __packed; 181d3466830SKalle Valo 182d3466830SKalle Valo enum p54_trap_type { 183d3466830SKalle Valo P54_TRAP_SCAN = 0, 184d3466830SKalle Valo P54_TRAP_TIMER, 185d3466830SKalle Valo P54_TRAP_BEACON_TX, 186d3466830SKalle Valo P54_TRAP_FAA_RADIO_ON, 187d3466830SKalle Valo P54_TRAP_FAA_RADIO_OFF, 188d3466830SKalle Valo P54_TRAP_RADAR, 189d3466830SKalle Valo P54_TRAP_NO_BEACON, 190d3466830SKalle Valo P54_TRAP_TBTT, 191d3466830SKalle Valo P54_TRAP_SCO_ENTER, 192d3466830SKalle Valo P54_TRAP_SCO_EXIT 193d3466830SKalle Valo }; 194d3466830SKalle Valo 195d3466830SKalle Valo struct p54_trap { 196d3466830SKalle Valo __le16 event; 197d3466830SKalle Valo __le16 frequency; 198d3466830SKalle Valo } __packed; 199d3466830SKalle Valo 200d3466830SKalle Valo enum p54_frame_sent_status { 201d3466830SKalle Valo P54_TX_OK = 0, 202d3466830SKalle Valo P54_TX_FAILED, 203d3466830SKalle Valo P54_TX_PSM, 204d3466830SKalle Valo P54_TX_PSM_CANCELLED = 4 205d3466830SKalle Valo }; 206d3466830SKalle Valo 207d3466830SKalle Valo struct p54_frame_sent { 208d3466830SKalle Valo u8 status; 209d3466830SKalle Valo u8 tries; 210d3466830SKalle Valo u8 ack_rssi; 211d3466830SKalle Valo u8 quality; 212d3466830SKalle Valo __le16 seq; 213d3466830SKalle Valo u8 antenna; 214d3466830SKalle Valo u8 padding; 215d3466830SKalle Valo } __packed; 216d3466830SKalle Valo 217d3466830SKalle Valo enum p54_tx_data_crypt { 218d3466830SKalle Valo P54_CRYPTO_NONE = 0, 219d3466830SKalle Valo P54_CRYPTO_WEP, 220d3466830SKalle Valo P54_CRYPTO_TKIP, 221d3466830SKalle Valo P54_CRYPTO_TKIPMICHAEL, 222d3466830SKalle Valo P54_CRYPTO_CCX_WEPMIC, 223d3466830SKalle Valo P54_CRYPTO_CCX_KPMIC, 224d3466830SKalle Valo P54_CRYPTO_CCX_KP, 225d3466830SKalle Valo P54_CRYPTO_AESCCMP 226d3466830SKalle Valo }; 227d3466830SKalle Valo 228d3466830SKalle Valo enum p54_tx_data_queue { 229d3466830SKalle Valo P54_QUEUE_BEACON = 0, 230d3466830SKalle Valo P54_QUEUE_FWSCAN = 1, 231d3466830SKalle Valo P54_QUEUE_MGMT = 2, 232d3466830SKalle Valo P54_QUEUE_CAB = 3, 233d3466830SKalle Valo P54_QUEUE_DATA = 4, 234d3466830SKalle Valo 235d3466830SKalle Valo P54_QUEUE_AC_NUM = 4, 236d3466830SKalle Valo P54_QUEUE_AC_VO = 4, 237d3466830SKalle Valo P54_QUEUE_AC_VI = 5, 238d3466830SKalle Valo P54_QUEUE_AC_BE = 6, 239d3466830SKalle Valo P54_QUEUE_AC_BK = 7, 240d3466830SKalle Valo 241d3466830SKalle Valo /* keep last */ 242d3466830SKalle Valo P54_QUEUE_NUM = 8, 243d3466830SKalle Valo }; 244d3466830SKalle Valo 245d3466830SKalle Valo #define IS_QOS_QUEUE(n) (n >= P54_QUEUE_DATA) 246d3466830SKalle Valo 247d3466830SKalle Valo struct p54_tx_data { 248d3466830SKalle Valo u8 rateset[8]; 249d3466830SKalle Valo u8 rts_rate_idx; 250d3466830SKalle Valo u8 crypt_offset; 251d3466830SKalle Valo u8 key_type; 252d3466830SKalle Valo u8 key_len; 253d3466830SKalle Valo u8 key[16]; 254d3466830SKalle Valo u8 hw_queue; 255d3466830SKalle Valo u8 backlog; 256d3466830SKalle Valo __le16 durations[4]; 257d3466830SKalle Valo u8 tx_antenna; 258d3466830SKalle Valo union { 259d3466830SKalle Valo struct { 260d3466830SKalle Valo u8 cts_rate; 261d3466830SKalle Valo __le16 output_power; 262d3466830SKalle Valo } __packed longbow; 263d3466830SKalle Valo struct { 264d3466830SKalle Valo u8 output_power; 265d3466830SKalle Valo u8 cts_rate; 266d3466830SKalle Valo u8 unalloc; 267d3466830SKalle Valo } __packed normal; 268d3466830SKalle Valo } __packed; 269d3466830SKalle Valo u8 unalloc2[2]; 2707b930713SGustavo A. R. Silva u8 align[]; 271d3466830SKalle Valo } __packed; 272d3466830SKalle Valo 273d3466830SKalle Valo /* unit is ms */ 274d3466830SKalle Valo #define P54_TX_FRAME_LIFETIME 2000 275d3466830SKalle Valo #define P54_TX_TIMEOUT 4000 276d3466830SKalle Valo #define P54_STATISTICS_UPDATE 5000 277d3466830SKalle Valo 278d3466830SKalle Valo #define P54_FILTER_TYPE_NONE 0 279d3466830SKalle Valo #define P54_FILTER_TYPE_STATION BIT(0) 280d3466830SKalle Valo #define P54_FILTER_TYPE_IBSS BIT(1) 281d3466830SKalle Valo #define P54_FILTER_TYPE_AP BIT(2) 282d3466830SKalle Valo #define P54_FILTER_TYPE_TRANSPARENT BIT(3) 283d3466830SKalle Valo #define P54_FILTER_TYPE_PROMISCUOUS BIT(4) 284d3466830SKalle Valo #define P54_FILTER_TYPE_HIBERNATE BIT(5) 285d3466830SKalle Valo #define P54_FILTER_TYPE_NOACK BIT(6) 286d3466830SKalle Valo #define P54_FILTER_TYPE_RX_DISABLED BIT(7) 287d3466830SKalle Valo 288d3466830SKalle Valo struct p54_setup_mac { 289d3466830SKalle Valo __le16 mac_mode; 290d3466830SKalle Valo u8 mac_addr[ETH_ALEN]; 291d3466830SKalle Valo u8 bssid[ETH_ALEN]; 292d3466830SKalle Valo u8 rx_antenna; 293d3466830SKalle Valo u8 rx_align; 294d3466830SKalle Valo union { 295d3466830SKalle Valo struct { 296d3466830SKalle Valo __le32 basic_rate_mask; 297d3466830SKalle Valo u8 rts_rates[8]; 298d3466830SKalle Valo __le32 rx_addr; 299d3466830SKalle Valo __le16 max_rx; 300d3466830SKalle Valo __le16 rxhw; 301d3466830SKalle Valo __le16 wakeup_timer; 302d3466830SKalle Valo __le16 unalloc0; 303d3466830SKalle Valo } __packed v1; 304d3466830SKalle Valo struct { 305d3466830SKalle Valo __le32 rx_addr; 306d3466830SKalle Valo __le16 max_rx; 307d3466830SKalle Valo __le16 rxhw; 308d3466830SKalle Valo __le16 timer; 309d3466830SKalle Valo __le16 truncate; 310d3466830SKalle Valo __le32 basic_rate_mask; 311d3466830SKalle Valo u8 sbss_offset; 312d3466830SKalle Valo u8 mcast_window; 313d3466830SKalle Valo u8 rx_rssi_threshold; 314d3466830SKalle Valo u8 rx_ed_threshold; 315d3466830SKalle Valo __le32 ref_clock; 316d3466830SKalle Valo __le16 lpf_bandwidth; 317d3466830SKalle Valo __le16 osc_start_delay; 318d3466830SKalle Valo } __packed v2; 319d3466830SKalle Valo } __packed; 320d3466830SKalle Valo } __packed; 321d3466830SKalle Valo 322d3466830SKalle Valo #define P54_SETUP_V1_LEN 40 323d3466830SKalle Valo #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac)) 324d3466830SKalle Valo 325d3466830SKalle Valo #define P54_SCAN_EXIT BIT(0) 326d3466830SKalle Valo #define P54_SCAN_TRAP BIT(1) 327d3466830SKalle Valo #define P54_SCAN_ACTIVE BIT(2) 328d3466830SKalle Valo #define P54_SCAN_FILTER BIT(3) 329d3466830SKalle Valo 330d3466830SKalle Valo struct p54_scan_head { 331d3466830SKalle Valo __le16 mode; 332d3466830SKalle Valo __le16 dwell; 333d3466830SKalle Valo u8 scan_params[20]; 334d3466830SKalle Valo __le16 freq; 335d3466830SKalle Valo } __packed; 336d3466830SKalle Valo 337d3466830SKalle Valo struct p54_pa_curve_data_sample { 338d3466830SKalle Valo u8 rf_power; 339d3466830SKalle Valo u8 pa_detector; 340d3466830SKalle Valo u8 data_barker; 341d3466830SKalle Valo u8 data_bpsk; 342d3466830SKalle Valo u8 data_qpsk; 343d3466830SKalle Valo u8 data_16qam; 344d3466830SKalle Valo u8 data_64qam; 345d3466830SKalle Valo u8 padding; 346d3466830SKalle Valo } __packed; 347d3466830SKalle Valo 348d3466830SKalle Valo struct p54_scan_body { 349d3466830SKalle Valo u8 pa_points_per_curve; 350d3466830SKalle Valo u8 val_barker; 351d3466830SKalle Valo u8 val_bpsk; 352d3466830SKalle Valo u8 val_qpsk; 353d3466830SKalle Valo u8 val_16qam; 354d3466830SKalle Valo u8 val_64qam; 355d3466830SKalle Valo struct p54_pa_curve_data_sample curve_data[8]; 356d3466830SKalle Valo u8 dup_bpsk; 357d3466830SKalle Valo u8 dup_qpsk; 358d3466830SKalle Valo u8 dup_16qam; 359d3466830SKalle Valo u8 dup_64qam; 360d3466830SKalle Valo } __packed; 361d3466830SKalle Valo 362d3466830SKalle Valo /* 363d3466830SKalle Valo * Warning: Longbow's structures are bogus. 364d3466830SKalle Valo */ 365d3466830SKalle Valo struct p54_channel_output_limit_longbow { 366d3466830SKalle Valo __le16 rf_power_points[12]; 367d3466830SKalle Valo } __packed; 368d3466830SKalle Valo 369d3466830SKalle Valo struct p54_pa_curve_data_sample_longbow { 370d3466830SKalle Valo __le16 rf_power; 371d3466830SKalle Valo __le16 pa_detector; 372d3466830SKalle Valo struct { 373d3466830SKalle Valo __le16 data[4]; 374d3466830SKalle Valo } points[3] __packed; 375d3466830SKalle Valo } __packed; 376d3466830SKalle Valo 377d3466830SKalle Valo struct p54_scan_body_longbow { 378d3466830SKalle Valo struct p54_channel_output_limit_longbow power_limits; 379d3466830SKalle Valo struct p54_pa_curve_data_sample_longbow curve_data[8]; 380d3466830SKalle Valo __le16 unkn[6]; /* maybe more power_limits or rate_mask */ 381d3466830SKalle Valo } __packed; 382d3466830SKalle Valo 383d3466830SKalle Valo union p54_scan_body_union { 384d3466830SKalle Valo struct p54_scan_body normal; 385d3466830SKalle Valo struct p54_scan_body_longbow longbow; 386d3466830SKalle Valo } __packed; 387d3466830SKalle Valo 388d3466830SKalle Valo struct p54_scan_tail_rate { 389d3466830SKalle Valo __le32 basic_rate_mask; 390d3466830SKalle Valo u8 rts_rates[8]; 391d3466830SKalle Valo } __packed; 392d3466830SKalle Valo 393d3466830SKalle Valo struct p54_led { 394d3466830SKalle Valo __le16 flags; 395d3466830SKalle Valo __le16 mask[2]; 396d3466830SKalle Valo __le16 delay[2]; 397d3466830SKalle Valo } __packed; 398d3466830SKalle Valo 399d3466830SKalle Valo struct p54_edcf { 400d3466830SKalle Valo u8 flags; 401d3466830SKalle Valo u8 slottime; 402d3466830SKalle Valo u8 sifs; 403d3466830SKalle Valo u8 eofpad; 404d3466830SKalle Valo struct p54_edcf_queue_param queue[8]; 405d3466830SKalle Valo u8 mapping[4]; 406d3466830SKalle Valo __le16 frameburst; 407d3466830SKalle Valo __le16 round_trip_delay; 408d3466830SKalle Valo } __packed; 409d3466830SKalle Valo 410d3466830SKalle Valo struct p54_statistics { 411d3466830SKalle Valo __le32 rx_success; 412d3466830SKalle Valo __le32 rx_bad_fcs; 413d3466830SKalle Valo __le32 rx_abort; 414d3466830SKalle Valo __le32 rx_abort_phy; 415d3466830SKalle Valo __le32 rts_success; 416d3466830SKalle Valo __le32 rts_fail; 417d3466830SKalle Valo __le32 tsf32; 418d3466830SKalle Valo __le32 airtime; 419d3466830SKalle Valo __le32 noise; 420d3466830SKalle Valo __le32 sample_noise[8]; 421d3466830SKalle Valo __le32 sample_cca; 422d3466830SKalle Valo __le32 sample_tx; 423d3466830SKalle Valo } __packed; 424d3466830SKalle Valo 425d3466830SKalle Valo struct p54_xbow_synth { 426d3466830SKalle Valo __le16 magic1; 427d3466830SKalle Valo __le16 magic2; 428d3466830SKalle Valo __le16 freq; 429d3466830SKalle Valo u32 padding[5]; 430d3466830SKalle Valo } __packed; 431d3466830SKalle Valo 432d3466830SKalle Valo struct p54_timer { 433d3466830SKalle Valo __le32 interval; 434d3466830SKalle Valo } __packed; 435d3466830SKalle Valo 436d3466830SKalle Valo struct p54_keycache { 437d3466830SKalle Valo u8 entry; 438d3466830SKalle Valo u8 key_id; 439d3466830SKalle Valo u8 mac[ETH_ALEN]; 440d3466830SKalle Valo u8 padding[2]; 441d3466830SKalle Valo u8 key_type; 442d3466830SKalle Valo u8 key_len; 443d3466830SKalle Valo u8 key[24]; 444d3466830SKalle Valo } __packed; 445d3466830SKalle Valo 446d3466830SKalle Valo struct p54_burst { 447d3466830SKalle Valo u8 flags; 448d3466830SKalle Valo u8 queue; 449d3466830SKalle Valo u8 backlog; 450d3466830SKalle Valo u8 pad; 451d3466830SKalle Valo __le16 durations[32]; 452d3466830SKalle Valo } __packed; 453d3466830SKalle Valo 454d3466830SKalle Valo struct p54_psm_interval { 455d3466830SKalle Valo __le16 interval; 456d3466830SKalle Valo __le16 periods; 457d3466830SKalle Valo } __packed; 458d3466830SKalle Valo 459d3466830SKalle Valo #define P54_PSM_CAM 0 460d3466830SKalle Valo #define P54_PSM BIT(0) 461d3466830SKalle Valo #define P54_PSM_DTIM BIT(1) 462d3466830SKalle Valo #define P54_PSM_MCBC BIT(2) 463d3466830SKalle Valo #define P54_PSM_CHECKSUM BIT(3) 464d3466830SKalle Valo #define P54_PSM_SKIP_MORE_DATA BIT(4) 465d3466830SKalle Valo #define P54_PSM_BEACON_TIMEOUT BIT(5) 466d3466830SKalle Valo #define P54_PSM_HFOSLEEP BIT(6) 467d3466830SKalle Valo #define P54_PSM_AUTOSWITCH_SLEEP BIT(7) 468d3466830SKalle Valo #define P54_PSM_LPIT BIT(8) 469d3466830SKalle Valo #define P54_PSM_BF_UCAST_SKIP BIT(9) 470d3466830SKalle Valo #define P54_PSM_BF_MCAST_SKIP BIT(10) 471d3466830SKalle Valo 472d3466830SKalle Valo struct p54_psm { 473d3466830SKalle Valo __le16 mode; 474d3466830SKalle Valo __le16 aid; 475d3466830SKalle Valo struct p54_psm_interval intervals[4]; 476d3466830SKalle Valo u8 beacon_rssi_skip_max; 477d3466830SKalle Valo u8 rssi_delta_threshold; 478d3466830SKalle Valo u8 nr; 479d3466830SKalle Valo u8 exclude[1]; 480d3466830SKalle Valo } __packed; 481d3466830SKalle Valo 482d3466830SKalle Valo #define MC_FILTER_ADDRESS_NUM 4 483d3466830SKalle Valo 484d3466830SKalle Valo struct p54_group_address_table { 485d3466830SKalle Valo __le16 filter_enable; 486d3466830SKalle Valo __le16 num_address; 487d3466830SKalle Valo u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN]; 488d3466830SKalle Valo } __packed; 489d3466830SKalle Valo 490d3466830SKalle Valo struct p54_txcancel { 491d3466830SKalle Valo __le32 req_id; 492d3466830SKalle Valo } __packed; 493d3466830SKalle Valo 494d3466830SKalle Valo struct p54_sta_unlock { 495d3466830SKalle Valo u8 addr[ETH_ALEN]; 496d3466830SKalle Valo u16 padding; 497d3466830SKalle Valo } __packed; 498d3466830SKalle Valo 499d3466830SKalle Valo #define P54_TIM_CLEAR BIT(15) 500d3466830SKalle Valo struct p54_tim { 501d3466830SKalle Valo u8 count; 502d3466830SKalle Valo u8 padding[3]; 503d3466830SKalle Valo __le16 entry[8]; 504d3466830SKalle Valo } __packed; 505d3466830SKalle Valo 506d3466830SKalle Valo struct p54_cce_quiet { 507d3466830SKalle Valo __le32 period; 508d3466830SKalle Valo } __packed; 509d3466830SKalle Valo 510d3466830SKalle Valo struct p54_bt_balancer { 511d3466830SKalle Valo __le16 prio_thresh; 512d3466830SKalle Valo __le16 acl_thresh; 513d3466830SKalle Valo } __packed; 514d3466830SKalle Valo 515d3466830SKalle Valo struct p54_arp_table { 516d3466830SKalle Valo __le16 filter_enable; 517d3466830SKalle Valo u8 ipv4_addr[4]; 518d3466830SKalle Valo } __packed; 519d3466830SKalle Valo 520d3466830SKalle Valo /* LED control */ 521d3466830SKalle Valo int p54_set_leds(struct p54_common *priv); 522d3466830SKalle Valo int p54_init_leds(struct p54_common *priv); 523d3466830SKalle Valo void p54_unregister_leds(struct p54_common *priv); 524d3466830SKalle Valo 525d3466830SKalle Valo /* xmit functions */ 526d3466830SKalle Valo void p54_tx_80211(struct ieee80211_hw *dev, 527d3466830SKalle Valo struct ieee80211_tx_control *control, 528d3466830SKalle Valo struct sk_buff *skb); 529d3466830SKalle Valo int p54_tx_cancel(struct p54_common *priv, __le32 req_id); 530d3466830SKalle Valo void p54_tx(struct p54_common *priv, struct sk_buff *skb); 531d3466830SKalle Valo 532d3466830SKalle Valo /* synth/phy configuration */ 533d3466830SKalle Valo int p54_init_xbow_synth(struct p54_common *priv); 534d3466830SKalle Valo int p54_scan(struct p54_common *priv, u16 mode, u16 dwell); 535d3466830SKalle Valo 536d3466830SKalle Valo /* MAC */ 537d3466830SKalle Valo int p54_sta_unlock(struct p54_common *priv, u8 *addr); 538d3466830SKalle Valo int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set); 539d3466830SKalle Valo int p54_setup_mac(struct p54_common *priv); 540d3466830SKalle Valo int p54_set_ps(struct p54_common *priv); 541d3466830SKalle Valo int p54_fetch_statistics(struct p54_common *priv); 542d3466830SKalle Valo int p54_set_groupfilter(struct p54_common *priv); 543d3466830SKalle Valo 544d3466830SKalle Valo /* e/v DCF setup */ 545d3466830SKalle Valo int p54_set_edcf(struct p54_common *priv); 546d3466830SKalle Valo 547d3466830SKalle Valo /* cryptographic engine */ 548d3466830SKalle Valo int p54_upload_key(struct p54_common *priv, u8 algo, int slot, 549d3466830SKalle Valo u8 idx, u8 len, u8 *addr, u8* key); 550d3466830SKalle Valo 551d3466830SKalle Valo /* eeprom */ 552d3466830SKalle Valo int p54_download_eeprom(struct p54_common *priv, void *buf, 553d3466830SKalle Valo u16 offset, u16 len); 554d3466830SKalle Valo struct p54_rssi_db_entry *p54_rssi_find(struct p54_common *p, const u16 freq); 555d3466830SKalle Valo 556d3466830SKalle Valo /* utility */ 557d3466830SKalle Valo u8 *p54_find_ie(struct sk_buff *skb, u8 ie); 558d3466830SKalle Valo 559d3466830SKalle Valo #endif /* LMAC_H */ 560