1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * 7 * Portions of this file are derived from the ipw3945 project, as well 8 * as portions of the ieee80211 subsystem header files. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22 * 23 * The full GNU General Public License is included in this distribution in the 24 * file called LICENSE. 25 * 26 * Contact Information: 27 * Intel Linux Wireless <linuxwifi@intel.com> 28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29 * 30 *****************************************************************************/ 31 #include <linux/etherdevice.h> 32 #include <linux/ieee80211.h> 33 #include <linux/slab.h> 34 #include <linux/sched.h> 35 #include <linux/pm_runtime.h> 36 #include <net/ip6_checksum.h> 37 #include <net/tso.h> 38 39 #include "iwl-debug.h" 40 #include "iwl-csr.h" 41 #include "iwl-prph.h" 42 #include "iwl-io.h" 43 #include "iwl-scd.h" 44 #include "iwl-op-mode.h" 45 #include "internal.h" 46 /* FIXME: need to abstract out TX command (once we know what it looks like) */ 47 #include "dvm/commands.h" 48 49 #define IWL_TX_CRC_SIZE 4 50 #define IWL_TX_DELIMITER_SIZE 4 51 52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 53 * DMA services 54 * 55 * Theory of operation 56 * 57 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 58 * of buffer descriptors, each of which points to one or more data buffers for 59 * the device to read from or fill. Driver and device exchange status of each 60 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 61 * entries in each circular buffer, to protect against confusing empty and full 62 * queue states. 63 * 64 * The device reads or writes the data in the queues via the device's several 65 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 66 * 67 * For Tx queue, there are low mark and high mark limits. If, after queuing 68 * the packet for Tx, free space become < low mark, Tx queue stopped. When 69 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 70 * Tx queue resumed. 71 * 72 ***************************************************/ 73 74 int iwl_queue_space(const struct iwl_txq *q) 75 { 76 unsigned int max; 77 unsigned int used; 78 79 /* 80 * To avoid ambiguity between empty and completely full queues, there 81 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 82 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 83 * to reserve any queue entries for this purpose. 84 */ 85 if (q->n_window < TFD_QUEUE_SIZE_MAX) 86 max = q->n_window; 87 else 88 max = TFD_QUEUE_SIZE_MAX - 1; 89 90 /* 91 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 92 * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 93 */ 94 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 95 96 if (WARN_ON(used > max)) 97 return 0; 98 99 return max - used; 100 } 101 102 /* 103 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 104 */ 105 static int iwl_queue_init(struct iwl_txq *q, int slots_num) 106 { 107 q->n_window = slots_num; 108 109 /* slots_num must be power-of-two size, otherwise 110 * get_cmd_index is broken. */ 111 if (WARN_ON(!is_power_of_2(slots_num))) 112 return -EINVAL; 113 114 q->low_mark = q->n_window / 4; 115 if (q->low_mark < 4) 116 q->low_mark = 4; 117 118 q->high_mark = q->n_window / 8; 119 if (q->high_mark < 2) 120 q->high_mark = 2; 121 122 q->write_ptr = 0; 123 q->read_ptr = 0; 124 125 return 0; 126 } 127 128 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 129 struct iwl_dma_ptr *ptr, size_t size) 130 { 131 if (WARN_ON(ptr->addr)) 132 return -EINVAL; 133 134 ptr->addr = dma_alloc_coherent(trans->dev, size, 135 &ptr->dma, GFP_KERNEL); 136 if (!ptr->addr) 137 return -ENOMEM; 138 ptr->size = size; 139 return 0; 140 } 141 142 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 143 { 144 if (unlikely(!ptr->addr)) 145 return; 146 147 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 148 memset(ptr, 0, sizeof(*ptr)); 149 } 150 151 static void iwl_pcie_txq_stuck_timer(unsigned long data) 152 { 153 struct iwl_txq *txq = (void *)data; 154 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 155 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 156 157 spin_lock(&txq->lock); 158 /* check if triggered erroneously */ 159 if (txq->read_ptr == txq->write_ptr) { 160 spin_unlock(&txq->lock); 161 return; 162 } 163 spin_unlock(&txq->lock); 164 165 iwl_trans_pcie_log_scd_error(trans, txq); 166 167 iwl_force_nmi(trans); 168 } 169 170 /* 171 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 172 */ 173 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 174 struct iwl_txq *txq, u16 byte_cnt, 175 int num_tbs) 176 { 177 struct iwlagn_scd_bc_tbl *scd_bc_tbl; 178 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 179 int write_ptr = txq->write_ptr; 180 int txq_id = txq->id; 181 u8 sec_ctl = 0; 182 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 183 __le16 bc_ent; 184 struct iwl_tx_cmd *tx_cmd = 185 (void *)txq->entries[txq->write_ptr].cmd->payload; 186 u8 sta_id = tx_cmd->sta_id; 187 188 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 189 190 sec_ctl = tx_cmd->sec_ctl; 191 192 switch (sec_ctl & TX_CMD_SEC_MSK) { 193 case TX_CMD_SEC_CCM: 194 len += IEEE80211_CCMP_MIC_LEN; 195 break; 196 case TX_CMD_SEC_TKIP: 197 len += IEEE80211_TKIP_ICV_LEN; 198 break; 199 case TX_CMD_SEC_WEP: 200 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 201 break; 202 } 203 if (trans_pcie->bc_table_dword) 204 len = DIV_ROUND_UP(len, 4); 205 206 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 207 return; 208 209 bc_ent = cpu_to_le16(len | (sta_id << 12)); 210 211 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 212 213 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 214 scd_bc_tbl[txq_id]. 215 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 216 } 217 218 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 219 struct iwl_txq *txq) 220 { 221 struct iwl_trans_pcie *trans_pcie = 222 IWL_TRANS_GET_PCIE_TRANS(trans); 223 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 224 int txq_id = txq->id; 225 int read_ptr = txq->read_ptr; 226 u8 sta_id = 0; 227 __le16 bc_ent; 228 struct iwl_tx_cmd *tx_cmd = 229 (void *)txq->entries[read_ptr].cmd->payload; 230 231 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 232 233 if (txq_id != trans_pcie->cmd_queue) 234 sta_id = tx_cmd->sta_id; 235 236 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 237 238 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 239 240 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 241 scd_bc_tbl[txq_id]. 242 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 243 } 244 245 /* 246 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 247 */ 248 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 249 struct iwl_txq *txq) 250 { 251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 252 u32 reg = 0; 253 int txq_id = txq->id; 254 255 lockdep_assert_held(&txq->lock); 256 257 /* 258 * explicitly wake up the NIC if: 259 * 1. shadow registers aren't enabled 260 * 2. NIC is woken up for CMD regardless of shadow outside this function 261 * 3. there is a chance that the NIC is asleep 262 */ 263 if (!trans->cfg->base_params->shadow_reg_enable && 264 txq_id != trans_pcie->cmd_queue && 265 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 266 /* 267 * wake up nic if it's powered down ... 268 * uCode will wake up, and interrupt us again, so next 269 * time we'll skip this part. 270 */ 271 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 272 273 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 274 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 275 txq_id, reg); 276 iwl_set_bit(trans, CSR_GP_CNTRL, 277 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 278 txq->need_update = true; 279 return; 280 } 281 } 282 283 /* 284 * if not in power-save mode, uCode will never sleep when we're 285 * trying to tx (during RFKILL, we're not trying to tx). 286 */ 287 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 288 if (!txq->block) 289 iwl_write32(trans, HBUS_TARG_WRPTR, 290 txq->write_ptr | (txq_id << 8)); 291 } 292 293 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 294 { 295 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 296 int i; 297 298 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 299 struct iwl_txq *txq = trans_pcie->txq[i]; 300 301 spin_lock_bh(&txq->lock); 302 if (txq->need_update) { 303 iwl_pcie_txq_inc_wr_ptr(trans, txq); 304 txq->need_update = false; 305 } 306 spin_unlock_bh(&txq->lock); 307 } 308 } 309 310 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 311 void *_tfd, u8 idx) 312 { 313 314 if (trans->cfg->use_tfh) { 315 struct iwl_tfh_tfd *tfd = _tfd; 316 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 317 318 return (dma_addr_t)(le64_to_cpu(tb->addr)); 319 } else { 320 struct iwl_tfd *tfd = _tfd; 321 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 322 dma_addr_t addr = get_unaligned_le32(&tb->lo); 323 dma_addr_t hi_len; 324 325 if (sizeof(dma_addr_t) <= sizeof(u32)) 326 return addr; 327 328 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 329 330 /* 331 * shift by 16 twice to avoid warnings on 32-bit 332 * (where this code never runs anyway due to the 333 * if statement above) 334 */ 335 return addr | ((hi_len << 16) << 16); 336 } 337 } 338 339 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 340 u8 idx, dma_addr_t addr, u16 len) 341 { 342 struct iwl_tfd *tfd_fh = (void *)tfd; 343 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 344 345 u16 hi_n_len = len << 4; 346 347 put_unaligned_le32(addr, &tb->lo); 348 hi_n_len |= iwl_get_dma_hi_addr(addr); 349 350 tb->hi_n_len = cpu_to_le16(hi_n_len); 351 352 tfd_fh->num_tbs = idx + 1; 353 } 354 355 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 356 { 357 if (trans->cfg->use_tfh) { 358 struct iwl_tfh_tfd *tfd = _tfd; 359 360 return le16_to_cpu(tfd->num_tbs) & 0x1f; 361 } else { 362 struct iwl_tfd *tfd = _tfd; 363 364 return tfd->num_tbs & 0x1f; 365 } 366 } 367 368 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 369 struct iwl_cmd_meta *meta, 370 struct iwl_txq *txq, int index) 371 { 372 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 373 int i, num_tbs; 374 void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index); 375 376 /* Sanity check on number of chunks */ 377 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 378 379 if (num_tbs >= trans_pcie->max_tbs) { 380 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 381 /* @todo issue fatal error, it is quite serious situation */ 382 return; 383 } 384 385 /* first TB is never freed - it's the bidirectional DMA data */ 386 387 for (i = 1; i < num_tbs; i++) { 388 if (meta->tbs & BIT(i)) 389 dma_unmap_page(trans->dev, 390 iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 391 iwl_pcie_tfd_tb_get_len(trans, tfd, i), 392 DMA_TO_DEVICE); 393 else 394 dma_unmap_single(trans->dev, 395 iwl_pcie_tfd_tb_get_addr(trans, tfd, 396 i), 397 iwl_pcie_tfd_tb_get_len(trans, tfd, 398 i), 399 DMA_TO_DEVICE); 400 } 401 402 if (trans->cfg->use_tfh) { 403 struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 404 405 tfd_fh->num_tbs = 0; 406 } else { 407 struct iwl_tfd *tfd_fh = (void *)tfd; 408 409 tfd_fh->num_tbs = 0; 410 } 411 412 } 413 414 /* 415 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 416 * @trans - transport private data 417 * @txq - tx queue 418 * @dma_dir - the direction of the DMA mapping 419 * 420 * Does NOT advance any TFD circular buffer read/write indexes 421 * Does NOT free the TFD itself (which is within circular buffer) 422 */ 423 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 424 { 425 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 426 * idx is bounded by n_window 427 */ 428 int rd_ptr = txq->read_ptr; 429 int idx = get_cmd_index(txq, rd_ptr); 430 431 lockdep_assert_held(&txq->lock); 432 433 /* We have only q->n_window txq->entries, but we use 434 * TFD_QUEUE_SIZE_MAX tfds 435 */ 436 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 437 438 /* free SKB */ 439 if (txq->entries) { 440 struct sk_buff *skb; 441 442 skb = txq->entries[idx].skb; 443 444 /* Can be called from irqs-disabled context 445 * If skb is not NULL, it means that the whole queue is being 446 * freed and that the queue is not empty - free the skb 447 */ 448 if (skb) { 449 iwl_op_mode_free_skb(trans->op_mode, skb); 450 txq->entries[idx].skb = NULL; 451 } 452 } 453 } 454 455 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 456 dma_addr_t addr, u16 len, bool reset) 457 { 458 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 459 void *tfd; 460 u32 num_tbs; 461 462 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 463 464 if (reset) 465 memset(tfd, 0, trans_pcie->tfd_size); 466 467 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 468 469 /* Each TFD can point to a maximum max_tbs Tx buffers */ 470 if (num_tbs >= trans_pcie->max_tbs) { 471 IWL_ERR(trans, "Error can not send more than %d chunks\n", 472 trans_pcie->max_tbs); 473 return -EINVAL; 474 } 475 476 if (WARN(addr & ~IWL_TX_DMA_MASK, 477 "Unaligned address = %llx\n", (unsigned long long)addr)) 478 return -EINVAL; 479 480 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 481 482 return num_tbs; 483 } 484 485 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 486 int slots_num, bool cmd_queue) 487 { 488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 489 size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX; 490 size_t tb0_buf_sz; 491 int i; 492 493 if (WARN_ON(txq->entries || txq->tfds)) 494 return -EINVAL; 495 496 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 497 (unsigned long)txq); 498 txq->trans_pcie = trans_pcie; 499 500 txq->n_window = slots_num; 501 502 txq->entries = kcalloc(slots_num, 503 sizeof(struct iwl_pcie_txq_entry), 504 GFP_KERNEL); 505 506 if (!txq->entries) 507 goto error; 508 509 if (cmd_queue) 510 for (i = 0; i < slots_num; i++) { 511 txq->entries[i].cmd = 512 kmalloc(sizeof(struct iwl_device_cmd), 513 GFP_KERNEL); 514 if (!txq->entries[i].cmd) 515 goto error; 516 } 517 518 /* Circular buffer of transmit frame descriptors (TFDs), 519 * shared with device */ 520 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 521 &txq->dma_addr, GFP_KERNEL); 522 if (!txq->tfds) 523 goto error; 524 525 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 526 527 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 528 529 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 530 &txq->first_tb_dma, 531 GFP_KERNEL); 532 if (!txq->first_tb_bufs) 533 goto err_free_tfds; 534 535 return 0; 536 err_free_tfds: 537 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 538 error: 539 if (txq->entries && cmd_queue) 540 for (i = 0; i < slots_num; i++) 541 kfree(txq->entries[i].cmd); 542 kfree(txq->entries); 543 txq->entries = NULL; 544 545 return -ENOMEM; 546 547 } 548 549 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 550 int slots_num, bool cmd_queue) 551 { 552 int ret; 553 554 txq->need_update = false; 555 556 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 557 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 558 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 559 560 /* Initialize queue's high/low-water marks, and head/tail indexes */ 561 ret = iwl_queue_init(txq, slots_num); 562 if (ret) 563 return ret; 564 565 spin_lock_init(&txq->lock); 566 567 if (cmd_queue) { 568 static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 569 570 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 571 } 572 573 __skb_queue_head_init(&txq->overflow_q); 574 575 return 0; 576 } 577 578 static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 579 struct sk_buff *skb) 580 { 581 struct page **page_ptr; 582 583 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 584 585 if (*page_ptr) { 586 __free_page(*page_ptr); 587 *page_ptr = NULL; 588 } 589 } 590 591 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 592 { 593 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 594 595 lockdep_assert_held(&trans_pcie->reg_lock); 596 597 if (trans_pcie->ref_cmd_in_flight) { 598 trans_pcie->ref_cmd_in_flight = false; 599 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 600 iwl_trans_unref(trans); 601 } 602 603 if (!trans->cfg->base_params->apmg_wake_up_wa) 604 return; 605 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 606 return; 607 608 trans_pcie->cmd_hold_nic_awake = false; 609 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 610 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 611 } 612 613 /* 614 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 615 */ 616 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 617 { 618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 619 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 620 621 spin_lock_bh(&txq->lock); 622 while (txq->write_ptr != txq->read_ptr) { 623 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 624 txq_id, txq->read_ptr); 625 626 if (txq_id != trans_pcie->cmd_queue) { 627 struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 628 629 if (WARN_ON_ONCE(!skb)) 630 continue; 631 632 iwl_pcie_free_tso_page(trans_pcie, skb); 633 } 634 iwl_pcie_txq_free_tfd(trans, txq); 635 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr); 636 637 if (txq->read_ptr == txq->write_ptr) { 638 unsigned long flags; 639 640 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 641 if (txq_id != trans_pcie->cmd_queue) { 642 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 643 txq->id); 644 iwl_trans_unref(trans); 645 } else { 646 iwl_pcie_clear_cmd_in_flight(trans); 647 } 648 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 649 } 650 } 651 652 while (!skb_queue_empty(&txq->overflow_q)) { 653 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 654 655 iwl_op_mode_free_skb(trans->op_mode, skb); 656 } 657 658 spin_unlock_bh(&txq->lock); 659 660 /* just in case - this queue may have been stopped */ 661 iwl_wake_queue(trans, txq); 662 } 663 664 /* 665 * iwl_pcie_txq_free - Deallocate DMA queue. 666 * @txq: Transmit queue to deallocate. 667 * 668 * Empty queue by removing and destroying all BD's. 669 * Free all buffers. 670 * 0-fill, but do not free "txq" descriptor structure. 671 */ 672 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 673 { 674 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 675 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 676 struct device *dev = trans->dev; 677 int i; 678 679 if (WARN_ON(!txq)) 680 return; 681 682 iwl_pcie_txq_unmap(trans, txq_id); 683 684 /* De-alloc array of command/tx buffers */ 685 if (txq_id == trans_pcie->cmd_queue) 686 for (i = 0; i < txq->n_window; i++) { 687 kzfree(txq->entries[i].cmd); 688 kzfree(txq->entries[i].free_buf); 689 } 690 691 /* De-alloc circular buffer of TFDs */ 692 if (txq->tfds) { 693 dma_free_coherent(dev, 694 trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX, 695 txq->tfds, txq->dma_addr); 696 txq->dma_addr = 0; 697 txq->tfds = NULL; 698 699 dma_free_coherent(dev, 700 sizeof(*txq->first_tb_bufs) * txq->n_window, 701 txq->first_tb_bufs, txq->first_tb_dma); 702 } 703 704 kfree(txq->entries); 705 txq->entries = NULL; 706 707 del_timer_sync(&txq->stuck_timer); 708 709 /* 0-fill queue descriptor structure */ 710 memset(txq, 0, sizeof(*txq)); 711 } 712 713 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 714 { 715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 716 int nq = trans->cfg->base_params->num_of_queues; 717 int chan; 718 u32 reg_val; 719 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 720 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 721 722 /* make sure all queue are not stopped/used */ 723 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 724 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 725 726 trans_pcie->scd_base_addr = 727 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 728 729 WARN_ON(scd_base_addr != 0 && 730 scd_base_addr != trans_pcie->scd_base_addr); 731 732 /* reset context data, TX status and translation data */ 733 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 734 SCD_CONTEXT_MEM_LOWER_BOUND, 735 NULL, clear_dwords); 736 737 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 738 trans_pcie->scd_bc_tbls.dma >> 10); 739 740 /* The chain extension of the SCD doesn't work well. This feature is 741 * enabled by default by the HW, so we need to disable it manually. 742 */ 743 if (trans->cfg->base_params->scd_chain_ext_wa) 744 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 745 746 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 747 trans_pcie->cmd_fifo, 748 trans_pcie->cmd_q_wdg_timeout); 749 750 /* Activate all Tx DMA/FIFO channels */ 751 iwl_scd_activate_fifos(trans); 752 753 /* Enable DMA channel */ 754 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 755 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 756 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 757 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 758 759 /* Update FH chicken bits */ 760 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 761 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 762 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 763 764 /* Enable L1-Active */ 765 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 766 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 767 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 768 } 769 770 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 771 { 772 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 773 int txq_id; 774 775 /* 776 * we should never get here in gen2 trans mode return early to avoid 777 * having invalid accesses 778 */ 779 if (WARN_ON_ONCE(trans->cfg->gen2)) 780 return; 781 782 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 783 txq_id++) { 784 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 785 if (trans->cfg->use_tfh) 786 iwl_write_direct64(trans, 787 FH_MEM_CBBC_QUEUE(trans, txq_id), 788 txq->dma_addr); 789 else 790 iwl_write_direct32(trans, 791 FH_MEM_CBBC_QUEUE(trans, txq_id), 792 txq->dma_addr >> 8); 793 iwl_pcie_txq_unmap(trans, txq_id); 794 txq->read_ptr = 0; 795 txq->write_ptr = 0; 796 } 797 798 /* Tell NIC where to find the "keep warm" buffer */ 799 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 800 trans_pcie->kw.dma >> 4); 801 802 /* 803 * Send 0 as the scd_base_addr since the device may have be reset 804 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 805 * contain garbage. 806 */ 807 iwl_pcie_tx_start(trans, 0); 808 } 809 810 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 811 { 812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 813 unsigned long flags; 814 int ch, ret; 815 u32 mask = 0; 816 817 spin_lock(&trans_pcie->irq_lock); 818 819 if (!iwl_trans_grab_nic_access(trans, &flags)) 820 goto out; 821 822 /* Stop each Tx DMA channel */ 823 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 824 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 825 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 826 } 827 828 /* Wait for DMA channels to be idle */ 829 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 830 if (ret < 0) 831 IWL_ERR(trans, 832 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 833 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 834 835 iwl_trans_release_nic_access(trans, &flags); 836 837 out: 838 spin_unlock(&trans_pcie->irq_lock); 839 } 840 841 /* 842 * iwl_pcie_tx_stop - Stop all Tx DMA channels 843 */ 844 int iwl_pcie_tx_stop(struct iwl_trans *trans) 845 { 846 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 847 int txq_id; 848 849 /* Turn off all Tx DMA fifos */ 850 iwl_scd_deactivate_fifos(trans); 851 852 /* Turn off all Tx DMA channels */ 853 iwl_pcie_tx_stop_fh(trans); 854 855 /* 856 * This function can be called before the op_mode disabled the 857 * queues. This happens when we have an rfkill interrupt. 858 * Since we stop Tx altogether - mark the queues as stopped. 859 */ 860 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 861 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 862 863 /* This can happen: start_hw, stop_device */ 864 if (!trans_pcie->txq_memory) 865 return 0; 866 867 /* Unmap DMA from host system and free skb's */ 868 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 869 txq_id++) 870 iwl_pcie_txq_unmap(trans, txq_id); 871 872 return 0; 873 } 874 875 /* 876 * iwl_trans_tx_free - Free TXQ Context 877 * 878 * Destroy all TX DMA queues and structures 879 */ 880 void iwl_pcie_tx_free(struct iwl_trans *trans) 881 { 882 int txq_id; 883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 884 885 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 886 887 /* Tx queues */ 888 if (trans_pcie->txq_memory) { 889 for (txq_id = 0; 890 txq_id < trans->cfg->base_params->num_of_queues; 891 txq_id++) { 892 iwl_pcie_txq_free(trans, txq_id); 893 trans_pcie->txq[txq_id] = NULL; 894 } 895 } 896 897 kfree(trans_pcie->txq_memory); 898 trans_pcie->txq_memory = NULL; 899 900 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 901 902 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 903 } 904 905 /* 906 * iwl_pcie_tx_alloc - allocate TX context 907 * Allocate all Tx DMA structures and initialize them 908 */ 909 static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 910 { 911 int ret; 912 int txq_id, slots_num; 913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 914 915 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 916 sizeof(struct iwlagn_scd_bc_tbl); 917 918 /*It is not allowed to alloc twice, so warn when this happens. 919 * We cannot rely on the previous allocation, so free and fail */ 920 if (WARN_ON(trans_pcie->txq_memory)) { 921 ret = -EINVAL; 922 goto error; 923 } 924 925 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 926 scd_bc_tbls_size); 927 if (ret) { 928 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 929 goto error; 930 } 931 932 /* Alloc keep-warm buffer */ 933 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 934 if (ret) { 935 IWL_ERR(trans, "Keep Warm allocation failed\n"); 936 goto error; 937 } 938 939 trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 940 sizeof(struct iwl_txq), GFP_KERNEL); 941 if (!trans_pcie->txq_memory) { 942 IWL_ERR(trans, "Not enough memory for txq\n"); 943 ret = -ENOMEM; 944 goto error; 945 } 946 947 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 948 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 949 txq_id++) { 950 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 951 952 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 953 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 954 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 955 slots_num, cmd_queue); 956 if (ret) { 957 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 958 goto error; 959 } 960 trans_pcie->txq[txq_id]->id = txq_id; 961 } 962 963 return 0; 964 965 error: 966 iwl_pcie_tx_free(trans); 967 968 return ret; 969 } 970 971 int iwl_pcie_tx_init(struct iwl_trans *trans) 972 { 973 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 974 int ret; 975 int txq_id, slots_num; 976 bool alloc = false; 977 978 if (!trans_pcie->txq_memory) { 979 ret = iwl_pcie_tx_alloc(trans); 980 if (ret) 981 goto error; 982 alloc = true; 983 } 984 985 spin_lock(&trans_pcie->irq_lock); 986 987 /* Turn off all Tx DMA fifos */ 988 iwl_scd_deactivate_fifos(trans); 989 990 /* Tell NIC where to find the "keep warm" buffer */ 991 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 992 trans_pcie->kw.dma >> 4); 993 994 spin_unlock(&trans_pcie->irq_lock); 995 996 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 997 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 998 txq_id++) { 999 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1000 1001 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1002 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1003 slots_num, cmd_queue); 1004 if (ret) { 1005 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1006 goto error; 1007 } 1008 1009 /* 1010 * Tell nic where to find circular buffer of TFDs for a 1011 * given Tx queue, and enable the DMA channel used for that 1012 * queue. 1013 * Circular buffer (TFD queue in DRAM) physical base address 1014 */ 1015 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1016 trans_pcie->txq[txq_id]->dma_addr >> 8); 1017 } 1018 1019 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1020 if (trans->cfg->base_params->num_of_queues > 20) 1021 iwl_set_bits_prph(trans, SCD_GP_CTRL, 1022 SCD_GP_CTRL_ENABLE_31_QUEUES); 1023 1024 return 0; 1025 error: 1026 /*Upon error, free only if we allocated something */ 1027 if (alloc) 1028 iwl_pcie_tx_free(trans); 1029 return ret; 1030 } 1031 1032 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1033 { 1034 lockdep_assert_held(&txq->lock); 1035 1036 if (!txq->wd_timeout) 1037 return; 1038 1039 /* 1040 * station is asleep and we send data - that must 1041 * be uAPSD or PS-Poll. Don't rearm the timer. 1042 */ 1043 if (txq->frozen) 1044 return; 1045 1046 /* 1047 * if empty delete timer, otherwise move timer forward 1048 * since we're making progress on this queue 1049 */ 1050 if (txq->read_ptr == txq->write_ptr) 1051 del_timer(&txq->stuck_timer); 1052 else 1053 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1054 } 1055 1056 /* Frees buffers until index _not_ inclusive */ 1057 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1058 struct sk_buff_head *skbs) 1059 { 1060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1061 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1062 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 1063 int last_to_free; 1064 1065 /* This function is not meant to release cmd queue*/ 1066 if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1067 return; 1068 1069 spin_lock_bh(&txq->lock); 1070 1071 if (!test_bit(txq_id, trans_pcie->queue_used)) { 1072 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1073 txq_id, ssn); 1074 goto out; 1075 } 1076 1077 if (txq->read_ptr == tfd_num) 1078 goto out; 1079 1080 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1081 txq_id, txq->read_ptr, tfd_num, ssn); 1082 1083 /*Since we free until index _not_ inclusive, the one before index is 1084 * the last we will free. This one must be used */ 1085 last_to_free = iwl_queue_dec_wrap(tfd_num); 1086 1087 if (!iwl_queue_used(txq, last_to_free)) { 1088 IWL_ERR(trans, 1089 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1090 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 1091 txq->write_ptr, txq->read_ptr); 1092 goto out; 1093 } 1094 1095 if (WARN_ON(!skb_queue_empty(skbs))) 1096 goto out; 1097 1098 for (; 1099 txq->read_ptr != tfd_num; 1100 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { 1101 struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 1102 1103 if (WARN_ON_ONCE(!skb)) 1104 continue; 1105 1106 iwl_pcie_free_tso_page(trans_pcie, skb); 1107 1108 __skb_queue_tail(skbs, skb); 1109 1110 txq->entries[txq->read_ptr].skb = NULL; 1111 1112 if (!trans->cfg->use_tfh) 1113 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1114 1115 iwl_pcie_txq_free_tfd(trans, txq); 1116 } 1117 1118 iwl_pcie_txq_progress(txq); 1119 1120 if (iwl_queue_space(txq) > txq->low_mark && 1121 test_bit(txq_id, trans_pcie->queue_stopped)) { 1122 struct sk_buff_head overflow_skbs; 1123 1124 __skb_queue_head_init(&overflow_skbs); 1125 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 1126 1127 /* 1128 * This is tricky: we are in reclaim path which is non 1129 * re-entrant, so noone will try to take the access the 1130 * txq data from that path. We stopped tx, so we can't 1131 * have tx as well. Bottom line, we can unlock and re-lock 1132 * later. 1133 */ 1134 spin_unlock_bh(&txq->lock); 1135 1136 while (!skb_queue_empty(&overflow_skbs)) { 1137 struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 1138 struct iwl_device_cmd *dev_cmd_ptr; 1139 1140 dev_cmd_ptr = *(void **)((u8 *)skb->cb + 1141 trans_pcie->dev_cmd_offs); 1142 1143 /* 1144 * Note that we can very well be overflowing again. 1145 * In that case, iwl_queue_space will be small again 1146 * and we won't wake mac80211's queue. 1147 */ 1148 iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); 1149 } 1150 spin_lock_bh(&txq->lock); 1151 1152 if (iwl_queue_space(txq) > txq->low_mark) 1153 iwl_wake_queue(trans, txq); 1154 } 1155 1156 if (txq->read_ptr == txq->write_ptr) { 1157 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); 1158 iwl_trans_unref(trans); 1159 } 1160 1161 out: 1162 spin_unlock_bh(&txq->lock); 1163 } 1164 1165 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1166 const struct iwl_host_cmd *cmd) 1167 { 1168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1169 int ret; 1170 1171 lockdep_assert_held(&trans_pcie->reg_lock); 1172 1173 if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1174 !trans_pcie->ref_cmd_in_flight) { 1175 trans_pcie->ref_cmd_in_flight = true; 1176 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1177 iwl_trans_ref(trans); 1178 } 1179 1180 /* 1181 * wake up the NIC to make sure that the firmware will see the host 1182 * command - we will let the NIC sleep once all the host commands 1183 * returned. This needs to be done only on NICs that have 1184 * apmg_wake_up_wa set. 1185 */ 1186 if (trans->cfg->base_params->apmg_wake_up_wa && 1187 !trans_pcie->cmd_hold_nic_awake) { 1188 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1189 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1190 1191 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1192 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1193 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1194 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1195 15000); 1196 if (ret < 0) { 1197 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1198 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1199 IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1200 return -EIO; 1201 } 1202 trans_pcie->cmd_hold_nic_awake = true; 1203 } 1204 1205 return 0; 1206 } 1207 1208 /* 1209 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1210 * 1211 * When FW advances 'R' index, all entries between old and new 'R' index 1212 * need to be reclaimed. As result, some free space forms. If there is 1213 * enough free space (> low mark), wake the stack that feeds us. 1214 */ 1215 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1216 { 1217 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1218 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1219 unsigned long flags; 1220 int nfreed = 0; 1221 1222 lockdep_assert_held(&txq->lock); 1223 1224 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) { 1225 IWL_ERR(trans, 1226 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1227 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1228 txq->write_ptr, txq->read_ptr); 1229 return; 1230 } 1231 1232 for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx; 1233 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { 1234 1235 if (nfreed++ > 0) { 1236 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1237 idx, txq->write_ptr, txq->read_ptr); 1238 iwl_force_nmi(trans); 1239 } 1240 } 1241 1242 if (txq->read_ptr == txq->write_ptr) { 1243 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1244 iwl_pcie_clear_cmd_in_flight(trans); 1245 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1246 } 1247 1248 iwl_pcie_txq_progress(txq); 1249 } 1250 1251 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1252 u16 txq_id) 1253 { 1254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1255 u32 tbl_dw_addr; 1256 u32 tbl_dw; 1257 u16 scd_q2ratid; 1258 1259 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1260 1261 tbl_dw_addr = trans_pcie->scd_base_addr + 1262 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1263 1264 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1265 1266 if (txq_id & 0x1) 1267 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1268 else 1269 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1270 1271 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1272 1273 return 0; 1274 } 1275 1276 /* Receiver address (actually, Rx station's index into station table), 1277 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1278 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1279 1280 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1281 const struct iwl_trans_txq_scd_cfg *cfg, 1282 unsigned int wdg_timeout) 1283 { 1284 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1285 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1286 int fifo = -1; 1287 bool scd_bug = false; 1288 1289 if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1290 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1291 1292 txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1293 1294 if (cfg) { 1295 fifo = cfg->fifo; 1296 1297 /* Disable the scheduler prior configuring the cmd queue */ 1298 if (txq_id == trans_pcie->cmd_queue && 1299 trans_pcie->scd_set_active) 1300 iwl_scd_enable_set_active(trans, 0); 1301 1302 /* Stop this Tx queue before configuring it */ 1303 iwl_scd_txq_set_inactive(trans, txq_id); 1304 1305 /* Set this queue as a chain-building queue unless it is CMD */ 1306 if (txq_id != trans_pcie->cmd_queue) 1307 iwl_scd_txq_set_chain(trans, txq_id); 1308 1309 if (cfg->aggregate) { 1310 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1311 1312 /* Map receiver-address / traffic-ID to this queue */ 1313 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1314 1315 /* enable aggregations for the queue */ 1316 iwl_scd_txq_enable_agg(trans, txq_id); 1317 txq->ampdu = true; 1318 } else { 1319 /* 1320 * disable aggregations for the queue, this will also 1321 * make the ra_tid mapping configuration irrelevant 1322 * since it is now a non-AGG queue. 1323 */ 1324 iwl_scd_txq_disable_agg(trans, txq_id); 1325 1326 ssn = txq->read_ptr; 1327 } 1328 } else { 1329 /* 1330 * If we need to move the SCD write pointer by steps of 1331 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1332 * the op_mode know by returning true later. 1333 * Do this only in case cfg is NULL since this trick can 1334 * be done only if we have DQA enabled which is true for mvm 1335 * only. And mvm never sets a cfg pointer. 1336 * This is really ugly, but this is the easiest way out for 1337 * this sad hardware issue. 1338 * This bug has been fixed on devices 9000 and up. 1339 */ 1340 scd_bug = !trans->cfg->mq_rx_supported && 1341 !((ssn - txq->write_ptr) & 0x3f) && 1342 (ssn != txq->write_ptr); 1343 if (scd_bug) 1344 ssn++; 1345 } 1346 1347 /* Place first TFD at index corresponding to start sequence number. 1348 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1349 txq->read_ptr = (ssn & 0xff); 1350 txq->write_ptr = (ssn & 0xff); 1351 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1352 (ssn & 0xff) | (txq_id << 8)); 1353 1354 if (cfg) { 1355 u8 frame_limit = cfg->frame_limit; 1356 1357 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1358 1359 /* Set up Tx window size and frame limit for this queue */ 1360 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1361 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1362 iwl_trans_write_mem32(trans, 1363 trans_pcie->scd_base_addr + 1364 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1365 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1366 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1367 1368 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1369 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1370 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1371 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1372 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1373 SCD_QUEUE_STTS_REG_MSK); 1374 1375 /* enable the scheduler for this queue (only) */ 1376 if (txq_id == trans_pcie->cmd_queue && 1377 trans_pcie->scd_set_active) 1378 iwl_scd_enable_set_active(trans, BIT(txq_id)); 1379 1380 IWL_DEBUG_TX_QUEUES(trans, 1381 "Activate queue %d on FIFO %d WrPtr: %d\n", 1382 txq_id, fifo, ssn & 0xff); 1383 } else { 1384 IWL_DEBUG_TX_QUEUES(trans, 1385 "Activate queue %d WrPtr: %d\n", 1386 txq_id, ssn & 0xff); 1387 } 1388 1389 return scd_bug; 1390 } 1391 1392 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 1393 bool shared_mode) 1394 { 1395 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1396 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1397 1398 txq->ampdu = !shared_mode; 1399 } 1400 1401 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1402 bool configure_scd) 1403 { 1404 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1405 u32 stts_addr = trans_pcie->scd_base_addr + 1406 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1407 static const u32 zero_val[4] = {}; 1408 1409 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1410 trans_pcie->txq[txq_id]->frozen = false; 1411 1412 /* 1413 * Upon HW Rfkill - we stop the device, and then stop the queues 1414 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1415 * allow the op_mode to call txq_disable after it already called 1416 * stop_device. 1417 */ 1418 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1419 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1420 "queue %d not used", txq_id); 1421 return; 1422 } 1423 1424 if (configure_scd) { 1425 iwl_scd_txq_set_inactive(trans, txq_id); 1426 1427 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1428 ARRAY_SIZE(zero_val)); 1429 } 1430 1431 iwl_pcie_txq_unmap(trans, txq_id); 1432 trans_pcie->txq[txq_id]->ampdu = false; 1433 1434 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1435 } 1436 1437 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1438 1439 /* 1440 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1441 * @priv: device private data point 1442 * @cmd: a pointer to the ucode command structure 1443 * 1444 * The function returns < 0 values to indicate the operation 1445 * failed. On success, it returns the index (>= 0) of command in the 1446 * command queue. 1447 */ 1448 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1449 struct iwl_host_cmd *cmd) 1450 { 1451 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1452 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1453 struct iwl_device_cmd *out_cmd; 1454 struct iwl_cmd_meta *out_meta; 1455 unsigned long flags; 1456 void *dup_buf = NULL; 1457 dma_addr_t phys_addr; 1458 int idx; 1459 u16 copy_size, cmd_size, tb0_size; 1460 bool had_nocopy = false; 1461 u8 group_id = iwl_cmd_groupid(cmd->id); 1462 int i, ret; 1463 u32 cmd_pos; 1464 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1465 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1466 1467 if (WARN(!trans->wide_cmd_header && 1468 group_id > IWL_ALWAYS_LONG_GROUP, 1469 "unsupported wide command %#x\n", cmd->id)) 1470 return -EINVAL; 1471 1472 if (group_id != 0) { 1473 copy_size = sizeof(struct iwl_cmd_header_wide); 1474 cmd_size = sizeof(struct iwl_cmd_header_wide); 1475 } else { 1476 copy_size = sizeof(struct iwl_cmd_header); 1477 cmd_size = sizeof(struct iwl_cmd_header); 1478 } 1479 1480 /* need one for the header if the first is NOCOPY */ 1481 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1482 1483 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1484 cmddata[i] = cmd->data[i]; 1485 cmdlen[i] = cmd->len[i]; 1486 1487 if (!cmd->len[i]) 1488 continue; 1489 1490 /* need at least IWL_FIRST_TB_SIZE copied */ 1491 if (copy_size < IWL_FIRST_TB_SIZE) { 1492 int copy = IWL_FIRST_TB_SIZE - copy_size; 1493 1494 if (copy > cmdlen[i]) 1495 copy = cmdlen[i]; 1496 cmdlen[i] -= copy; 1497 cmddata[i] += copy; 1498 copy_size += copy; 1499 } 1500 1501 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1502 had_nocopy = true; 1503 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1504 idx = -EINVAL; 1505 goto free_dup_buf; 1506 } 1507 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1508 /* 1509 * This is also a chunk that isn't copied 1510 * to the static buffer so set had_nocopy. 1511 */ 1512 had_nocopy = true; 1513 1514 /* only allowed once */ 1515 if (WARN_ON(dup_buf)) { 1516 idx = -EINVAL; 1517 goto free_dup_buf; 1518 } 1519 1520 dup_buf = kmemdup(cmddata[i], cmdlen[i], 1521 GFP_ATOMIC); 1522 if (!dup_buf) 1523 return -ENOMEM; 1524 } else { 1525 /* NOCOPY must not be followed by normal! */ 1526 if (WARN_ON(had_nocopy)) { 1527 idx = -EINVAL; 1528 goto free_dup_buf; 1529 } 1530 copy_size += cmdlen[i]; 1531 } 1532 cmd_size += cmd->len[i]; 1533 } 1534 1535 /* 1536 * If any of the command structures end up being larger than 1537 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1538 * allocated into separate TFDs, then we will need to 1539 * increase the size of the buffers. 1540 */ 1541 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1542 "Command %s (%#x) is too large (%d bytes)\n", 1543 iwl_get_cmd_string(trans, cmd->id), 1544 cmd->id, copy_size)) { 1545 idx = -EINVAL; 1546 goto free_dup_buf; 1547 } 1548 1549 spin_lock_bh(&txq->lock); 1550 1551 if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1552 spin_unlock_bh(&txq->lock); 1553 1554 IWL_ERR(trans, "No space in command queue\n"); 1555 iwl_op_mode_cmd_queue_full(trans->op_mode); 1556 idx = -ENOSPC; 1557 goto free_dup_buf; 1558 } 1559 1560 idx = get_cmd_index(txq, txq->write_ptr); 1561 out_cmd = txq->entries[idx].cmd; 1562 out_meta = &txq->entries[idx].meta; 1563 1564 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1565 if (cmd->flags & CMD_WANT_SKB) 1566 out_meta->source = cmd; 1567 1568 /* set up the header */ 1569 if (group_id != 0) { 1570 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1571 out_cmd->hdr_wide.group_id = group_id; 1572 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1573 out_cmd->hdr_wide.length = 1574 cpu_to_le16(cmd_size - 1575 sizeof(struct iwl_cmd_header_wide)); 1576 out_cmd->hdr_wide.reserved = 0; 1577 out_cmd->hdr_wide.sequence = 1578 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1579 INDEX_TO_SEQ(txq->write_ptr)); 1580 1581 cmd_pos = sizeof(struct iwl_cmd_header_wide); 1582 copy_size = sizeof(struct iwl_cmd_header_wide); 1583 } else { 1584 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1585 out_cmd->hdr.sequence = 1586 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1587 INDEX_TO_SEQ(txq->write_ptr)); 1588 out_cmd->hdr.group_id = 0; 1589 1590 cmd_pos = sizeof(struct iwl_cmd_header); 1591 copy_size = sizeof(struct iwl_cmd_header); 1592 } 1593 1594 /* and copy the data that needs to be copied */ 1595 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1596 int copy; 1597 1598 if (!cmd->len[i]) 1599 continue; 1600 1601 /* copy everything if not nocopy/dup */ 1602 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1603 IWL_HCMD_DFL_DUP))) { 1604 copy = cmd->len[i]; 1605 1606 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1607 cmd_pos += copy; 1608 copy_size += copy; 1609 continue; 1610 } 1611 1612 /* 1613 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 1614 * in total (for bi-directional DMA), but copy up to what 1615 * we can fit into the payload for debug dump purposes. 1616 */ 1617 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1618 1619 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1620 cmd_pos += copy; 1621 1622 /* However, treat copy_size the proper way, we need it below */ 1623 if (copy_size < IWL_FIRST_TB_SIZE) { 1624 copy = IWL_FIRST_TB_SIZE - copy_size; 1625 1626 if (copy > cmd->len[i]) 1627 copy = cmd->len[i]; 1628 copy_size += copy; 1629 } 1630 } 1631 1632 IWL_DEBUG_HC(trans, 1633 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1634 iwl_get_cmd_string(trans, cmd->id), 1635 group_id, out_cmd->hdr.cmd, 1636 le16_to_cpu(out_cmd->hdr.sequence), 1637 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1638 1639 /* start the TFD with the minimum copy bytes */ 1640 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 1641 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1642 iwl_pcie_txq_build_tfd(trans, txq, 1643 iwl_pcie_get_first_tb_dma(txq, idx), 1644 tb0_size, true); 1645 1646 /* map first command fragment, if any remains */ 1647 if (copy_size > tb0_size) { 1648 phys_addr = dma_map_single(trans->dev, 1649 ((u8 *)&out_cmd->hdr) + tb0_size, 1650 copy_size - tb0_size, 1651 DMA_TO_DEVICE); 1652 if (dma_mapping_error(trans->dev, phys_addr)) { 1653 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1654 txq->write_ptr); 1655 idx = -ENOMEM; 1656 goto out; 1657 } 1658 1659 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1660 copy_size - tb0_size, false); 1661 } 1662 1663 /* map the remaining (adjusted) nocopy/dup fragments */ 1664 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1665 const void *data = cmddata[i]; 1666 1667 if (!cmdlen[i]) 1668 continue; 1669 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1670 IWL_HCMD_DFL_DUP))) 1671 continue; 1672 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1673 data = dup_buf; 1674 phys_addr = dma_map_single(trans->dev, (void *)data, 1675 cmdlen[i], DMA_TO_DEVICE); 1676 if (dma_mapping_error(trans->dev, phys_addr)) { 1677 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1678 txq->write_ptr); 1679 idx = -ENOMEM; 1680 goto out; 1681 } 1682 1683 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1684 } 1685 1686 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1687 out_meta->flags = cmd->flags; 1688 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1689 kzfree(txq->entries[idx].free_buf); 1690 txq->entries[idx].free_buf = dup_buf; 1691 1692 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1693 1694 /* start timer if queue currently empty */ 1695 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1696 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1697 1698 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1699 ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1700 if (ret < 0) { 1701 idx = ret; 1702 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1703 goto out; 1704 } 1705 1706 /* Increment and update queue's write index */ 1707 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 1708 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1709 1710 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1711 1712 out: 1713 spin_unlock_bh(&txq->lock); 1714 free_dup_buf: 1715 if (idx < 0) 1716 kfree(dup_buf); 1717 return idx; 1718 } 1719 1720 /* 1721 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1722 * @rxb: Rx buffer to reclaim 1723 */ 1724 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1725 struct iwl_rx_cmd_buffer *rxb) 1726 { 1727 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1728 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1729 u8 group_id; 1730 u32 cmd_id; 1731 int txq_id = SEQ_TO_QUEUE(sequence); 1732 int index = SEQ_TO_INDEX(sequence); 1733 int cmd_index; 1734 struct iwl_device_cmd *cmd; 1735 struct iwl_cmd_meta *meta; 1736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1737 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1738 1739 /* If a Tx command is being handled and it isn't in the actual 1740 * command queue then there a command routing bug has been introduced 1741 * in the queue management code. */ 1742 if (WARN(txq_id != trans_pcie->cmd_queue, 1743 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1744 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1745 txq->write_ptr)) { 1746 iwl_print_hex_error(trans, pkt, 32); 1747 return; 1748 } 1749 1750 spin_lock_bh(&txq->lock); 1751 1752 cmd_index = get_cmd_index(txq, index); 1753 cmd = txq->entries[cmd_index].cmd; 1754 meta = &txq->entries[cmd_index].meta; 1755 group_id = cmd->hdr.group_id; 1756 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1757 1758 iwl_pcie_tfd_unmap(trans, meta, txq, index); 1759 1760 /* Input error checking is done when commands are added to queue. */ 1761 if (meta->flags & CMD_WANT_SKB) { 1762 struct page *p = rxb_steal_page(rxb); 1763 1764 meta->source->resp_pkt = pkt; 1765 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1766 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1767 } 1768 1769 if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1770 iwl_op_mode_async_cb(trans->op_mode, cmd); 1771 1772 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1773 1774 if (!(meta->flags & CMD_ASYNC)) { 1775 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1776 IWL_WARN(trans, 1777 "HCMD_ACTIVE already clear for command %s\n", 1778 iwl_get_cmd_string(trans, cmd_id)); 1779 } 1780 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1781 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1782 iwl_get_cmd_string(trans, cmd_id)); 1783 wake_up(&trans_pcie->wait_command_queue); 1784 } 1785 1786 if (meta->flags & CMD_MAKE_TRANS_IDLE) { 1787 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 1788 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1789 set_bit(STATUS_TRANS_IDLE, &trans->status); 1790 wake_up(&trans_pcie->d0i3_waitq); 1791 } 1792 1793 if (meta->flags & CMD_WAKE_UP_TRANS) { 1794 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 1795 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1796 clear_bit(STATUS_TRANS_IDLE, &trans->status); 1797 wake_up(&trans_pcie->d0i3_waitq); 1798 } 1799 1800 meta->flags = 0; 1801 1802 spin_unlock_bh(&txq->lock); 1803 } 1804 1805 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1806 1807 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1808 struct iwl_host_cmd *cmd) 1809 { 1810 int ret; 1811 1812 /* An asynchronous command can not expect an SKB to be set. */ 1813 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1814 return -EINVAL; 1815 1816 ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1817 if (ret < 0) { 1818 IWL_ERR(trans, 1819 "Error sending %s: enqueue_hcmd failed: %d\n", 1820 iwl_get_cmd_string(trans, cmd->id), ret); 1821 return ret; 1822 } 1823 return 0; 1824 } 1825 1826 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1827 struct iwl_host_cmd *cmd) 1828 { 1829 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1830 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1831 int cmd_idx; 1832 int ret; 1833 1834 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 1835 iwl_get_cmd_string(trans, cmd->id)); 1836 1837 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1838 &trans->status), 1839 "Command %s: a command is already active!\n", 1840 iwl_get_cmd_string(trans, cmd->id))) 1841 return -EIO; 1842 1843 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 1844 iwl_get_cmd_string(trans, cmd->id)); 1845 1846 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 1847 ret = wait_event_timeout(trans_pcie->d0i3_waitq, 1848 pm_runtime_active(&trans_pcie->pci_dev->dev), 1849 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 1850 if (!ret) { 1851 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 1852 return -ETIMEDOUT; 1853 } 1854 } 1855 1856 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1857 if (cmd_idx < 0) { 1858 ret = cmd_idx; 1859 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1860 IWL_ERR(trans, 1861 "Error sending %s: enqueue_hcmd failed: %d\n", 1862 iwl_get_cmd_string(trans, cmd->id), ret); 1863 return ret; 1864 } 1865 1866 ret = wait_event_timeout(trans_pcie->wait_command_queue, 1867 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1868 &trans->status), 1869 HOST_COMPLETE_TIMEOUT); 1870 if (!ret) { 1871 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 1872 iwl_get_cmd_string(trans, cmd->id), 1873 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1874 1875 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1876 txq->read_ptr, txq->write_ptr); 1877 1878 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1879 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1880 iwl_get_cmd_string(trans, cmd->id)); 1881 ret = -ETIMEDOUT; 1882 1883 iwl_force_nmi(trans); 1884 iwl_trans_fw_error(trans); 1885 1886 goto cancel; 1887 } 1888 1889 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1890 IWL_ERR(trans, "FW error in SYNC CMD %s\n", 1891 iwl_get_cmd_string(trans, cmd->id)); 1892 dump_stack(); 1893 ret = -EIO; 1894 goto cancel; 1895 } 1896 1897 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1898 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1899 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1900 ret = -ERFKILL; 1901 goto cancel; 1902 } 1903 1904 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1905 IWL_ERR(trans, "Error: Response NULL in '%s'\n", 1906 iwl_get_cmd_string(trans, cmd->id)); 1907 ret = -EIO; 1908 goto cancel; 1909 } 1910 1911 return 0; 1912 1913 cancel: 1914 if (cmd->flags & CMD_WANT_SKB) { 1915 /* 1916 * Cancel the CMD_WANT_SKB flag for the cmd in the 1917 * TX cmd queue. Otherwise in case the cmd comes 1918 * in later, it will possibly set an invalid 1919 * address (cmd->meta.source). 1920 */ 1921 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1922 } 1923 1924 if (cmd->resp_pkt) { 1925 iwl_free_resp(cmd); 1926 cmd->resp_pkt = NULL; 1927 } 1928 1929 return ret; 1930 } 1931 1932 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1933 { 1934 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1935 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1936 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1937 cmd->id); 1938 return -ERFKILL; 1939 } 1940 1941 if (cmd->flags & CMD_ASYNC) 1942 return iwl_pcie_send_hcmd_async(trans, cmd); 1943 1944 /* We still can fail on RFKILL that can be asserted while we wait */ 1945 return iwl_pcie_send_hcmd_sync(trans, cmd); 1946 } 1947 1948 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 1949 struct iwl_txq *txq, u8 hdr_len, 1950 struct iwl_cmd_meta *out_meta, 1951 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 1952 { 1953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1954 u16 tb2_len; 1955 int i; 1956 1957 /* 1958 * Set up TFD's third entry to point directly to remainder 1959 * of skb's head, if any 1960 */ 1961 tb2_len = skb_headlen(skb) - hdr_len; 1962 1963 if (tb2_len > 0) { 1964 dma_addr_t tb2_phys = dma_map_single(trans->dev, 1965 skb->data + hdr_len, 1966 tb2_len, DMA_TO_DEVICE); 1967 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 1968 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1969 txq->write_ptr); 1970 return -EINVAL; 1971 } 1972 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 1973 } 1974 1975 /* set up the remaining entries to point to the data */ 1976 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1977 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1978 dma_addr_t tb_phys; 1979 int tb_idx; 1980 1981 if (!skb_frag_size(frag)) 1982 continue; 1983 1984 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 1985 skb_frag_size(frag), DMA_TO_DEVICE); 1986 1987 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 1988 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1989 txq->write_ptr); 1990 return -EINVAL; 1991 } 1992 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 1993 skb_frag_size(frag), false); 1994 1995 out_meta->tbs |= BIT(tb_idx); 1996 } 1997 1998 trace_iwlwifi_dev_tx(trans->dev, skb, 1999 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), 2000 trans_pcie->tfd_size, 2001 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2002 hdr_len); 2003 trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len); 2004 return 0; 2005 } 2006 2007 #ifdef CONFIG_INET 2008 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 2009 { 2010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2011 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 2012 2013 if (!p->page) 2014 goto alloc; 2015 2016 /* enough room on this page */ 2017 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 2018 return p; 2019 2020 /* We don't have enough room on this page, get a new one. */ 2021 __free_page(p->page); 2022 2023 alloc: 2024 p->page = alloc_page(GFP_ATOMIC); 2025 if (!p->page) 2026 return NULL; 2027 p->pos = page_address(p->page); 2028 return p; 2029 } 2030 2031 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 2032 bool ipv6, unsigned int len) 2033 { 2034 if (ipv6) { 2035 struct ipv6hdr *iphv6 = iph; 2036 2037 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 2038 len + tcph->doff * 4, 2039 IPPROTO_TCP, 0); 2040 } else { 2041 struct iphdr *iphv4 = iph; 2042 2043 ip_send_check(iphv4); 2044 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 2045 len + tcph->doff * 4, 2046 IPPROTO_TCP, 0); 2047 } 2048 } 2049 2050 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2051 struct iwl_txq *txq, u8 hdr_len, 2052 struct iwl_cmd_meta *out_meta, 2053 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2054 { 2055 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 2056 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 2057 struct ieee80211_hdr *hdr = (void *)skb->data; 2058 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 2059 unsigned int mss = skb_shinfo(skb)->gso_size; 2060 u16 length, iv_len, amsdu_pad; 2061 u8 *start_hdr; 2062 struct iwl_tso_hdr_page *hdr_page; 2063 struct page **page_ptr; 2064 int ret; 2065 struct tso_t tso; 2066 2067 /* if the packet is protected, then it must be CCMP or GCMP */ 2068 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 2069 iv_len = ieee80211_has_protected(hdr->frame_control) ? 2070 IEEE80211_CCMP_HDR_LEN : 0; 2071 2072 trace_iwlwifi_dev_tx(trans->dev, skb, 2073 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), 2074 trans_pcie->tfd_size, 2075 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 2076 2077 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 2078 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 2079 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 2080 amsdu_pad = 0; 2081 2082 /* total amount of header we may need for this A-MSDU */ 2083 hdr_room = DIV_ROUND_UP(total_len, mss) * 2084 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 2085 2086 /* Our device supports 9 segments at most, it will fit in 1 page */ 2087 hdr_page = get_page_hdr(trans, hdr_room); 2088 if (!hdr_page) 2089 return -ENOMEM; 2090 2091 get_page(hdr_page->page); 2092 start_hdr = hdr_page->pos; 2093 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 2094 *page_ptr = hdr_page->page; 2095 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 2096 hdr_page->pos += iv_len; 2097 2098 /* 2099 * Pull the ieee80211 header + IV to be able to use TSO core, 2100 * we will restore it for the tx_status flow. 2101 */ 2102 skb_pull(skb, hdr_len + iv_len); 2103 2104 /* 2105 * Remove the length of all the headers that we don't actually 2106 * have in the MPDU by themselves, but that we duplicate into 2107 * all the different MSDUs inside the A-MSDU. 2108 */ 2109 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 2110 2111 tso_start(skb, &tso); 2112 2113 while (total_len) { 2114 /* this is the data left for this subframe */ 2115 unsigned int data_left = 2116 min_t(unsigned int, mss, total_len); 2117 struct sk_buff *csum_skb = NULL; 2118 unsigned int hdr_tb_len; 2119 dma_addr_t hdr_tb_phys; 2120 struct tcphdr *tcph; 2121 u8 *iph, *subf_hdrs_start = hdr_page->pos; 2122 2123 total_len -= data_left; 2124 2125 memset(hdr_page->pos, 0, amsdu_pad); 2126 hdr_page->pos += amsdu_pad; 2127 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 2128 data_left)) & 0x3; 2129 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 2130 hdr_page->pos += ETH_ALEN; 2131 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 2132 hdr_page->pos += ETH_ALEN; 2133 2134 length = snap_ip_tcp_hdrlen + data_left; 2135 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 2136 hdr_page->pos += sizeof(length); 2137 2138 /* 2139 * This will copy the SNAP as well which will be considered 2140 * as MAC header. 2141 */ 2142 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 2143 iph = hdr_page->pos + 8; 2144 tcph = (void *)(iph + ip_hdrlen); 2145 2146 /* For testing on current hardware only */ 2147 if (trans_pcie->sw_csum_tx) { 2148 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 2149 GFP_ATOMIC); 2150 if (!csum_skb) { 2151 ret = -ENOMEM; 2152 goto out_unmap; 2153 } 2154 2155 iwl_compute_pseudo_hdr_csum(iph, tcph, 2156 skb->protocol == 2157 htons(ETH_P_IPV6), 2158 data_left); 2159 2160 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2161 skb_reset_transport_header(csum_skb); 2162 csum_skb->csum_start = 2163 (unsigned char *)tcp_hdr(csum_skb) - 2164 csum_skb->head; 2165 } 2166 2167 hdr_page->pos += snap_ip_tcp_hdrlen; 2168 2169 hdr_tb_len = hdr_page->pos - start_hdr; 2170 hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 2171 hdr_tb_len, DMA_TO_DEVICE); 2172 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 2173 dev_kfree_skb(csum_skb); 2174 ret = -EINVAL; 2175 goto out_unmap; 2176 } 2177 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 2178 hdr_tb_len, false); 2179 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 2180 hdr_tb_len); 2181 /* add this subframe's headers' length to the tx_cmd */ 2182 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 2183 2184 /* prepare the start_hdr for the next subframe */ 2185 start_hdr = hdr_page->pos; 2186 2187 /* put the payload */ 2188 while (data_left) { 2189 unsigned int size = min_t(unsigned int, tso.size, 2190 data_left); 2191 dma_addr_t tb_phys; 2192 2193 if (trans_pcie->sw_csum_tx) 2194 skb_put_data(csum_skb, tso.data, size); 2195 2196 tb_phys = dma_map_single(trans->dev, tso.data, 2197 size, DMA_TO_DEVICE); 2198 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2199 dev_kfree_skb(csum_skb); 2200 ret = -EINVAL; 2201 goto out_unmap; 2202 } 2203 2204 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2205 size, false); 2206 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 2207 size); 2208 2209 data_left -= size; 2210 tso_build_data(skb, &tso, size); 2211 } 2212 2213 /* For testing on early hardware only */ 2214 if (trans_pcie->sw_csum_tx) { 2215 __wsum csum; 2216 2217 csum = skb_checksum(csum_skb, 2218 skb_checksum_start_offset(csum_skb), 2219 csum_skb->len - 2220 skb_checksum_start_offset(csum_skb), 2221 0); 2222 dev_kfree_skb(csum_skb); 2223 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 2224 hdr_tb_len, DMA_TO_DEVICE); 2225 tcph->check = csum_fold(csum); 2226 dma_sync_single_for_device(trans->dev, hdr_tb_phys, 2227 hdr_tb_len, DMA_TO_DEVICE); 2228 } 2229 } 2230 2231 /* re -add the WiFi header and IV */ 2232 skb_push(skb, hdr_len + iv_len); 2233 2234 return 0; 2235 2236 out_unmap: 2237 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 2238 return ret; 2239 } 2240 #else /* CONFIG_INET */ 2241 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2242 struct iwl_txq *txq, u8 hdr_len, 2243 struct iwl_cmd_meta *out_meta, 2244 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2245 { 2246 /* No A-MSDU without CONFIG_INET */ 2247 WARN_ON(1); 2248 2249 return -1; 2250 } 2251 #endif /* CONFIG_INET */ 2252 2253 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2254 struct iwl_device_cmd *dev_cmd, int txq_id) 2255 { 2256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2257 struct ieee80211_hdr *hdr; 2258 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2259 struct iwl_cmd_meta *out_meta; 2260 struct iwl_txq *txq; 2261 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2262 void *tb1_addr; 2263 void *tfd; 2264 u16 len, tb1_len; 2265 bool wait_write_ptr; 2266 __le16 fc; 2267 u8 hdr_len; 2268 u16 wifi_seq; 2269 bool amsdu; 2270 2271 txq = trans_pcie->txq[txq_id]; 2272 2273 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2274 "TX on unused queue %d\n", txq_id)) 2275 return -EINVAL; 2276 2277 if (unlikely(trans_pcie->sw_csum_tx && 2278 skb->ip_summed == CHECKSUM_PARTIAL)) { 2279 int offs = skb_checksum_start_offset(skb); 2280 int csum_offs = offs + skb->csum_offset; 2281 __wsum csum; 2282 2283 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 2284 return -1; 2285 2286 csum = skb_checksum(skb, offs, skb->len - offs, 0); 2287 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 2288 2289 skb->ip_summed = CHECKSUM_UNNECESSARY; 2290 } 2291 2292 if (skb_is_nonlinear(skb) && 2293 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2294 __skb_linearize(skb)) 2295 return -ENOMEM; 2296 2297 /* mac80211 always puts the full header into the SKB's head, 2298 * so there's no need to check if it's readable there 2299 */ 2300 hdr = (struct ieee80211_hdr *)skb->data; 2301 fc = hdr->frame_control; 2302 hdr_len = ieee80211_hdrlen(fc); 2303 2304 spin_lock(&txq->lock); 2305 2306 if (iwl_queue_space(txq) < txq->high_mark) { 2307 iwl_stop_queue(trans, txq); 2308 2309 /* don't put the packet on the ring, if there is no room */ 2310 if (unlikely(iwl_queue_space(txq) < 3)) { 2311 struct iwl_device_cmd **dev_cmd_ptr; 2312 2313 dev_cmd_ptr = (void *)((u8 *)skb->cb + 2314 trans_pcie->dev_cmd_offs); 2315 2316 *dev_cmd_ptr = dev_cmd; 2317 __skb_queue_tail(&txq->overflow_q, skb); 2318 2319 spin_unlock(&txq->lock); 2320 return 0; 2321 } 2322 } 2323 2324 /* In AGG mode, the index in the ring must correspond to the WiFi 2325 * sequence number. This is a HW requirements to help the SCD to parse 2326 * the BA. 2327 * Check here that the packets are in the right place on the ring. 2328 */ 2329 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2330 WARN_ONCE(txq->ampdu && 2331 (wifi_seq & 0xff) != txq->write_ptr, 2332 "Q: %d WiFi Seq %d tfdNum %d", 2333 txq_id, wifi_seq, txq->write_ptr); 2334 2335 /* Set up driver data for this TFD */ 2336 txq->entries[txq->write_ptr].skb = skb; 2337 txq->entries[txq->write_ptr].cmd = dev_cmd; 2338 2339 dev_cmd->hdr.sequence = 2340 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2341 INDEX_TO_SEQ(txq->write_ptr))); 2342 2343 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2344 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2345 offsetof(struct iwl_tx_cmd, scratch); 2346 2347 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2348 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2349 2350 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2351 out_meta = &txq->entries[txq->write_ptr].meta; 2352 out_meta->flags = 0; 2353 2354 /* 2355 * The second TB (tb1) points to the remainder of the TX command 2356 * and the 802.11 header - dword aligned size 2357 * (This calculation modifies the TX command, so do it before the 2358 * setup of the first TB) 2359 */ 2360 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 2361 hdr_len - IWL_FIRST_TB_SIZE; 2362 /* do not align A-MSDU to dword as the subframe header aligns it */ 2363 amsdu = ieee80211_is_data_qos(fc) && 2364 (*ieee80211_get_qos_ctl(hdr) & 2365 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2366 if (trans_pcie->sw_csum_tx || !amsdu) { 2367 tb1_len = ALIGN(len, 4); 2368 /* Tell NIC about any 2-byte padding after MAC header */ 2369 if (tb1_len != len) 2370 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 2371 } else { 2372 tb1_len = len; 2373 } 2374 2375 /* 2376 * The first TB points to bi-directional DMA data, we'll 2377 * memcpy the data into it later. 2378 */ 2379 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 2380 IWL_FIRST_TB_SIZE, true); 2381 2382 /* there must be data left over for TB1 or this code must be changed */ 2383 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2384 2385 /* map the data for TB1 */ 2386 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2387 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2388 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2389 goto out_err; 2390 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2391 2392 if (amsdu) { 2393 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 2394 out_meta, dev_cmd, 2395 tb1_len))) 2396 goto out_err; 2397 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2398 out_meta, dev_cmd, tb1_len))) { 2399 goto out_err; 2400 } 2401 2402 /* building the A-MSDU might have changed this data, so memcpy it now */ 2403 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 2404 IWL_FIRST_TB_SIZE); 2405 2406 tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr); 2407 /* Set up entry for this TFD in Tx byte-count array */ 2408 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 2409 iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2410 2411 wait_write_ptr = ieee80211_has_morefrags(fc); 2412 2413 /* start timer if queue currently empty */ 2414 if (txq->read_ptr == txq->write_ptr) { 2415 if (txq->wd_timeout) { 2416 /* 2417 * If the TXQ is active, then set the timer, if not, 2418 * set the timer in remainder so that the timer will 2419 * be armed with the right value when the station will 2420 * wake up. 2421 */ 2422 if (!txq->frozen) 2423 mod_timer(&txq->stuck_timer, 2424 jiffies + txq->wd_timeout); 2425 else 2426 txq->frozen_expiry_remainder = txq->wd_timeout; 2427 } 2428 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 2429 iwl_trans_ref(trans); 2430 } 2431 2432 /* Tell device the write index *just past* this latest filled TFD */ 2433 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 2434 if (!wait_write_ptr) 2435 iwl_pcie_txq_inc_wr_ptr(trans, txq); 2436 2437 /* 2438 * At this point the frame is "transmitted" successfully 2439 * and we will get a TX status notification eventually. 2440 */ 2441 spin_unlock(&txq->lock); 2442 return 0; 2443 out_err: 2444 spin_unlock(&txq->lock); 2445 return -1; 2446 } 2447