1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * The full GNU General Public License is included in this distribution in the 23 * file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/etherdevice.h> 65 #include <linux/ieee80211.h> 66 #include <linux/slab.h> 67 #include <linux/sched.h> 68 #include <net/ip6_checksum.h> 69 #include <net/tso.h> 70 71 #include "iwl-debug.h" 72 #include "iwl-csr.h" 73 #include "iwl-prph.h" 74 #include "iwl-io.h" 75 #include "iwl-scd.h" 76 #include "iwl-op-mode.h" 77 #include "internal.h" 78 #include "fw/api/tx.h" 79 80 #define IWL_TX_CRC_SIZE 4 81 #define IWL_TX_DELIMITER_SIZE 4 82 83 /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 84 * DMA services 85 * 86 * Theory of operation 87 * 88 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 89 * of buffer descriptors, each of which points to one or more data buffers for 90 * the device to read from or fill. Driver and device exchange status of each 91 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 92 * entries in each circular buffer, to protect against confusing empty and full 93 * queue states. 94 * 95 * The device reads or writes the data in the queues via the device's several 96 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 97 * 98 * For Tx queue, there are low mark and high mark limits. If, after queuing 99 * the packet for Tx, free space become < low mark, Tx queue stopped. When 100 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 101 * Tx queue resumed. 102 * 103 ***************************************************/ 104 105 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q) 106 { 107 unsigned int max; 108 unsigned int used; 109 110 /* 111 * To avoid ambiguity between empty and completely full queues, there 112 * should always be less than max_tfd_queue_size elements in the queue. 113 * If q->n_window is smaller than max_tfd_queue_size, there is no need 114 * to reserve any queue entries for this purpose. 115 */ 116 if (q->n_window < trans->trans_cfg->base_params->max_tfd_queue_size) 117 max = q->n_window; 118 else 119 max = trans->trans_cfg->base_params->max_tfd_queue_size - 1; 120 121 /* 122 * max_tfd_queue_size is a power of 2, so the following is equivalent to 123 * modulo by max_tfd_queue_size and is well defined. 124 */ 125 used = (q->write_ptr - q->read_ptr) & 126 (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 127 128 if (WARN_ON(used > max)) 129 return 0; 130 131 return max - used; 132 } 133 134 /* 135 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 136 */ 137 static int iwl_queue_init(struct iwl_txq *q, int slots_num) 138 { 139 q->n_window = slots_num; 140 141 /* slots_num must be power-of-two size, otherwise 142 * iwl_pcie_get_cmd_index is broken. */ 143 if (WARN_ON(!is_power_of_2(slots_num))) 144 return -EINVAL; 145 146 q->low_mark = q->n_window / 4; 147 if (q->low_mark < 4) 148 q->low_mark = 4; 149 150 q->high_mark = q->n_window / 8; 151 if (q->high_mark < 2) 152 q->high_mark = 2; 153 154 q->write_ptr = 0; 155 q->read_ptr = 0; 156 157 return 0; 158 } 159 160 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 161 struct iwl_dma_ptr *ptr, size_t size) 162 { 163 if (WARN_ON(ptr->addr)) 164 return -EINVAL; 165 166 ptr->addr = dma_alloc_coherent(trans->dev, size, 167 &ptr->dma, GFP_KERNEL); 168 if (!ptr->addr) 169 return -ENOMEM; 170 ptr->size = size; 171 return 0; 172 } 173 174 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 175 { 176 if (unlikely(!ptr->addr)) 177 return; 178 179 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 180 memset(ptr, 0, sizeof(*ptr)); 181 } 182 183 static void iwl_pcie_txq_stuck_timer(struct timer_list *t) 184 { 185 struct iwl_txq *txq = from_timer(txq, t, stuck_timer); 186 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 187 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 188 189 spin_lock(&txq->lock); 190 /* check if triggered erroneously */ 191 if (txq->read_ptr == txq->write_ptr) { 192 spin_unlock(&txq->lock); 193 return; 194 } 195 spin_unlock(&txq->lock); 196 197 iwl_trans_pcie_log_scd_error(trans, txq); 198 199 iwl_force_nmi(trans); 200 } 201 202 /* 203 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 204 */ 205 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 206 struct iwl_txq *txq, u16 byte_cnt, 207 int num_tbs) 208 { 209 struct iwlagn_scd_bc_tbl *scd_bc_tbl; 210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 211 int write_ptr = txq->write_ptr; 212 int txq_id = txq->id; 213 u8 sec_ctl = 0; 214 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 215 __le16 bc_ent; 216 struct iwl_device_tx_cmd *dev_cmd = txq->entries[txq->write_ptr].cmd; 217 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 218 u8 sta_id = tx_cmd->sta_id; 219 220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 221 222 sec_ctl = tx_cmd->sec_ctl; 223 224 switch (sec_ctl & TX_CMD_SEC_MSK) { 225 case TX_CMD_SEC_CCM: 226 len += IEEE80211_CCMP_MIC_LEN; 227 break; 228 case TX_CMD_SEC_TKIP: 229 len += IEEE80211_TKIP_ICV_LEN; 230 break; 231 case TX_CMD_SEC_WEP: 232 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 233 break; 234 } 235 if (trans_pcie->bc_table_dword) 236 len = DIV_ROUND_UP(len, 4); 237 238 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 239 return; 240 241 bc_ent = cpu_to_le16(len | (sta_id << 12)); 242 243 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 244 245 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 246 scd_bc_tbl[txq_id]. 247 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 248 } 249 250 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 251 struct iwl_txq *txq) 252 { 253 struct iwl_trans_pcie *trans_pcie = 254 IWL_TRANS_GET_PCIE_TRANS(trans); 255 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 256 int txq_id = txq->id; 257 int read_ptr = txq->read_ptr; 258 u8 sta_id = 0; 259 __le16 bc_ent; 260 struct iwl_device_tx_cmd *dev_cmd = txq->entries[read_ptr].cmd; 261 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 262 263 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 264 265 if (txq_id != trans_pcie->cmd_queue) 266 sta_id = tx_cmd->sta_id; 267 268 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 269 270 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 271 272 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 273 scd_bc_tbl[txq_id]. 274 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 275 } 276 277 /* 278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 279 */ 280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 281 struct iwl_txq *txq) 282 { 283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 284 u32 reg = 0; 285 int txq_id = txq->id; 286 287 lockdep_assert_held(&txq->lock); 288 289 /* 290 * explicitly wake up the NIC if: 291 * 1. shadow registers aren't enabled 292 * 2. NIC is woken up for CMD regardless of shadow outside this function 293 * 3. there is a chance that the NIC is asleep 294 */ 295 if (!trans->trans_cfg->base_params->shadow_reg_enable && 296 txq_id != trans_pcie->cmd_queue && 297 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 298 /* 299 * wake up nic if it's powered down ... 300 * uCode will wake up, and interrupt us again, so next 301 * time we'll skip this part. 302 */ 303 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 304 305 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 306 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 307 txq_id, reg); 308 iwl_set_bit(trans, CSR_GP_CNTRL, 309 BIT(trans->trans_cfg->csr->flag_mac_access_req)); 310 txq->need_update = true; 311 return; 312 } 313 } 314 315 /* 316 * if not in power-save mode, uCode will never sleep when we're 317 * trying to tx (during RFKILL, we're not trying to tx). 318 */ 319 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 320 if (!txq->block) 321 iwl_write32(trans, HBUS_TARG_WRPTR, 322 txq->write_ptr | (txq_id << 8)); 323 } 324 325 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 326 { 327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 328 int i; 329 330 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 331 struct iwl_txq *txq = trans_pcie->txq[i]; 332 333 if (!test_bit(i, trans_pcie->queue_used)) 334 continue; 335 336 spin_lock_bh(&txq->lock); 337 if (txq->need_update) { 338 iwl_pcie_txq_inc_wr_ptr(trans, txq); 339 txq->need_update = false; 340 } 341 spin_unlock_bh(&txq->lock); 342 } 343 } 344 345 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 346 void *_tfd, u8 idx) 347 { 348 349 if (trans->trans_cfg->use_tfh) { 350 struct iwl_tfh_tfd *tfd = _tfd; 351 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 352 353 return (dma_addr_t)(le64_to_cpu(tb->addr)); 354 } else { 355 struct iwl_tfd *tfd = _tfd; 356 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 357 dma_addr_t addr = get_unaligned_le32(&tb->lo); 358 dma_addr_t hi_len; 359 360 if (sizeof(dma_addr_t) <= sizeof(u32)) 361 return addr; 362 363 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 364 365 /* 366 * shift by 16 twice to avoid warnings on 32-bit 367 * (where this code never runs anyway due to the 368 * if statement above) 369 */ 370 return addr | ((hi_len << 16) << 16); 371 } 372 } 373 374 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 375 u8 idx, dma_addr_t addr, u16 len) 376 { 377 struct iwl_tfd *tfd_fh = (void *)tfd; 378 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 379 380 u16 hi_n_len = len << 4; 381 382 put_unaligned_le32(addr, &tb->lo); 383 hi_n_len |= iwl_get_dma_hi_addr(addr); 384 385 tb->hi_n_len = cpu_to_le16(hi_n_len); 386 387 tfd_fh->num_tbs = idx + 1; 388 } 389 390 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 391 { 392 if (trans->trans_cfg->use_tfh) { 393 struct iwl_tfh_tfd *tfd = _tfd; 394 395 return le16_to_cpu(tfd->num_tbs) & 0x1f; 396 } else { 397 struct iwl_tfd *tfd = _tfd; 398 399 return tfd->num_tbs & 0x1f; 400 } 401 } 402 403 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 404 struct iwl_cmd_meta *meta, 405 struct iwl_txq *txq, int index) 406 { 407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 408 int i, num_tbs; 409 void *tfd = iwl_pcie_get_tfd(trans, txq, index); 410 411 /* Sanity check on number of chunks */ 412 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 413 414 if (num_tbs > trans_pcie->max_tbs) { 415 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 416 /* @todo issue fatal error, it is quite serious situation */ 417 return; 418 } 419 420 /* first TB is never freed - it's the bidirectional DMA data */ 421 422 for (i = 1; i < num_tbs; i++) { 423 if (meta->tbs & BIT(i)) 424 dma_unmap_page(trans->dev, 425 iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 426 iwl_pcie_tfd_tb_get_len(trans, tfd, i), 427 DMA_TO_DEVICE); 428 else 429 dma_unmap_single(trans->dev, 430 iwl_pcie_tfd_tb_get_addr(trans, tfd, 431 i), 432 iwl_pcie_tfd_tb_get_len(trans, tfd, 433 i), 434 DMA_TO_DEVICE); 435 } 436 437 meta->tbs = 0; 438 439 if (trans->trans_cfg->use_tfh) { 440 struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 441 442 tfd_fh->num_tbs = 0; 443 } else { 444 struct iwl_tfd *tfd_fh = (void *)tfd; 445 446 tfd_fh->num_tbs = 0; 447 } 448 449 } 450 451 /* 452 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 453 * @trans - transport private data 454 * @txq - tx queue 455 * @dma_dir - the direction of the DMA mapping 456 * 457 * Does NOT advance any TFD circular buffer read/write indexes 458 * Does NOT free the TFD itself (which is within circular buffer) 459 */ 460 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 461 { 462 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 463 * idx is bounded by n_window 464 */ 465 int rd_ptr = txq->read_ptr; 466 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 467 468 lockdep_assert_held(&txq->lock); 469 470 /* We have only q->n_window txq->entries, but we use 471 * TFD_QUEUE_SIZE_MAX tfds 472 */ 473 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 474 475 /* free SKB */ 476 if (txq->entries) { 477 struct sk_buff *skb; 478 479 skb = txq->entries[idx].skb; 480 481 /* Can be called from irqs-disabled context 482 * If skb is not NULL, it means that the whole queue is being 483 * freed and that the queue is not empty - free the skb 484 */ 485 if (skb) { 486 iwl_op_mode_free_skb(trans->op_mode, skb); 487 txq->entries[idx].skb = NULL; 488 } 489 } 490 } 491 492 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 493 dma_addr_t addr, u16 len, bool reset) 494 { 495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 496 void *tfd; 497 u32 num_tbs; 498 499 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 500 501 if (reset) 502 memset(tfd, 0, trans_pcie->tfd_size); 503 504 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 505 506 /* Each TFD can point to a maximum max_tbs Tx buffers */ 507 if (num_tbs >= trans_pcie->max_tbs) { 508 IWL_ERR(trans, "Error can not send more than %d chunks\n", 509 trans_pcie->max_tbs); 510 return -EINVAL; 511 } 512 513 if (WARN(addr & ~IWL_TX_DMA_MASK, 514 "Unaligned address = %llx\n", (unsigned long long)addr)) 515 return -EINVAL; 516 517 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 518 519 return num_tbs; 520 } 521 522 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 523 int slots_num, bool cmd_queue) 524 { 525 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 526 size_t tfd_sz = trans_pcie->tfd_size * 527 trans->trans_cfg->base_params->max_tfd_queue_size; 528 size_t tb0_buf_sz; 529 int i; 530 531 if (WARN_ON(txq->entries || txq->tfds)) 532 return -EINVAL; 533 534 if (trans->trans_cfg->use_tfh) 535 tfd_sz = trans_pcie->tfd_size * slots_num; 536 537 timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0); 538 txq->trans_pcie = trans_pcie; 539 540 txq->n_window = slots_num; 541 542 txq->entries = kcalloc(slots_num, 543 sizeof(struct iwl_pcie_txq_entry), 544 GFP_KERNEL); 545 546 if (!txq->entries) 547 goto error; 548 549 if (cmd_queue) 550 for (i = 0; i < slots_num; i++) { 551 txq->entries[i].cmd = 552 kmalloc(sizeof(struct iwl_device_cmd), 553 GFP_KERNEL); 554 if (!txq->entries[i].cmd) 555 goto error; 556 } 557 558 /* Circular buffer of transmit frame descriptors (TFDs), 559 * shared with device */ 560 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 561 &txq->dma_addr, GFP_KERNEL); 562 if (!txq->tfds) 563 goto error; 564 565 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 566 567 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 568 569 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 570 &txq->first_tb_dma, 571 GFP_KERNEL); 572 if (!txq->first_tb_bufs) 573 goto err_free_tfds; 574 575 return 0; 576 err_free_tfds: 577 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 578 error: 579 if (txq->entries && cmd_queue) 580 for (i = 0; i < slots_num; i++) 581 kfree(txq->entries[i].cmd); 582 kfree(txq->entries); 583 txq->entries = NULL; 584 585 return -ENOMEM; 586 587 } 588 589 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 590 int slots_num, bool cmd_queue) 591 { 592 int ret; 593 u32 tfd_queue_max_size = 594 trans->trans_cfg->base_params->max_tfd_queue_size; 595 596 txq->need_update = false; 597 598 /* max_tfd_queue_size must be power-of-two size, otherwise 599 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 600 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1), 601 "Max tfd queue size must be a power of two, but is %d", 602 tfd_queue_max_size)) 603 return -EINVAL; 604 605 /* Initialize queue's high/low-water marks, and head/tail indexes */ 606 ret = iwl_queue_init(txq, slots_num); 607 if (ret) 608 return ret; 609 610 spin_lock_init(&txq->lock); 611 612 if (cmd_queue) { 613 static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 614 615 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 616 } 617 618 __skb_queue_head_init(&txq->overflow_q); 619 620 return 0; 621 } 622 623 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 624 struct sk_buff *skb) 625 { 626 struct page **page_ptr; 627 struct page *next; 628 629 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 630 next = *page_ptr; 631 *page_ptr = NULL; 632 633 while (next) { 634 struct page *tmp = next; 635 636 next = *(void **)(page_address(next) + PAGE_SIZE - 637 sizeof(void *)); 638 __free_page(tmp); 639 } 640 } 641 642 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 643 { 644 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 645 646 lockdep_assert_held(&trans_pcie->reg_lock); 647 648 if (!trans->trans_cfg->base_params->apmg_wake_up_wa) 649 return; 650 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 651 return; 652 653 trans_pcie->cmd_hold_nic_awake = false; 654 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 655 BIT(trans->trans_cfg->csr->flag_mac_access_req)); 656 } 657 658 /* 659 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 660 */ 661 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 662 { 663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 664 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 665 666 spin_lock_bh(&txq->lock); 667 while (txq->write_ptr != txq->read_ptr) { 668 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 669 txq_id, txq->read_ptr); 670 671 if (txq_id != trans_pcie->cmd_queue) { 672 struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 673 674 if (WARN_ON_ONCE(!skb)) 675 continue; 676 677 iwl_pcie_free_tso_page(trans_pcie, skb); 678 } 679 iwl_pcie_txq_free_tfd(trans, txq); 680 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 681 682 if (txq->read_ptr == txq->write_ptr) { 683 unsigned long flags; 684 685 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 686 if (txq_id == trans_pcie->cmd_queue) 687 iwl_pcie_clear_cmd_in_flight(trans); 688 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 689 } 690 } 691 692 while (!skb_queue_empty(&txq->overflow_q)) { 693 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 694 695 iwl_op_mode_free_skb(trans->op_mode, skb); 696 } 697 698 spin_unlock_bh(&txq->lock); 699 700 /* just in case - this queue may have been stopped */ 701 iwl_wake_queue(trans, txq); 702 } 703 704 /* 705 * iwl_pcie_txq_free - Deallocate DMA queue. 706 * @txq: Transmit queue to deallocate. 707 * 708 * Empty queue by removing and destroying all BD's. 709 * Free all buffers. 710 * 0-fill, but do not free "txq" descriptor structure. 711 */ 712 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 713 { 714 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 715 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 716 struct device *dev = trans->dev; 717 int i; 718 719 if (WARN_ON(!txq)) 720 return; 721 722 iwl_pcie_txq_unmap(trans, txq_id); 723 724 /* De-alloc array of command/tx buffers */ 725 if (txq_id == trans_pcie->cmd_queue) 726 for (i = 0; i < txq->n_window; i++) { 727 kzfree(txq->entries[i].cmd); 728 kzfree(txq->entries[i].free_buf); 729 } 730 731 /* De-alloc circular buffer of TFDs */ 732 if (txq->tfds) { 733 dma_free_coherent(dev, 734 trans_pcie->tfd_size * 735 trans->trans_cfg->base_params->max_tfd_queue_size, 736 txq->tfds, txq->dma_addr); 737 txq->dma_addr = 0; 738 txq->tfds = NULL; 739 740 dma_free_coherent(dev, 741 sizeof(*txq->first_tb_bufs) * txq->n_window, 742 txq->first_tb_bufs, txq->first_tb_dma); 743 } 744 745 kfree(txq->entries); 746 txq->entries = NULL; 747 748 del_timer_sync(&txq->stuck_timer); 749 750 /* 0-fill queue descriptor structure */ 751 memset(txq, 0, sizeof(*txq)); 752 } 753 754 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 755 { 756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 757 int nq = trans->trans_cfg->base_params->num_of_queues; 758 int chan; 759 u32 reg_val; 760 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 761 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 762 763 /* make sure all queue are not stopped/used */ 764 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 765 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 766 767 trans_pcie->scd_base_addr = 768 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 769 770 WARN_ON(scd_base_addr != 0 && 771 scd_base_addr != trans_pcie->scd_base_addr); 772 773 /* reset context data, TX status and translation data */ 774 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 775 SCD_CONTEXT_MEM_LOWER_BOUND, 776 NULL, clear_dwords); 777 778 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 779 trans_pcie->scd_bc_tbls.dma >> 10); 780 781 /* The chain extension of the SCD doesn't work well. This feature is 782 * enabled by default by the HW, so we need to disable it manually. 783 */ 784 if (trans->trans_cfg->base_params->scd_chain_ext_wa) 785 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 786 787 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 788 trans_pcie->cmd_fifo, 789 trans_pcie->cmd_q_wdg_timeout); 790 791 /* Activate all Tx DMA/FIFO channels */ 792 iwl_scd_activate_fifos(trans); 793 794 /* Enable DMA channel */ 795 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 796 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 797 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 798 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 799 800 /* Update FH chicken bits */ 801 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 802 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 803 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 804 805 /* Enable L1-Active */ 806 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 807 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 808 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 809 } 810 811 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 812 { 813 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 814 int txq_id; 815 816 /* 817 * we should never get here in gen2 trans mode return early to avoid 818 * having invalid accesses 819 */ 820 if (WARN_ON_ONCE(trans->trans_cfg->gen2)) 821 return; 822 823 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 824 txq_id++) { 825 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 826 if (trans->trans_cfg->use_tfh) 827 iwl_write_direct64(trans, 828 FH_MEM_CBBC_QUEUE(trans, txq_id), 829 txq->dma_addr); 830 else 831 iwl_write_direct32(trans, 832 FH_MEM_CBBC_QUEUE(trans, txq_id), 833 txq->dma_addr >> 8); 834 iwl_pcie_txq_unmap(trans, txq_id); 835 txq->read_ptr = 0; 836 txq->write_ptr = 0; 837 } 838 839 /* Tell NIC where to find the "keep warm" buffer */ 840 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 841 trans_pcie->kw.dma >> 4); 842 843 /* 844 * Send 0 as the scd_base_addr since the device may have be reset 845 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 846 * contain garbage. 847 */ 848 iwl_pcie_tx_start(trans, 0); 849 } 850 851 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 852 { 853 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 854 unsigned long flags; 855 int ch, ret; 856 u32 mask = 0; 857 858 spin_lock(&trans_pcie->irq_lock); 859 860 if (!iwl_trans_grab_nic_access(trans, &flags)) 861 goto out; 862 863 /* Stop each Tx DMA channel */ 864 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 865 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 866 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 867 } 868 869 /* Wait for DMA channels to be idle */ 870 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 871 if (ret < 0) 872 IWL_ERR(trans, 873 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 874 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 875 876 iwl_trans_release_nic_access(trans, &flags); 877 878 out: 879 spin_unlock(&trans_pcie->irq_lock); 880 } 881 882 /* 883 * iwl_pcie_tx_stop - Stop all Tx DMA channels 884 */ 885 int iwl_pcie_tx_stop(struct iwl_trans *trans) 886 { 887 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 888 int txq_id; 889 890 /* Turn off all Tx DMA fifos */ 891 iwl_scd_deactivate_fifos(trans); 892 893 /* Turn off all Tx DMA channels */ 894 iwl_pcie_tx_stop_fh(trans); 895 896 /* 897 * This function can be called before the op_mode disabled the 898 * queues. This happens when we have an rfkill interrupt. 899 * Since we stop Tx altogether - mark the queues as stopped. 900 */ 901 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 902 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 903 904 /* This can happen: start_hw, stop_device */ 905 if (!trans_pcie->txq_memory) 906 return 0; 907 908 /* Unmap DMA from host system and free skb's */ 909 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 910 txq_id++) 911 iwl_pcie_txq_unmap(trans, txq_id); 912 913 return 0; 914 } 915 916 /* 917 * iwl_trans_tx_free - Free TXQ Context 918 * 919 * Destroy all TX DMA queues and structures 920 */ 921 void iwl_pcie_tx_free(struct iwl_trans *trans) 922 { 923 int txq_id; 924 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 925 926 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 927 928 /* Tx queues */ 929 if (trans_pcie->txq_memory) { 930 for (txq_id = 0; 931 txq_id < trans->trans_cfg->base_params->num_of_queues; 932 txq_id++) { 933 iwl_pcie_txq_free(trans, txq_id); 934 trans_pcie->txq[txq_id] = NULL; 935 } 936 } 937 938 kfree(trans_pcie->txq_memory); 939 trans_pcie->txq_memory = NULL; 940 941 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 942 943 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 944 } 945 946 /* 947 * iwl_pcie_tx_alloc - allocate TX context 948 * Allocate all Tx DMA structures and initialize them 949 */ 950 static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 951 { 952 int ret; 953 int txq_id, slots_num; 954 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 955 u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues; 956 957 bc_tbls_size *= (trans->trans_cfg->device_family >= 958 IWL_DEVICE_FAMILY_AX210) ? 959 sizeof(struct iwl_gen3_bc_tbl) : 960 sizeof(struct iwlagn_scd_bc_tbl); 961 962 /*It is not allowed to alloc twice, so warn when this happens. 963 * We cannot rely on the previous allocation, so free and fail */ 964 if (WARN_ON(trans_pcie->txq_memory)) { 965 ret = -EINVAL; 966 goto error; 967 } 968 969 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 970 bc_tbls_size); 971 if (ret) { 972 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 973 goto error; 974 } 975 976 /* Alloc keep-warm buffer */ 977 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 978 if (ret) { 979 IWL_ERR(trans, "Keep Warm allocation failed\n"); 980 goto error; 981 } 982 983 trans_pcie->txq_memory = 984 kcalloc(trans->trans_cfg->base_params->num_of_queues, 985 sizeof(struct iwl_txq), GFP_KERNEL); 986 if (!trans_pcie->txq_memory) { 987 IWL_ERR(trans, "Not enough memory for txq\n"); 988 ret = -ENOMEM; 989 goto error; 990 } 991 992 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 993 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 994 txq_id++) { 995 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 996 997 if (cmd_queue) 998 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 999 trans->cfg->min_txq_size); 1000 else 1001 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 1002 trans->cfg->min_256_ba_txq_size); 1003 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 1004 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 1005 slots_num, cmd_queue); 1006 if (ret) { 1007 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 1008 goto error; 1009 } 1010 trans_pcie->txq[txq_id]->id = txq_id; 1011 } 1012 1013 return 0; 1014 1015 error: 1016 iwl_pcie_tx_free(trans); 1017 1018 return ret; 1019 } 1020 1021 int iwl_pcie_tx_init(struct iwl_trans *trans) 1022 { 1023 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1024 int ret; 1025 int txq_id, slots_num; 1026 bool alloc = false; 1027 1028 if (!trans_pcie->txq_memory) { 1029 ret = iwl_pcie_tx_alloc(trans); 1030 if (ret) 1031 goto error; 1032 alloc = true; 1033 } 1034 1035 spin_lock(&trans_pcie->irq_lock); 1036 1037 /* Turn off all Tx DMA fifos */ 1038 iwl_scd_deactivate_fifos(trans); 1039 1040 /* Tell NIC where to find the "keep warm" buffer */ 1041 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1042 trans_pcie->kw.dma >> 4); 1043 1044 spin_unlock(&trans_pcie->irq_lock); 1045 1046 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1047 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 1048 txq_id++) { 1049 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1050 1051 if (cmd_queue) 1052 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 1053 trans->cfg->min_txq_size); 1054 else 1055 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 1056 trans->cfg->min_256_ba_txq_size); 1057 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1058 slots_num, cmd_queue); 1059 if (ret) { 1060 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1061 goto error; 1062 } 1063 1064 /* 1065 * Tell nic where to find circular buffer of TFDs for a 1066 * given Tx queue, and enable the DMA channel used for that 1067 * queue. 1068 * Circular buffer (TFD queue in DRAM) physical base address 1069 */ 1070 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1071 trans_pcie->txq[txq_id]->dma_addr >> 8); 1072 } 1073 1074 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1075 if (trans->trans_cfg->base_params->num_of_queues > 20) 1076 iwl_set_bits_prph(trans, SCD_GP_CTRL, 1077 SCD_GP_CTRL_ENABLE_31_QUEUES); 1078 1079 return 0; 1080 error: 1081 /*Upon error, free only if we allocated something */ 1082 if (alloc) 1083 iwl_pcie_tx_free(trans); 1084 return ret; 1085 } 1086 1087 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1088 { 1089 lockdep_assert_held(&txq->lock); 1090 1091 if (!txq->wd_timeout) 1092 return; 1093 1094 /* 1095 * station is asleep and we send data - that must 1096 * be uAPSD or PS-Poll. Don't rearm the timer. 1097 */ 1098 if (txq->frozen) 1099 return; 1100 1101 /* 1102 * if empty delete timer, otherwise move timer forward 1103 * since we're making progress on this queue 1104 */ 1105 if (txq->read_ptr == txq->write_ptr) 1106 del_timer(&txq->stuck_timer); 1107 else 1108 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1109 } 1110 1111 /* Frees buffers until index _not_ inclusive */ 1112 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1113 struct sk_buff_head *skbs) 1114 { 1115 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1116 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1117 int tfd_num = iwl_pcie_get_cmd_index(txq, ssn); 1118 int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1119 int last_to_free; 1120 1121 /* This function is not meant to release cmd queue*/ 1122 if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1123 return; 1124 1125 spin_lock_bh(&txq->lock); 1126 1127 if (!test_bit(txq_id, trans_pcie->queue_used)) { 1128 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1129 txq_id, ssn); 1130 goto out; 1131 } 1132 1133 if (read_ptr == tfd_num) 1134 goto out; 1135 1136 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1137 txq_id, txq->read_ptr, tfd_num, ssn); 1138 1139 /*Since we free until index _not_ inclusive, the one before index is 1140 * the last we will free. This one must be used */ 1141 last_to_free = iwl_queue_dec_wrap(trans, tfd_num); 1142 1143 if (!iwl_queue_used(txq, last_to_free)) { 1144 IWL_ERR(trans, 1145 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1146 __func__, txq_id, last_to_free, 1147 trans->trans_cfg->base_params->max_tfd_queue_size, 1148 txq->write_ptr, txq->read_ptr); 1149 goto out; 1150 } 1151 1152 if (WARN_ON(!skb_queue_empty(skbs))) 1153 goto out; 1154 1155 for (; 1156 read_ptr != tfd_num; 1157 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr), 1158 read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) { 1159 struct sk_buff *skb = txq->entries[read_ptr].skb; 1160 1161 if (WARN_ON_ONCE(!skb)) 1162 continue; 1163 1164 iwl_pcie_free_tso_page(trans_pcie, skb); 1165 1166 __skb_queue_tail(skbs, skb); 1167 1168 txq->entries[read_ptr].skb = NULL; 1169 1170 if (!trans->trans_cfg->use_tfh) 1171 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1172 1173 iwl_pcie_txq_free_tfd(trans, txq); 1174 } 1175 1176 iwl_pcie_txq_progress(txq); 1177 1178 if (iwl_queue_space(trans, txq) > txq->low_mark && 1179 test_bit(txq_id, trans_pcie->queue_stopped)) { 1180 struct sk_buff_head overflow_skbs; 1181 1182 __skb_queue_head_init(&overflow_skbs); 1183 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 1184 1185 /* 1186 * We are going to transmit from the overflow queue. 1187 * Remember this state so that wait_for_txq_empty will know we 1188 * are adding more packets to the TFD queue. It cannot rely on 1189 * the state of &txq->overflow_q, as we just emptied it, but 1190 * haven't TXed the content yet. 1191 */ 1192 txq->overflow_tx = true; 1193 1194 /* 1195 * This is tricky: we are in reclaim path which is non 1196 * re-entrant, so noone will try to take the access the 1197 * txq data from that path. We stopped tx, so we can't 1198 * have tx as well. Bottom line, we can unlock and re-lock 1199 * later. 1200 */ 1201 spin_unlock_bh(&txq->lock); 1202 1203 while (!skb_queue_empty(&overflow_skbs)) { 1204 struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 1205 struct iwl_device_tx_cmd *dev_cmd_ptr; 1206 1207 dev_cmd_ptr = *(void **)((u8 *)skb->cb + 1208 trans_pcie->dev_cmd_offs); 1209 1210 /* 1211 * Note that we can very well be overflowing again. 1212 * In that case, iwl_queue_space will be small again 1213 * and we won't wake mac80211's queue. 1214 */ 1215 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id); 1216 } 1217 1218 if (iwl_queue_space(trans, txq) > txq->low_mark) 1219 iwl_wake_queue(trans, txq); 1220 1221 spin_lock_bh(&txq->lock); 1222 txq->overflow_tx = false; 1223 } 1224 1225 out: 1226 spin_unlock_bh(&txq->lock); 1227 } 1228 1229 /* Set wr_ptr of specific device and txq */ 1230 void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr) 1231 { 1232 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1233 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1234 1235 spin_lock_bh(&txq->lock); 1236 1237 txq->write_ptr = ptr; 1238 txq->read_ptr = txq->write_ptr; 1239 1240 spin_unlock_bh(&txq->lock); 1241 } 1242 1243 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1244 const struct iwl_host_cmd *cmd) 1245 { 1246 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1247 int ret; 1248 1249 lockdep_assert_held(&trans_pcie->reg_lock); 1250 1251 /* Make sure the NIC is still alive in the bus */ 1252 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1253 return -ENODEV; 1254 1255 /* 1256 * wake up the NIC to make sure that the firmware will see the host 1257 * command - we will let the NIC sleep once all the host commands 1258 * returned. This needs to be done only on NICs that have 1259 * apmg_wake_up_wa set. 1260 */ 1261 if (trans->trans_cfg->base_params->apmg_wake_up_wa && 1262 !trans_pcie->cmd_hold_nic_awake) { 1263 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1264 BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1265 1266 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1267 BIT(trans->trans_cfg->csr->flag_val_mac_access_en), 1268 (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) | 1269 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1270 15000); 1271 if (ret < 0) { 1272 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1273 BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1274 IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1275 return -EIO; 1276 } 1277 trans_pcie->cmd_hold_nic_awake = true; 1278 } 1279 1280 return 0; 1281 } 1282 1283 /* 1284 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1285 * 1286 * When FW advances 'R' index, all entries between old and new 'R' index 1287 * need to be reclaimed. As result, some free space forms. If there is 1288 * enough free space (> low mark), wake the stack that feeds us. 1289 */ 1290 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1291 { 1292 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1293 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1294 unsigned long flags; 1295 int nfreed = 0; 1296 u16 r; 1297 1298 lockdep_assert_held(&txq->lock); 1299 1300 idx = iwl_pcie_get_cmd_index(txq, idx); 1301 r = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1302 1303 if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size || 1304 (!iwl_queue_used(txq, idx))) { 1305 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used), 1306 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1307 __func__, txq_id, idx, 1308 trans->trans_cfg->base_params->max_tfd_queue_size, 1309 txq->write_ptr, txq->read_ptr); 1310 return; 1311 } 1312 1313 for (idx = iwl_queue_inc_wrap(trans, idx); r != idx; 1314 r = iwl_queue_inc_wrap(trans, r)) { 1315 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1316 1317 if (nfreed++ > 0) { 1318 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1319 idx, txq->write_ptr, r); 1320 iwl_force_nmi(trans); 1321 } 1322 } 1323 1324 if (txq->read_ptr == txq->write_ptr) { 1325 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1326 iwl_pcie_clear_cmd_in_flight(trans); 1327 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1328 } 1329 1330 iwl_pcie_txq_progress(txq); 1331 } 1332 1333 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1334 u16 txq_id) 1335 { 1336 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1337 u32 tbl_dw_addr; 1338 u32 tbl_dw; 1339 u16 scd_q2ratid; 1340 1341 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1342 1343 tbl_dw_addr = trans_pcie->scd_base_addr + 1344 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1345 1346 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1347 1348 if (txq_id & 0x1) 1349 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1350 else 1351 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1352 1353 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1354 1355 return 0; 1356 } 1357 1358 /* Receiver address (actually, Rx station's index into station table), 1359 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1360 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1361 1362 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1363 const struct iwl_trans_txq_scd_cfg *cfg, 1364 unsigned int wdg_timeout) 1365 { 1366 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1367 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1368 int fifo = -1; 1369 bool scd_bug = false; 1370 1371 if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1372 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1373 1374 txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1375 1376 if (cfg) { 1377 fifo = cfg->fifo; 1378 1379 /* Disable the scheduler prior configuring the cmd queue */ 1380 if (txq_id == trans_pcie->cmd_queue && 1381 trans_pcie->scd_set_active) 1382 iwl_scd_enable_set_active(trans, 0); 1383 1384 /* Stop this Tx queue before configuring it */ 1385 iwl_scd_txq_set_inactive(trans, txq_id); 1386 1387 /* Set this queue as a chain-building queue unless it is CMD */ 1388 if (txq_id != trans_pcie->cmd_queue) 1389 iwl_scd_txq_set_chain(trans, txq_id); 1390 1391 if (cfg->aggregate) { 1392 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1393 1394 /* Map receiver-address / traffic-ID to this queue */ 1395 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1396 1397 /* enable aggregations for the queue */ 1398 iwl_scd_txq_enable_agg(trans, txq_id); 1399 txq->ampdu = true; 1400 } else { 1401 /* 1402 * disable aggregations for the queue, this will also 1403 * make the ra_tid mapping configuration irrelevant 1404 * since it is now a non-AGG queue. 1405 */ 1406 iwl_scd_txq_disable_agg(trans, txq_id); 1407 1408 ssn = txq->read_ptr; 1409 } 1410 } else { 1411 /* 1412 * If we need to move the SCD write pointer by steps of 1413 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1414 * the op_mode know by returning true later. 1415 * Do this only in case cfg is NULL since this trick can 1416 * be done only if we have DQA enabled which is true for mvm 1417 * only. And mvm never sets a cfg pointer. 1418 * This is really ugly, but this is the easiest way out for 1419 * this sad hardware issue. 1420 * This bug has been fixed on devices 9000 and up. 1421 */ 1422 scd_bug = !trans->trans_cfg->mq_rx_supported && 1423 !((ssn - txq->write_ptr) & 0x3f) && 1424 (ssn != txq->write_ptr); 1425 if (scd_bug) 1426 ssn++; 1427 } 1428 1429 /* Place first TFD at index corresponding to start sequence number. 1430 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1431 txq->read_ptr = (ssn & 0xff); 1432 txq->write_ptr = (ssn & 0xff); 1433 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1434 (ssn & 0xff) | (txq_id << 8)); 1435 1436 if (cfg) { 1437 u8 frame_limit = cfg->frame_limit; 1438 1439 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1440 1441 /* Set up Tx window size and frame limit for this queue */ 1442 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1443 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1444 iwl_trans_write_mem32(trans, 1445 trans_pcie->scd_base_addr + 1446 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1447 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1448 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1449 1450 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1451 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1452 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1453 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1454 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1455 SCD_QUEUE_STTS_REG_MSK); 1456 1457 /* enable the scheduler for this queue (only) */ 1458 if (txq_id == trans_pcie->cmd_queue && 1459 trans_pcie->scd_set_active) 1460 iwl_scd_enable_set_active(trans, BIT(txq_id)); 1461 1462 IWL_DEBUG_TX_QUEUES(trans, 1463 "Activate queue %d on FIFO %d WrPtr: %d\n", 1464 txq_id, fifo, ssn & 0xff); 1465 } else { 1466 IWL_DEBUG_TX_QUEUES(trans, 1467 "Activate queue %d WrPtr: %d\n", 1468 txq_id, ssn & 0xff); 1469 } 1470 1471 return scd_bug; 1472 } 1473 1474 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 1475 bool shared_mode) 1476 { 1477 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1478 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1479 1480 txq->ampdu = !shared_mode; 1481 } 1482 1483 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1484 bool configure_scd) 1485 { 1486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1487 u32 stts_addr = trans_pcie->scd_base_addr + 1488 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1489 static const u32 zero_val[4] = {}; 1490 1491 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1492 trans_pcie->txq[txq_id]->frozen = false; 1493 1494 /* 1495 * Upon HW Rfkill - we stop the device, and then stop the queues 1496 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1497 * allow the op_mode to call txq_disable after it already called 1498 * stop_device. 1499 */ 1500 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1501 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1502 "queue %d not used", txq_id); 1503 return; 1504 } 1505 1506 if (configure_scd) { 1507 iwl_scd_txq_set_inactive(trans, txq_id); 1508 1509 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1510 ARRAY_SIZE(zero_val)); 1511 } 1512 1513 iwl_pcie_txq_unmap(trans, txq_id); 1514 trans_pcie->txq[txq_id]->ampdu = false; 1515 1516 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1517 } 1518 1519 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1520 1521 /* 1522 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1523 * @priv: device private data point 1524 * @cmd: a pointer to the ucode command structure 1525 * 1526 * The function returns < 0 values to indicate the operation 1527 * failed. On success, it returns the index (>= 0) of command in the 1528 * command queue. 1529 */ 1530 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1531 struct iwl_host_cmd *cmd) 1532 { 1533 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1534 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1535 struct iwl_device_cmd *out_cmd; 1536 struct iwl_cmd_meta *out_meta; 1537 unsigned long flags; 1538 void *dup_buf = NULL; 1539 dma_addr_t phys_addr; 1540 int idx; 1541 u16 copy_size, cmd_size, tb0_size; 1542 bool had_nocopy = false; 1543 u8 group_id = iwl_cmd_groupid(cmd->id); 1544 int i, ret; 1545 u32 cmd_pos; 1546 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1547 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1548 1549 if (WARN(!trans->wide_cmd_header && 1550 group_id > IWL_ALWAYS_LONG_GROUP, 1551 "unsupported wide command %#x\n", cmd->id)) 1552 return -EINVAL; 1553 1554 if (group_id != 0) { 1555 copy_size = sizeof(struct iwl_cmd_header_wide); 1556 cmd_size = sizeof(struct iwl_cmd_header_wide); 1557 } else { 1558 copy_size = sizeof(struct iwl_cmd_header); 1559 cmd_size = sizeof(struct iwl_cmd_header); 1560 } 1561 1562 /* need one for the header if the first is NOCOPY */ 1563 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1564 1565 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1566 cmddata[i] = cmd->data[i]; 1567 cmdlen[i] = cmd->len[i]; 1568 1569 if (!cmd->len[i]) 1570 continue; 1571 1572 /* need at least IWL_FIRST_TB_SIZE copied */ 1573 if (copy_size < IWL_FIRST_TB_SIZE) { 1574 int copy = IWL_FIRST_TB_SIZE - copy_size; 1575 1576 if (copy > cmdlen[i]) 1577 copy = cmdlen[i]; 1578 cmdlen[i] -= copy; 1579 cmddata[i] += copy; 1580 copy_size += copy; 1581 } 1582 1583 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1584 had_nocopy = true; 1585 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1586 idx = -EINVAL; 1587 goto free_dup_buf; 1588 } 1589 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1590 /* 1591 * This is also a chunk that isn't copied 1592 * to the static buffer so set had_nocopy. 1593 */ 1594 had_nocopy = true; 1595 1596 /* only allowed once */ 1597 if (WARN_ON(dup_buf)) { 1598 idx = -EINVAL; 1599 goto free_dup_buf; 1600 } 1601 1602 dup_buf = kmemdup(cmddata[i], cmdlen[i], 1603 GFP_ATOMIC); 1604 if (!dup_buf) 1605 return -ENOMEM; 1606 } else { 1607 /* NOCOPY must not be followed by normal! */ 1608 if (WARN_ON(had_nocopy)) { 1609 idx = -EINVAL; 1610 goto free_dup_buf; 1611 } 1612 copy_size += cmdlen[i]; 1613 } 1614 cmd_size += cmd->len[i]; 1615 } 1616 1617 /* 1618 * If any of the command structures end up being larger than 1619 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1620 * allocated into separate TFDs, then we will need to 1621 * increase the size of the buffers. 1622 */ 1623 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1624 "Command %s (%#x) is too large (%d bytes)\n", 1625 iwl_get_cmd_string(trans, cmd->id), 1626 cmd->id, copy_size)) { 1627 idx = -EINVAL; 1628 goto free_dup_buf; 1629 } 1630 1631 spin_lock_bh(&txq->lock); 1632 1633 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1634 spin_unlock_bh(&txq->lock); 1635 1636 IWL_ERR(trans, "No space in command queue\n"); 1637 iwl_op_mode_cmd_queue_full(trans->op_mode); 1638 idx = -ENOSPC; 1639 goto free_dup_buf; 1640 } 1641 1642 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1643 out_cmd = txq->entries[idx].cmd; 1644 out_meta = &txq->entries[idx].meta; 1645 1646 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1647 if (cmd->flags & CMD_WANT_SKB) 1648 out_meta->source = cmd; 1649 1650 /* set up the header */ 1651 if (group_id != 0) { 1652 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1653 out_cmd->hdr_wide.group_id = group_id; 1654 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1655 out_cmd->hdr_wide.length = 1656 cpu_to_le16(cmd_size - 1657 sizeof(struct iwl_cmd_header_wide)); 1658 out_cmd->hdr_wide.reserved = 0; 1659 out_cmd->hdr_wide.sequence = 1660 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1661 INDEX_TO_SEQ(txq->write_ptr)); 1662 1663 cmd_pos = sizeof(struct iwl_cmd_header_wide); 1664 copy_size = sizeof(struct iwl_cmd_header_wide); 1665 } else { 1666 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1667 out_cmd->hdr.sequence = 1668 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1669 INDEX_TO_SEQ(txq->write_ptr)); 1670 out_cmd->hdr.group_id = 0; 1671 1672 cmd_pos = sizeof(struct iwl_cmd_header); 1673 copy_size = sizeof(struct iwl_cmd_header); 1674 } 1675 1676 /* and copy the data that needs to be copied */ 1677 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1678 int copy; 1679 1680 if (!cmd->len[i]) 1681 continue; 1682 1683 /* copy everything if not nocopy/dup */ 1684 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1685 IWL_HCMD_DFL_DUP))) { 1686 copy = cmd->len[i]; 1687 1688 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1689 cmd_pos += copy; 1690 copy_size += copy; 1691 continue; 1692 } 1693 1694 /* 1695 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 1696 * in total (for bi-directional DMA), but copy up to what 1697 * we can fit into the payload for debug dump purposes. 1698 */ 1699 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1700 1701 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1702 cmd_pos += copy; 1703 1704 /* However, treat copy_size the proper way, we need it below */ 1705 if (copy_size < IWL_FIRST_TB_SIZE) { 1706 copy = IWL_FIRST_TB_SIZE - copy_size; 1707 1708 if (copy > cmd->len[i]) 1709 copy = cmd->len[i]; 1710 copy_size += copy; 1711 } 1712 } 1713 1714 IWL_DEBUG_HC(trans, 1715 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1716 iwl_get_cmd_string(trans, cmd->id), 1717 group_id, out_cmd->hdr.cmd, 1718 le16_to_cpu(out_cmd->hdr.sequence), 1719 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1720 1721 /* start the TFD with the minimum copy bytes */ 1722 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 1723 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1724 iwl_pcie_txq_build_tfd(trans, txq, 1725 iwl_pcie_get_first_tb_dma(txq, idx), 1726 tb0_size, true); 1727 1728 /* map first command fragment, if any remains */ 1729 if (copy_size > tb0_size) { 1730 phys_addr = dma_map_single(trans->dev, 1731 ((u8 *)&out_cmd->hdr) + tb0_size, 1732 copy_size - tb0_size, 1733 DMA_TO_DEVICE); 1734 if (dma_mapping_error(trans->dev, phys_addr)) { 1735 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1736 txq->write_ptr); 1737 idx = -ENOMEM; 1738 goto out; 1739 } 1740 1741 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1742 copy_size - tb0_size, false); 1743 } 1744 1745 /* map the remaining (adjusted) nocopy/dup fragments */ 1746 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1747 const void *data = cmddata[i]; 1748 1749 if (!cmdlen[i]) 1750 continue; 1751 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1752 IWL_HCMD_DFL_DUP))) 1753 continue; 1754 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1755 data = dup_buf; 1756 phys_addr = dma_map_single(trans->dev, (void *)data, 1757 cmdlen[i], DMA_TO_DEVICE); 1758 if (dma_mapping_error(trans->dev, phys_addr)) { 1759 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1760 txq->write_ptr); 1761 idx = -ENOMEM; 1762 goto out; 1763 } 1764 1765 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1766 } 1767 1768 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1769 out_meta->flags = cmd->flags; 1770 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1771 kzfree(txq->entries[idx].free_buf); 1772 txq->entries[idx].free_buf = dup_buf; 1773 1774 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1775 1776 /* start timer if queue currently empty */ 1777 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1778 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1779 1780 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1781 ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1782 if (ret < 0) { 1783 idx = ret; 1784 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1785 goto out; 1786 } 1787 1788 /* Increment and update queue's write index */ 1789 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 1790 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1791 1792 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1793 1794 out: 1795 spin_unlock_bh(&txq->lock); 1796 free_dup_buf: 1797 if (idx < 0) 1798 kfree(dup_buf); 1799 return idx; 1800 } 1801 1802 /* 1803 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1804 * @rxb: Rx buffer to reclaim 1805 */ 1806 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1807 struct iwl_rx_cmd_buffer *rxb) 1808 { 1809 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1810 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1811 u8 group_id; 1812 u32 cmd_id; 1813 int txq_id = SEQ_TO_QUEUE(sequence); 1814 int index = SEQ_TO_INDEX(sequence); 1815 int cmd_index; 1816 struct iwl_device_cmd *cmd; 1817 struct iwl_cmd_meta *meta; 1818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1819 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1820 1821 /* If a Tx command is being handled and it isn't in the actual 1822 * command queue then there a command routing bug has been introduced 1823 * in the queue management code. */ 1824 if (WARN(txq_id != trans_pcie->cmd_queue, 1825 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1826 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1827 txq->write_ptr)) { 1828 iwl_print_hex_error(trans, pkt, 32); 1829 return; 1830 } 1831 1832 spin_lock_bh(&txq->lock); 1833 1834 cmd_index = iwl_pcie_get_cmd_index(txq, index); 1835 cmd = txq->entries[cmd_index].cmd; 1836 meta = &txq->entries[cmd_index].meta; 1837 group_id = cmd->hdr.group_id; 1838 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1839 1840 iwl_pcie_tfd_unmap(trans, meta, txq, index); 1841 1842 /* Input error checking is done when commands are added to queue. */ 1843 if (meta->flags & CMD_WANT_SKB) { 1844 struct page *p = rxb_steal_page(rxb); 1845 1846 meta->source->resp_pkt = pkt; 1847 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1848 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1849 } 1850 1851 if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1852 iwl_op_mode_async_cb(trans->op_mode, cmd); 1853 1854 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1855 1856 if (!(meta->flags & CMD_ASYNC)) { 1857 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1858 IWL_WARN(trans, 1859 "HCMD_ACTIVE already clear for command %s\n", 1860 iwl_get_cmd_string(trans, cmd_id)); 1861 } 1862 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1863 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1864 iwl_get_cmd_string(trans, cmd_id)); 1865 wake_up(&trans_pcie->wait_command_queue); 1866 } 1867 1868 meta->flags = 0; 1869 1870 spin_unlock_bh(&txq->lock); 1871 } 1872 1873 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1874 1875 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1876 struct iwl_host_cmd *cmd) 1877 { 1878 int ret; 1879 1880 /* An asynchronous command can not expect an SKB to be set. */ 1881 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1882 return -EINVAL; 1883 1884 ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1885 if (ret < 0) { 1886 IWL_ERR(trans, 1887 "Error sending %s: enqueue_hcmd failed: %d\n", 1888 iwl_get_cmd_string(trans, cmd->id), ret); 1889 return ret; 1890 } 1891 return 0; 1892 } 1893 1894 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1895 struct iwl_host_cmd *cmd) 1896 { 1897 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1898 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1899 int cmd_idx; 1900 int ret; 1901 1902 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 1903 iwl_get_cmd_string(trans, cmd->id)); 1904 1905 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1906 &trans->status), 1907 "Command %s: a command is already active!\n", 1908 iwl_get_cmd_string(trans, cmd->id))) 1909 return -EIO; 1910 1911 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 1912 iwl_get_cmd_string(trans, cmd->id)); 1913 1914 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1915 if (cmd_idx < 0) { 1916 ret = cmd_idx; 1917 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1918 IWL_ERR(trans, 1919 "Error sending %s: enqueue_hcmd failed: %d\n", 1920 iwl_get_cmd_string(trans, cmd->id), ret); 1921 return ret; 1922 } 1923 1924 ret = wait_event_timeout(trans_pcie->wait_command_queue, 1925 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1926 &trans->status), 1927 HOST_COMPLETE_TIMEOUT); 1928 if (!ret) { 1929 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 1930 iwl_get_cmd_string(trans, cmd->id), 1931 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1932 1933 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1934 txq->read_ptr, txq->write_ptr); 1935 1936 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1937 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1938 iwl_get_cmd_string(trans, cmd->id)); 1939 ret = -ETIMEDOUT; 1940 1941 iwl_trans_pcie_sync_nmi(trans); 1942 goto cancel; 1943 } 1944 1945 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1946 iwl_trans_pcie_dump_regs(trans); 1947 IWL_ERR(trans, "FW error in SYNC CMD %s\n", 1948 iwl_get_cmd_string(trans, cmd->id)); 1949 dump_stack(); 1950 ret = -EIO; 1951 goto cancel; 1952 } 1953 1954 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1955 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1956 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1957 ret = -ERFKILL; 1958 goto cancel; 1959 } 1960 1961 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1962 IWL_ERR(trans, "Error: Response NULL in '%s'\n", 1963 iwl_get_cmd_string(trans, cmd->id)); 1964 ret = -EIO; 1965 goto cancel; 1966 } 1967 1968 return 0; 1969 1970 cancel: 1971 if (cmd->flags & CMD_WANT_SKB) { 1972 /* 1973 * Cancel the CMD_WANT_SKB flag for the cmd in the 1974 * TX cmd queue. Otherwise in case the cmd comes 1975 * in later, it will possibly set an invalid 1976 * address (cmd->meta.source). 1977 */ 1978 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1979 } 1980 1981 if (cmd->resp_pkt) { 1982 iwl_free_resp(cmd); 1983 cmd->resp_pkt = NULL; 1984 } 1985 1986 return ret; 1987 } 1988 1989 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1990 { 1991 /* Make sure the NIC is still alive in the bus */ 1992 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1993 return -ENODEV; 1994 1995 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1996 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1997 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1998 cmd->id); 1999 return -ERFKILL; 2000 } 2001 2002 if (cmd->flags & CMD_ASYNC) 2003 return iwl_pcie_send_hcmd_async(trans, cmd); 2004 2005 /* We still can fail on RFKILL that can be asserted while we wait */ 2006 return iwl_pcie_send_hcmd_sync(trans, cmd); 2007 } 2008 2009 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 2010 struct iwl_txq *txq, u8 hdr_len, 2011 struct iwl_cmd_meta *out_meta) 2012 { 2013 u16 head_tb_len; 2014 int i; 2015 2016 /* 2017 * Set up TFD's third entry to point directly to remainder 2018 * of skb's head, if any 2019 */ 2020 head_tb_len = skb_headlen(skb) - hdr_len; 2021 2022 if (head_tb_len > 0) { 2023 dma_addr_t tb_phys = dma_map_single(trans->dev, 2024 skb->data + hdr_len, 2025 head_tb_len, DMA_TO_DEVICE); 2026 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 2027 return -EINVAL; 2028 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len, 2029 tb_phys, head_tb_len); 2030 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false); 2031 } 2032 2033 /* set up the remaining entries to point to the data */ 2034 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2035 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2036 dma_addr_t tb_phys; 2037 int tb_idx; 2038 2039 if (!skb_frag_size(frag)) 2040 continue; 2041 2042 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 2043 skb_frag_size(frag), DMA_TO_DEVICE); 2044 2045 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 2046 return -EINVAL; 2047 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag), 2048 tb_phys, skb_frag_size(frag)); 2049 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2050 skb_frag_size(frag), false); 2051 if (tb_idx < 0) 2052 return tb_idx; 2053 2054 out_meta->tbs |= BIT(tb_idx); 2055 } 2056 2057 return 0; 2058 } 2059 2060 #ifdef CONFIG_INET 2061 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len, 2062 struct sk_buff *skb) 2063 { 2064 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2065 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 2066 struct page **page_ptr; 2067 2068 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 2069 2070 if (WARN_ON(*page_ptr)) 2071 return NULL; 2072 2073 if (!p->page) 2074 goto alloc; 2075 2076 /* 2077 * Check if there's enough room on this page 2078 * 2079 * Note that we put a page chaining pointer *last* in the 2080 * page - we need it somewhere, and if it's there then we 2081 * avoid DMA mapping the last bits of the page which may 2082 * trigger the 32-bit boundary hardware bug. 2083 * 2084 * (see also get_workaround_page() in tx-gen2.c) 2085 */ 2086 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE - 2087 sizeof(void *)) 2088 goto out; 2089 2090 /* We don't have enough room on this page, get a new one. */ 2091 __free_page(p->page); 2092 2093 alloc: 2094 p->page = alloc_page(GFP_ATOMIC); 2095 if (!p->page) 2096 return NULL; 2097 p->pos = page_address(p->page); 2098 /* set the chaining pointer to NULL */ 2099 *(void **)(page_address(p->page) + PAGE_SIZE - sizeof(void *)) = NULL; 2100 out: 2101 *page_ptr = p->page; 2102 get_page(p->page); 2103 return p; 2104 } 2105 2106 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 2107 bool ipv6, unsigned int len) 2108 { 2109 if (ipv6) { 2110 struct ipv6hdr *iphv6 = iph; 2111 2112 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 2113 len + tcph->doff * 4, 2114 IPPROTO_TCP, 0); 2115 } else { 2116 struct iphdr *iphv4 = iph; 2117 2118 ip_send_check(iphv4); 2119 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 2120 len + tcph->doff * 4, 2121 IPPROTO_TCP, 0); 2122 } 2123 } 2124 2125 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2126 struct iwl_txq *txq, u8 hdr_len, 2127 struct iwl_cmd_meta *out_meta, 2128 struct iwl_device_tx_cmd *dev_cmd, 2129 u16 tb1_len) 2130 { 2131 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 2132 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 2133 struct ieee80211_hdr *hdr = (void *)skb->data; 2134 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 2135 unsigned int mss = skb_shinfo(skb)->gso_size; 2136 u16 length, iv_len, amsdu_pad; 2137 u8 *start_hdr; 2138 struct iwl_tso_hdr_page *hdr_page; 2139 struct tso_t tso; 2140 2141 /* if the packet is protected, then it must be CCMP or GCMP */ 2142 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 2143 iv_len = ieee80211_has_protected(hdr->frame_control) ? 2144 IEEE80211_CCMP_HDR_LEN : 0; 2145 2146 trace_iwlwifi_dev_tx(trans->dev, skb, 2147 iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 2148 trans_pcie->tfd_size, 2149 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 2150 2151 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 2152 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 2153 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 2154 amsdu_pad = 0; 2155 2156 /* total amount of header we may need for this A-MSDU */ 2157 hdr_room = DIV_ROUND_UP(total_len, mss) * 2158 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 2159 2160 /* Our device supports 9 segments at most, it will fit in 1 page */ 2161 hdr_page = get_page_hdr(trans, hdr_room, skb); 2162 if (!hdr_page) 2163 return -ENOMEM; 2164 2165 start_hdr = hdr_page->pos; 2166 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 2167 hdr_page->pos += iv_len; 2168 2169 /* 2170 * Pull the ieee80211 header + IV to be able to use TSO core, 2171 * we will restore it for the tx_status flow. 2172 */ 2173 skb_pull(skb, hdr_len + iv_len); 2174 2175 /* 2176 * Remove the length of all the headers that we don't actually 2177 * have in the MPDU by themselves, but that we duplicate into 2178 * all the different MSDUs inside the A-MSDU. 2179 */ 2180 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 2181 2182 tso_start(skb, &tso); 2183 2184 while (total_len) { 2185 /* this is the data left for this subframe */ 2186 unsigned int data_left = 2187 min_t(unsigned int, mss, total_len); 2188 struct sk_buff *csum_skb = NULL; 2189 unsigned int hdr_tb_len; 2190 dma_addr_t hdr_tb_phys; 2191 struct tcphdr *tcph; 2192 u8 *iph, *subf_hdrs_start = hdr_page->pos; 2193 2194 total_len -= data_left; 2195 2196 memset(hdr_page->pos, 0, amsdu_pad); 2197 hdr_page->pos += amsdu_pad; 2198 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 2199 data_left)) & 0x3; 2200 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 2201 hdr_page->pos += ETH_ALEN; 2202 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 2203 hdr_page->pos += ETH_ALEN; 2204 2205 length = snap_ip_tcp_hdrlen + data_left; 2206 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 2207 hdr_page->pos += sizeof(length); 2208 2209 /* 2210 * This will copy the SNAP as well which will be considered 2211 * as MAC header. 2212 */ 2213 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 2214 iph = hdr_page->pos + 8; 2215 tcph = (void *)(iph + ip_hdrlen); 2216 2217 /* For testing on current hardware only */ 2218 if (trans_pcie->sw_csum_tx) { 2219 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 2220 GFP_ATOMIC); 2221 if (!csum_skb) 2222 return -ENOMEM; 2223 2224 iwl_compute_pseudo_hdr_csum(iph, tcph, 2225 skb->protocol == 2226 htons(ETH_P_IPV6), 2227 data_left); 2228 2229 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2230 skb_reset_transport_header(csum_skb); 2231 csum_skb->csum_start = 2232 (unsigned char *)tcp_hdr(csum_skb) - 2233 csum_skb->head; 2234 } 2235 2236 hdr_page->pos += snap_ip_tcp_hdrlen; 2237 2238 hdr_tb_len = hdr_page->pos - start_hdr; 2239 hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 2240 hdr_tb_len, DMA_TO_DEVICE); 2241 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 2242 dev_kfree_skb(csum_skb); 2243 return -EINVAL; 2244 } 2245 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 2246 hdr_tb_len, false); 2247 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, 2248 hdr_tb_phys, hdr_tb_len); 2249 /* add this subframe's headers' length to the tx_cmd */ 2250 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 2251 2252 /* prepare the start_hdr for the next subframe */ 2253 start_hdr = hdr_page->pos; 2254 2255 /* put the payload */ 2256 while (data_left) { 2257 unsigned int size = min_t(unsigned int, tso.size, 2258 data_left); 2259 dma_addr_t tb_phys; 2260 2261 if (trans_pcie->sw_csum_tx) 2262 skb_put_data(csum_skb, tso.data, size); 2263 2264 tb_phys = dma_map_single(trans->dev, tso.data, 2265 size, DMA_TO_DEVICE); 2266 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2267 dev_kfree_skb(csum_skb); 2268 return -EINVAL; 2269 } 2270 2271 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2272 size, false); 2273 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 2274 tb_phys, size); 2275 2276 data_left -= size; 2277 tso_build_data(skb, &tso, size); 2278 } 2279 2280 /* For testing on early hardware only */ 2281 if (trans_pcie->sw_csum_tx) { 2282 __wsum csum; 2283 2284 csum = skb_checksum(csum_skb, 2285 skb_checksum_start_offset(csum_skb), 2286 csum_skb->len - 2287 skb_checksum_start_offset(csum_skb), 2288 0); 2289 dev_kfree_skb(csum_skb); 2290 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 2291 hdr_tb_len, DMA_TO_DEVICE); 2292 tcph->check = csum_fold(csum); 2293 dma_sync_single_for_device(trans->dev, hdr_tb_phys, 2294 hdr_tb_len, DMA_TO_DEVICE); 2295 } 2296 } 2297 2298 /* re -add the WiFi header and IV */ 2299 skb_push(skb, hdr_len + iv_len); 2300 2301 return 0; 2302 } 2303 #else /* CONFIG_INET */ 2304 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2305 struct iwl_txq *txq, u8 hdr_len, 2306 struct iwl_cmd_meta *out_meta, 2307 struct iwl_device_tx_cmd *dev_cmd, 2308 u16 tb1_len) 2309 { 2310 /* No A-MSDU without CONFIG_INET */ 2311 WARN_ON(1); 2312 2313 return -1; 2314 } 2315 #endif /* CONFIG_INET */ 2316 2317 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2318 struct iwl_device_tx_cmd *dev_cmd, int txq_id) 2319 { 2320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2321 struct ieee80211_hdr *hdr; 2322 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2323 struct iwl_cmd_meta *out_meta; 2324 struct iwl_txq *txq; 2325 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2326 void *tb1_addr; 2327 void *tfd; 2328 u16 len, tb1_len; 2329 bool wait_write_ptr; 2330 __le16 fc; 2331 u8 hdr_len; 2332 u16 wifi_seq; 2333 bool amsdu; 2334 2335 txq = trans_pcie->txq[txq_id]; 2336 2337 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2338 "TX on unused queue %d\n", txq_id)) 2339 return -EINVAL; 2340 2341 if (unlikely(trans_pcie->sw_csum_tx && 2342 skb->ip_summed == CHECKSUM_PARTIAL)) { 2343 int offs = skb_checksum_start_offset(skb); 2344 int csum_offs = offs + skb->csum_offset; 2345 __wsum csum; 2346 2347 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 2348 return -1; 2349 2350 csum = skb_checksum(skb, offs, skb->len - offs, 0); 2351 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 2352 2353 skb->ip_summed = CHECKSUM_UNNECESSARY; 2354 } 2355 2356 if (skb_is_nonlinear(skb) && 2357 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2358 __skb_linearize(skb)) 2359 return -ENOMEM; 2360 2361 /* mac80211 always puts the full header into the SKB's head, 2362 * so there's no need to check if it's readable there 2363 */ 2364 hdr = (struct ieee80211_hdr *)skb->data; 2365 fc = hdr->frame_control; 2366 hdr_len = ieee80211_hdrlen(fc); 2367 2368 spin_lock(&txq->lock); 2369 2370 if (iwl_queue_space(trans, txq) < txq->high_mark) { 2371 iwl_stop_queue(trans, txq); 2372 2373 /* don't put the packet on the ring, if there is no room */ 2374 if (unlikely(iwl_queue_space(trans, txq) < 3)) { 2375 struct iwl_device_tx_cmd **dev_cmd_ptr; 2376 2377 dev_cmd_ptr = (void *)((u8 *)skb->cb + 2378 trans_pcie->dev_cmd_offs); 2379 2380 *dev_cmd_ptr = dev_cmd; 2381 __skb_queue_tail(&txq->overflow_q, skb); 2382 2383 spin_unlock(&txq->lock); 2384 return 0; 2385 } 2386 } 2387 2388 /* In AGG mode, the index in the ring must correspond to the WiFi 2389 * sequence number. This is a HW requirements to help the SCD to parse 2390 * the BA. 2391 * Check here that the packets are in the right place on the ring. 2392 */ 2393 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2394 WARN_ONCE(txq->ampdu && 2395 (wifi_seq & 0xff) != txq->write_ptr, 2396 "Q: %d WiFi Seq %d tfdNum %d", 2397 txq_id, wifi_seq, txq->write_ptr); 2398 2399 /* Set up driver data for this TFD */ 2400 txq->entries[txq->write_ptr].skb = skb; 2401 txq->entries[txq->write_ptr].cmd = dev_cmd; 2402 2403 dev_cmd->hdr.sequence = 2404 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2405 INDEX_TO_SEQ(txq->write_ptr))); 2406 2407 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2408 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2409 offsetof(struct iwl_tx_cmd, scratch); 2410 2411 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2412 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2413 2414 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2415 out_meta = &txq->entries[txq->write_ptr].meta; 2416 out_meta->flags = 0; 2417 2418 /* 2419 * The second TB (tb1) points to the remainder of the TX command 2420 * and the 802.11 header - dword aligned size 2421 * (This calculation modifies the TX command, so do it before the 2422 * setup of the first TB) 2423 */ 2424 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 2425 hdr_len - IWL_FIRST_TB_SIZE; 2426 /* do not align A-MSDU to dword as the subframe header aligns it */ 2427 amsdu = ieee80211_is_data_qos(fc) && 2428 (*ieee80211_get_qos_ctl(hdr) & 2429 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2430 if (trans_pcie->sw_csum_tx || !amsdu) { 2431 tb1_len = ALIGN(len, 4); 2432 /* Tell NIC about any 2-byte padding after MAC header */ 2433 if (tb1_len != len) 2434 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2435 } else { 2436 tb1_len = len; 2437 } 2438 2439 /* 2440 * The first TB points to bi-directional DMA data, we'll 2441 * memcpy the data into it later. 2442 */ 2443 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 2444 IWL_FIRST_TB_SIZE, true); 2445 2446 /* there must be data left over for TB1 or this code must be changed */ 2447 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2448 2449 /* map the data for TB1 */ 2450 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2451 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2452 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2453 goto out_err; 2454 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2455 2456 trace_iwlwifi_dev_tx(trans->dev, skb, 2457 iwl_pcie_get_tfd(trans, txq, 2458 txq->write_ptr), 2459 trans_pcie->tfd_size, 2460 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2461 hdr_len); 2462 2463 /* 2464 * If gso_size wasn't set, don't give the frame "amsdu treatment" 2465 * (adding subframes, etc.). 2466 * This can happen in some testing flows when the amsdu was already 2467 * pre-built, and we just need to send the resulting skb. 2468 */ 2469 if (amsdu && skb_shinfo(skb)->gso_size) { 2470 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 2471 out_meta, dev_cmd, 2472 tb1_len))) 2473 goto out_err; 2474 } else { 2475 struct sk_buff *frag; 2476 2477 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2478 out_meta))) 2479 goto out_err; 2480 2481 skb_walk_frags(skb, frag) { 2482 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0, 2483 out_meta))) 2484 goto out_err; 2485 } 2486 } 2487 2488 /* building the A-MSDU might have changed this data, so memcpy it now */ 2489 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE); 2490 2491 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 2492 /* Set up entry for this TFD in Tx byte-count array */ 2493 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 2494 iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2495 2496 wait_write_ptr = ieee80211_has_morefrags(fc); 2497 2498 /* start timer if queue currently empty */ 2499 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) { 2500 /* 2501 * If the TXQ is active, then set the timer, if not, 2502 * set the timer in remainder so that the timer will 2503 * be armed with the right value when the station will 2504 * wake up. 2505 */ 2506 if (!txq->frozen) 2507 mod_timer(&txq->stuck_timer, 2508 jiffies + txq->wd_timeout); 2509 else 2510 txq->frozen_expiry_remainder = txq->wd_timeout; 2511 } 2512 2513 /* Tell device the write index *just past* this latest filled TFD */ 2514 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 2515 if (!wait_write_ptr) 2516 iwl_pcie_txq_inc_wr_ptr(trans, txq); 2517 2518 /* 2519 * At this point the frame is "transmitted" successfully 2520 * and we will get a TX status notification eventually. 2521 */ 2522 spin_unlock(&txq->lock); 2523 return 0; 2524 out_err: 2525 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 2526 spin_unlock(&txq->lock); 2527 return -1; 2528 } 2529