1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 Intel Deutschland GmbH 6 * 7 * Portions of this file are derived from the ipw3945 project, as well 8 * as portions of the ieee80211 subsystem header files. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22 * 23 * The full GNU General Public License is included in this distribution in the 24 * file called LICENSE. 25 * 26 * Contact Information: 27 * Intel Linux Wireless <linuxwifi@intel.com> 28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29 * 30 *****************************************************************************/ 31 #include <linux/etherdevice.h> 32 #include <linux/ieee80211.h> 33 #include <linux/slab.h> 34 #include <linux/sched.h> 35 #include <linux/pm_runtime.h> 36 #include <net/ip6_checksum.h> 37 #include <net/tso.h> 38 39 #include "iwl-debug.h" 40 #include "iwl-csr.h" 41 #include "iwl-prph.h" 42 #include "iwl-io.h" 43 #include "iwl-scd.h" 44 #include "iwl-op-mode.h" 45 #include "internal.h" 46 /* FIXME: need to abstract out TX command (once we know what it looks like) */ 47 #include "dvm/commands.h" 48 49 #define IWL_TX_CRC_SIZE 4 50 #define IWL_TX_DELIMITER_SIZE 4 51 52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 53 * DMA services 54 * 55 * Theory of operation 56 * 57 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 58 * of buffer descriptors, each of which points to one or more data buffers for 59 * the device to read from or fill. Driver and device exchange status of each 60 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 61 * entries in each circular buffer, to protect against confusing empty and full 62 * queue states. 63 * 64 * The device reads or writes the data in the queues via the device's several 65 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 66 * 67 * For Tx queue, there are low mark and high mark limits. If, after queuing 68 * the packet for Tx, free space become < low mark, Tx queue stopped. When 69 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 70 * Tx queue resumed. 71 * 72 ***************************************************/ 73 74 static int iwl_queue_space(const struct iwl_queue *q) 75 { 76 unsigned int max; 77 unsigned int used; 78 79 /* 80 * To avoid ambiguity between empty and completely full queues, there 81 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 82 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 83 * to reserve any queue entries for this purpose. 84 */ 85 if (q->n_window < TFD_QUEUE_SIZE_MAX) 86 max = q->n_window; 87 else 88 max = TFD_QUEUE_SIZE_MAX - 1; 89 90 /* 91 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 92 * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 93 */ 94 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 95 96 if (WARN_ON(used > max)) 97 return 0; 98 99 return max - used; 100 } 101 102 /* 103 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 104 */ 105 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) 106 { 107 q->n_window = slots_num; 108 q->id = id; 109 110 /* slots_num must be power-of-two size, otherwise 111 * get_cmd_index is broken. */ 112 if (WARN_ON(!is_power_of_2(slots_num))) 113 return -EINVAL; 114 115 q->low_mark = q->n_window / 4; 116 if (q->low_mark < 4) 117 q->low_mark = 4; 118 119 q->high_mark = q->n_window / 8; 120 if (q->high_mark < 2) 121 q->high_mark = 2; 122 123 q->write_ptr = 0; 124 q->read_ptr = 0; 125 126 return 0; 127 } 128 129 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 130 struct iwl_dma_ptr *ptr, size_t size) 131 { 132 if (WARN_ON(ptr->addr)) 133 return -EINVAL; 134 135 ptr->addr = dma_alloc_coherent(trans->dev, size, 136 &ptr->dma, GFP_KERNEL); 137 if (!ptr->addr) 138 return -ENOMEM; 139 ptr->size = size; 140 return 0; 141 } 142 143 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, 144 struct iwl_dma_ptr *ptr) 145 { 146 if (unlikely(!ptr->addr)) 147 return; 148 149 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 150 memset(ptr, 0, sizeof(*ptr)); 151 } 152 153 static void iwl_pcie_txq_stuck_timer(unsigned long data) 154 { 155 struct iwl_txq *txq = (void *)data; 156 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 157 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 158 159 spin_lock(&txq->lock); 160 /* check if triggered erroneously */ 161 if (txq->q.read_ptr == txq->q.write_ptr) { 162 spin_unlock(&txq->lock); 163 return; 164 } 165 spin_unlock(&txq->lock); 166 167 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, 168 jiffies_to_msecs(txq->wd_timeout)); 169 170 iwl_trans_pcie_log_scd_error(trans, txq); 171 172 iwl_force_nmi(trans); 173 } 174 175 /* 176 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 177 */ 178 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 179 struct iwl_txq *txq, u16 byte_cnt) 180 { 181 struct iwlagn_scd_bc_tbl *scd_bc_tbl; 182 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 183 int write_ptr = txq->q.write_ptr; 184 int txq_id = txq->q.id; 185 u8 sec_ctl = 0; 186 u8 sta_id = 0; 187 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 188 __le16 bc_ent; 189 struct iwl_tx_cmd *tx_cmd = 190 (void *) txq->entries[txq->q.write_ptr].cmd->payload; 191 192 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 193 194 sta_id = tx_cmd->sta_id; 195 sec_ctl = tx_cmd->sec_ctl; 196 197 switch (sec_ctl & TX_CMD_SEC_MSK) { 198 case TX_CMD_SEC_CCM: 199 len += IEEE80211_CCMP_MIC_LEN; 200 break; 201 case TX_CMD_SEC_TKIP: 202 len += IEEE80211_TKIP_ICV_LEN; 203 break; 204 case TX_CMD_SEC_WEP: 205 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 206 break; 207 } 208 209 if (trans_pcie->bc_table_dword) 210 len = DIV_ROUND_UP(len, 4); 211 212 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 213 return; 214 215 bc_ent = cpu_to_le16(len | (sta_id << 12)); 216 217 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 218 219 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 220 scd_bc_tbl[txq_id]. 221 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 222 } 223 224 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 225 struct iwl_txq *txq) 226 { 227 struct iwl_trans_pcie *trans_pcie = 228 IWL_TRANS_GET_PCIE_TRANS(trans); 229 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 230 int txq_id = txq->q.id; 231 int read_ptr = txq->q.read_ptr; 232 u8 sta_id = 0; 233 __le16 bc_ent; 234 struct iwl_tx_cmd *tx_cmd = 235 (void *)txq->entries[txq->q.read_ptr].cmd->payload; 236 237 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 238 239 if (txq_id != trans_pcie->cmd_queue) 240 sta_id = tx_cmd->sta_id; 241 242 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 243 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 244 245 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 246 scd_bc_tbl[txq_id]. 247 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 248 } 249 250 /* 251 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 252 */ 253 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 254 struct iwl_txq *txq) 255 { 256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 257 u32 reg = 0; 258 int txq_id = txq->q.id; 259 260 lockdep_assert_held(&txq->lock); 261 262 /* 263 * explicitly wake up the NIC if: 264 * 1. shadow registers aren't enabled 265 * 2. NIC is woken up for CMD regardless of shadow outside this function 266 * 3. there is a chance that the NIC is asleep 267 */ 268 if (!trans->cfg->base_params->shadow_reg_enable && 269 txq_id != trans_pcie->cmd_queue && 270 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 271 /* 272 * wake up nic if it's powered down ... 273 * uCode will wake up, and interrupt us again, so next 274 * time we'll skip this part. 275 */ 276 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 277 278 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 279 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 280 txq_id, reg); 281 iwl_set_bit(trans, CSR_GP_CNTRL, 282 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 283 txq->need_update = true; 284 return; 285 } 286 } 287 288 /* 289 * if not in power-save mode, uCode will never sleep when we're 290 * trying to tx (during RFKILL, we're not trying to tx). 291 */ 292 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); 293 if (!txq->block) 294 iwl_write32(trans, HBUS_TARG_WRPTR, 295 txq->q.write_ptr | (txq_id << 8)); 296 } 297 298 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 299 { 300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301 int i; 302 303 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 304 struct iwl_txq *txq = &trans_pcie->txq[i]; 305 306 spin_lock_bh(&txq->lock); 307 if (trans_pcie->txq[i].need_update) { 308 iwl_pcie_txq_inc_wr_ptr(trans, txq); 309 trans_pcie->txq[i].need_update = false; 310 } 311 spin_unlock_bh(&txq->lock); 312 } 313 } 314 315 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) 316 { 317 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 318 319 dma_addr_t addr = get_unaligned_le32(&tb->lo); 320 if (sizeof(dma_addr_t) > sizeof(u32)) 321 addr |= 322 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; 323 324 return addr; 325 } 326 327 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, 328 dma_addr_t addr, u16 len) 329 { 330 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 331 u16 hi_n_len = len << 4; 332 333 put_unaligned_le32(addr, &tb->lo); 334 if (sizeof(dma_addr_t) > sizeof(u32)) 335 hi_n_len |= ((addr >> 16) >> 16) & 0xF; 336 337 tb->hi_n_len = cpu_to_le16(hi_n_len); 338 339 tfd->num_tbs = idx + 1; 340 } 341 342 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) 343 { 344 return tfd->num_tbs & 0x1f; 345 } 346 347 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 348 struct iwl_cmd_meta *meta, 349 struct iwl_tfd *tfd) 350 { 351 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 352 int i, num_tbs; 353 354 /* Sanity check on number of chunks */ 355 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 356 357 if (num_tbs >= trans_pcie->max_tbs) { 358 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 359 /* @todo issue fatal error, it is quite serious situation */ 360 return; 361 } 362 363 /* first TB is never freed - it's the bidirectional DMA data */ 364 365 for (i = 1; i < num_tbs; i++) { 366 if (meta->tbs & BIT(i)) 367 dma_unmap_page(trans->dev, 368 iwl_pcie_tfd_tb_get_addr(tfd, i), 369 iwl_pcie_tfd_tb_get_len(tfd, i), 370 DMA_TO_DEVICE); 371 else 372 dma_unmap_single(trans->dev, 373 iwl_pcie_tfd_tb_get_addr(tfd, i), 374 iwl_pcie_tfd_tb_get_len(tfd, i), 375 DMA_TO_DEVICE); 376 } 377 tfd->num_tbs = 0; 378 } 379 380 /* 381 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 382 * @trans - transport private data 383 * @txq - tx queue 384 * @dma_dir - the direction of the DMA mapping 385 * 386 * Does NOT advance any TFD circular buffer read/write indexes 387 * Does NOT free the TFD itself (which is within circular buffer) 388 */ 389 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 390 { 391 struct iwl_tfd *tfd_tmp = txq->tfds; 392 393 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 394 * idx is bounded by n_window 395 */ 396 int rd_ptr = txq->q.read_ptr; 397 int idx = get_cmd_index(&txq->q, rd_ptr); 398 399 lockdep_assert_held(&txq->lock); 400 401 /* We have only q->n_window txq->entries, but we use 402 * TFD_QUEUE_SIZE_MAX tfds 403 */ 404 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); 405 406 /* free SKB */ 407 if (txq->entries) { 408 struct sk_buff *skb; 409 410 skb = txq->entries[idx].skb; 411 412 /* Can be called from irqs-disabled context 413 * If skb is not NULL, it means that the whole queue is being 414 * freed and that the queue is not empty - free the skb 415 */ 416 if (skb) { 417 iwl_op_mode_free_skb(trans->op_mode, skb); 418 txq->entries[idx].skb = NULL; 419 } 420 } 421 } 422 423 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 424 dma_addr_t addr, u16 len, bool reset) 425 { 426 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 427 struct iwl_queue *q; 428 struct iwl_tfd *tfd, *tfd_tmp; 429 u32 num_tbs; 430 431 q = &txq->q; 432 tfd_tmp = txq->tfds; 433 tfd = &tfd_tmp[q->write_ptr]; 434 435 if (reset) 436 memset(tfd, 0, sizeof(*tfd)); 437 438 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 439 440 /* Each TFD can point to a maximum 20 Tx buffers */ 441 if (num_tbs >= trans_pcie->max_tbs) { 442 IWL_ERR(trans, "Error can not send more than %d chunks\n", 443 trans_pcie->max_tbs); 444 return -EINVAL; 445 } 446 447 if (WARN(addr & ~IWL_TX_DMA_MASK, 448 "Unaligned address = %llx\n", (unsigned long long)addr)) 449 return -EINVAL; 450 451 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); 452 453 return num_tbs; 454 } 455 456 static int iwl_pcie_txq_alloc(struct iwl_trans *trans, 457 struct iwl_txq *txq, int slots_num, 458 u32 txq_id) 459 { 460 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 461 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; 462 size_t tb0_buf_sz; 463 int i; 464 465 if (WARN_ON(txq->entries || txq->tfds)) 466 return -EINVAL; 467 468 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 469 (unsigned long)txq); 470 txq->trans_pcie = trans_pcie; 471 472 txq->q.n_window = slots_num; 473 474 txq->entries = kcalloc(slots_num, 475 sizeof(struct iwl_pcie_txq_entry), 476 GFP_KERNEL); 477 478 if (!txq->entries) 479 goto error; 480 481 if (txq_id == trans_pcie->cmd_queue) 482 for (i = 0; i < slots_num; i++) { 483 txq->entries[i].cmd = 484 kmalloc(sizeof(struct iwl_device_cmd), 485 GFP_KERNEL); 486 if (!txq->entries[i].cmd) 487 goto error; 488 } 489 490 /* Circular buffer of transmit frame descriptors (TFDs), 491 * shared with device */ 492 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 493 &txq->q.dma_addr, GFP_KERNEL); 494 if (!txq->tfds) 495 goto error; 496 497 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 498 499 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 500 501 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 502 &txq->first_tb_dma, 503 GFP_KERNEL); 504 if (!txq->first_tb_bufs) 505 goto err_free_tfds; 506 507 txq->q.id = txq_id; 508 509 return 0; 510 err_free_tfds: 511 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); 512 error: 513 if (txq->entries && txq_id == trans_pcie->cmd_queue) 514 for (i = 0; i < slots_num; i++) 515 kfree(txq->entries[i].cmd); 516 kfree(txq->entries); 517 txq->entries = NULL; 518 519 return -ENOMEM; 520 521 } 522 523 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 524 int slots_num, u32 txq_id) 525 { 526 int ret; 527 528 txq->need_update = false; 529 530 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 531 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 532 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 533 534 /* Initialize queue's high/low-water marks, and head/tail indexes */ 535 ret = iwl_queue_init(&txq->q, slots_num, txq_id); 536 if (ret) 537 return ret; 538 539 spin_lock_init(&txq->lock); 540 __skb_queue_head_init(&txq->overflow_q); 541 542 /* 543 * Tell nic where to find circular buffer of Tx Frame Descriptors for 544 * given Tx queue, and enable the DMA channel used for that queue. 545 * Circular buffer (TFD queue in DRAM) physical base address */ 546 if (trans->cfg->use_tfh) 547 iwl_write_direct64(trans, 548 FH_MEM_CBBC_QUEUE(trans, txq_id), 549 txq->q.dma_addr); 550 else 551 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 552 txq->q.dma_addr >> 8); 553 554 return 0; 555 } 556 557 static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 558 struct sk_buff *skb) 559 { 560 struct page **page_ptr; 561 562 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 563 564 if (*page_ptr) { 565 __free_page(*page_ptr); 566 *page_ptr = NULL; 567 } 568 } 569 570 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 571 { 572 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 573 574 lockdep_assert_held(&trans_pcie->reg_lock); 575 576 if (trans_pcie->ref_cmd_in_flight) { 577 trans_pcie->ref_cmd_in_flight = false; 578 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 579 iwl_trans_unref(trans); 580 } 581 582 if (!trans->cfg->base_params->apmg_wake_up_wa) 583 return; 584 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 585 return; 586 587 trans_pcie->cmd_hold_nic_awake = false; 588 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 589 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 590 } 591 592 /* 593 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 594 */ 595 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 596 { 597 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 598 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 599 struct iwl_queue *q = &txq->q; 600 601 spin_lock_bh(&txq->lock); 602 while (q->write_ptr != q->read_ptr) { 603 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 604 txq_id, q->read_ptr); 605 606 if (txq_id != trans_pcie->cmd_queue) { 607 struct sk_buff *skb = txq->entries[q->read_ptr].skb; 608 609 if (WARN_ON_ONCE(!skb)) 610 continue; 611 612 iwl_pcie_free_tso_page(trans_pcie, skb); 613 } 614 iwl_pcie_txq_free_tfd(trans, txq); 615 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); 616 617 if (q->read_ptr == q->write_ptr) { 618 unsigned long flags; 619 620 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 621 if (txq_id != trans_pcie->cmd_queue) { 622 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 623 q->id); 624 iwl_trans_unref(trans); 625 } else { 626 iwl_pcie_clear_cmd_in_flight(trans); 627 } 628 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 629 } 630 } 631 txq->active = false; 632 633 while (!skb_queue_empty(&txq->overflow_q)) { 634 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 635 636 iwl_op_mode_free_skb(trans->op_mode, skb); 637 } 638 639 spin_unlock_bh(&txq->lock); 640 641 /* just in case - this queue may have been stopped */ 642 iwl_wake_queue(trans, txq); 643 } 644 645 /* 646 * iwl_pcie_txq_free - Deallocate DMA queue. 647 * @txq: Transmit queue to deallocate. 648 * 649 * Empty queue by removing and destroying all BD's. 650 * Free all buffers. 651 * 0-fill, but do not free "txq" descriptor structure. 652 */ 653 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 654 { 655 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 656 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 657 struct device *dev = trans->dev; 658 int i; 659 660 if (WARN_ON(!txq)) 661 return; 662 663 iwl_pcie_txq_unmap(trans, txq_id); 664 665 /* De-alloc array of command/tx buffers */ 666 if (txq_id == trans_pcie->cmd_queue) 667 for (i = 0; i < txq->q.n_window; i++) { 668 kzfree(txq->entries[i].cmd); 669 kzfree(txq->entries[i].free_buf); 670 } 671 672 /* De-alloc circular buffer of TFDs */ 673 if (txq->tfds) { 674 dma_free_coherent(dev, 675 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, 676 txq->tfds, txq->q.dma_addr); 677 txq->q.dma_addr = 0; 678 txq->tfds = NULL; 679 680 dma_free_coherent(dev, 681 sizeof(*txq->first_tb_bufs) * txq->q.n_window, 682 txq->first_tb_bufs, txq->first_tb_dma); 683 } 684 685 kfree(txq->entries); 686 txq->entries = NULL; 687 688 del_timer_sync(&txq->stuck_timer); 689 690 /* 0-fill queue descriptor structure */ 691 memset(txq, 0, sizeof(*txq)); 692 } 693 694 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 695 { 696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 697 int nq = trans->cfg->base_params->num_of_queues; 698 int chan; 699 u32 reg_val; 700 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 701 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 702 703 /* make sure all queue are not stopped/used */ 704 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 705 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 706 707 if (trans->cfg->use_tfh) 708 return; 709 710 trans_pcie->scd_base_addr = 711 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 712 713 WARN_ON(scd_base_addr != 0 && 714 scd_base_addr != trans_pcie->scd_base_addr); 715 716 /* reset context data, TX status and translation data */ 717 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 718 SCD_CONTEXT_MEM_LOWER_BOUND, 719 NULL, clear_dwords); 720 721 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 722 trans_pcie->scd_bc_tbls.dma >> 10); 723 724 /* The chain extension of the SCD doesn't work well. This feature is 725 * enabled by default by the HW, so we need to disable it manually. 726 */ 727 if (trans->cfg->base_params->scd_chain_ext_wa) 728 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 729 730 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 731 trans_pcie->cmd_fifo, 732 trans_pcie->cmd_q_wdg_timeout); 733 734 /* Activate all Tx DMA/FIFO channels */ 735 iwl_scd_activate_fifos(trans); 736 737 /* Enable DMA channel */ 738 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 739 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 740 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 741 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 742 743 /* Update FH chicken bits */ 744 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 745 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 746 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 747 748 /* Enable L1-Active */ 749 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 750 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 751 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 752 } 753 754 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 755 { 756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 757 int txq_id; 758 759 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 760 txq_id++) { 761 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 762 if (trans->cfg->use_tfh) 763 iwl_write_direct64(trans, 764 FH_MEM_CBBC_QUEUE(trans, txq_id), 765 txq->q.dma_addr); 766 else 767 iwl_write_direct32(trans, 768 FH_MEM_CBBC_QUEUE(trans, txq_id), 769 txq->q.dma_addr >> 8); 770 iwl_pcie_txq_unmap(trans, txq_id); 771 txq->q.read_ptr = 0; 772 txq->q.write_ptr = 0; 773 } 774 775 /* Tell NIC where to find the "keep warm" buffer */ 776 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 777 trans_pcie->kw.dma >> 4); 778 779 /* 780 * Send 0 as the scd_base_addr since the device may have be reset 781 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 782 * contain garbage. 783 */ 784 iwl_pcie_tx_start(trans, 0); 785 } 786 787 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 788 { 789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 790 unsigned long flags; 791 int ch, ret; 792 u32 mask = 0; 793 794 spin_lock(&trans_pcie->irq_lock); 795 796 if (!iwl_trans_grab_nic_access(trans, &flags)) 797 goto out; 798 799 /* Stop each Tx DMA channel */ 800 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 801 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 802 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 803 } 804 805 /* Wait for DMA channels to be idle */ 806 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 807 if (ret < 0) 808 IWL_ERR(trans, 809 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 810 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 811 812 iwl_trans_release_nic_access(trans, &flags); 813 814 out: 815 spin_unlock(&trans_pcie->irq_lock); 816 } 817 818 /* 819 * iwl_pcie_tx_stop - Stop all Tx DMA channels 820 */ 821 int iwl_pcie_tx_stop(struct iwl_trans *trans) 822 { 823 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 824 int txq_id; 825 826 /* Turn off all Tx DMA fifos */ 827 iwl_scd_deactivate_fifos(trans); 828 829 /* Turn off all Tx DMA channels */ 830 iwl_pcie_tx_stop_fh(trans); 831 832 /* 833 * This function can be called before the op_mode disabled the 834 * queues. This happens when we have an rfkill interrupt. 835 * Since we stop Tx altogether - mark the queues as stopped. 836 */ 837 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 838 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 839 840 /* This can happen: start_hw, stop_device */ 841 if (!trans_pcie->txq) 842 return 0; 843 844 /* Unmap DMA from host system and free skb's */ 845 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 846 txq_id++) 847 iwl_pcie_txq_unmap(trans, txq_id); 848 849 return 0; 850 } 851 852 /* 853 * iwl_trans_tx_free - Free TXQ Context 854 * 855 * Destroy all TX DMA queues and structures 856 */ 857 void iwl_pcie_tx_free(struct iwl_trans *trans) 858 { 859 int txq_id; 860 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 861 862 /* Tx queues */ 863 if (trans_pcie->txq) { 864 for (txq_id = 0; 865 txq_id < trans->cfg->base_params->num_of_queues; txq_id++) 866 iwl_pcie_txq_free(trans, txq_id); 867 } 868 869 kfree(trans_pcie->txq); 870 trans_pcie->txq = NULL; 871 872 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 873 874 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 875 } 876 877 /* 878 * iwl_pcie_tx_alloc - allocate TX context 879 * Allocate all Tx DMA structures and initialize them 880 */ 881 static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 882 { 883 int ret; 884 int txq_id, slots_num; 885 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 886 887 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 888 sizeof(struct iwlagn_scd_bc_tbl); 889 890 /*It is not allowed to alloc twice, so warn when this happens. 891 * We cannot rely on the previous allocation, so free and fail */ 892 if (WARN_ON(trans_pcie->txq)) { 893 ret = -EINVAL; 894 goto error; 895 } 896 897 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 898 scd_bc_tbls_size); 899 if (ret) { 900 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 901 goto error; 902 } 903 904 /* Alloc keep-warm buffer */ 905 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 906 if (ret) { 907 IWL_ERR(trans, "Keep Warm allocation failed\n"); 908 goto error; 909 } 910 911 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, 912 sizeof(struct iwl_txq), GFP_KERNEL); 913 if (!trans_pcie->txq) { 914 IWL_ERR(trans, "Not enough memory for txq\n"); 915 ret = -ENOMEM; 916 goto error; 917 } 918 919 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 920 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 921 txq_id++) { 922 slots_num = (txq_id == trans_pcie->cmd_queue) ? 923 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 924 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], 925 slots_num, txq_id); 926 if (ret) { 927 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 928 goto error; 929 } 930 } 931 932 return 0; 933 934 error: 935 iwl_pcie_tx_free(trans); 936 937 return ret; 938 } 939 int iwl_pcie_tx_init(struct iwl_trans *trans) 940 { 941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 942 int ret; 943 int txq_id, slots_num; 944 bool alloc = false; 945 946 if (!trans_pcie->txq) { 947 ret = iwl_pcie_tx_alloc(trans); 948 if (ret) 949 goto error; 950 alloc = true; 951 } 952 953 spin_lock(&trans_pcie->irq_lock); 954 955 /* Turn off all Tx DMA fifos */ 956 iwl_scd_deactivate_fifos(trans); 957 958 /* Tell NIC where to find the "keep warm" buffer */ 959 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 960 trans_pcie->kw.dma >> 4); 961 962 spin_unlock(&trans_pcie->irq_lock); 963 964 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 965 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 966 txq_id++) { 967 slots_num = (txq_id == trans_pcie->cmd_queue) ? 968 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 969 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], 970 slots_num, txq_id); 971 if (ret) { 972 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 973 goto error; 974 } 975 } 976 977 if (trans->cfg->use_tfh) { 978 iwl_write_direct32(trans, TFH_TRANSFER_MODE, 979 TFH_TRANSFER_MAX_PENDING_REQ | 980 TFH_CHUNK_SIZE_128 | 981 TFH_CHUNK_SPLIT_MODE); 982 return 0; 983 } 984 985 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 986 if (trans->cfg->base_params->num_of_queues > 20) 987 iwl_set_bits_prph(trans, SCD_GP_CTRL, 988 SCD_GP_CTRL_ENABLE_31_QUEUES); 989 990 return 0; 991 error: 992 /*Upon error, free only if we allocated something */ 993 if (alloc) 994 iwl_pcie_tx_free(trans); 995 return ret; 996 } 997 998 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 999 { 1000 lockdep_assert_held(&txq->lock); 1001 1002 if (!txq->wd_timeout) 1003 return; 1004 1005 /* 1006 * station is asleep and we send data - that must 1007 * be uAPSD or PS-Poll. Don't rearm the timer. 1008 */ 1009 if (txq->frozen) 1010 return; 1011 1012 /* 1013 * if empty delete timer, otherwise move timer forward 1014 * since we're making progress on this queue 1015 */ 1016 if (txq->q.read_ptr == txq->q.write_ptr) 1017 del_timer(&txq->stuck_timer); 1018 else 1019 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1020 } 1021 1022 /* Frees buffers until index _not_ inclusive */ 1023 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1024 struct sk_buff_head *skbs) 1025 { 1026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1027 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1028 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 1029 struct iwl_queue *q = &txq->q; 1030 int last_to_free; 1031 1032 /* This function is not meant to release cmd queue*/ 1033 if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1034 return; 1035 1036 spin_lock_bh(&txq->lock); 1037 1038 if (!txq->active) { 1039 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1040 txq_id, ssn); 1041 goto out; 1042 } 1043 1044 if (txq->q.read_ptr == tfd_num) 1045 goto out; 1046 1047 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1048 txq_id, txq->q.read_ptr, tfd_num, ssn); 1049 1050 /*Since we free until index _not_ inclusive, the one before index is 1051 * the last we will free. This one must be used */ 1052 last_to_free = iwl_queue_dec_wrap(tfd_num); 1053 1054 if (!iwl_queue_used(q, last_to_free)) { 1055 IWL_ERR(trans, 1056 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1057 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 1058 q->write_ptr, q->read_ptr); 1059 goto out; 1060 } 1061 1062 if (WARN_ON(!skb_queue_empty(skbs))) 1063 goto out; 1064 1065 for (; 1066 q->read_ptr != tfd_num; 1067 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 1068 struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb; 1069 1070 if (WARN_ON_ONCE(!skb)) 1071 continue; 1072 1073 iwl_pcie_free_tso_page(trans_pcie, skb); 1074 1075 __skb_queue_tail(skbs, skb); 1076 1077 txq->entries[txq->q.read_ptr].skb = NULL; 1078 1079 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1080 1081 iwl_pcie_txq_free_tfd(trans, txq); 1082 } 1083 1084 iwl_pcie_txq_progress(txq); 1085 1086 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1087 test_bit(txq_id, trans_pcie->queue_stopped)) { 1088 struct sk_buff_head overflow_skbs; 1089 1090 __skb_queue_head_init(&overflow_skbs); 1091 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 1092 1093 /* 1094 * This is tricky: we are in reclaim path which is non 1095 * re-entrant, so noone will try to take the access the 1096 * txq data from that path. We stopped tx, so we can't 1097 * have tx as well. Bottom line, we can unlock and re-lock 1098 * later. 1099 */ 1100 spin_unlock_bh(&txq->lock); 1101 1102 while (!skb_queue_empty(&overflow_skbs)) { 1103 struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 1104 struct iwl_device_cmd *dev_cmd_ptr; 1105 1106 dev_cmd_ptr = *(void **)((u8 *)skb->cb + 1107 trans_pcie->dev_cmd_offs); 1108 1109 /* 1110 * Note that we can very well be overflowing again. 1111 * In that case, iwl_queue_space will be small again 1112 * and we won't wake mac80211's queue. 1113 */ 1114 iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); 1115 } 1116 spin_lock_bh(&txq->lock); 1117 1118 if (iwl_queue_space(&txq->q) > txq->q.low_mark) 1119 iwl_wake_queue(trans, txq); 1120 } 1121 1122 if (q->read_ptr == q->write_ptr) { 1123 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); 1124 iwl_trans_unref(trans); 1125 } 1126 1127 out: 1128 spin_unlock_bh(&txq->lock); 1129 } 1130 1131 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1132 const struct iwl_host_cmd *cmd) 1133 { 1134 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1135 int ret; 1136 1137 lockdep_assert_held(&trans_pcie->reg_lock); 1138 1139 if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1140 !trans_pcie->ref_cmd_in_flight) { 1141 trans_pcie->ref_cmd_in_flight = true; 1142 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1143 iwl_trans_ref(trans); 1144 } 1145 1146 /* 1147 * wake up the NIC to make sure that the firmware will see the host 1148 * command - we will let the NIC sleep once all the host commands 1149 * returned. This needs to be done only on NICs that have 1150 * apmg_wake_up_wa set. 1151 */ 1152 if (trans->cfg->base_params->apmg_wake_up_wa && 1153 !trans_pcie->cmd_hold_nic_awake) { 1154 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1155 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1156 1157 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1158 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1159 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1160 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1161 15000); 1162 if (ret < 0) { 1163 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1164 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1165 IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1166 return -EIO; 1167 } 1168 trans_pcie->cmd_hold_nic_awake = true; 1169 } 1170 1171 return 0; 1172 } 1173 1174 /* 1175 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1176 * 1177 * When FW advances 'R' index, all entries between old and new 'R' index 1178 * need to be reclaimed. As result, some free space forms. If there is 1179 * enough free space (> low mark), wake the stack that feeds us. 1180 */ 1181 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1182 { 1183 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1184 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1185 struct iwl_queue *q = &txq->q; 1186 unsigned long flags; 1187 int nfreed = 0; 1188 1189 lockdep_assert_held(&txq->lock); 1190 1191 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { 1192 IWL_ERR(trans, 1193 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1194 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1195 q->write_ptr, q->read_ptr); 1196 return; 1197 } 1198 1199 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; 1200 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 1201 1202 if (nfreed++ > 0) { 1203 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1204 idx, q->write_ptr, q->read_ptr); 1205 iwl_force_nmi(trans); 1206 } 1207 } 1208 1209 if (q->read_ptr == q->write_ptr) { 1210 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1211 iwl_pcie_clear_cmd_in_flight(trans); 1212 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1213 } 1214 1215 iwl_pcie_txq_progress(txq); 1216 } 1217 1218 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1219 u16 txq_id) 1220 { 1221 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1222 u32 tbl_dw_addr; 1223 u32 tbl_dw; 1224 u16 scd_q2ratid; 1225 1226 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1227 1228 tbl_dw_addr = trans_pcie->scd_base_addr + 1229 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1230 1231 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1232 1233 if (txq_id & 0x1) 1234 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1235 else 1236 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1237 1238 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1239 1240 return 0; 1241 } 1242 1243 /* Receiver address (actually, Rx station's index into station table), 1244 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1245 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1246 1247 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1248 const struct iwl_trans_txq_scd_cfg *cfg, 1249 unsigned int wdg_timeout) 1250 { 1251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1252 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1253 int fifo = -1; 1254 1255 if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1256 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1257 1258 if (cfg && trans->cfg->use_tfh) 1259 WARN_ONCE(1, "Expected no calls to SCD configuration"); 1260 1261 txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1262 1263 if (cfg) { 1264 fifo = cfg->fifo; 1265 1266 /* Disable the scheduler prior configuring the cmd queue */ 1267 if (txq_id == trans_pcie->cmd_queue && 1268 trans_pcie->scd_set_active) 1269 iwl_scd_enable_set_active(trans, 0); 1270 1271 /* Stop this Tx queue before configuring it */ 1272 iwl_scd_txq_set_inactive(trans, txq_id); 1273 1274 /* Set this queue as a chain-building queue unless it is CMD */ 1275 if (txq_id != trans_pcie->cmd_queue) 1276 iwl_scd_txq_set_chain(trans, txq_id); 1277 1278 if (cfg->aggregate) { 1279 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1280 1281 /* Map receiver-address / traffic-ID to this queue */ 1282 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1283 1284 /* enable aggregations for the queue */ 1285 iwl_scd_txq_enable_agg(trans, txq_id); 1286 txq->ampdu = true; 1287 } else { 1288 /* 1289 * disable aggregations for the queue, this will also 1290 * make the ra_tid mapping configuration irrelevant 1291 * since it is now a non-AGG queue. 1292 */ 1293 iwl_scd_txq_disable_agg(trans, txq_id); 1294 1295 ssn = txq->q.read_ptr; 1296 } 1297 } 1298 1299 /* Place first TFD at index corresponding to start sequence number. 1300 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1301 txq->q.read_ptr = (ssn & 0xff); 1302 txq->q.write_ptr = (ssn & 0xff); 1303 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1304 (ssn & 0xff) | (txq_id << 8)); 1305 1306 if (cfg) { 1307 u8 frame_limit = cfg->frame_limit; 1308 1309 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1310 1311 /* Set up Tx window size and frame limit for this queue */ 1312 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1313 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1314 iwl_trans_write_mem32(trans, 1315 trans_pcie->scd_base_addr + 1316 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1317 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1318 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1319 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1320 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1321 1322 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1323 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1324 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1325 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1326 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1327 SCD_QUEUE_STTS_REG_MSK); 1328 1329 /* enable the scheduler for this queue (only) */ 1330 if (txq_id == trans_pcie->cmd_queue && 1331 trans_pcie->scd_set_active) 1332 iwl_scd_enable_set_active(trans, BIT(txq_id)); 1333 1334 IWL_DEBUG_TX_QUEUES(trans, 1335 "Activate queue %d on FIFO %d WrPtr: %d\n", 1336 txq_id, fifo, ssn & 0xff); 1337 } else { 1338 IWL_DEBUG_TX_QUEUES(trans, 1339 "Activate queue %d WrPtr: %d\n", 1340 txq_id, ssn & 0xff); 1341 } 1342 1343 txq->active = true; 1344 } 1345 1346 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 1347 bool shared_mode) 1348 { 1349 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1350 struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1351 1352 txq->ampdu = !shared_mode; 1353 } 1354 1355 dma_addr_t iwl_trans_pcie_get_txq_byte_table(struct iwl_trans *trans, int txq) 1356 { 1357 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1358 1359 return trans_pcie->scd_bc_tbls.dma + 1360 txq * sizeof(struct iwlagn_scd_bc_tbl); 1361 } 1362 1363 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1364 bool configure_scd) 1365 { 1366 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1367 u32 stts_addr = trans_pcie->scd_base_addr + 1368 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1369 static const u32 zero_val[4] = {}; 1370 1371 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; 1372 trans_pcie->txq[txq_id].frozen = false; 1373 1374 /* 1375 * Upon HW Rfkill - we stop the device, and then stop the queues 1376 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1377 * allow the op_mode to call txq_disable after it already called 1378 * stop_device. 1379 */ 1380 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1381 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1382 "queue %d not used", txq_id); 1383 return; 1384 } 1385 1386 if (configure_scd && trans->cfg->use_tfh) 1387 WARN_ONCE(1, "Expected no calls to SCD configuration"); 1388 1389 if (configure_scd) { 1390 iwl_scd_txq_set_inactive(trans, txq_id); 1391 1392 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1393 ARRAY_SIZE(zero_val)); 1394 } 1395 1396 iwl_pcie_txq_unmap(trans, txq_id); 1397 trans_pcie->txq[txq_id].ampdu = false; 1398 1399 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1400 } 1401 1402 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1403 1404 /* 1405 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1406 * @priv: device private data point 1407 * @cmd: a pointer to the ucode command structure 1408 * 1409 * The function returns < 0 values to indicate the operation 1410 * failed. On success, it returns the index (>= 0) of command in the 1411 * command queue. 1412 */ 1413 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1414 struct iwl_host_cmd *cmd) 1415 { 1416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1417 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1418 struct iwl_queue *q = &txq->q; 1419 struct iwl_device_cmd *out_cmd; 1420 struct iwl_cmd_meta *out_meta; 1421 unsigned long flags; 1422 void *dup_buf = NULL; 1423 dma_addr_t phys_addr; 1424 int idx; 1425 u16 copy_size, cmd_size, tb0_size; 1426 bool had_nocopy = false; 1427 u8 group_id = iwl_cmd_groupid(cmd->id); 1428 int i, ret; 1429 u32 cmd_pos; 1430 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1431 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1432 1433 if (WARN(!trans_pcie->wide_cmd_header && 1434 group_id > IWL_ALWAYS_LONG_GROUP, 1435 "unsupported wide command %#x\n", cmd->id)) 1436 return -EINVAL; 1437 1438 if (group_id != 0) { 1439 copy_size = sizeof(struct iwl_cmd_header_wide); 1440 cmd_size = sizeof(struct iwl_cmd_header_wide); 1441 } else { 1442 copy_size = sizeof(struct iwl_cmd_header); 1443 cmd_size = sizeof(struct iwl_cmd_header); 1444 } 1445 1446 /* need one for the header if the first is NOCOPY */ 1447 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1448 1449 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1450 cmddata[i] = cmd->data[i]; 1451 cmdlen[i] = cmd->len[i]; 1452 1453 if (!cmd->len[i]) 1454 continue; 1455 1456 /* need at least IWL_FIRST_TB_SIZE copied */ 1457 if (copy_size < IWL_FIRST_TB_SIZE) { 1458 int copy = IWL_FIRST_TB_SIZE - copy_size; 1459 1460 if (copy > cmdlen[i]) 1461 copy = cmdlen[i]; 1462 cmdlen[i] -= copy; 1463 cmddata[i] += copy; 1464 copy_size += copy; 1465 } 1466 1467 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1468 had_nocopy = true; 1469 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1470 idx = -EINVAL; 1471 goto free_dup_buf; 1472 } 1473 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1474 /* 1475 * This is also a chunk that isn't copied 1476 * to the static buffer so set had_nocopy. 1477 */ 1478 had_nocopy = true; 1479 1480 /* only allowed once */ 1481 if (WARN_ON(dup_buf)) { 1482 idx = -EINVAL; 1483 goto free_dup_buf; 1484 } 1485 1486 dup_buf = kmemdup(cmddata[i], cmdlen[i], 1487 GFP_ATOMIC); 1488 if (!dup_buf) 1489 return -ENOMEM; 1490 } else { 1491 /* NOCOPY must not be followed by normal! */ 1492 if (WARN_ON(had_nocopy)) { 1493 idx = -EINVAL; 1494 goto free_dup_buf; 1495 } 1496 copy_size += cmdlen[i]; 1497 } 1498 cmd_size += cmd->len[i]; 1499 } 1500 1501 /* 1502 * If any of the command structures end up being larger than 1503 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1504 * allocated into separate TFDs, then we will need to 1505 * increase the size of the buffers. 1506 */ 1507 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1508 "Command %s (%#x) is too large (%d bytes)\n", 1509 iwl_get_cmd_string(trans, cmd->id), 1510 cmd->id, copy_size)) { 1511 idx = -EINVAL; 1512 goto free_dup_buf; 1513 } 1514 1515 spin_lock_bh(&txq->lock); 1516 1517 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1518 spin_unlock_bh(&txq->lock); 1519 1520 IWL_ERR(trans, "No space in command queue\n"); 1521 iwl_op_mode_cmd_queue_full(trans->op_mode); 1522 idx = -ENOSPC; 1523 goto free_dup_buf; 1524 } 1525 1526 idx = get_cmd_index(q, q->write_ptr); 1527 out_cmd = txq->entries[idx].cmd; 1528 out_meta = &txq->entries[idx].meta; 1529 1530 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1531 if (cmd->flags & CMD_WANT_SKB) 1532 out_meta->source = cmd; 1533 1534 /* set up the header */ 1535 if (group_id != 0) { 1536 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1537 out_cmd->hdr_wide.group_id = group_id; 1538 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1539 out_cmd->hdr_wide.length = 1540 cpu_to_le16(cmd_size - 1541 sizeof(struct iwl_cmd_header_wide)); 1542 out_cmd->hdr_wide.reserved = 0; 1543 out_cmd->hdr_wide.sequence = 1544 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1545 INDEX_TO_SEQ(q->write_ptr)); 1546 1547 cmd_pos = sizeof(struct iwl_cmd_header_wide); 1548 copy_size = sizeof(struct iwl_cmd_header_wide); 1549 } else { 1550 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1551 out_cmd->hdr.sequence = 1552 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1553 INDEX_TO_SEQ(q->write_ptr)); 1554 out_cmd->hdr.group_id = 0; 1555 1556 cmd_pos = sizeof(struct iwl_cmd_header); 1557 copy_size = sizeof(struct iwl_cmd_header); 1558 } 1559 1560 /* and copy the data that needs to be copied */ 1561 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1562 int copy; 1563 1564 if (!cmd->len[i]) 1565 continue; 1566 1567 /* copy everything if not nocopy/dup */ 1568 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1569 IWL_HCMD_DFL_DUP))) { 1570 copy = cmd->len[i]; 1571 1572 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1573 cmd_pos += copy; 1574 copy_size += copy; 1575 continue; 1576 } 1577 1578 /* 1579 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 1580 * in total (for bi-directional DMA), but copy up to what 1581 * we can fit into the payload for debug dump purposes. 1582 */ 1583 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1584 1585 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1586 cmd_pos += copy; 1587 1588 /* However, treat copy_size the proper way, we need it below */ 1589 if (copy_size < IWL_FIRST_TB_SIZE) { 1590 copy = IWL_FIRST_TB_SIZE - copy_size; 1591 1592 if (copy > cmd->len[i]) 1593 copy = cmd->len[i]; 1594 copy_size += copy; 1595 } 1596 } 1597 1598 IWL_DEBUG_HC(trans, 1599 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1600 iwl_get_cmd_string(trans, cmd->id), 1601 group_id, out_cmd->hdr.cmd, 1602 le16_to_cpu(out_cmd->hdr.sequence), 1603 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); 1604 1605 /* start the TFD with the minimum copy bytes */ 1606 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 1607 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1608 iwl_pcie_txq_build_tfd(trans, txq, 1609 iwl_pcie_get_first_tb_dma(txq, idx), 1610 tb0_size, true); 1611 1612 /* map first command fragment, if any remains */ 1613 if (copy_size > tb0_size) { 1614 phys_addr = dma_map_single(trans->dev, 1615 ((u8 *)&out_cmd->hdr) + tb0_size, 1616 copy_size - tb0_size, 1617 DMA_TO_DEVICE); 1618 if (dma_mapping_error(trans->dev, phys_addr)) { 1619 iwl_pcie_tfd_unmap(trans, out_meta, 1620 &txq->tfds[q->write_ptr]); 1621 idx = -ENOMEM; 1622 goto out; 1623 } 1624 1625 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1626 copy_size - tb0_size, false); 1627 } 1628 1629 /* map the remaining (adjusted) nocopy/dup fragments */ 1630 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1631 const void *data = cmddata[i]; 1632 1633 if (!cmdlen[i]) 1634 continue; 1635 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1636 IWL_HCMD_DFL_DUP))) 1637 continue; 1638 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1639 data = dup_buf; 1640 phys_addr = dma_map_single(trans->dev, (void *)data, 1641 cmdlen[i], DMA_TO_DEVICE); 1642 if (dma_mapping_error(trans->dev, phys_addr)) { 1643 iwl_pcie_tfd_unmap(trans, out_meta, 1644 &txq->tfds[q->write_ptr]); 1645 idx = -ENOMEM; 1646 goto out; 1647 } 1648 1649 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1650 } 1651 1652 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1653 out_meta->flags = cmd->flags; 1654 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1655 kzfree(txq->entries[idx].free_buf); 1656 txq->entries[idx].free_buf = dup_buf; 1657 1658 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1659 1660 /* start timer if queue currently empty */ 1661 if (q->read_ptr == q->write_ptr && txq->wd_timeout) 1662 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1663 1664 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1665 ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1666 if (ret < 0) { 1667 idx = ret; 1668 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1669 goto out; 1670 } 1671 1672 /* Increment and update queue's write index */ 1673 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 1674 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1675 1676 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1677 1678 out: 1679 spin_unlock_bh(&txq->lock); 1680 free_dup_buf: 1681 if (idx < 0) 1682 kfree(dup_buf); 1683 return idx; 1684 } 1685 1686 /* 1687 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1688 * @rxb: Rx buffer to reclaim 1689 */ 1690 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1691 struct iwl_rx_cmd_buffer *rxb) 1692 { 1693 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1694 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1695 u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id); 1696 u32 cmd_id; 1697 int txq_id = SEQ_TO_QUEUE(sequence); 1698 int index = SEQ_TO_INDEX(sequence); 1699 int cmd_index; 1700 struct iwl_device_cmd *cmd; 1701 struct iwl_cmd_meta *meta; 1702 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1703 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1704 1705 /* If a Tx command is being handled and it isn't in the actual 1706 * command queue then there a command routing bug has been introduced 1707 * in the queue management code. */ 1708 if (WARN(txq_id != trans_pcie->cmd_queue, 1709 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1710 txq_id, trans_pcie->cmd_queue, sequence, 1711 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, 1712 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { 1713 iwl_print_hex_error(trans, pkt, 32); 1714 return; 1715 } 1716 1717 spin_lock_bh(&txq->lock); 1718 1719 cmd_index = get_cmd_index(&txq->q, index); 1720 cmd = txq->entries[cmd_index].cmd; 1721 meta = &txq->entries[cmd_index].meta; 1722 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1723 1724 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); 1725 1726 /* Input error checking is done when commands are added to queue. */ 1727 if (meta->flags & CMD_WANT_SKB) { 1728 struct page *p = rxb_steal_page(rxb); 1729 1730 meta->source->resp_pkt = pkt; 1731 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1732 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1733 } 1734 1735 if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1736 iwl_op_mode_async_cb(trans->op_mode, cmd); 1737 1738 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1739 1740 if (!(meta->flags & CMD_ASYNC)) { 1741 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1742 IWL_WARN(trans, 1743 "HCMD_ACTIVE already clear for command %s\n", 1744 iwl_get_cmd_string(trans, cmd_id)); 1745 } 1746 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1747 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1748 iwl_get_cmd_string(trans, cmd_id)); 1749 wake_up(&trans_pcie->wait_command_queue); 1750 } 1751 1752 if (meta->flags & CMD_MAKE_TRANS_IDLE) { 1753 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 1754 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1755 set_bit(STATUS_TRANS_IDLE, &trans->status); 1756 wake_up(&trans_pcie->d0i3_waitq); 1757 } 1758 1759 if (meta->flags & CMD_WAKE_UP_TRANS) { 1760 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 1761 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1762 clear_bit(STATUS_TRANS_IDLE, &trans->status); 1763 wake_up(&trans_pcie->d0i3_waitq); 1764 } 1765 1766 meta->flags = 0; 1767 1768 spin_unlock_bh(&txq->lock); 1769 } 1770 1771 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1772 1773 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1774 struct iwl_host_cmd *cmd) 1775 { 1776 int ret; 1777 1778 /* An asynchronous command can not expect an SKB to be set. */ 1779 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1780 return -EINVAL; 1781 1782 ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1783 if (ret < 0) { 1784 IWL_ERR(trans, 1785 "Error sending %s: enqueue_hcmd failed: %d\n", 1786 iwl_get_cmd_string(trans, cmd->id), ret); 1787 return ret; 1788 } 1789 return 0; 1790 } 1791 1792 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1793 struct iwl_host_cmd *cmd) 1794 { 1795 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1796 int cmd_idx; 1797 int ret; 1798 1799 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 1800 iwl_get_cmd_string(trans, cmd->id)); 1801 1802 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1803 &trans->status), 1804 "Command %s: a command is already active!\n", 1805 iwl_get_cmd_string(trans, cmd->id))) 1806 return -EIO; 1807 1808 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 1809 iwl_get_cmd_string(trans, cmd->id)); 1810 1811 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 1812 ret = wait_event_timeout(trans_pcie->d0i3_waitq, 1813 pm_runtime_active(&trans_pcie->pci_dev->dev), 1814 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 1815 if (!ret) { 1816 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 1817 return -ETIMEDOUT; 1818 } 1819 } 1820 1821 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1822 if (cmd_idx < 0) { 1823 ret = cmd_idx; 1824 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1825 IWL_ERR(trans, 1826 "Error sending %s: enqueue_hcmd failed: %d\n", 1827 iwl_get_cmd_string(trans, cmd->id), ret); 1828 return ret; 1829 } 1830 1831 ret = wait_event_timeout(trans_pcie->wait_command_queue, 1832 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1833 &trans->status), 1834 HOST_COMPLETE_TIMEOUT); 1835 if (!ret) { 1836 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1837 struct iwl_queue *q = &txq->q; 1838 1839 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 1840 iwl_get_cmd_string(trans, cmd->id), 1841 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1842 1843 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1844 q->read_ptr, q->write_ptr); 1845 1846 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1847 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1848 iwl_get_cmd_string(trans, cmd->id)); 1849 ret = -ETIMEDOUT; 1850 1851 iwl_force_nmi(trans); 1852 iwl_trans_fw_error(trans); 1853 1854 goto cancel; 1855 } 1856 1857 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1858 IWL_ERR(trans, "FW error in SYNC CMD %s\n", 1859 iwl_get_cmd_string(trans, cmd->id)); 1860 dump_stack(); 1861 ret = -EIO; 1862 goto cancel; 1863 } 1864 1865 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1866 test_bit(STATUS_RFKILL, &trans->status)) { 1867 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1868 ret = -ERFKILL; 1869 goto cancel; 1870 } 1871 1872 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1873 IWL_ERR(trans, "Error: Response NULL in '%s'\n", 1874 iwl_get_cmd_string(trans, cmd->id)); 1875 ret = -EIO; 1876 goto cancel; 1877 } 1878 1879 return 0; 1880 1881 cancel: 1882 if (cmd->flags & CMD_WANT_SKB) { 1883 /* 1884 * Cancel the CMD_WANT_SKB flag for the cmd in the 1885 * TX cmd queue. Otherwise in case the cmd comes 1886 * in later, it will possibly set an invalid 1887 * address (cmd->meta.source). 1888 */ 1889 trans_pcie->txq[trans_pcie->cmd_queue]. 1890 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1891 } 1892 1893 if (cmd->resp_pkt) { 1894 iwl_free_resp(cmd); 1895 cmd->resp_pkt = NULL; 1896 } 1897 1898 return ret; 1899 } 1900 1901 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1902 { 1903 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1904 test_bit(STATUS_RFKILL, &trans->status)) { 1905 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1906 cmd->id); 1907 return -ERFKILL; 1908 } 1909 1910 if (cmd->flags & CMD_ASYNC) 1911 return iwl_pcie_send_hcmd_async(trans, cmd); 1912 1913 /* We still can fail on RFKILL that can be asserted while we wait */ 1914 return iwl_pcie_send_hcmd_sync(trans, cmd); 1915 } 1916 1917 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 1918 struct iwl_txq *txq, u8 hdr_len, 1919 struct iwl_cmd_meta *out_meta, 1920 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 1921 { 1922 struct iwl_queue *q = &txq->q; 1923 u16 tb2_len; 1924 int i; 1925 1926 /* 1927 * Set up TFD's third entry to point directly to remainder 1928 * of skb's head, if any 1929 */ 1930 tb2_len = skb_headlen(skb) - hdr_len; 1931 1932 if (tb2_len > 0) { 1933 dma_addr_t tb2_phys = dma_map_single(trans->dev, 1934 skb->data + hdr_len, 1935 tb2_len, DMA_TO_DEVICE); 1936 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 1937 iwl_pcie_tfd_unmap(trans, out_meta, 1938 &txq->tfds[q->write_ptr]); 1939 return -EINVAL; 1940 } 1941 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 1942 } 1943 1944 /* set up the remaining entries to point to the data */ 1945 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1946 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1947 dma_addr_t tb_phys; 1948 int tb_idx; 1949 1950 if (!skb_frag_size(frag)) 1951 continue; 1952 1953 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 1954 skb_frag_size(frag), DMA_TO_DEVICE); 1955 1956 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 1957 iwl_pcie_tfd_unmap(trans, out_meta, 1958 &txq->tfds[q->write_ptr]); 1959 return -EINVAL; 1960 } 1961 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 1962 skb_frag_size(frag), false); 1963 1964 out_meta->tbs |= BIT(tb_idx); 1965 } 1966 1967 trace_iwlwifi_dev_tx(trans->dev, skb, 1968 &txq->tfds[txq->q.write_ptr], 1969 sizeof(struct iwl_tfd), 1970 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 1971 skb->data + hdr_len, tb2_len); 1972 trace_iwlwifi_dev_tx_data(trans->dev, skb, 1973 hdr_len, skb->len - hdr_len); 1974 return 0; 1975 } 1976 1977 #ifdef CONFIG_INET 1978 static struct iwl_tso_hdr_page * 1979 get_page_hdr(struct iwl_trans *trans, size_t len) 1980 { 1981 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1982 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 1983 1984 if (!p->page) 1985 goto alloc; 1986 1987 /* enough room on this page */ 1988 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 1989 return p; 1990 1991 /* We don't have enough room on this page, get a new one. */ 1992 __free_page(p->page); 1993 1994 alloc: 1995 p->page = alloc_page(GFP_ATOMIC); 1996 if (!p->page) 1997 return NULL; 1998 p->pos = page_address(p->page); 1999 return p; 2000 } 2001 2002 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 2003 bool ipv6, unsigned int len) 2004 { 2005 if (ipv6) { 2006 struct ipv6hdr *iphv6 = iph; 2007 2008 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 2009 len + tcph->doff * 4, 2010 IPPROTO_TCP, 0); 2011 } else { 2012 struct iphdr *iphv4 = iph; 2013 2014 ip_send_check(iphv4); 2015 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 2016 len + tcph->doff * 4, 2017 IPPROTO_TCP, 0); 2018 } 2019 } 2020 2021 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2022 struct iwl_txq *txq, u8 hdr_len, 2023 struct iwl_cmd_meta *out_meta, 2024 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2025 { 2026 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 2027 struct ieee80211_hdr *hdr = (void *)skb->data; 2028 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 2029 unsigned int mss = skb_shinfo(skb)->gso_size; 2030 struct iwl_queue *q = &txq->q; 2031 u16 length, iv_len, amsdu_pad; 2032 u8 *start_hdr; 2033 struct iwl_tso_hdr_page *hdr_page; 2034 struct page **page_ptr; 2035 int ret; 2036 struct tso_t tso; 2037 2038 /* if the packet is protected, then it must be CCMP or GCMP */ 2039 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 2040 iv_len = ieee80211_has_protected(hdr->frame_control) ? 2041 IEEE80211_CCMP_HDR_LEN : 0; 2042 2043 trace_iwlwifi_dev_tx(trans->dev, skb, 2044 &txq->tfds[txq->q.write_ptr], 2045 sizeof(struct iwl_tfd), 2046 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2047 NULL, 0); 2048 2049 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 2050 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 2051 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 2052 amsdu_pad = 0; 2053 2054 /* total amount of header we may need for this A-MSDU */ 2055 hdr_room = DIV_ROUND_UP(total_len, mss) * 2056 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 2057 2058 /* Our device supports 9 segments at most, it will fit in 1 page */ 2059 hdr_page = get_page_hdr(trans, hdr_room); 2060 if (!hdr_page) 2061 return -ENOMEM; 2062 2063 get_page(hdr_page->page); 2064 start_hdr = hdr_page->pos; 2065 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 2066 *page_ptr = hdr_page->page; 2067 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 2068 hdr_page->pos += iv_len; 2069 2070 /* 2071 * Pull the ieee80211 header + IV to be able to use TSO core, 2072 * we will restore it for the tx_status flow. 2073 */ 2074 skb_pull(skb, hdr_len + iv_len); 2075 2076 tso_start(skb, &tso); 2077 2078 while (total_len) { 2079 /* this is the data left for this subframe */ 2080 unsigned int data_left = 2081 min_t(unsigned int, mss, total_len); 2082 struct sk_buff *csum_skb = NULL; 2083 unsigned int hdr_tb_len; 2084 dma_addr_t hdr_tb_phys; 2085 struct tcphdr *tcph; 2086 u8 *iph; 2087 2088 total_len -= data_left; 2089 2090 memset(hdr_page->pos, 0, amsdu_pad); 2091 hdr_page->pos += amsdu_pad; 2092 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 2093 data_left)) & 0x3; 2094 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 2095 hdr_page->pos += ETH_ALEN; 2096 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 2097 hdr_page->pos += ETH_ALEN; 2098 2099 length = snap_ip_tcp_hdrlen + data_left; 2100 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 2101 hdr_page->pos += sizeof(length); 2102 2103 /* 2104 * This will copy the SNAP as well which will be considered 2105 * as MAC header. 2106 */ 2107 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 2108 iph = hdr_page->pos + 8; 2109 tcph = (void *)(iph + ip_hdrlen); 2110 2111 /* For testing on current hardware only */ 2112 if (trans_pcie->sw_csum_tx) { 2113 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 2114 GFP_ATOMIC); 2115 if (!csum_skb) { 2116 ret = -ENOMEM; 2117 goto out_unmap; 2118 } 2119 2120 iwl_compute_pseudo_hdr_csum(iph, tcph, 2121 skb->protocol == 2122 htons(ETH_P_IPV6), 2123 data_left); 2124 2125 memcpy(skb_put(csum_skb, tcp_hdrlen(skb)), 2126 tcph, tcp_hdrlen(skb)); 2127 skb_set_transport_header(csum_skb, 0); 2128 csum_skb->csum_start = 2129 (unsigned char *)tcp_hdr(csum_skb) - 2130 csum_skb->head; 2131 } 2132 2133 hdr_page->pos += snap_ip_tcp_hdrlen; 2134 2135 hdr_tb_len = hdr_page->pos - start_hdr; 2136 hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 2137 hdr_tb_len, DMA_TO_DEVICE); 2138 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 2139 dev_kfree_skb(csum_skb); 2140 ret = -EINVAL; 2141 goto out_unmap; 2142 } 2143 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 2144 hdr_tb_len, false); 2145 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 2146 hdr_tb_len); 2147 2148 /* prepare the start_hdr for the next subframe */ 2149 start_hdr = hdr_page->pos; 2150 2151 /* put the payload */ 2152 while (data_left) { 2153 unsigned int size = min_t(unsigned int, tso.size, 2154 data_left); 2155 dma_addr_t tb_phys; 2156 2157 if (trans_pcie->sw_csum_tx) 2158 memcpy(skb_put(csum_skb, size), tso.data, size); 2159 2160 tb_phys = dma_map_single(trans->dev, tso.data, 2161 size, DMA_TO_DEVICE); 2162 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2163 dev_kfree_skb(csum_skb); 2164 ret = -EINVAL; 2165 goto out_unmap; 2166 } 2167 2168 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2169 size, false); 2170 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 2171 size); 2172 2173 data_left -= size; 2174 tso_build_data(skb, &tso, size); 2175 } 2176 2177 /* For testing on early hardware only */ 2178 if (trans_pcie->sw_csum_tx) { 2179 __wsum csum; 2180 2181 csum = skb_checksum(csum_skb, 2182 skb_checksum_start_offset(csum_skb), 2183 csum_skb->len - 2184 skb_checksum_start_offset(csum_skb), 2185 0); 2186 dev_kfree_skb(csum_skb); 2187 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 2188 hdr_tb_len, DMA_TO_DEVICE); 2189 tcph->check = csum_fold(csum); 2190 dma_sync_single_for_device(trans->dev, hdr_tb_phys, 2191 hdr_tb_len, DMA_TO_DEVICE); 2192 } 2193 } 2194 2195 /* re -add the WiFi header and IV */ 2196 skb_push(skb, hdr_len + iv_len); 2197 2198 return 0; 2199 2200 out_unmap: 2201 iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]); 2202 return ret; 2203 } 2204 #else /* CONFIG_INET */ 2205 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2206 struct iwl_txq *txq, u8 hdr_len, 2207 struct iwl_cmd_meta *out_meta, 2208 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2209 { 2210 /* No A-MSDU without CONFIG_INET */ 2211 WARN_ON(1); 2212 2213 return -1; 2214 } 2215 #endif /* CONFIG_INET */ 2216 2217 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2218 struct iwl_device_cmd *dev_cmd, int txq_id) 2219 { 2220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2221 struct ieee80211_hdr *hdr; 2222 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2223 struct iwl_cmd_meta *out_meta; 2224 struct iwl_txq *txq; 2225 struct iwl_queue *q; 2226 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2227 void *tb1_addr; 2228 u16 len, tb1_len; 2229 bool wait_write_ptr; 2230 __le16 fc; 2231 u8 hdr_len; 2232 u16 wifi_seq; 2233 bool amsdu; 2234 2235 txq = &trans_pcie->txq[txq_id]; 2236 q = &txq->q; 2237 2238 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2239 "TX on unused queue %d\n", txq_id)) 2240 return -EINVAL; 2241 2242 if (unlikely(trans_pcie->sw_csum_tx && 2243 skb->ip_summed == CHECKSUM_PARTIAL)) { 2244 int offs = skb_checksum_start_offset(skb); 2245 int csum_offs = offs + skb->csum_offset; 2246 __wsum csum; 2247 2248 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 2249 return -1; 2250 2251 csum = skb_checksum(skb, offs, skb->len - offs, 0); 2252 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 2253 2254 skb->ip_summed = CHECKSUM_UNNECESSARY; 2255 } 2256 2257 if (skb_is_nonlinear(skb) && 2258 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2259 __skb_linearize(skb)) 2260 return -ENOMEM; 2261 2262 /* mac80211 always puts the full header into the SKB's head, 2263 * so there's no need to check if it's readable there 2264 */ 2265 hdr = (struct ieee80211_hdr *)skb->data; 2266 fc = hdr->frame_control; 2267 hdr_len = ieee80211_hdrlen(fc); 2268 2269 spin_lock(&txq->lock); 2270 2271 if (iwl_queue_space(q) < q->high_mark) { 2272 iwl_stop_queue(trans, txq); 2273 2274 /* don't put the packet on the ring, if there is no room */ 2275 if (unlikely(iwl_queue_space(q) < 3)) { 2276 struct iwl_device_cmd **dev_cmd_ptr; 2277 2278 dev_cmd_ptr = (void *)((u8 *)skb->cb + 2279 trans_pcie->dev_cmd_offs); 2280 2281 *dev_cmd_ptr = dev_cmd; 2282 __skb_queue_tail(&txq->overflow_q, skb); 2283 2284 spin_unlock(&txq->lock); 2285 return 0; 2286 } 2287 } 2288 2289 /* In AGG mode, the index in the ring must correspond to the WiFi 2290 * sequence number. This is a HW requirements to help the SCD to parse 2291 * the BA. 2292 * Check here that the packets are in the right place on the ring. 2293 */ 2294 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2295 WARN_ONCE(txq->ampdu && 2296 (wifi_seq & 0xff) != q->write_ptr, 2297 "Q: %d WiFi Seq %d tfdNum %d", 2298 txq_id, wifi_seq, q->write_ptr); 2299 2300 /* Set up driver data for this TFD */ 2301 txq->entries[q->write_ptr].skb = skb; 2302 txq->entries[q->write_ptr].cmd = dev_cmd; 2303 2304 dev_cmd->hdr.sequence = 2305 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2306 INDEX_TO_SEQ(q->write_ptr))); 2307 2308 tb0_phys = iwl_pcie_get_first_tb_dma(txq, q->write_ptr); 2309 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2310 offsetof(struct iwl_tx_cmd, scratch); 2311 2312 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2313 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2314 2315 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2316 out_meta = &txq->entries[q->write_ptr].meta; 2317 out_meta->flags = 0; 2318 2319 /* 2320 * The second TB (tb1) points to the remainder of the TX command 2321 * and the 802.11 header - dword aligned size 2322 * (This calculation modifies the TX command, so do it before the 2323 * setup of the first TB) 2324 */ 2325 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 2326 hdr_len - IWL_FIRST_TB_SIZE; 2327 /* do not align A-MSDU to dword as the subframe header aligns it */ 2328 amsdu = ieee80211_is_data_qos(fc) && 2329 (*ieee80211_get_qos_ctl(hdr) & 2330 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2331 if (trans_pcie->sw_csum_tx || !amsdu) { 2332 tb1_len = ALIGN(len, 4); 2333 /* Tell NIC about any 2-byte padding after MAC header */ 2334 if (tb1_len != len) 2335 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 2336 } else { 2337 tb1_len = len; 2338 } 2339 2340 /* The first TB points to bi-directional DMA data */ 2341 memcpy(&txq->first_tb_bufs[q->write_ptr], &dev_cmd->hdr, 2342 IWL_FIRST_TB_SIZE); 2343 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 2344 IWL_FIRST_TB_SIZE, true); 2345 2346 /* there must be data left over for TB1 or this code must be changed */ 2347 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2348 2349 /* map the data for TB1 */ 2350 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2351 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2352 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2353 goto out_err; 2354 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2355 2356 if (amsdu) { 2357 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 2358 out_meta, dev_cmd, 2359 tb1_len))) 2360 goto out_err; 2361 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2362 out_meta, dev_cmd, tb1_len))) { 2363 goto out_err; 2364 } 2365 2366 /* Set up entry for this TFD in Tx byte-count array */ 2367 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); 2368 2369 wait_write_ptr = ieee80211_has_morefrags(fc); 2370 2371 /* start timer if queue currently empty */ 2372 if (q->read_ptr == q->write_ptr) { 2373 if (txq->wd_timeout) { 2374 /* 2375 * If the TXQ is active, then set the timer, if not, 2376 * set the timer in remainder so that the timer will 2377 * be armed with the right value when the station will 2378 * wake up. 2379 */ 2380 if (!txq->frozen) 2381 mod_timer(&txq->stuck_timer, 2382 jiffies + txq->wd_timeout); 2383 else 2384 txq->frozen_expiry_remainder = txq->wd_timeout; 2385 } 2386 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); 2387 iwl_trans_ref(trans); 2388 } 2389 2390 /* Tell device the write index *just past* this latest filled TFD */ 2391 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 2392 if (!wait_write_ptr) 2393 iwl_pcie_txq_inc_wr_ptr(trans, txq); 2394 2395 /* 2396 * At this point the frame is "transmitted" successfully 2397 * and we will get a TX status notification eventually. 2398 */ 2399 spin_unlock(&txq->lock); 2400 return 0; 2401 out_err: 2402 spin_unlock(&txq->lock); 2403 return -1; 2404 } 2405