1 /****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6 * Copyright(c) 2018 Intel Corporation 7 * 8 * Portions of this file are derived from the ipw3945 project, as well 9 * as portions of the ieee80211 subsystem header files. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * The full GNU General Public License is included in this distribution in the 21 * file called LICENSE. 22 * 23 * Contact Information: 24 * Intel Linux Wireless <linuxwifi@intel.com> 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * 27 *****************************************************************************/ 28 #include <linux/etherdevice.h> 29 #include <linux/ieee80211.h> 30 #include <linux/slab.h> 31 #include <linux/sched.h> 32 #include <linux/pm_runtime.h> 33 #include <net/ip6_checksum.h> 34 #include <net/tso.h> 35 36 #include "iwl-debug.h" 37 #include "iwl-csr.h" 38 #include "iwl-prph.h" 39 #include "iwl-io.h" 40 #include "iwl-scd.h" 41 #include "iwl-op-mode.h" 42 #include "internal.h" 43 #include "fw/api/tx.h" 44 45 #define IWL_TX_CRC_SIZE 4 46 #define IWL_TX_DELIMITER_SIZE 4 47 48 /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 49 * DMA services 50 * 51 * Theory of operation 52 * 53 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 54 * of buffer descriptors, each of which points to one or more data buffers for 55 * the device to read from or fill. Driver and device exchange status of each 56 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 57 * entries in each circular buffer, to protect against confusing empty and full 58 * queue states. 59 * 60 * The device reads or writes the data in the queues via the device's several 61 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 62 * 63 * For Tx queue, there are low mark and high mark limits. If, after queuing 64 * the packet for Tx, free space become < low mark, Tx queue stopped. When 65 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 66 * Tx queue resumed. 67 * 68 ***************************************************/ 69 70 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q) 71 { 72 unsigned int max; 73 unsigned int used; 74 75 /* 76 * To avoid ambiguity between empty and completely full queues, there 77 * should always be less than max_tfd_queue_size elements in the queue. 78 * If q->n_window is smaller than max_tfd_queue_size, there is no need 79 * to reserve any queue entries for this purpose. 80 */ 81 if (q->n_window < trans->cfg->base_params->max_tfd_queue_size) 82 max = q->n_window; 83 else 84 max = trans->cfg->base_params->max_tfd_queue_size - 1; 85 86 /* 87 * max_tfd_queue_size is a power of 2, so the following is equivalent to 88 * modulo by max_tfd_queue_size and is well defined. 89 */ 90 used = (q->write_ptr - q->read_ptr) & 91 (trans->cfg->base_params->max_tfd_queue_size - 1); 92 93 if (WARN_ON(used > max)) 94 return 0; 95 96 return max - used; 97 } 98 99 /* 100 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 101 */ 102 static int iwl_queue_init(struct iwl_txq *q, int slots_num) 103 { 104 q->n_window = slots_num; 105 106 /* slots_num must be power-of-two size, otherwise 107 * iwl_pcie_get_cmd_index is broken. */ 108 if (WARN_ON(!is_power_of_2(slots_num))) 109 return -EINVAL; 110 111 q->low_mark = q->n_window / 4; 112 if (q->low_mark < 4) 113 q->low_mark = 4; 114 115 q->high_mark = q->n_window / 8; 116 if (q->high_mark < 2) 117 q->high_mark = 2; 118 119 q->write_ptr = 0; 120 q->read_ptr = 0; 121 122 return 0; 123 } 124 125 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 126 struct iwl_dma_ptr *ptr, size_t size) 127 { 128 if (WARN_ON(ptr->addr)) 129 return -EINVAL; 130 131 ptr->addr = dma_alloc_coherent(trans->dev, size, 132 &ptr->dma, GFP_KERNEL); 133 if (!ptr->addr) 134 return -ENOMEM; 135 ptr->size = size; 136 return 0; 137 } 138 139 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 140 { 141 if (unlikely(!ptr->addr)) 142 return; 143 144 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 145 memset(ptr, 0, sizeof(*ptr)); 146 } 147 148 static void iwl_pcie_txq_stuck_timer(struct timer_list *t) 149 { 150 struct iwl_txq *txq = from_timer(txq, t, stuck_timer); 151 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 152 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 153 154 spin_lock(&txq->lock); 155 /* check if triggered erroneously */ 156 if (txq->read_ptr == txq->write_ptr) { 157 spin_unlock(&txq->lock); 158 return; 159 } 160 spin_unlock(&txq->lock); 161 162 iwl_trans_pcie_log_scd_error(trans, txq); 163 164 iwl_force_nmi(trans); 165 } 166 167 /* 168 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 169 */ 170 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 171 struct iwl_txq *txq, u16 byte_cnt, 172 int num_tbs) 173 { 174 struct iwlagn_scd_bc_tbl *scd_bc_tbl; 175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 176 int write_ptr = txq->write_ptr; 177 int txq_id = txq->id; 178 u8 sec_ctl = 0; 179 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 180 __le16 bc_ent; 181 struct iwl_tx_cmd *tx_cmd = 182 (void *)txq->entries[txq->write_ptr].cmd->payload; 183 u8 sta_id = tx_cmd->sta_id; 184 185 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 186 187 sec_ctl = tx_cmd->sec_ctl; 188 189 switch (sec_ctl & TX_CMD_SEC_MSK) { 190 case TX_CMD_SEC_CCM: 191 len += IEEE80211_CCMP_MIC_LEN; 192 break; 193 case TX_CMD_SEC_TKIP: 194 len += IEEE80211_TKIP_ICV_LEN; 195 break; 196 case TX_CMD_SEC_WEP: 197 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 198 break; 199 } 200 if (trans_pcie->bc_table_dword) 201 len = DIV_ROUND_UP(len, 4); 202 203 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 204 return; 205 206 bc_ent = cpu_to_le16(len | (sta_id << 12)); 207 208 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 209 210 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 211 scd_bc_tbl[txq_id]. 212 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 213 } 214 215 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 216 struct iwl_txq *txq) 217 { 218 struct iwl_trans_pcie *trans_pcie = 219 IWL_TRANS_GET_PCIE_TRANS(trans); 220 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 221 int txq_id = txq->id; 222 int read_ptr = txq->read_ptr; 223 u8 sta_id = 0; 224 __le16 bc_ent; 225 struct iwl_tx_cmd *tx_cmd = 226 (void *)txq->entries[read_ptr].cmd->payload; 227 228 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 229 230 if (txq_id != trans_pcie->cmd_queue) 231 sta_id = tx_cmd->sta_id; 232 233 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 234 235 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 236 237 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 238 scd_bc_tbl[txq_id]. 239 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 240 } 241 242 /* 243 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 244 */ 245 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 246 struct iwl_txq *txq) 247 { 248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 249 u32 reg = 0; 250 int txq_id = txq->id; 251 252 lockdep_assert_held(&txq->lock); 253 254 /* 255 * explicitly wake up the NIC if: 256 * 1. shadow registers aren't enabled 257 * 2. NIC is woken up for CMD regardless of shadow outside this function 258 * 3. there is a chance that the NIC is asleep 259 */ 260 if (!trans->cfg->base_params->shadow_reg_enable && 261 txq_id != trans_pcie->cmd_queue && 262 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 263 /* 264 * wake up nic if it's powered down ... 265 * uCode will wake up, and interrupt us again, so next 266 * time we'll skip this part. 267 */ 268 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 269 270 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 271 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 272 txq_id, reg); 273 iwl_set_bit(trans, CSR_GP_CNTRL, 274 BIT(trans->cfg->csr->flag_mac_access_req)); 275 txq->need_update = true; 276 return; 277 } 278 } 279 280 /* 281 * if not in power-save mode, uCode will never sleep when we're 282 * trying to tx (during RFKILL, we're not trying to tx). 283 */ 284 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 285 if (!txq->block) 286 iwl_write32(trans, HBUS_TARG_WRPTR, 287 txq->write_ptr | (txq_id << 8)); 288 } 289 290 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 291 { 292 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 293 int i; 294 295 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 296 struct iwl_txq *txq = trans_pcie->txq[i]; 297 298 if (!test_bit(i, trans_pcie->queue_used)) 299 continue; 300 301 spin_lock_bh(&txq->lock); 302 if (txq->need_update) { 303 iwl_pcie_txq_inc_wr_ptr(trans, txq); 304 txq->need_update = false; 305 } 306 spin_unlock_bh(&txq->lock); 307 } 308 } 309 310 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 311 void *_tfd, u8 idx) 312 { 313 314 if (trans->cfg->use_tfh) { 315 struct iwl_tfh_tfd *tfd = _tfd; 316 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 317 318 return (dma_addr_t)(le64_to_cpu(tb->addr)); 319 } else { 320 struct iwl_tfd *tfd = _tfd; 321 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 322 dma_addr_t addr = get_unaligned_le32(&tb->lo); 323 dma_addr_t hi_len; 324 325 if (sizeof(dma_addr_t) <= sizeof(u32)) 326 return addr; 327 328 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 329 330 /* 331 * shift by 16 twice to avoid warnings on 32-bit 332 * (where this code never runs anyway due to the 333 * if statement above) 334 */ 335 return addr | ((hi_len << 16) << 16); 336 } 337 } 338 339 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 340 u8 idx, dma_addr_t addr, u16 len) 341 { 342 struct iwl_tfd *tfd_fh = (void *)tfd; 343 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 344 345 u16 hi_n_len = len << 4; 346 347 put_unaligned_le32(addr, &tb->lo); 348 hi_n_len |= iwl_get_dma_hi_addr(addr); 349 350 tb->hi_n_len = cpu_to_le16(hi_n_len); 351 352 tfd_fh->num_tbs = idx + 1; 353 } 354 355 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 356 { 357 if (trans->cfg->use_tfh) { 358 struct iwl_tfh_tfd *tfd = _tfd; 359 360 return le16_to_cpu(tfd->num_tbs) & 0x1f; 361 } else { 362 struct iwl_tfd *tfd = _tfd; 363 364 return tfd->num_tbs & 0x1f; 365 } 366 } 367 368 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 369 struct iwl_cmd_meta *meta, 370 struct iwl_txq *txq, int index) 371 { 372 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 373 int i, num_tbs; 374 void *tfd = iwl_pcie_get_tfd(trans, txq, index); 375 376 /* Sanity check on number of chunks */ 377 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 378 379 if (num_tbs > trans_pcie->max_tbs) { 380 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 381 /* @todo issue fatal error, it is quite serious situation */ 382 return; 383 } 384 385 /* first TB is never freed - it's the bidirectional DMA data */ 386 387 for (i = 1; i < num_tbs; i++) { 388 if (meta->tbs & BIT(i)) 389 dma_unmap_page(trans->dev, 390 iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 391 iwl_pcie_tfd_tb_get_len(trans, tfd, i), 392 DMA_TO_DEVICE); 393 else 394 dma_unmap_single(trans->dev, 395 iwl_pcie_tfd_tb_get_addr(trans, tfd, 396 i), 397 iwl_pcie_tfd_tb_get_len(trans, tfd, 398 i), 399 DMA_TO_DEVICE); 400 } 401 402 if (trans->cfg->use_tfh) { 403 struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 404 405 tfd_fh->num_tbs = 0; 406 } else { 407 struct iwl_tfd *tfd_fh = (void *)tfd; 408 409 tfd_fh->num_tbs = 0; 410 } 411 412 } 413 414 /* 415 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 416 * @trans - transport private data 417 * @txq - tx queue 418 * @dma_dir - the direction of the DMA mapping 419 * 420 * Does NOT advance any TFD circular buffer read/write indexes 421 * Does NOT free the TFD itself (which is within circular buffer) 422 */ 423 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 424 { 425 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 426 * idx is bounded by n_window 427 */ 428 int rd_ptr = txq->read_ptr; 429 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 430 431 lockdep_assert_held(&txq->lock); 432 433 /* We have only q->n_window txq->entries, but we use 434 * TFD_QUEUE_SIZE_MAX tfds 435 */ 436 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 437 438 /* free SKB */ 439 if (txq->entries) { 440 struct sk_buff *skb; 441 442 skb = txq->entries[idx].skb; 443 444 /* Can be called from irqs-disabled context 445 * If skb is not NULL, it means that the whole queue is being 446 * freed and that the queue is not empty - free the skb 447 */ 448 if (skb) { 449 iwl_op_mode_free_skb(trans->op_mode, skb); 450 txq->entries[idx].skb = NULL; 451 } 452 } 453 } 454 455 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 456 dma_addr_t addr, u16 len, bool reset) 457 { 458 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 459 void *tfd; 460 u32 num_tbs; 461 462 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 463 464 if (reset) 465 memset(tfd, 0, trans_pcie->tfd_size); 466 467 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 468 469 /* Each TFD can point to a maximum max_tbs Tx buffers */ 470 if (num_tbs >= trans_pcie->max_tbs) { 471 IWL_ERR(trans, "Error can not send more than %d chunks\n", 472 trans_pcie->max_tbs); 473 return -EINVAL; 474 } 475 476 if (WARN(addr & ~IWL_TX_DMA_MASK, 477 "Unaligned address = %llx\n", (unsigned long long)addr)) 478 return -EINVAL; 479 480 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 481 482 return num_tbs; 483 } 484 485 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 486 int slots_num, bool cmd_queue) 487 { 488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 489 size_t tfd_sz = trans_pcie->tfd_size * 490 trans->cfg->base_params->max_tfd_queue_size; 491 size_t tb0_buf_sz; 492 int i; 493 494 if (WARN_ON(txq->entries || txq->tfds)) 495 return -EINVAL; 496 497 if (trans->cfg->use_tfh) 498 tfd_sz = trans_pcie->tfd_size * slots_num; 499 500 timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0); 501 txq->trans_pcie = trans_pcie; 502 503 txq->n_window = slots_num; 504 505 txq->entries = kcalloc(slots_num, 506 sizeof(struct iwl_pcie_txq_entry), 507 GFP_KERNEL); 508 509 if (!txq->entries) 510 goto error; 511 512 if (cmd_queue) 513 for (i = 0; i < slots_num; i++) { 514 txq->entries[i].cmd = 515 kmalloc(sizeof(struct iwl_device_cmd), 516 GFP_KERNEL); 517 if (!txq->entries[i].cmd) 518 goto error; 519 } 520 521 /* Circular buffer of transmit frame descriptors (TFDs), 522 * shared with device */ 523 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 524 &txq->dma_addr, GFP_KERNEL); 525 if (!txq->tfds) 526 goto error; 527 528 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 529 530 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 531 532 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 533 &txq->first_tb_dma, 534 GFP_KERNEL); 535 if (!txq->first_tb_bufs) 536 goto err_free_tfds; 537 538 return 0; 539 err_free_tfds: 540 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 541 error: 542 if (txq->entries && cmd_queue) 543 for (i = 0; i < slots_num; i++) 544 kfree(txq->entries[i].cmd); 545 kfree(txq->entries); 546 txq->entries = NULL; 547 548 return -ENOMEM; 549 550 } 551 552 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 553 int slots_num, bool cmd_queue) 554 { 555 int ret; 556 u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size; 557 558 txq->need_update = false; 559 560 /* max_tfd_queue_size must be power-of-two size, otherwise 561 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 562 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1), 563 "Max tfd queue size must be a power of two, but is %d", 564 tfd_queue_max_size)) 565 return -EINVAL; 566 567 /* Initialize queue's high/low-water marks, and head/tail indexes */ 568 ret = iwl_queue_init(txq, slots_num); 569 if (ret) 570 return ret; 571 572 spin_lock_init(&txq->lock); 573 574 if (cmd_queue) { 575 static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 576 577 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 578 } 579 580 __skb_queue_head_init(&txq->overflow_q); 581 582 return 0; 583 } 584 585 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 586 struct sk_buff *skb) 587 { 588 struct page **page_ptr; 589 590 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 591 592 if (*page_ptr) { 593 __free_page(*page_ptr); 594 *page_ptr = NULL; 595 } 596 } 597 598 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 599 { 600 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 601 602 lockdep_assert_held(&trans_pcie->reg_lock); 603 604 if (trans_pcie->ref_cmd_in_flight) { 605 trans_pcie->ref_cmd_in_flight = false; 606 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 607 iwl_trans_unref(trans); 608 } 609 610 if (!trans->cfg->base_params->apmg_wake_up_wa) 611 return; 612 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 613 return; 614 615 trans_pcie->cmd_hold_nic_awake = false; 616 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 617 BIT(trans->cfg->csr->flag_mac_access_req)); 618 } 619 620 /* 621 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 622 */ 623 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 624 { 625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 626 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 627 628 spin_lock_bh(&txq->lock); 629 while (txq->write_ptr != txq->read_ptr) { 630 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 631 txq_id, txq->read_ptr); 632 633 if (txq_id != trans_pcie->cmd_queue) { 634 struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 635 636 if (WARN_ON_ONCE(!skb)) 637 continue; 638 639 iwl_pcie_free_tso_page(trans_pcie, skb); 640 } 641 iwl_pcie_txq_free_tfd(trans, txq); 642 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 643 644 if (txq->read_ptr == txq->write_ptr) { 645 unsigned long flags; 646 647 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 648 if (txq_id != trans_pcie->cmd_queue) { 649 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 650 txq->id); 651 iwl_trans_unref(trans); 652 } else { 653 iwl_pcie_clear_cmd_in_flight(trans); 654 } 655 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 656 } 657 } 658 659 while (!skb_queue_empty(&txq->overflow_q)) { 660 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 661 662 iwl_op_mode_free_skb(trans->op_mode, skb); 663 } 664 665 spin_unlock_bh(&txq->lock); 666 667 /* just in case - this queue may have been stopped */ 668 iwl_wake_queue(trans, txq); 669 } 670 671 /* 672 * iwl_pcie_txq_free - Deallocate DMA queue. 673 * @txq: Transmit queue to deallocate. 674 * 675 * Empty queue by removing and destroying all BD's. 676 * Free all buffers. 677 * 0-fill, but do not free "txq" descriptor structure. 678 */ 679 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 680 { 681 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 682 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 683 struct device *dev = trans->dev; 684 int i; 685 686 if (WARN_ON(!txq)) 687 return; 688 689 iwl_pcie_txq_unmap(trans, txq_id); 690 691 /* De-alloc array of command/tx buffers */ 692 if (txq_id == trans_pcie->cmd_queue) 693 for (i = 0; i < txq->n_window; i++) { 694 kzfree(txq->entries[i].cmd); 695 kzfree(txq->entries[i].free_buf); 696 } 697 698 /* De-alloc circular buffer of TFDs */ 699 if (txq->tfds) { 700 dma_free_coherent(dev, 701 trans_pcie->tfd_size * 702 trans->cfg->base_params->max_tfd_queue_size, 703 txq->tfds, txq->dma_addr); 704 txq->dma_addr = 0; 705 txq->tfds = NULL; 706 707 dma_free_coherent(dev, 708 sizeof(*txq->first_tb_bufs) * txq->n_window, 709 txq->first_tb_bufs, txq->first_tb_dma); 710 } 711 712 kfree(txq->entries); 713 txq->entries = NULL; 714 715 del_timer_sync(&txq->stuck_timer); 716 717 /* 0-fill queue descriptor structure */ 718 memset(txq, 0, sizeof(*txq)); 719 } 720 721 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 722 { 723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724 int nq = trans->cfg->base_params->num_of_queues; 725 int chan; 726 u32 reg_val; 727 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 728 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 729 730 /* make sure all queue are not stopped/used */ 731 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 732 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 733 734 trans_pcie->scd_base_addr = 735 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 736 737 WARN_ON(scd_base_addr != 0 && 738 scd_base_addr != trans_pcie->scd_base_addr); 739 740 /* reset context data, TX status and translation data */ 741 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 742 SCD_CONTEXT_MEM_LOWER_BOUND, 743 NULL, clear_dwords); 744 745 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 746 trans_pcie->scd_bc_tbls.dma >> 10); 747 748 /* The chain extension of the SCD doesn't work well. This feature is 749 * enabled by default by the HW, so we need to disable it manually. 750 */ 751 if (trans->cfg->base_params->scd_chain_ext_wa) 752 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 753 754 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 755 trans_pcie->cmd_fifo, 756 trans_pcie->cmd_q_wdg_timeout); 757 758 /* Activate all Tx DMA/FIFO channels */ 759 iwl_scd_activate_fifos(trans); 760 761 /* Enable DMA channel */ 762 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 763 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 764 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 765 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 766 767 /* Update FH chicken bits */ 768 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 769 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 770 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 771 772 /* Enable L1-Active */ 773 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 774 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 775 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 776 } 777 778 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 779 { 780 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 781 int txq_id; 782 783 /* 784 * we should never get here in gen2 trans mode return early to avoid 785 * having invalid accesses 786 */ 787 if (WARN_ON_ONCE(trans->cfg->gen2)) 788 return; 789 790 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 791 txq_id++) { 792 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 793 if (trans->cfg->use_tfh) 794 iwl_write_direct64(trans, 795 FH_MEM_CBBC_QUEUE(trans, txq_id), 796 txq->dma_addr); 797 else 798 iwl_write_direct32(trans, 799 FH_MEM_CBBC_QUEUE(trans, txq_id), 800 txq->dma_addr >> 8); 801 iwl_pcie_txq_unmap(trans, txq_id); 802 txq->read_ptr = 0; 803 txq->write_ptr = 0; 804 } 805 806 /* Tell NIC where to find the "keep warm" buffer */ 807 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 808 trans_pcie->kw.dma >> 4); 809 810 /* 811 * Send 0 as the scd_base_addr since the device may have be reset 812 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 813 * contain garbage. 814 */ 815 iwl_pcie_tx_start(trans, 0); 816 } 817 818 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 819 { 820 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 821 unsigned long flags; 822 int ch, ret; 823 u32 mask = 0; 824 825 spin_lock(&trans_pcie->irq_lock); 826 827 if (!iwl_trans_grab_nic_access(trans, &flags)) 828 goto out; 829 830 /* Stop each Tx DMA channel */ 831 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 832 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 833 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 834 } 835 836 /* Wait for DMA channels to be idle */ 837 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 838 if (ret < 0) 839 IWL_ERR(trans, 840 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 841 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 842 843 iwl_trans_release_nic_access(trans, &flags); 844 845 out: 846 spin_unlock(&trans_pcie->irq_lock); 847 } 848 849 /* 850 * iwl_pcie_tx_stop - Stop all Tx DMA channels 851 */ 852 int iwl_pcie_tx_stop(struct iwl_trans *trans) 853 { 854 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 855 int txq_id; 856 857 /* Turn off all Tx DMA fifos */ 858 iwl_scd_deactivate_fifos(trans); 859 860 /* Turn off all Tx DMA channels */ 861 iwl_pcie_tx_stop_fh(trans); 862 863 /* 864 * This function can be called before the op_mode disabled the 865 * queues. This happens when we have an rfkill interrupt. 866 * Since we stop Tx altogether - mark the queues as stopped. 867 */ 868 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 869 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 870 871 /* This can happen: start_hw, stop_device */ 872 if (!trans_pcie->txq_memory) 873 return 0; 874 875 /* Unmap DMA from host system and free skb's */ 876 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 877 txq_id++) 878 iwl_pcie_txq_unmap(trans, txq_id); 879 880 return 0; 881 } 882 883 /* 884 * iwl_trans_tx_free - Free TXQ Context 885 * 886 * Destroy all TX DMA queues and structures 887 */ 888 void iwl_pcie_tx_free(struct iwl_trans *trans) 889 { 890 int txq_id; 891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 892 893 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 894 895 /* Tx queues */ 896 if (trans_pcie->txq_memory) { 897 for (txq_id = 0; 898 txq_id < trans->cfg->base_params->num_of_queues; 899 txq_id++) { 900 iwl_pcie_txq_free(trans, txq_id); 901 trans_pcie->txq[txq_id] = NULL; 902 } 903 } 904 905 kfree(trans_pcie->txq_memory); 906 trans_pcie->txq_memory = NULL; 907 908 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 909 910 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 911 } 912 913 /* 914 * iwl_pcie_tx_alloc - allocate TX context 915 * Allocate all Tx DMA structures and initialize them 916 */ 917 static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 918 { 919 int ret; 920 int txq_id, slots_num; 921 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 922 u16 bc_tbls_size = trans->cfg->base_params->num_of_queues; 923 924 bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 925 sizeof(struct iwl_gen3_bc_tbl) : 926 sizeof(struct iwlagn_scd_bc_tbl); 927 928 /*It is not allowed to alloc twice, so warn when this happens. 929 * We cannot rely on the previous allocation, so free and fail */ 930 if (WARN_ON(trans_pcie->txq_memory)) { 931 ret = -EINVAL; 932 goto error; 933 } 934 935 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 936 bc_tbls_size); 937 if (ret) { 938 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 939 goto error; 940 } 941 942 /* Alloc keep-warm buffer */ 943 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 944 if (ret) { 945 IWL_ERR(trans, "Keep Warm allocation failed\n"); 946 goto error; 947 } 948 949 trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 950 sizeof(struct iwl_txq), GFP_KERNEL); 951 if (!trans_pcie->txq_memory) { 952 IWL_ERR(trans, "Not enough memory for txq\n"); 953 ret = -ENOMEM; 954 goto error; 955 } 956 957 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 958 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 959 txq_id++) { 960 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 961 962 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 963 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 964 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 965 slots_num, cmd_queue); 966 if (ret) { 967 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 968 goto error; 969 } 970 trans_pcie->txq[txq_id]->id = txq_id; 971 } 972 973 return 0; 974 975 error: 976 iwl_pcie_tx_free(trans); 977 978 return ret; 979 } 980 981 int iwl_pcie_tx_init(struct iwl_trans *trans) 982 { 983 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 984 int ret; 985 int txq_id, slots_num; 986 bool alloc = false; 987 988 if (!trans_pcie->txq_memory) { 989 ret = iwl_pcie_tx_alloc(trans); 990 if (ret) 991 goto error; 992 alloc = true; 993 } 994 995 spin_lock(&trans_pcie->irq_lock); 996 997 /* Turn off all Tx DMA fifos */ 998 iwl_scd_deactivate_fifos(trans); 999 1000 /* Tell NIC where to find the "keep warm" buffer */ 1001 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1002 trans_pcie->kw.dma >> 4); 1003 1004 spin_unlock(&trans_pcie->irq_lock); 1005 1006 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1007 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1008 txq_id++) { 1009 bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1010 1011 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1012 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1013 slots_num, cmd_queue); 1014 if (ret) { 1015 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1016 goto error; 1017 } 1018 1019 /* 1020 * Tell nic where to find circular buffer of TFDs for a 1021 * given Tx queue, and enable the DMA channel used for that 1022 * queue. 1023 * Circular buffer (TFD queue in DRAM) physical base address 1024 */ 1025 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1026 trans_pcie->txq[txq_id]->dma_addr >> 8); 1027 } 1028 1029 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1030 if (trans->cfg->base_params->num_of_queues > 20) 1031 iwl_set_bits_prph(trans, SCD_GP_CTRL, 1032 SCD_GP_CTRL_ENABLE_31_QUEUES); 1033 1034 return 0; 1035 error: 1036 /*Upon error, free only if we allocated something */ 1037 if (alloc) 1038 iwl_pcie_tx_free(trans); 1039 return ret; 1040 } 1041 1042 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1043 { 1044 lockdep_assert_held(&txq->lock); 1045 1046 if (!txq->wd_timeout) 1047 return; 1048 1049 /* 1050 * station is asleep and we send data - that must 1051 * be uAPSD or PS-Poll. Don't rearm the timer. 1052 */ 1053 if (txq->frozen) 1054 return; 1055 1056 /* 1057 * if empty delete timer, otherwise move timer forward 1058 * since we're making progress on this queue 1059 */ 1060 if (txq->read_ptr == txq->write_ptr) 1061 del_timer(&txq->stuck_timer); 1062 else 1063 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1064 } 1065 1066 /* Frees buffers until index _not_ inclusive */ 1067 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1068 struct sk_buff_head *skbs) 1069 { 1070 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1071 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1072 int tfd_num = iwl_pcie_get_cmd_index(txq, ssn); 1073 int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1074 int last_to_free; 1075 1076 /* This function is not meant to release cmd queue*/ 1077 if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1078 return; 1079 1080 spin_lock_bh(&txq->lock); 1081 1082 if (!test_bit(txq_id, trans_pcie->queue_used)) { 1083 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1084 txq_id, ssn); 1085 goto out; 1086 } 1087 1088 if (read_ptr == tfd_num) 1089 goto out; 1090 1091 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1092 txq_id, txq->read_ptr, tfd_num, ssn); 1093 1094 /*Since we free until index _not_ inclusive, the one before index is 1095 * the last we will free. This one must be used */ 1096 last_to_free = iwl_queue_dec_wrap(trans, tfd_num); 1097 1098 if (!iwl_queue_used(txq, last_to_free)) { 1099 IWL_ERR(trans, 1100 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1101 __func__, txq_id, last_to_free, 1102 trans->cfg->base_params->max_tfd_queue_size, 1103 txq->write_ptr, txq->read_ptr); 1104 goto out; 1105 } 1106 1107 if (WARN_ON(!skb_queue_empty(skbs))) 1108 goto out; 1109 1110 for (; 1111 read_ptr != tfd_num; 1112 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr), 1113 read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) { 1114 struct sk_buff *skb = txq->entries[read_ptr].skb; 1115 1116 if (WARN_ON_ONCE(!skb)) 1117 continue; 1118 1119 iwl_pcie_free_tso_page(trans_pcie, skb); 1120 1121 __skb_queue_tail(skbs, skb); 1122 1123 txq->entries[read_ptr].skb = NULL; 1124 1125 if (!trans->cfg->use_tfh) 1126 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1127 1128 iwl_pcie_txq_free_tfd(trans, txq); 1129 } 1130 1131 iwl_pcie_txq_progress(txq); 1132 1133 if (iwl_queue_space(trans, txq) > txq->low_mark && 1134 test_bit(txq_id, trans_pcie->queue_stopped)) { 1135 struct sk_buff_head overflow_skbs; 1136 1137 __skb_queue_head_init(&overflow_skbs); 1138 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 1139 1140 /* 1141 * This is tricky: we are in reclaim path which is non 1142 * re-entrant, so noone will try to take the access the 1143 * txq data from that path. We stopped tx, so we can't 1144 * have tx as well. Bottom line, we can unlock and re-lock 1145 * later. 1146 */ 1147 spin_unlock_bh(&txq->lock); 1148 1149 while (!skb_queue_empty(&overflow_skbs)) { 1150 struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 1151 struct iwl_device_cmd *dev_cmd_ptr; 1152 1153 dev_cmd_ptr = *(void **)((u8 *)skb->cb + 1154 trans_pcie->dev_cmd_offs); 1155 1156 /* 1157 * Note that we can very well be overflowing again. 1158 * In that case, iwl_queue_space will be small again 1159 * and we won't wake mac80211's queue. 1160 */ 1161 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id); 1162 } 1163 1164 if (iwl_queue_space(trans, txq) > txq->low_mark) 1165 iwl_wake_queue(trans, txq); 1166 1167 spin_lock_bh(&txq->lock); 1168 } 1169 1170 if (txq->read_ptr == txq->write_ptr) { 1171 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); 1172 iwl_trans_unref(trans); 1173 } 1174 1175 out: 1176 spin_unlock_bh(&txq->lock); 1177 } 1178 1179 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1180 const struct iwl_host_cmd *cmd) 1181 { 1182 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1183 const struct iwl_cfg *cfg = trans->cfg; 1184 int ret; 1185 1186 lockdep_assert_held(&trans_pcie->reg_lock); 1187 1188 /* Make sure the NIC is still alive in the bus */ 1189 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1190 return -ENODEV; 1191 1192 if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1193 !trans_pcie->ref_cmd_in_flight) { 1194 trans_pcie->ref_cmd_in_flight = true; 1195 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1196 iwl_trans_ref(trans); 1197 } 1198 1199 /* 1200 * wake up the NIC to make sure that the firmware will see the host 1201 * command - we will let the NIC sleep once all the host commands 1202 * returned. This needs to be done only on NICs that have 1203 * apmg_wake_up_wa set. 1204 */ 1205 if (cfg->base_params->apmg_wake_up_wa && 1206 !trans_pcie->cmd_hold_nic_awake) { 1207 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1208 BIT(cfg->csr->flag_mac_access_req)); 1209 1210 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1211 BIT(cfg->csr->flag_val_mac_access_en), 1212 (BIT(cfg->csr->flag_mac_clock_ready) | 1213 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1214 15000); 1215 if (ret < 0) { 1216 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1217 BIT(cfg->csr->flag_mac_access_req)); 1218 IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1219 return -EIO; 1220 } 1221 trans_pcie->cmd_hold_nic_awake = true; 1222 } 1223 1224 return 0; 1225 } 1226 1227 /* 1228 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1229 * 1230 * When FW advances 'R' index, all entries between old and new 'R' index 1231 * need to be reclaimed. As result, some free space forms. If there is 1232 * enough free space (> low mark), wake the stack that feeds us. 1233 */ 1234 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1235 { 1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1238 unsigned long flags; 1239 int nfreed = 0; 1240 u16 r; 1241 1242 lockdep_assert_held(&txq->lock); 1243 1244 idx = iwl_pcie_get_cmd_index(txq, idx); 1245 r = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1246 1247 if (idx >= trans->cfg->base_params->max_tfd_queue_size || 1248 (!iwl_queue_used(txq, idx))) { 1249 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used), 1250 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1251 __func__, txq_id, idx, 1252 trans->cfg->base_params->max_tfd_queue_size, 1253 txq->write_ptr, txq->read_ptr); 1254 return; 1255 } 1256 1257 for (idx = iwl_queue_inc_wrap(trans, idx); r != idx; 1258 r = iwl_queue_inc_wrap(trans, r)) { 1259 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1260 1261 if (nfreed++ > 0) { 1262 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1263 idx, txq->write_ptr, r); 1264 iwl_force_nmi(trans); 1265 } 1266 } 1267 1268 if (txq->read_ptr == txq->write_ptr) { 1269 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1270 iwl_pcie_clear_cmd_in_flight(trans); 1271 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1272 } 1273 1274 iwl_pcie_txq_progress(txq); 1275 } 1276 1277 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1278 u16 txq_id) 1279 { 1280 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1281 u32 tbl_dw_addr; 1282 u32 tbl_dw; 1283 u16 scd_q2ratid; 1284 1285 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1286 1287 tbl_dw_addr = trans_pcie->scd_base_addr + 1288 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1289 1290 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1291 1292 if (txq_id & 0x1) 1293 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1294 else 1295 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1296 1297 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1298 1299 return 0; 1300 } 1301 1302 /* Receiver address (actually, Rx station's index into station table), 1303 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1304 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1305 1306 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1307 const struct iwl_trans_txq_scd_cfg *cfg, 1308 unsigned int wdg_timeout) 1309 { 1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1311 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1312 int fifo = -1; 1313 bool scd_bug = false; 1314 1315 if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1316 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1317 1318 txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1319 1320 if (cfg) { 1321 fifo = cfg->fifo; 1322 1323 /* Disable the scheduler prior configuring the cmd queue */ 1324 if (txq_id == trans_pcie->cmd_queue && 1325 trans_pcie->scd_set_active) 1326 iwl_scd_enable_set_active(trans, 0); 1327 1328 /* Stop this Tx queue before configuring it */ 1329 iwl_scd_txq_set_inactive(trans, txq_id); 1330 1331 /* Set this queue as a chain-building queue unless it is CMD */ 1332 if (txq_id != trans_pcie->cmd_queue) 1333 iwl_scd_txq_set_chain(trans, txq_id); 1334 1335 if (cfg->aggregate) { 1336 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1337 1338 /* Map receiver-address / traffic-ID to this queue */ 1339 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1340 1341 /* enable aggregations for the queue */ 1342 iwl_scd_txq_enable_agg(trans, txq_id); 1343 txq->ampdu = true; 1344 } else { 1345 /* 1346 * disable aggregations for the queue, this will also 1347 * make the ra_tid mapping configuration irrelevant 1348 * since it is now a non-AGG queue. 1349 */ 1350 iwl_scd_txq_disable_agg(trans, txq_id); 1351 1352 ssn = txq->read_ptr; 1353 } 1354 } else { 1355 /* 1356 * If we need to move the SCD write pointer by steps of 1357 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1358 * the op_mode know by returning true later. 1359 * Do this only in case cfg is NULL since this trick can 1360 * be done only if we have DQA enabled which is true for mvm 1361 * only. And mvm never sets a cfg pointer. 1362 * This is really ugly, but this is the easiest way out for 1363 * this sad hardware issue. 1364 * This bug has been fixed on devices 9000 and up. 1365 */ 1366 scd_bug = !trans->cfg->mq_rx_supported && 1367 !((ssn - txq->write_ptr) & 0x3f) && 1368 (ssn != txq->write_ptr); 1369 if (scd_bug) 1370 ssn++; 1371 } 1372 1373 /* Place first TFD at index corresponding to start sequence number. 1374 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1375 txq->read_ptr = (ssn & 0xff); 1376 txq->write_ptr = (ssn & 0xff); 1377 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1378 (ssn & 0xff) | (txq_id << 8)); 1379 1380 if (cfg) { 1381 u8 frame_limit = cfg->frame_limit; 1382 1383 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1384 1385 /* Set up Tx window size and frame limit for this queue */ 1386 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1387 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1388 iwl_trans_write_mem32(trans, 1389 trans_pcie->scd_base_addr + 1390 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1391 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1392 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1393 1394 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1395 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1396 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1397 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1398 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1399 SCD_QUEUE_STTS_REG_MSK); 1400 1401 /* enable the scheduler for this queue (only) */ 1402 if (txq_id == trans_pcie->cmd_queue && 1403 trans_pcie->scd_set_active) 1404 iwl_scd_enable_set_active(trans, BIT(txq_id)); 1405 1406 IWL_DEBUG_TX_QUEUES(trans, 1407 "Activate queue %d on FIFO %d WrPtr: %d\n", 1408 txq_id, fifo, ssn & 0xff); 1409 } else { 1410 IWL_DEBUG_TX_QUEUES(trans, 1411 "Activate queue %d WrPtr: %d\n", 1412 txq_id, ssn & 0xff); 1413 } 1414 1415 return scd_bug; 1416 } 1417 1418 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 1419 bool shared_mode) 1420 { 1421 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1422 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1423 1424 txq->ampdu = !shared_mode; 1425 } 1426 1427 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1428 bool configure_scd) 1429 { 1430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1431 u32 stts_addr = trans_pcie->scd_base_addr + 1432 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1433 static const u32 zero_val[4] = {}; 1434 1435 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1436 trans_pcie->txq[txq_id]->frozen = false; 1437 1438 /* 1439 * Upon HW Rfkill - we stop the device, and then stop the queues 1440 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1441 * allow the op_mode to call txq_disable after it already called 1442 * stop_device. 1443 */ 1444 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1445 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1446 "queue %d not used", txq_id); 1447 return; 1448 } 1449 1450 if (configure_scd) { 1451 iwl_scd_txq_set_inactive(trans, txq_id); 1452 1453 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1454 ARRAY_SIZE(zero_val)); 1455 } 1456 1457 iwl_pcie_txq_unmap(trans, txq_id); 1458 trans_pcie->txq[txq_id]->ampdu = false; 1459 1460 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1461 } 1462 1463 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1464 1465 /* 1466 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1467 * @priv: device private data point 1468 * @cmd: a pointer to the ucode command structure 1469 * 1470 * The function returns < 0 values to indicate the operation 1471 * failed. On success, it returns the index (>= 0) of command in the 1472 * command queue. 1473 */ 1474 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1475 struct iwl_host_cmd *cmd) 1476 { 1477 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1478 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1479 struct iwl_device_cmd *out_cmd; 1480 struct iwl_cmd_meta *out_meta; 1481 unsigned long flags; 1482 void *dup_buf = NULL; 1483 dma_addr_t phys_addr; 1484 int idx; 1485 u16 copy_size, cmd_size, tb0_size; 1486 bool had_nocopy = false; 1487 u8 group_id = iwl_cmd_groupid(cmd->id); 1488 int i, ret; 1489 u32 cmd_pos; 1490 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1491 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1492 1493 if (WARN(!trans->wide_cmd_header && 1494 group_id > IWL_ALWAYS_LONG_GROUP, 1495 "unsupported wide command %#x\n", cmd->id)) 1496 return -EINVAL; 1497 1498 if (group_id != 0) { 1499 copy_size = sizeof(struct iwl_cmd_header_wide); 1500 cmd_size = sizeof(struct iwl_cmd_header_wide); 1501 } else { 1502 copy_size = sizeof(struct iwl_cmd_header); 1503 cmd_size = sizeof(struct iwl_cmd_header); 1504 } 1505 1506 /* need one for the header if the first is NOCOPY */ 1507 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1508 1509 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1510 cmddata[i] = cmd->data[i]; 1511 cmdlen[i] = cmd->len[i]; 1512 1513 if (!cmd->len[i]) 1514 continue; 1515 1516 /* need at least IWL_FIRST_TB_SIZE copied */ 1517 if (copy_size < IWL_FIRST_TB_SIZE) { 1518 int copy = IWL_FIRST_TB_SIZE - copy_size; 1519 1520 if (copy > cmdlen[i]) 1521 copy = cmdlen[i]; 1522 cmdlen[i] -= copy; 1523 cmddata[i] += copy; 1524 copy_size += copy; 1525 } 1526 1527 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1528 had_nocopy = true; 1529 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1530 idx = -EINVAL; 1531 goto free_dup_buf; 1532 } 1533 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1534 /* 1535 * This is also a chunk that isn't copied 1536 * to the static buffer so set had_nocopy. 1537 */ 1538 had_nocopy = true; 1539 1540 /* only allowed once */ 1541 if (WARN_ON(dup_buf)) { 1542 idx = -EINVAL; 1543 goto free_dup_buf; 1544 } 1545 1546 dup_buf = kmemdup(cmddata[i], cmdlen[i], 1547 GFP_ATOMIC); 1548 if (!dup_buf) 1549 return -ENOMEM; 1550 } else { 1551 /* NOCOPY must not be followed by normal! */ 1552 if (WARN_ON(had_nocopy)) { 1553 idx = -EINVAL; 1554 goto free_dup_buf; 1555 } 1556 copy_size += cmdlen[i]; 1557 } 1558 cmd_size += cmd->len[i]; 1559 } 1560 1561 /* 1562 * If any of the command structures end up being larger than 1563 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1564 * allocated into separate TFDs, then we will need to 1565 * increase the size of the buffers. 1566 */ 1567 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1568 "Command %s (%#x) is too large (%d bytes)\n", 1569 iwl_get_cmd_string(trans, cmd->id), 1570 cmd->id, copy_size)) { 1571 idx = -EINVAL; 1572 goto free_dup_buf; 1573 } 1574 1575 spin_lock_bh(&txq->lock); 1576 1577 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1578 spin_unlock_bh(&txq->lock); 1579 1580 IWL_ERR(trans, "No space in command queue\n"); 1581 iwl_op_mode_cmd_queue_full(trans->op_mode); 1582 idx = -ENOSPC; 1583 goto free_dup_buf; 1584 } 1585 1586 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1587 out_cmd = txq->entries[idx].cmd; 1588 out_meta = &txq->entries[idx].meta; 1589 1590 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1591 if (cmd->flags & CMD_WANT_SKB) 1592 out_meta->source = cmd; 1593 1594 /* set up the header */ 1595 if (group_id != 0) { 1596 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1597 out_cmd->hdr_wide.group_id = group_id; 1598 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1599 out_cmd->hdr_wide.length = 1600 cpu_to_le16(cmd_size - 1601 sizeof(struct iwl_cmd_header_wide)); 1602 out_cmd->hdr_wide.reserved = 0; 1603 out_cmd->hdr_wide.sequence = 1604 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1605 INDEX_TO_SEQ(txq->write_ptr)); 1606 1607 cmd_pos = sizeof(struct iwl_cmd_header_wide); 1608 copy_size = sizeof(struct iwl_cmd_header_wide); 1609 } else { 1610 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1611 out_cmd->hdr.sequence = 1612 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1613 INDEX_TO_SEQ(txq->write_ptr)); 1614 out_cmd->hdr.group_id = 0; 1615 1616 cmd_pos = sizeof(struct iwl_cmd_header); 1617 copy_size = sizeof(struct iwl_cmd_header); 1618 } 1619 1620 /* and copy the data that needs to be copied */ 1621 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1622 int copy; 1623 1624 if (!cmd->len[i]) 1625 continue; 1626 1627 /* copy everything if not nocopy/dup */ 1628 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1629 IWL_HCMD_DFL_DUP))) { 1630 copy = cmd->len[i]; 1631 1632 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1633 cmd_pos += copy; 1634 copy_size += copy; 1635 continue; 1636 } 1637 1638 /* 1639 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 1640 * in total (for bi-directional DMA), but copy up to what 1641 * we can fit into the payload for debug dump purposes. 1642 */ 1643 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1644 1645 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1646 cmd_pos += copy; 1647 1648 /* However, treat copy_size the proper way, we need it below */ 1649 if (copy_size < IWL_FIRST_TB_SIZE) { 1650 copy = IWL_FIRST_TB_SIZE - copy_size; 1651 1652 if (copy > cmd->len[i]) 1653 copy = cmd->len[i]; 1654 copy_size += copy; 1655 } 1656 } 1657 1658 IWL_DEBUG_HC(trans, 1659 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1660 iwl_get_cmd_string(trans, cmd->id), 1661 group_id, out_cmd->hdr.cmd, 1662 le16_to_cpu(out_cmd->hdr.sequence), 1663 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1664 1665 /* start the TFD with the minimum copy bytes */ 1666 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 1667 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1668 iwl_pcie_txq_build_tfd(trans, txq, 1669 iwl_pcie_get_first_tb_dma(txq, idx), 1670 tb0_size, true); 1671 1672 /* map first command fragment, if any remains */ 1673 if (copy_size > tb0_size) { 1674 phys_addr = dma_map_single(trans->dev, 1675 ((u8 *)&out_cmd->hdr) + tb0_size, 1676 copy_size - tb0_size, 1677 DMA_TO_DEVICE); 1678 if (dma_mapping_error(trans->dev, phys_addr)) { 1679 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1680 txq->write_ptr); 1681 idx = -ENOMEM; 1682 goto out; 1683 } 1684 1685 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1686 copy_size - tb0_size, false); 1687 } 1688 1689 /* map the remaining (adjusted) nocopy/dup fragments */ 1690 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1691 const void *data = cmddata[i]; 1692 1693 if (!cmdlen[i]) 1694 continue; 1695 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1696 IWL_HCMD_DFL_DUP))) 1697 continue; 1698 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1699 data = dup_buf; 1700 phys_addr = dma_map_single(trans->dev, (void *)data, 1701 cmdlen[i], DMA_TO_DEVICE); 1702 if (dma_mapping_error(trans->dev, phys_addr)) { 1703 iwl_pcie_tfd_unmap(trans, out_meta, txq, 1704 txq->write_ptr); 1705 idx = -ENOMEM; 1706 goto out; 1707 } 1708 1709 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1710 } 1711 1712 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1713 out_meta->flags = cmd->flags; 1714 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1715 kzfree(txq->entries[idx].free_buf); 1716 txq->entries[idx].free_buf = dup_buf; 1717 1718 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1719 1720 /* start timer if queue currently empty */ 1721 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1722 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1723 1724 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1725 ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1726 if (ret < 0) { 1727 idx = ret; 1728 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1729 goto out; 1730 } 1731 1732 /* Increment and update queue's write index */ 1733 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 1734 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1735 1736 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1737 1738 out: 1739 spin_unlock_bh(&txq->lock); 1740 free_dup_buf: 1741 if (idx < 0) 1742 kfree(dup_buf); 1743 return idx; 1744 } 1745 1746 /* 1747 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1748 * @rxb: Rx buffer to reclaim 1749 */ 1750 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1751 struct iwl_rx_cmd_buffer *rxb) 1752 { 1753 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1754 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1755 u8 group_id; 1756 u32 cmd_id; 1757 int txq_id = SEQ_TO_QUEUE(sequence); 1758 int index = SEQ_TO_INDEX(sequence); 1759 int cmd_index; 1760 struct iwl_device_cmd *cmd; 1761 struct iwl_cmd_meta *meta; 1762 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1763 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1764 1765 /* If a Tx command is being handled and it isn't in the actual 1766 * command queue then there a command routing bug has been introduced 1767 * in the queue management code. */ 1768 if (WARN(txq_id != trans_pcie->cmd_queue, 1769 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1770 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1771 txq->write_ptr)) { 1772 iwl_print_hex_error(trans, pkt, 32); 1773 return; 1774 } 1775 1776 spin_lock_bh(&txq->lock); 1777 1778 cmd_index = iwl_pcie_get_cmd_index(txq, index); 1779 cmd = txq->entries[cmd_index].cmd; 1780 meta = &txq->entries[cmd_index].meta; 1781 group_id = cmd->hdr.group_id; 1782 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1783 1784 iwl_pcie_tfd_unmap(trans, meta, txq, index); 1785 1786 /* Input error checking is done when commands are added to queue. */ 1787 if (meta->flags & CMD_WANT_SKB) { 1788 struct page *p = rxb_steal_page(rxb); 1789 1790 meta->source->resp_pkt = pkt; 1791 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1792 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1793 } 1794 1795 if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1796 iwl_op_mode_async_cb(trans->op_mode, cmd); 1797 1798 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1799 1800 if (!(meta->flags & CMD_ASYNC)) { 1801 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1802 IWL_WARN(trans, 1803 "HCMD_ACTIVE already clear for command %s\n", 1804 iwl_get_cmd_string(trans, cmd_id)); 1805 } 1806 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1807 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1808 iwl_get_cmd_string(trans, cmd_id)); 1809 wake_up(&trans_pcie->wait_command_queue); 1810 } 1811 1812 if (meta->flags & CMD_MAKE_TRANS_IDLE) { 1813 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 1814 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1815 set_bit(STATUS_TRANS_IDLE, &trans->status); 1816 wake_up(&trans_pcie->d0i3_waitq); 1817 } 1818 1819 if (meta->flags & CMD_WAKE_UP_TRANS) { 1820 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 1821 iwl_get_cmd_string(trans, cmd->hdr.cmd)); 1822 clear_bit(STATUS_TRANS_IDLE, &trans->status); 1823 wake_up(&trans_pcie->d0i3_waitq); 1824 } 1825 1826 meta->flags = 0; 1827 1828 spin_unlock_bh(&txq->lock); 1829 } 1830 1831 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1832 1833 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1834 struct iwl_host_cmd *cmd) 1835 { 1836 int ret; 1837 1838 /* An asynchronous command can not expect an SKB to be set. */ 1839 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1840 return -EINVAL; 1841 1842 ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1843 if (ret < 0) { 1844 IWL_ERR(trans, 1845 "Error sending %s: enqueue_hcmd failed: %d\n", 1846 iwl_get_cmd_string(trans, cmd->id), ret); 1847 return ret; 1848 } 1849 return 0; 1850 } 1851 1852 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1853 struct iwl_host_cmd *cmd) 1854 { 1855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1856 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1857 int cmd_idx; 1858 int ret; 1859 1860 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 1861 iwl_get_cmd_string(trans, cmd->id)); 1862 1863 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1864 &trans->status), 1865 "Command %s: a command is already active!\n", 1866 iwl_get_cmd_string(trans, cmd->id))) 1867 return -EIO; 1868 1869 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 1870 iwl_get_cmd_string(trans, cmd->id)); 1871 1872 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 1873 ret = wait_event_timeout(trans_pcie->d0i3_waitq, 1874 pm_runtime_active(&trans_pcie->pci_dev->dev), 1875 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 1876 if (!ret) { 1877 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 1878 return -ETIMEDOUT; 1879 } 1880 } 1881 1882 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1883 if (cmd_idx < 0) { 1884 ret = cmd_idx; 1885 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1886 IWL_ERR(trans, 1887 "Error sending %s: enqueue_hcmd failed: %d\n", 1888 iwl_get_cmd_string(trans, cmd->id), ret); 1889 return ret; 1890 } 1891 1892 ret = wait_event_timeout(trans_pcie->wait_command_queue, 1893 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1894 &trans->status), 1895 HOST_COMPLETE_TIMEOUT); 1896 if (!ret) { 1897 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 1898 iwl_get_cmd_string(trans, cmd->id), 1899 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1900 1901 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1902 txq->read_ptr, txq->write_ptr); 1903 1904 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1905 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1906 iwl_get_cmd_string(trans, cmd->id)); 1907 ret = -ETIMEDOUT; 1908 1909 iwl_force_nmi(trans); 1910 iwl_trans_fw_error(trans); 1911 1912 goto cancel; 1913 } 1914 1915 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1916 iwl_trans_pcie_dump_regs(trans); 1917 IWL_ERR(trans, "FW error in SYNC CMD %s\n", 1918 iwl_get_cmd_string(trans, cmd->id)); 1919 dump_stack(); 1920 ret = -EIO; 1921 goto cancel; 1922 } 1923 1924 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1925 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1926 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1927 ret = -ERFKILL; 1928 goto cancel; 1929 } 1930 1931 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1932 IWL_ERR(trans, "Error: Response NULL in '%s'\n", 1933 iwl_get_cmd_string(trans, cmd->id)); 1934 ret = -EIO; 1935 goto cancel; 1936 } 1937 1938 return 0; 1939 1940 cancel: 1941 if (cmd->flags & CMD_WANT_SKB) { 1942 /* 1943 * Cancel the CMD_WANT_SKB flag for the cmd in the 1944 * TX cmd queue. Otherwise in case the cmd comes 1945 * in later, it will possibly set an invalid 1946 * address (cmd->meta.source). 1947 */ 1948 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1949 } 1950 1951 if (cmd->resp_pkt) { 1952 iwl_free_resp(cmd); 1953 cmd->resp_pkt = NULL; 1954 } 1955 1956 return ret; 1957 } 1958 1959 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1960 { 1961 /* Make sure the NIC is still alive in the bus */ 1962 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1963 return -ENODEV; 1964 1965 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1966 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1967 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1968 cmd->id); 1969 return -ERFKILL; 1970 } 1971 1972 if (cmd->flags & CMD_ASYNC) 1973 return iwl_pcie_send_hcmd_async(trans, cmd); 1974 1975 /* We still can fail on RFKILL that can be asserted while we wait */ 1976 return iwl_pcie_send_hcmd_sync(trans, cmd); 1977 } 1978 1979 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 1980 struct iwl_txq *txq, u8 hdr_len, 1981 struct iwl_cmd_meta *out_meta) 1982 { 1983 u16 head_tb_len; 1984 int i; 1985 1986 /* 1987 * Set up TFD's third entry to point directly to remainder 1988 * of skb's head, if any 1989 */ 1990 head_tb_len = skb_headlen(skb) - hdr_len; 1991 1992 if (head_tb_len > 0) { 1993 dma_addr_t tb_phys = dma_map_single(trans->dev, 1994 skb->data + hdr_len, 1995 head_tb_len, DMA_TO_DEVICE); 1996 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 1997 return -EINVAL; 1998 trace_iwlwifi_dev_tx_tb(trans->dev, skb, 1999 skb->data + hdr_len, 2000 head_tb_len); 2001 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false); 2002 } 2003 2004 /* set up the remaining entries to point to the data */ 2005 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2006 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2007 dma_addr_t tb_phys; 2008 int tb_idx; 2009 2010 if (!skb_frag_size(frag)) 2011 continue; 2012 2013 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 2014 skb_frag_size(frag), DMA_TO_DEVICE); 2015 2016 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 2017 return -EINVAL; 2018 trace_iwlwifi_dev_tx_tb(trans->dev, skb, 2019 skb_frag_address(frag), 2020 skb_frag_size(frag)); 2021 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2022 skb_frag_size(frag), false); 2023 if (tb_idx < 0) 2024 return tb_idx; 2025 2026 out_meta->tbs |= BIT(tb_idx); 2027 } 2028 2029 return 0; 2030 } 2031 2032 #ifdef CONFIG_INET 2033 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 2034 { 2035 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2036 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 2037 2038 if (!p->page) 2039 goto alloc; 2040 2041 /* enough room on this page */ 2042 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 2043 return p; 2044 2045 /* We don't have enough room on this page, get a new one. */ 2046 __free_page(p->page); 2047 2048 alloc: 2049 p->page = alloc_page(GFP_ATOMIC); 2050 if (!p->page) 2051 return NULL; 2052 p->pos = page_address(p->page); 2053 return p; 2054 } 2055 2056 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 2057 bool ipv6, unsigned int len) 2058 { 2059 if (ipv6) { 2060 struct ipv6hdr *iphv6 = iph; 2061 2062 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 2063 len + tcph->doff * 4, 2064 IPPROTO_TCP, 0); 2065 } else { 2066 struct iphdr *iphv4 = iph; 2067 2068 ip_send_check(iphv4); 2069 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 2070 len + tcph->doff * 4, 2071 IPPROTO_TCP, 0); 2072 } 2073 } 2074 2075 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2076 struct iwl_txq *txq, u8 hdr_len, 2077 struct iwl_cmd_meta *out_meta, 2078 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2079 { 2080 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 2081 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 2082 struct ieee80211_hdr *hdr = (void *)skb->data; 2083 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 2084 unsigned int mss = skb_shinfo(skb)->gso_size; 2085 u16 length, iv_len, amsdu_pad; 2086 u8 *start_hdr; 2087 struct iwl_tso_hdr_page *hdr_page; 2088 struct page **page_ptr; 2089 struct tso_t tso; 2090 2091 /* if the packet is protected, then it must be CCMP or GCMP */ 2092 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 2093 iv_len = ieee80211_has_protected(hdr->frame_control) ? 2094 IEEE80211_CCMP_HDR_LEN : 0; 2095 2096 trace_iwlwifi_dev_tx(trans->dev, skb, 2097 iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 2098 trans_pcie->tfd_size, 2099 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 2100 2101 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 2102 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 2103 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 2104 amsdu_pad = 0; 2105 2106 /* total amount of header we may need for this A-MSDU */ 2107 hdr_room = DIV_ROUND_UP(total_len, mss) * 2108 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 2109 2110 /* Our device supports 9 segments at most, it will fit in 1 page */ 2111 hdr_page = get_page_hdr(trans, hdr_room); 2112 if (!hdr_page) 2113 return -ENOMEM; 2114 2115 get_page(hdr_page->page); 2116 start_hdr = hdr_page->pos; 2117 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 2118 *page_ptr = hdr_page->page; 2119 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 2120 hdr_page->pos += iv_len; 2121 2122 /* 2123 * Pull the ieee80211 header + IV to be able to use TSO core, 2124 * we will restore it for the tx_status flow. 2125 */ 2126 skb_pull(skb, hdr_len + iv_len); 2127 2128 /* 2129 * Remove the length of all the headers that we don't actually 2130 * have in the MPDU by themselves, but that we duplicate into 2131 * all the different MSDUs inside the A-MSDU. 2132 */ 2133 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 2134 2135 tso_start(skb, &tso); 2136 2137 while (total_len) { 2138 /* this is the data left for this subframe */ 2139 unsigned int data_left = 2140 min_t(unsigned int, mss, total_len); 2141 struct sk_buff *csum_skb = NULL; 2142 unsigned int hdr_tb_len; 2143 dma_addr_t hdr_tb_phys; 2144 struct tcphdr *tcph; 2145 u8 *iph, *subf_hdrs_start = hdr_page->pos; 2146 2147 total_len -= data_left; 2148 2149 memset(hdr_page->pos, 0, amsdu_pad); 2150 hdr_page->pos += amsdu_pad; 2151 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 2152 data_left)) & 0x3; 2153 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 2154 hdr_page->pos += ETH_ALEN; 2155 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 2156 hdr_page->pos += ETH_ALEN; 2157 2158 length = snap_ip_tcp_hdrlen + data_left; 2159 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 2160 hdr_page->pos += sizeof(length); 2161 2162 /* 2163 * This will copy the SNAP as well which will be considered 2164 * as MAC header. 2165 */ 2166 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 2167 iph = hdr_page->pos + 8; 2168 tcph = (void *)(iph + ip_hdrlen); 2169 2170 /* For testing on current hardware only */ 2171 if (trans_pcie->sw_csum_tx) { 2172 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 2173 GFP_ATOMIC); 2174 if (!csum_skb) 2175 return -ENOMEM; 2176 2177 iwl_compute_pseudo_hdr_csum(iph, tcph, 2178 skb->protocol == 2179 htons(ETH_P_IPV6), 2180 data_left); 2181 2182 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2183 skb_reset_transport_header(csum_skb); 2184 csum_skb->csum_start = 2185 (unsigned char *)tcp_hdr(csum_skb) - 2186 csum_skb->head; 2187 } 2188 2189 hdr_page->pos += snap_ip_tcp_hdrlen; 2190 2191 hdr_tb_len = hdr_page->pos - start_hdr; 2192 hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 2193 hdr_tb_len, DMA_TO_DEVICE); 2194 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 2195 dev_kfree_skb(csum_skb); 2196 return -EINVAL; 2197 } 2198 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 2199 hdr_tb_len, false); 2200 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, 2201 hdr_tb_len); 2202 /* add this subframe's headers' length to the tx_cmd */ 2203 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 2204 2205 /* prepare the start_hdr for the next subframe */ 2206 start_hdr = hdr_page->pos; 2207 2208 /* put the payload */ 2209 while (data_left) { 2210 unsigned int size = min_t(unsigned int, tso.size, 2211 data_left); 2212 dma_addr_t tb_phys; 2213 2214 if (trans_pcie->sw_csum_tx) 2215 skb_put_data(csum_skb, tso.data, size); 2216 2217 tb_phys = dma_map_single(trans->dev, tso.data, 2218 size, DMA_TO_DEVICE); 2219 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2220 dev_kfree_skb(csum_skb); 2221 return -EINVAL; 2222 } 2223 2224 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 2225 size, false); 2226 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 2227 size); 2228 2229 data_left -= size; 2230 tso_build_data(skb, &tso, size); 2231 } 2232 2233 /* For testing on early hardware only */ 2234 if (trans_pcie->sw_csum_tx) { 2235 __wsum csum; 2236 2237 csum = skb_checksum(csum_skb, 2238 skb_checksum_start_offset(csum_skb), 2239 csum_skb->len - 2240 skb_checksum_start_offset(csum_skb), 2241 0); 2242 dev_kfree_skb(csum_skb); 2243 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 2244 hdr_tb_len, DMA_TO_DEVICE); 2245 tcph->check = csum_fold(csum); 2246 dma_sync_single_for_device(trans->dev, hdr_tb_phys, 2247 hdr_tb_len, DMA_TO_DEVICE); 2248 } 2249 } 2250 2251 /* re -add the WiFi header and IV */ 2252 skb_push(skb, hdr_len + iv_len); 2253 2254 return 0; 2255 } 2256 #else /* CONFIG_INET */ 2257 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 2258 struct iwl_txq *txq, u8 hdr_len, 2259 struct iwl_cmd_meta *out_meta, 2260 struct iwl_device_cmd *dev_cmd, u16 tb1_len) 2261 { 2262 /* No A-MSDU without CONFIG_INET */ 2263 WARN_ON(1); 2264 2265 return -1; 2266 } 2267 #endif /* CONFIG_INET */ 2268 2269 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2270 struct iwl_device_cmd *dev_cmd, int txq_id) 2271 { 2272 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2273 struct ieee80211_hdr *hdr; 2274 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2275 struct iwl_cmd_meta *out_meta; 2276 struct iwl_txq *txq; 2277 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2278 void *tb1_addr; 2279 void *tfd; 2280 u16 len, tb1_len; 2281 bool wait_write_ptr; 2282 __le16 fc; 2283 u8 hdr_len; 2284 u16 wifi_seq; 2285 bool amsdu; 2286 2287 txq = trans_pcie->txq[txq_id]; 2288 2289 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2290 "TX on unused queue %d\n", txq_id)) 2291 return -EINVAL; 2292 2293 if (unlikely(trans_pcie->sw_csum_tx && 2294 skb->ip_summed == CHECKSUM_PARTIAL)) { 2295 int offs = skb_checksum_start_offset(skb); 2296 int csum_offs = offs + skb->csum_offset; 2297 __wsum csum; 2298 2299 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 2300 return -1; 2301 2302 csum = skb_checksum(skb, offs, skb->len - offs, 0); 2303 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 2304 2305 skb->ip_summed = CHECKSUM_UNNECESSARY; 2306 } 2307 2308 if (skb_is_nonlinear(skb) && 2309 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2310 __skb_linearize(skb)) 2311 return -ENOMEM; 2312 2313 /* mac80211 always puts the full header into the SKB's head, 2314 * so there's no need to check if it's readable there 2315 */ 2316 hdr = (struct ieee80211_hdr *)skb->data; 2317 fc = hdr->frame_control; 2318 hdr_len = ieee80211_hdrlen(fc); 2319 2320 spin_lock(&txq->lock); 2321 2322 if (iwl_queue_space(trans, txq) < txq->high_mark) { 2323 iwl_stop_queue(trans, txq); 2324 2325 /* don't put the packet on the ring, if there is no room */ 2326 if (unlikely(iwl_queue_space(trans, txq) < 3)) { 2327 struct iwl_device_cmd **dev_cmd_ptr; 2328 2329 dev_cmd_ptr = (void *)((u8 *)skb->cb + 2330 trans_pcie->dev_cmd_offs); 2331 2332 *dev_cmd_ptr = dev_cmd; 2333 __skb_queue_tail(&txq->overflow_q, skb); 2334 2335 spin_unlock(&txq->lock); 2336 return 0; 2337 } 2338 } 2339 2340 /* In AGG mode, the index in the ring must correspond to the WiFi 2341 * sequence number. This is a HW requirements to help the SCD to parse 2342 * the BA. 2343 * Check here that the packets are in the right place on the ring. 2344 */ 2345 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2346 WARN_ONCE(txq->ampdu && 2347 (wifi_seq & 0xff) != txq->write_ptr, 2348 "Q: %d WiFi Seq %d tfdNum %d", 2349 txq_id, wifi_seq, txq->write_ptr); 2350 2351 /* Set up driver data for this TFD */ 2352 txq->entries[txq->write_ptr].skb = skb; 2353 txq->entries[txq->write_ptr].cmd = dev_cmd; 2354 2355 dev_cmd->hdr.sequence = 2356 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2357 INDEX_TO_SEQ(txq->write_ptr))); 2358 2359 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2360 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2361 offsetof(struct iwl_tx_cmd, scratch); 2362 2363 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2364 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2365 2366 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2367 out_meta = &txq->entries[txq->write_ptr].meta; 2368 out_meta->flags = 0; 2369 2370 /* 2371 * The second TB (tb1) points to the remainder of the TX command 2372 * and the 802.11 header - dword aligned size 2373 * (This calculation modifies the TX command, so do it before the 2374 * setup of the first TB) 2375 */ 2376 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 2377 hdr_len - IWL_FIRST_TB_SIZE; 2378 /* do not align A-MSDU to dword as the subframe header aligns it */ 2379 amsdu = ieee80211_is_data_qos(fc) && 2380 (*ieee80211_get_qos_ctl(hdr) & 2381 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2382 if (trans_pcie->sw_csum_tx || !amsdu) { 2383 tb1_len = ALIGN(len, 4); 2384 /* Tell NIC about any 2-byte padding after MAC header */ 2385 if (tb1_len != len) 2386 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2387 } else { 2388 tb1_len = len; 2389 } 2390 2391 /* 2392 * The first TB points to bi-directional DMA data, we'll 2393 * memcpy the data into it later. 2394 */ 2395 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 2396 IWL_FIRST_TB_SIZE, true); 2397 2398 /* there must be data left over for TB1 or this code must be changed */ 2399 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2400 2401 /* map the data for TB1 */ 2402 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2403 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2404 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2405 goto out_err; 2406 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2407 2408 trace_iwlwifi_dev_tx(trans->dev, skb, 2409 iwl_pcie_get_tfd(trans, txq, 2410 txq->write_ptr), 2411 trans_pcie->tfd_size, 2412 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2413 hdr_len); 2414 2415 /* 2416 * If gso_size wasn't set, don't give the frame "amsdu treatment" 2417 * (adding subframes, etc.). 2418 * This can happen in some testing flows when the amsdu was already 2419 * pre-built, and we just need to send the resulting skb. 2420 */ 2421 if (amsdu && skb_shinfo(skb)->gso_size) { 2422 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 2423 out_meta, dev_cmd, 2424 tb1_len))) 2425 goto out_err; 2426 } else { 2427 struct sk_buff *frag; 2428 2429 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2430 out_meta))) 2431 goto out_err; 2432 2433 skb_walk_frags(skb, frag) { 2434 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0, 2435 out_meta))) 2436 goto out_err; 2437 } 2438 } 2439 2440 /* building the A-MSDU might have changed this data, so memcpy it now */ 2441 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 2442 IWL_FIRST_TB_SIZE); 2443 2444 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 2445 /* Set up entry for this TFD in Tx byte-count array */ 2446 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 2447 iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2448 2449 wait_write_ptr = ieee80211_has_morefrags(fc); 2450 2451 /* start timer if queue currently empty */ 2452 if (txq->read_ptr == txq->write_ptr) { 2453 if (txq->wd_timeout) { 2454 /* 2455 * If the TXQ is active, then set the timer, if not, 2456 * set the timer in remainder so that the timer will 2457 * be armed with the right value when the station will 2458 * wake up. 2459 */ 2460 if (!txq->frozen) 2461 mod_timer(&txq->stuck_timer, 2462 jiffies + txq->wd_timeout); 2463 else 2464 txq->frozen_expiry_remainder = txq->wd_timeout; 2465 } 2466 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 2467 iwl_trans_ref(trans); 2468 } 2469 2470 /* Tell device the write index *just past* this latest filled TFD */ 2471 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 2472 if (!wait_write_ptr) 2473 iwl_pcie_txq_inc_wr_ptr(trans, txq); 2474 2475 /* 2476 * At this point the frame is "transmitted" successfully 2477 * and we will get a TX status notification eventually. 2478 */ 2479 spin_unlock(&txq->lock); 2480 return 0; 2481 out_err: 2482 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 2483 spin_unlock(&txq->lock); 2484 return -1; 2485 } 2486