1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2003-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ieee80211.h> 9 #include <linux/slab.h> 10 #include <linux/sched.h> 11 #include <net/ip6_checksum.h> 12 #include <net/tso.h> 13 14 #include "iwl-debug.h" 15 #include "iwl-csr.h" 16 #include "iwl-prph.h" 17 #include "iwl-io.h" 18 #include "iwl-scd.h" 19 #include "iwl-op-mode.h" 20 #include "internal.h" 21 #include "fw/api/tx.h" 22 23 /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 24 * DMA services 25 * 26 * Theory of operation 27 * 28 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 29 * of buffer descriptors, each of which points to one or more data buffers for 30 * the device to read from or fill. Driver and device exchange status of each 31 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 32 * entries in each circular buffer, to protect against confusing empty and full 33 * queue states. 34 * 35 * The device reads or writes the data in the queues via the device's several 36 * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 37 * 38 * For Tx queue, there are low mark and high mark limits. If, after queuing 39 * the packet for Tx, free space become < low mark, Tx queue stopped. When 40 * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 41 * Tx queue resumed. 42 * 43 ***************************************************/ 44 45 46 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 47 struct iwl_dma_ptr *ptr, size_t size) 48 { 49 if (WARN_ON(ptr->addr)) 50 return -EINVAL; 51 52 ptr->addr = dma_alloc_coherent(trans->dev, size, 53 &ptr->dma, GFP_KERNEL); 54 if (!ptr->addr) 55 return -ENOMEM; 56 ptr->size = size; 57 return 0; 58 } 59 60 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 61 { 62 if (unlikely(!ptr->addr)) 63 return; 64 65 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 66 memset(ptr, 0, sizeof(*ptr)); 67 } 68 69 /* 70 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 71 */ 72 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 73 struct iwl_txq *txq) 74 { 75 u32 reg = 0; 76 int txq_id = txq->id; 77 78 lockdep_assert_held(&txq->lock); 79 80 /* 81 * explicitly wake up the NIC if: 82 * 1. shadow registers aren't enabled 83 * 2. NIC is woken up for CMD regardless of shadow outside this function 84 * 3. there is a chance that the NIC is asleep 85 */ 86 if (!trans->trans_cfg->base_params->shadow_reg_enable && 87 txq_id != trans->txqs.cmd.q_id && 88 test_bit(STATUS_TPOWER_PMI, &trans->status)) { 89 /* 90 * wake up nic if it's powered down ... 91 * uCode will wake up, and interrupt us again, so next 92 * time we'll skip this part. 93 */ 94 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 95 96 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 97 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 98 txq_id, reg); 99 iwl_set_bit(trans, CSR_GP_CNTRL, 100 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 101 txq->need_update = true; 102 return; 103 } 104 } 105 106 /* 107 * if not in power-save mode, uCode will never sleep when we're 108 * trying to tx (during RFKILL, we're not trying to tx). 109 */ 110 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 111 if (!txq->block) 112 iwl_write32(trans, HBUS_TARG_WRPTR, 113 txq->write_ptr | (txq_id << 8)); 114 } 115 116 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 117 { 118 int i; 119 120 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 121 struct iwl_txq *txq = trans->txqs.txq[i]; 122 123 if (!test_bit(i, trans->txqs.queue_used)) 124 continue; 125 126 spin_lock_bh(&txq->lock); 127 if (txq->need_update) { 128 iwl_pcie_txq_inc_wr_ptr(trans, txq); 129 txq->need_update = false; 130 } 131 spin_unlock_bh(&txq->lock); 132 } 133 } 134 135 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 136 u8 idx, dma_addr_t addr, u16 len) 137 { 138 struct iwl_tfd *tfd_fh = (void *)tfd; 139 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 140 141 u16 hi_n_len = len << 4; 142 143 put_unaligned_le32(addr, &tb->lo); 144 hi_n_len |= iwl_get_dma_hi_addr(addr); 145 146 tb->hi_n_len = cpu_to_le16(hi_n_len); 147 148 tfd_fh->num_tbs = idx + 1; 149 } 150 151 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 152 dma_addr_t addr, u16 len, bool reset) 153 { 154 void *tfd; 155 u32 num_tbs; 156 157 tfd = (u8 *)txq->tfds + trans->txqs.tfd.size * txq->write_ptr; 158 159 if (reset) 160 memset(tfd, 0, trans->txqs.tfd.size); 161 162 num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd); 163 164 /* Each TFD can point to a maximum max_tbs Tx buffers */ 165 if (num_tbs >= trans->txqs.tfd.max_tbs) { 166 IWL_ERR(trans, "Error can not send more than %d chunks\n", 167 trans->txqs.tfd.max_tbs); 168 return -EINVAL; 169 } 170 171 if (WARN(addr & ~IWL_TX_DMA_MASK, 172 "Unaligned address = %llx\n", (unsigned long long)addr)) 173 return -EINVAL; 174 175 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 176 177 return num_tbs; 178 } 179 180 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 181 { 182 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 183 184 if (!trans->trans_cfg->base_params->apmg_wake_up_wa) 185 return; 186 187 spin_lock(&trans_pcie->reg_lock); 188 189 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) { 190 spin_unlock(&trans_pcie->reg_lock); 191 return; 192 } 193 194 trans_pcie->cmd_hold_nic_awake = false; 195 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 196 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 197 spin_unlock(&trans_pcie->reg_lock); 198 } 199 200 /* 201 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 202 */ 203 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 204 { 205 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 206 207 if (!txq) { 208 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n"); 209 return; 210 } 211 212 spin_lock_bh(&txq->lock); 213 while (txq->write_ptr != txq->read_ptr) { 214 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 215 txq_id, txq->read_ptr); 216 217 if (txq_id != trans->txqs.cmd.q_id) { 218 struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 219 220 if (WARN_ON_ONCE(!skb)) 221 continue; 222 223 iwl_txq_free_tso_page(trans, skb); 224 } 225 iwl_txq_free_tfd(trans, txq); 226 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr); 227 228 if (txq->read_ptr == txq->write_ptr && 229 txq_id == trans->txqs.cmd.q_id) 230 iwl_pcie_clear_cmd_in_flight(trans); 231 } 232 233 while (!skb_queue_empty(&txq->overflow_q)) { 234 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 235 236 iwl_op_mode_free_skb(trans->op_mode, skb); 237 } 238 239 spin_unlock_bh(&txq->lock); 240 241 /* just in case - this queue may have been stopped */ 242 iwl_wake_queue(trans, txq); 243 } 244 245 /* 246 * iwl_pcie_txq_free - Deallocate DMA queue. 247 * @txq: Transmit queue to deallocate. 248 * 249 * Empty queue by removing and destroying all BD's. 250 * Free all buffers. 251 * 0-fill, but do not free "txq" descriptor structure. 252 */ 253 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 254 { 255 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 256 struct device *dev = trans->dev; 257 int i; 258 259 if (WARN_ON(!txq)) 260 return; 261 262 iwl_pcie_txq_unmap(trans, txq_id); 263 264 /* De-alloc array of command/tx buffers */ 265 if (txq_id == trans->txqs.cmd.q_id) 266 for (i = 0; i < txq->n_window; i++) { 267 kfree_sensitive(txq->entries[i].cmd); 268 kfree_sensitive(txq->entries[i].free_buf); 269 } 270 271 /* De-alloc circular buffer of TFDs */ 272 if (txq->tfds) { 273 dma_free_coherent(dev, 274 trans->txqs.tfd.size * 275 trans->trans_cfg->base_params->max_tfd_queue_size, 276 txq->tfds, txq->dma_addr); 277 txq->dma_addr = 0; 278 txq->tfds = NULL; 279 280 dma_free_coherent(dev, 281 sizeof(*txq->first_tb_bufs) * txq->n_window, 282 txq->first_tb_bufs, txq->first_tb_dma); 283 } 284 285 kfree(txq->entries); 286 txq->entries = NULL; 287 288 del_timer_sync(&txq->stuck_timer); 289 290 /* 0-fill queue descriptor structure */ 291 memset(txq, 0, sizeof(*txq)); 292 } 293 294 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 295 { 296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 297 int nq = trans->trans_cfg->base_params->num_of_queues; 298 int chan; 299 u32 reg_val; 300 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 301 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 302 303 /* make sure all queue are not stopped/used */ 304 memset(trans->txqs.queue_stopped, 0, 305 sizeof(trans->txqs.queue_stopped)); 306 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 307 308 trans_pcie->scd_base_addr = 309 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 310 311 WARN_ON(scd_base_addr != 0 && 312 scd_base_addr != trans_pcie->scd_base_addr); 313 314 /* reset context data, TX status and translation data */ 315 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 316 SCD_CONTEXT_MEM_LOWER_BOUND, 317 NULL, clear_dwords); 318 319 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 320 trans->txqs.scd_bc_tbls.dma >> 10); 321 322 /* The chain extension of the SCD doesn't work well. This feature is 323 * enabled by default by the HW, so we need to disable it manually. 324 */ 325 if (trans->trans_cfg->base_params->scd_chain_ext_wa) 326 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 327 328 iwl_trans_ac_txq_enable(trans, trans->txqs.cmd.q_id, 329 trans->txqs.cmd.fifo, 330 trans->txqs.cmd.wdg_timeout); 331 332 /* Activate all Tx DMA/FIFO channels */ 333 iwl_scd_activate_fifos(trans); 334 335 /* Enable DMA channel */ 336 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 337 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 338 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 339 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 340 341 /* Update FH chicken bits */ 342 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 343 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 344 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 345 346 /* Enable L1-Active */ 347 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 348 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 349 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 350 } 351 352 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 353 { 354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 355 int txq_id; 356 357 /* 358 * we should never get here in gen2 trans mode return early to avoid 359 * having invalid accesses 360 */ 361 if (WARN_ON_ONCE(trans->trans_cfg->gen2)) 362 return; 363 364 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 365 txq_id++) { 366 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 367 if (trans->trans_cfg->use_tfh) 368 iwl_write_direct64(trans, 369 FH_MEM_CBBC_QUEUE(trans, txq_id), 370 txq->dma_addr); 371 else 372 iwl_write_direct32(trans, 373 FH_MEM_CBBC_QUEUE(trans, txq_id), 374 txq->dma_addr >> 8); 375 iwl_pcie_txq_unmap(trans, txq_id); 376 txq->read_ptr = 0; 377 txq->write_ptr = 0; 378 } 379 380 /* Tell NIC where to find the "keep warm" buffer */ 381 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 382 trans_pcie->kw.dma >> 4); 383 384 /* 385 * Send 0 as the scd_base_addr since the device may have be reset 386 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 387 * contain garbage. 388 */ 389 iwl_pcie_tx_start(trans, 0); 390 } 391 392 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 393 { 394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 395 int ch, ret; 396 u32 mask = 0; 397 398 spin_lock_bh(&trans_pcie->irq_lock); 399 400 if (!iwl_trans_grab_nic_access(trans)) 401 goto out; 402 403 /* Stop each Tx DMA channel */ 404 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 405 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 406 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 407 } 408 409 /* Wait for DMA channels to be idle */ 410 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 411 if (ret < 0) 412 IWL_ERR(trans, 413 "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 414 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 415 416 iwl_trans_release_nic_access(trans); 417 418 out: 419 spin_unlock_bh(&trans_pcie->irq_lock); 420 } 421 422 /* 423 * iwl_pcie_tx_stop - Stop all Tx DMA channels 424 */ 425 int iwl_pcie_tx_stop(struct iwl_trans *trans) 426 { 427 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 428 int txq_id; 429 430 /* Turn off all Tx DMA fifos */ 431 iwl_scd_deactivate_fifos(trans); 432 433 /* Turn off all Tx DMA channels */ 434 iwl_pcie_tx_stop_fh(trans); 435 436 /* 437 * This function can be called before the op_mode disabled the 438 * queues. This happens when we have an rfkill interrupt. 439 * Since we stop Tx altogether - mark the queues as stopped. 440 */ 441 memset(trans->txqs.queue_stopped, 0, 442 sizeof(trans->txqs.queue_stopped)); 443 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 444 445 /* This can happen: start_hw, stop_device */ 446 if (!trans_pcie->txq_memory) 447 return 0; 448 449 /* Unmap DMA from host system and free skb's */ 450 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 451 txq_id++) 452 iwl_pcie_txq_unmap(trans, txq_id); 453 454 return 0; 455 } 456 457 /* 458 * iwl_trans_tx_free - Free TXQ Context 459 * 460 * Destroy all TX DMA queues and structures 461 */ 462 void iwl_pcie_tx_free(struct iwl_trans *trans) 463 { 464 int txq_id; 465 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 466 467 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 468 469 /* Tx queues */ 470 if (trans_pcie->txq_memory) { 471 for (txq_id = 0; 472 txq_id < trans->trans_cfg->base_params->num_of_queues; 473 txq_id++) { 474 iwl_pcie_txq_free(trans, txq_id); 475 trans->txqs.txq[txq_id] = NULL; 476 } 477 } 478 479 kfree(trans_pcie->txq_memory); 480 trans_pcie->txq_memory = NULL; 481 482 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 483 484 iwl_pcie_free_dma_ptr(trans, &trans->txqs.scd_bc_tbls); 485 } 486 487 /* 488 * iwl_pcie_tx_alloc - allocate TX context 489 * Allocate all Tx DMA structures and initialize them 490 */ 491 static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 492 { 493 int ret; 494 int txq_id, slots_num; 495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 496 u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues; 497 498 if (WARN_ON(trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)) 499 return -EINVAL; 500 501 bc_tbls_size *= sizeof(struct iwlagn_scd_bc_tbl); 502 503 /*It is not allowed to alloc twice, so warn when this happens. 504 * We cannot rely on the previous allocation, so free and fail */ 505 if (WARN_ON(trans_pcie->txq_memory)) { 506 ret = -EINVAL; 507 goto error; 508 } 509 510 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->txqs.scd_bc_tbls, 511 bc_tbls_size); 512 if (ret) { 513 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 514 goto error; 515 } 516 517 /* Alloc keep-warm buffer */ 518 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 519 if (ret) { 520 IWL_ERR(trans, "Keep Warm allocation failed\n"); 521 goto error; 522 } 523 524 trans_pcie->txq_memory = 525 kcalloc(trans->trans_cfg->base_params->num_of_queues, 526 sizeof(struct iwl_txq), GFP_KERNEL); 527 if (!trans_pcie->txq_memory) { 528 IWL_ERR(trans, "Not enough memory for txq\n"); 529 ret = -ENOMEM; 530 goto error; 531 } 532 533 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 534 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 535 txq_id++) { 536 bool cmd_queue = (txq_id == trans->txqs.cmd.q_id); 537 538 if (cmd_queue) 539 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 540 trans->cfg->min_txq_size); 541 else 542 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 543 trans->cfg->min_ba_txq_size); 544 trans->txqs.txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 545 ret = iwl_txq_alloc(trans, trans->txqs.txq[txq_id], slots_num, 546 cmd_queue); 547 if (ret) { 548 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 549 goto error; 550 } 551 trans->txqs.txq[txq_id]->id = txq_id; 552 } 553 554 return 0; 555 556 error: 557 iwl_pcie_tx_free(trans); 558 559 return ret; 560 } 561 562 int iwl_pcie_tx_init(struct iwl_trans *trans) 563 { 564 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 565 int ret; 566 int txq_id, slots_num; 567 bool alloc = false; 568 569 if (!trans_pcie->txq_memory) { 570 ret = iwl_pcie_tx_alloc(trans); 571 if (ret) 572 goto error; 573 alloc = true; 574 } 575 576 spin_lock_bh(&trans_pcie->irq_lock); 577 578 /* Turn off all Tx DMA fifos */ 579 iwl_scd_deactivate_fifos(trans); 580 581 /* Tell NIC where to find the "keep warm" buffer */ 582 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 583 trans_pcie->kw.dma >> 4); 584 585 spin_unlock_bh(&trans_pcie->irq_lock); 586 587 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 588 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues; 589 txq_id++) { 590 bool cmd_queue = (txq_id == trans->txqs.cmd.q_id); 591 592 if (cmd_queue) 593 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 594 trans->cfg->min_txq_size); 595 else 596 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 597 trans->cfg->min_ba_txq_size); 598 ret = iwl_txq_init(trans, trans->txqs.txq[txq_id], slots_num, 599 cmd_queue); 600 if (ret) { 601 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 602 goto error; 603 } 604 605 /* 606 * Tell nic where to find circular buffer of TFDs for a 607 * given Tx queue, and enable the DMA channel used for that 608 * queue. 609 * Circular buffer (TFD queue in DRAM) physical base address 610 */ 611 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 612 trans->txqs.txq[txq_id]->dma_addr >> 8); 613 } 614 615 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 616 if (trans->trans_cfg->base_params->num_of_queues > 20) 617 iwl_set_bits_prph(trans, SCD_GP_CTRL, 618 SCD_GP_CTRL_ENABLE_31_QUEUES); 619 620 return 0; 621 error: 622 /*Upon error, free only if we allocated something */ 623 if (alloc) 624 iwl_pcie_tx_free(trans); 625 return ret; 626 } 627 628 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 629 const struct iwl_host_cmd *cmd) 630 { 631 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 632 633 /* Make sure the NIC is still alive in the bus */ 634 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 635 return -ENODEV; 636 637 if (!trans->trans_cfg->base_params->apmg_wake_up_wa) 638 return 0; 639 640 /* 641 * wake up the NIC to make sure that the firmware will see the host 642 * command - we will let the NIC sleep once all the host commands 643 * returned. This needs to be done only on NICs that have 644 * apmg_wake_up_wa set (see above.) 645 */ 646 if (!_iwl_trans_pcie_grab_nic_access(trans)) 647 return -EIO; 648 649 /* 650 * In iwl_trans_grab_nic_access(), we've acquired the reg_lock. 651 * There, we also returned immediately if cmd_hold_nic_awake is 652 * already true, so it's OK to unconditionally set it to true. 653 */ 654 trans_pcie->cmd_hold_nic_awake = true; 655 spin_unlock(&trans_pcie->reg_lock); 656 657 return 0; 658 } 659 660 /* 661 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 662 * 663 * When FW advances 'R' index, all entries between old and new 'R' index 664 * need to be reclaimed. As result, some free space forms. If there is 665 * enough free space (> low mark), wake the stack that feeds us. 666 */ 667 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 668 { 669 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 670 int nfreed = 0; 671 u16 r; 672 673 lockdep_assert_held(&txq->lock); 674 675 idx = iwl_txq_get_cmd_index(txq, idx); 676 r = iwl_txq_get_cmd_index(txq, txq->read_ptr); 677 678 if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size || 679 (!iwl_txq_used(txq, idx))) { 680 WARN_ONCE(test_bit(txq_id, trans->txqs.queue_used), 681 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 682 __func__, txq_id, idx, 683 trans->trans_cfg->base_params->max_tfd_queue_size, 684 txq->write_ptr, txq->read_ptr); 685 return; 686 } 687 688 for (idx = iwl_txq_inc_wrap(trans, idx); r != idx; 689 r = iwl_txq_inc_wrap(trans, r)) { 690 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr); 691 692 if (nfreed++ > 0) { 693 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 694 idx, txq->write_ptr, r); 695 iwl_force_nmi(trans); 696 } 697 } 698 699 if (txq->read_ptr == txq->write_ptr) 700 iwl_pcie_clear_cmd_in_flight(trans); 701 702 iwl_txq_progress(txq); 703 } 704 705 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 706 u16 txq_id) 707 { 708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 709 u32 tbl_dw_addr; 710 u32 tbl_dw; 711 u16 scd_q2ratid; 712 713 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 714 715 tbl_dw_addr = trans_pcie->scd_base_addr + 716 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 717 718 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 719 720 if (txq_id & 0x1) 721 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 722 else 723 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 724 725 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 726 727 return 0; 728 } 729 730 /* Receiver address (actually, Rx station's index into station table), 731 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 732 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 733 734 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 735 const struct iwl_trans_txq_scd_cfg *cfg, 736 unsigned int wdg_timeout) 737 { 738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 739 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 740 int fifo = -1; 741 bool scd_bug = false; 742 743 if (test_and_set_bit(txq_id, trans->txqs.queue_used)) 744 WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 745 746 txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 747 748 if (cfg) { 749 fifo = cfg->fifo; 750 751 /* Disable the scheduler prior configuring the cmd queue */ 752 if (txq_id == trans->txqs.cmd.q_id && 753 trans_pcie->scd_set_active) 754 iwl_scd_enable_set_active(trans, 0); 755 756 /* Stop this Tx queue before configuring it */ 757 iwl_scd_txq_set_inactive(trans, txq_id); 758 759 /* Set this queue as a chain-building queue unless it is CMD */ 760 if (txq_id != trans->txqs.cmd.q_id) 761 iwl_scd_txq_set_chain(trans, txq_id); 762 763 if (cfg->aggregate) { 764 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 765 766 /* Map receiver-address / traffic-ID to this queue */ 767 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 768 769 /* enable aggregations for the queue */ 770 iwl_scd_txq_enable_agg(trans, txq_id); 771 txq->ampdu = true; 772 } else { 773 /* 774 * disable aggregations for the queue, this will also 775 * make the ra_tid mapping configuration irrelevant 776 * since it is now a non-AGG queue. 777 */ 778 iwl_scd_txq_disable_agg(trans, txq_id); 779 780 ssn = txq->read_ptr; 781 } 782 } else { 783 /* 784 * If we need to move the SCD write pointer by steps of 785 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 786 * the op_mode know by returning true later. 787 * Do this only in case cfg is NULL since this trick can 788 * be done only if we have DQA enabled which is true for mvm 789 * only. And mvm never sets a cfg pointer. 790 * This is really ugly, but this is the easiest way out for 791 * this sad hardware issue. 792 * This bug has been fixed on devices 9000 and up. 793 */ 794 scd_bug = !trans->trans_cfg->mq_rx_supported && 795 !((ssn - txq->write_ptr) & 0x3f) && 796 (ssn != txq->write_ptr); 797 if (scd_bug) 798 ssn++; 799 } 800 801 /* Place first TFD at index corresponding to start sequence number. 802 * Assumes that ssn_idx is valid (!= 0xFFF) */ 803 txq->read_ptr = (ssn & 0xff); 804 txq->write_ptr = (ssn & 0xff); 805 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 806 (ssn & 0xff) | (txq_id << 8)); 807 808 if (cfg) { 809 u8 frame_limit = cfg->frame_limit; 810 811 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 812 813 /* Set up Tx window size and frame limit for this queue */ 814 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 815 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 816 iwl_trans_write_mem32(trans, 817 trans_pcie->scd_base_addr + 818 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 819 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 820 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 821 822 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 823 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 824 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 825 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 826 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 827 SCD_QUEUE_STTS_REG_MSK); 828 829 /* enable the scheduler for this queue (only) */ 830 if (txq_id == trans->txqs.cmd.q_id && 831 trans_pcie->scd_set_active) 832 iwl_scd_enable_set_active(trans, BIT(txq_id)); 833 834 IWL_DEBUG_TX_QUEUES(trans, 835 "Activate queue %d on FIFO %d WrPtr: %d\n", 836 txq_id, fifo, ssn & 0xff); 837 } else { 838 IWL_DEBUG_TX_QUEUES(trans, 839 "Activate queue %d WrPtr: %d\n", 840 txq_id, ssn & 0xff); 841 } 842 843 return scd_bug; 844 } 845 846 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 847 bool shared_mode) 848 { 849 struct iwl_txq *txq = trans->txqs.txq[txq_id]; 850 851 txq->ampdu = !shared_mode; 852 } 853 854 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 855 bool configure_scd) 856 { 857 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 858 u32 stts_addr = trans_pcie->scd_base_addr + 859 SCD_TX_STTS_QUEUE_OFFSET(txq_id); 860 static const u32 zero_val[4] = {}; 861 862 trans->txqs.txq[txq_id]->frozen_expiry_remainder = 0; 863 trans->txqs.txq[txq_id]->frozen = false; 864 865 /* 866 * Upon HW Rfkill - we stop the device, and then stop the queues 867 * in the op_mode. Just for the sake of the simplicity of the op_mode, 868 * allow the op_mode to call txq_disable after it already called 869 * stop_device. 870 */ 871 if (!test_and_clear_bit(txq_id, trans->txqs.queue_used)) { 872 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 873 "queue %d not used", txq_id); 874 return; 875 } 876 877 if (configure_scd) { 878 iwl_scd_txq_set_inactive(trans, txq_id); 879 880 iwl_trans_write_mem(trans, stts_addr, (const void *)zero_val, 881 ARRAY_SIZE(zero_val)); 882 } 883 884 iwl_pcie_txq_unmap(trans, txq_id); 885 trans->txqs.txq[txq_id]->ampdu = false; 886 887 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 888 } 889 890 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 891 892 /* 893 * iwl_pcie_enqueue_hcmd - enqueue a uCode command 894 * @priv: device private data point 895 * @cmd: a pointer to the ucode command structure 896 * 897 * The function returns < 0 values to indicate the operation 898 * failed. On success, it returns the index (>= 0) of command in the 899 * command queue. 900 */ 901 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 902 struct iwl_host_cmd *cmd) 903 { 904 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 905 struct iwl_device_cmd *out_cmd; 906 struct iwl_cmd_meta *out_meta; 907 void *dup_buf = NULL; 908 dma_addr_t phys_addr; 909 int idx; 910 u16 copy_size, cmd_size, tb0_size; 911 bool had_nocopy = false; 912 u8 group_id = iwl_cmd_groupid(cmd->id); 913 int i, ret; 914 u32 cmd_pos; 915 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 916 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 917 unsigned long flags; 918 919 if (WARN(!trans->wide_cmd_header && 920 group_id > IWL_ALWAYS_LONG_GROUP, 921 "unsupported wide command %#x\n", cmd->id)) 922 return -EINVAL; 923 924 if (group_id != 0) { 925 copy_size = sizeof(struct iwl_cmd_header_wide); 926 cmd_size = sizeof(struct iwl_cmd_header_wide); 927 } else { 928 copy_size = sizeof(struct iwl_cmd_header); 929 cmd_size = sizeof(struct iwl_cmd_header); 930 } 931 932 /* need one for the header if the first is NOCOPY */ 933 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 934 935 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 936 cmddata[i] = cmd->data[i]; 937 cmdlen[i] = cmd->len[i]; 938 939 if (!cmd->len[i]) 940 continue; 941 942 /* need at least IWL_FIRST_TB_SIZE copied */ 943 if (copy_size < IWL_FIRST_TB_SIZE) { 944 int copy = IWL_FIRST_TB_SIZE - copy_size; 945 946 if (copy > cmdlen[i]) 947 copy = cmdlen[i]; 948 cmdlen[i] -= copy; 949 cmddata[i] += copy; 950 copy_size += copy; 951 } 952 953 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 954 had_nocopy = true; 955 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 956 idx = -EINVAL; 957 goto free_dup_buf; 958 } 959 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 960 /* 961 * This is also a chunk that isn't copied 962 * to the static buffer so set had_nocopy. 963 */ 964 had_nocopy = true; 965 966 /* only allowed once */ 967 if (WARN_ON(dup_buf)) { 968 idx = -EINVAL; 969 goto free_dup_buf; 970 } 971 972 dup_buf = kmemdup(cmddata[i], cmdlen[i], 973 GFP_ATOMIC); 974 if (!dup_buf) 975 return -ENOMEM; 976 } else { 977 /* NOCOPY must not be followed by normal! */ 978 if (WARN_ON(had_nocopy)) { 979 idx = -EINVAL; 980 goto free_dup_buf; 981 } 982 copy_size += cmdlen[i]; 983 } 984 cmd_size += cmd->len[i]; 985 } 986 987 /* 988 * If any of the command structures end up being larger than 989 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 990 * allocated into separate TFDs, then we will need to 991 * increase the size of the buffers. 992 */ 993 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 994 "Command %s (%#x) is too large (%d bytes)\n", 995 iwl_get_cmd_string(trans, cmd->id), 996 cmd->id, copy_size)) { 997 idx = -EINVAL; 998 goto free_dup_buf; 999 } 1000 1001 spin_lock_irqsave(&txq->lock, flags); 1002 1003 if (iwl_txq_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1004 spin_unlock_irqrestore(&txq->lock, flags); 1005 1006 IWL_ERR(trans, "No space in command queue\n"); 1007 iwl_op_mode_cmd_queue_full(trans->op_mode); 1008 idx = -ENOSPC; 1009 goto free_dup_buf; 1010 } 1011 1012 idx = iwl_txq_get_cmd_index(txq, txq->write_ptr); 1013 out_cmd = txq->entries[idx].cmd; 1014 out_meta = &txq->entries[idx].meta; 1015 1016 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1017 if (cmd->flags & CMD_WANT_SKB) 1018 out_meta->source = cmd; 1019 1020 /* set up the header */ 1021 if (group_id != 0) { 1022 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1023 out_cmd->hdr_wide.group_id = group_id; 1024 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1025 out_cmd->hdr_wide.length = 1026 cpu_to_le16(cmd_size - 1027 sizeof(struct iwl_cmd_header_wide)); 1028 out_cmd->hdr_wide.reserved = 0; 1029 out_cmd->hdr_wide.sequence = 1030 cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) | 1031 INDEX_TO_SEQ(txq->write_ptr)); 1032 1033 cmd_pos = sizeof(struct iwl_cmd_header_wide); 1034 copy_size = sizeof(struct iwl_cmd_header_wide); 1035 } else { 1036 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1037 out_cmd->hdr.sequence = 1038 cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) | 1039 INDEX_TO_SEQ(txq->write_ptr)); 1040 out_cmd->hdr.group_id = 0; 1041 1042 cmd_pos = sizeof(struct iwl_cmd_header); 1043 copy_size = sizeof(struct iwl_cmd_header); 1044 } 1045 1046 /* and copy the data that needs to be copied */ 1047 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1048 int copy; 1049 1050 if (!cmd->len[i]) 1051 continue; 1052 1053 /* copy everything if not nocopy/dup */ 1054 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1055 IWL_HCMD_DFL_DUP))) { 1056 copy = cmd->len[i]; 1057 1058 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1059 cmd_pos += copy; 1060 copy_size += copy; 1061 continue; 1062 } 1063 1064 /* 1065 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 1066 * in total (for bi-directional DMA), but copy up to what 1067 * we can fit into the payload for debug dump purposes. 1068 */ 1069 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1070 1071 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1072 cmd_pos += copy; 1073 1074 /* However, treat copy_size the proper way, we need it below */ 1075 if (copy_size < IWL_FIRST_TB_SIZE) { 1076 copy = IWL_FIRST_TB_SIZE - copy_size; 1077 1078 if (copy > cmd->len[i]) 1079 copy = cmd->len[i]; 1080 copy_size += copy; 1081 } 1082 } 1083 1084 IWL_DEBUG_HC(trans, 1085 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 1086 iwl_get_cmd_string(trans, cmd->id), 1087 group_id, out_cmd->hdr.cmd, 1088 le16_to_cpu(out_cmd->hdr.sequence), 1089 cmd_size, txq->write_ptr, idx, trans->txqs.cmd.q_id); 1090 1091 /* start the TFD with the minimum copy bytes */ 1092 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 1093 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1094 iwl_pcie_txq_build_tfd(trans, txq, 1095 iwl_txq_get_first_tb_dma(txq, idx), 1096 tb0_size, true); 1097 1098 /* map first command fragment, if any remains */ 1099 if (copy_size > tb0_size) { 1100 phys_addr = dma_map_single(trans->dev, 1101 ((u8 *)&out_cmd->hdr) + tb0_size, 1102 copy_size - tb0_size, 1103 DMA_TO_DEVICE); 1104 if (dma_mapping_error(trans->dev, phys_addr)) { 1105 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, 1106 txq->write_ptr); 1107 idx = -ENOMEM; 1108 goto out; 1109 } 1110 1111 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1112 copy_size - tb0_size, false); 1113 } 1114 1115 /* map the remaining (adjusted) nocopy/dup fragments */ 1116 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1117 void *data = (void *)(uintptr_t)cmddata[i]; 1118 1119 if (!cmdlen[i]) 1120 continue; 1121 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1122 IWL_HCMD_DFL_DUP))) 1123 continue; 1124 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1125 data = dup_buf; 1126 phys_addr = dma_map_single(trans->dev, data, 1127 cmdlen[i], DMA_TO_DEVICE); 1128 if (dma_mapping_error(trans->dev, phys_addr)) { 1129 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, 1130 txq->write_ptr); 1131 idx = -ENOMEM; 1132 goto out; 1133 } 1134 1135 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1136 } 1137 1138 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1139 out_meta->flags = cmd->flags; 1140 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1141 kfree_sensitive(txq->entries[idx].free_buf); 1142 txq->entries[idx].free_buf = dup_buf; 1143 1144 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1145 1146 /* start timer if queue currently empty */ 1147 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1148 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1149 1150 ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1151 if (ret < 0) { 1152 idx = ret; 1153 goto out; 1154 } 1155 1156 /* Increment and update queue's write index */ 1157 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr); 1158 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1159 1160 out: 1161 spin_unlock_irqrestore(&txq->lock, flags); 1162 free_dup_buf: 1163 if (idx < 0) 1164 kfree(dup_buf); 1165 return idx; 1166 } 1167 1168 /* 1169 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1170 * @rxb: Rx buffer to reclaim 1171 */ 1172 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1173 struct iwl_rx_cmd_buffer *rxb) 1174 { 1175 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1176 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1177 u8 group_id; 1178 u32 cmd_id; 1179 int txq_id = SEQ_TO_QUEUE(sequence); 1180 int index = SEQ_TO_INDEX(sequence); 1181 int cmd_index; 1182 struct iwl_device_cmd *cmd; 1183 struct iwl_cmd_meta *meta; 1184 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1185 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id]; 1186 1187 /* If a Tx command is being handled and it isn't in the actual 1188 * command queue then there a command routing bug has been introduced 1189 * in the queue management code. */ 1190 if (WARN(txq_id != trans->txqs.cmd.q_id, 1191 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1192 txq_id, trans->txqs.cmd.q_id, sequence, txq->read_ptr, 1193 txq->write_ptr)) { 1194 iwl_print_hex_error(trans, pkt, 32); 1195 return; 1196 } 1197 1198 spin_lock_bh(&txq->lock); 1199 1200 cmd_index = iwl_txq_get_cmd_index(txq, index); 1201 cmd = txq->entries[cmd_index].cmd; 1202 meta = &txq->entries[cmd_index].meta; 1203 group_id = cmd->hdr.group_id; 1204 cmd_id = WIDE_ID(group_id, cmd->hdr.cmd); 1205 1206 iwl_txq_gen1_tfd_unmap(trans, meta, txq, index); 1207 1208 /* Input error checking is done when commands are added to queue. */ 1209 if (meta->flags & CMD_WANT_SKB) { 1210 struct page *p = rxb_steal_page(rxb); 1211 1212 meta->source->resp_pkt = pkt; 1213 meta->source->_rx_page_addr = (unsigned long)page_address(p); 1214 meta->source->_rx_page_order = trans_pcie->rx_page_order; 1215 } 1216 1217 if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1218 iwl_op_mode_async_cb(trans->op_mode, cmd); 1219 1220 iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1221 1222 if (!(meta->flags & CMD_ASYNC)) { 1223 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1224 IWL_WARN(trans, 1225 "HCMD_ACTIVE already clear for command %s\n", 1226 iwl_get_cmd_string(trans, cmd_id)); 1227 } 1228 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1229 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 1230 iwl_get_cmd_string(trans, cmd_id)); 1231 wake_up(&trans->wait_command_queue); 1232 } 1233 1234 meta->flags = 0; 1235 1236 spin_unlock_bh(&txq->lock); 1237 } 1238 1239 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 1240 struct iwl_txq *txq, u8 hdr_len, 1241 struct iwl_cmd_meta *out_meta) 1242 { 1243 u16 head_tb_len; 1244 int i; 1245 1246 /* 1247 * Set up TFD's third entry to point directly to remainder 1248 * of skb's head, if any 1249 */ 1250 head_tb_len = skb_headlen(skb) - hdr_len; 1251 1252 if (head_tb_len > 0) { 1253 dma_addr_t tb_phys = dma_map_single(trans->dev, 1254 skb->data + hdr_len, 1255 head_tb_len, DMA_TO_DEVICE); 1256 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 1257 return -EINVAL; 1258 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len, 1259 tb_phys, head_tb_len); 1260 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false); 1261 } 1262 1263 /* set up the remaining entries to point to the data */ 1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1265 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1266 dma_addr_t tb_phys; 1267 int tb_idx; 1268 1269 if (!skb_frag_size(frag)) 1270 continue; 1271 1272 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 1273 skb_frag_size(frag), DMA_TO_DEVICE); 1274 1275 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 1276 return -EINVAL; 1277 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag), 1278 tb_phys, skb_frag_size(frag)); 1279 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 1280 skb_frag_size(frag), false); 1281 if (tb_idx < 0) 1282 return tb_idx; 1283 1284 out_meta->tbs |= BIT(tb_idx); 1285 } 1286 1287 return 0; 1288 } 1289 1290 #ifdef CONFIG_INET 1291 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 1292 struct iwl_txq *txq, u8 hdr_len, 1293 struct iwl_cmd_meta *out_meta, 1294 struct iwl_device_tx_cmd *dev_cmd, 1295 u16 tb1_len) 1296 { 1297 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 1298 struct ieee80211_hdr *hdr = (void *)skb->data; 1299 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 1300 unsigned int mss = skb_shinfo(skb)->gso_size; 1301 u16 length, iv_len, amsdu_pad; 1302 u8 *start_hdr; 1303 struct iwl_tso_hdr_page *hdr_page; 1304 struct tso_t tso; 1305 1306 /* if the packet is protected, then it must be CCMP or GCMP */ 1307 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 1308 iv_len = ieee80211_has_protected(hdr->frame_control) ? 1309 IEEE80211_CCMP_HDR_LEN : 0; 1310 1311 trace_iwlwifi_dev_tx(trans->dev, skb, 1312 iwl_txq_get_tfd(trans, txq, txq->write_ptr), 1313 trans->txqs.tfd.size, 1314 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 1315 1316 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 1317 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 1318 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 1319 amsdu_pad = 0; 1320 1321 /* total amount of header we may need for this A-MSDU */ 1322 hdr_room = DIV_ROUND_UP(total_len, mss) * 1323 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 1324 1325 /* Our device supports 9 segments at most, it will fit in 1 page */ 1326 hdr_page = get_page_hdr(trans, hdr_room, skb); 1327 if (!hdr_page) 1328 return -ENOMEM; 1329 1330 start_hdr = hdr_page->pos; 1331 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 1332 hdr_page->pos += iv_len; 1333 1334 /* 1335 * Pull the ieee80211 header + IV to be able to use TSO core, 1336 * we will restore it for the tx_status flow. 1337 */ 1338 skb_pull(skb, hdr_len + iv_len); 1339 1340 /* 1341 * Remove the length of all the headers that we don't actually 1342 * have in the MPDU by themselves, but that we duplicate into 1343 * all the different MSDUs inside the A-MSDU. 1344 */ 1345 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 1346 1347 tso_start(skb, &tso); 1348 1349 while (total_len) { 1350 /* this is the data left for this subframe */ 1351 unsigned int data_left = 1352 min_t(unsigned int, mss, total_len); 1353 unsigned int hdr_tb_len; 1354 dma_addr_t hdr_tb_phys; 1355 u8 *subf_hdrs_start = hdr_page->pos; 1356 1357 total_len -= data_left; 1358 1359 memset(hdr_page->pos, 0, amsdu_pad); 1360 hdr_page->pos += amsdu_pad; 1361 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 1362 data_left)) & 0x3; 1363 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 1364 hdr_page->pos += ETH_ALEN; 1365 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 1366 hdr_page->pos += ETH_ALEN; 1367 1368 length = snap_ip_tcp_hdrlen + data_left; 1369 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 1370 hdr_page->pos += sizeof(length); 1371 1372 /* 1373 * This will copy the SNAP as well which will be considered 1374 * as MAC header. 1375 */ 1376 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 1377 1378 hdr_page->pos += snap_ip_tcp_hdrlen; 1379 1380 hdr_tb_len = hdr_page->pos - start_hdr; 1381 hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 1382 hdr_tb_len, DMA_TO_DEVICE); 1383 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) 1384 return -EINVAL; 1385 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 1386 hdr_tb_len, false); 1387 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, 1388 hdr_tb_phys, hdr_tb_len); 1389 /* add this subframe's headers' length to the tx_cmd */ 1390 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 1391 1392 /* prepare the start_hdr for the next subframe */ 1393 start_hdr = hdr_page->pos; 1394 1395 /* put the payload */ 1396 while (data_left) { 1397 unsigned int size = min_t(unsigned int, tso.size, 1398 data_left); 1399 dma_addr_t tb_phys; 1400 1401 tb_phys = dma_map_single(trans->dev, tso.data, 1402 size, DMA_TO_DEVICE); 1403 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 1404 return -EINVAL; 1405 1406 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 1407 size, false); 1408 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 1409 tb_phys, size); 1410 1411 data_left -= size; 1412 tso_build_data(skb, &tso, size); 1413 } 1414 } 1415 1416 /* re -add the WiFi header and IV */ 1417 skb_push(skb, hdr_len + iv_len); 1418 1419 return 0; 1420 } 1421 #else /* CONFIG_INET */ 1422 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 1423 struct iwl_txq *txq, u8 hdr_len, 1424 struct iwl_cmd_meta *out_meta, 1425 struct iwl_device_tx_cmd *dev_cmd, 1426 u16 tb1_len) 1427 { 1428 /* No A-MSDU without CONFIG_INET */ 1429 WARN_ON(1); 1430 1431 return -1; 1432 } 1433 #endif /* CONFIG_INET */ 1434 1435 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 1436 struct iwl_device_tx_cmd *dev_cmd, int txq_id) 1437 { 1438 struct ieee80211_hdr *hdr; 1439 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 1440 struct iwl_cmd_meta *out_meta; 1441 struct iwl_txq *txq; 1442 dma_addr_t tb0_phys, tb1_phys, scratch_phys; 1443 void *tb1_addr; 1444 void *tfd; 1445 u16 len, tb1_len; 1446 bool wait_write_ptr; 1447 __le16 fc; 1448 u8 hdr_len; 1449 u16 wifi_seq; 1450 bool amsdu; 1451 1452 txq = trans->txqs.txq[txq_id]; 1453 1454 if (WARN_ONCE(!test_bit(txq_id, trans->txqs.queue_used), 1455 "TX on unused queue %d\n", txq_id)) 1456 return -EINVAL; 1457 1458 if (skb_is_nonlinear(skb) && 1459 skb_shinfo(skb)->nr_frags > IWL_TRANS_MAX_FRAGS(trans) && 1460 __skb_linearize(skb)) 1461 return -ENOMEM; 1462 1463 /* mac80211 always puts the full header into the SKB's head, 1464 * so there's no need to check if it's readable there 1465 */ 1466 hdr = (struct ieee80211_hdr *)skb->data; 1467 fc = hdr->frame_control; 1468 hdr_len = ieee80211_hdrlen(fc); 1469 1470 spin_lock(&txq->lock); 1471 1472 if (iwl_txq_space(trans, txq) < txq->high_mark) { 1473 iwl_txq_stop(trans, txq); 1474 1475 /* don't put the packet on the ring, if there is no room */ 1476 if (unlikely(iwl_txq_space(trans, txq) < 3)) { 1477 struct iwl_device_tx_cmd **dev_cmd_ptr; 1478 1479 dev_cmd_ptr = (void *)((u8 *)skb->cb + 1480 trans->txqs.dev_cmd_offs); 1481 1482 *dev_cmd_ptr = dev_cmd; 1483 __skb_queue_tail(&txq->overflow_q, skb); 1484 1485 spin_unlock(&txq->lock); 1486 return 0; 1487 } 1488 } 1489 1490 /* In AGG mode, the index in the ring must correspond to the WiFi 1491 * sequence number. This is a HW requirements to help the SCD to parse 1492 * the BA. 1493 * Check here that the packets are in the right place on the ring. 1494 */ 1495 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 1496 WARN_ONCE(txq->ampdu && 1497 (wifi_seq & 0xff) != txq->write_ptr, 1498 "Q: %d WiFi Seq %d tfdNum %d", 1499 txq_id, wifi_seq, txq->write_ptr); 1500 1501 /* Set up driver data for this TFD */ 1502 txq->entries[txq->write_ptr].skb = skb; 1503 txq->entries[txq->write_ptr].cmd = dev_cmd; 1504 1505 dev_cmd->hdr.sequence = 1506 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 1507 INDEX_TO_SEQ(txq->write_ptr))); 1508 1509 tb0_phys = iwl_txq_get_first_tb_dma(txq, txq->write_ptr); 1510 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 1511 offsetof(struct iwl_tx_cmd, scratch); 1512 1513 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1514 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 1515 1516 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 1517 out_meta = &txq->entries[txq->write_ptr].meta; 1518 out_meta->flags = 0; 1519 1520 /* 1521 * The second TB (tb1) points to the remainder of the TX command 1522 * and the 802.11 header - dword aligned size 1523 * (This calculation modifies the TX command, so do it before the 1524 * setup of the first TB) 1525 */ 1526 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 1527 hdr_len - IWL_FIRST_TB_SIZE; 1528 /* do not align A-MSDU to dword as the subframe header aligns it */ 1529 amsdu = ieee80211_is_data_qos(fc) && 1530 (*ieee80211_get_qos_ctl(hdr) & 1531 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 1532 if (!amsdu) { 1533 tb1_len = ALIGN(len, 4); 1534 /* Tell NIC about any 2-byte padding after MAC header */ 1535 if (tb1_len != len) 1536 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 1537 } else { 1538 tb1_len = len; 1539 } 1540 1541 /* 1542 * The first TB points to bi-directional DMA data, we'll 1543 * memcpy the data into it later. 1544 */ 1545 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 1546 IWL_FIRST_TB_SIZE, true); 1547 1548 /* there must be data left over for TB1 or this code must be changed */ 1549 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 1550 1551 /* map the data for TB1 */ 1552 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 1553 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 1554 if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 1555 goto out_err; 1556 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 1557 1558 trace_iwlwifi_dev_tx(trans->dev, skb, 1559 iwl_txq_get_tfd(trans, txq, txq->write_ptr), 1560 trans->txqs.tfd.size, 1561 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 1562 hdr_len); 1563 1564 /* 1565 * If gso_size wasn't set, don't give the frame "amsdu treatment" 1566 * (adding subframes, etc.). 1567 * This can happen in some testing flows when the amsdu was already 1568 * pre-built, and we just need to send the resulting skb. 1569 */ 1570 if (amsdu && skb_shinfo(skb)->gso_size) { 1571 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 1572 out_meta, dev_cmd, 1573 tb1_len))) 1574 goto out_err; 1575 } else { 1576 struct sk_buff *frag; 1577 1578 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 1579 out_meta))) 1580 goto out_err; 1581 1582 skb_walk_frags(skb, frag) { 1583 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0, 1584 out_meta))) 1585 goto out_err; 1586 } 1587 } 1588 1589 /* building the A-MSDU might have changed this data, so memcpy it now */ 1590 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE); 1591 1592 tfd = iwl_txq_get_tfd(trans, txq, txq->write_ptr); 1593 /* Set up entry for this TFD in Tx byte-count array */ 1594 iwl_txq_gen1_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 1595 iwl_txq_gen1_tfd_get_num_tbs(trans, 1596 tfd)); 1597 1598 wait_write_ptr = ieee80211_has_morefrags(fc); 1599 1600 /* start timer if queue currently empty */ 1601 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) { 1602 /* 1603 * If the TXQ is active, then set the timer, if not, 1604 * set the timer in remainder so that the timer will 1605 * be armed with the right value when the station will 1606 * wake up. 1607 */ 1608 if (!txq->frozen) 1609 mod_timer(&txq->stuck_timer, 1610 jiffies + txq->wd_timeout); 1611 else 1612 txq->frozen_expiry_remainder = txq->wd_timeout; 1613 } 1614 1615 /* Tell device the write index *just past* this latest filled TFD */ 1616 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr); 1617 if (!wait_write_ptr) 1618 iwl_pcie_txq_inc_wr_ptr(trans, txq); 1619 1620 /* 1621 * At this point the frame is "transmitted" successfully 1622 * and we will get a TX status notification eventually. 1623 */ 1624 spin_unlock(&txq->lock); 1625 return 0; 1626 out_err: 1627 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 1628 spin_unlock(&txq->lock); 1629 return -1; 1630 } 1631