1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 44cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/etherdevice.h> 326eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 33e705c121SKalle Valo #include <linux/slab.h> 34e705c121SKalle Valo #include <linux/sched.h> 3571b1230cSLuca Coelho #include <linux/pm_runtime.h> 366eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 376eb5e529SEmmanuel Grumbach #include <net/tso.h> 38e705c121SKalle Valo 39e705c121SKalle Valo #include "iwl-debug.h" 40e705c121SKalle Valo #include "iwl-csr.h" 41e705c121SKalle Valo #include "iwl-prph.h" 42e705c121SKalle Valo #include "iwl-io.h" 43e705c121SKalle Valo #include "iwl-scd.h" 44e705c121SKalle Valo #include "iwl-op-mode.h" 45e705c121SKalle Valo #include "internal.h" 46d172a5efSJohannes Berg #include "fw/api/tx.h" 47e705c121SKalle Valo 48e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 49e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 50e705c121SKalle Valo 51e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 52e705c121SKalle Valo * DMA services 53e705c121SKalle Valo * 54e705c121SKalle Valo * Theory of operation 55e705c121SKalle Valo * 56e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 57e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 58e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 59e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 60e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 61e705c121SKalle Valo * queue states. 62e705c121SKalle Valo * 63e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 64e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 65e705c121SKalle Valo * 66e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 67e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 68e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 69e705c121SKalle Valo * Tx queue resumed. 70e705c121SKalle Valo * 71e705c121SKalle Valo ***************************************************/ 72e22744afSSara Sharon 73ab6c6445SSara Sharon int iwl_queue_space(const struct iwl_txq *q) 74e705c121SKalle Valo { 75e705c121SKalle Valo unsigned int max; 76e705c121SKalle Valo unsigned int used; 77e705c121SKalle Valo 78e705c121SKalle Valo /* 79e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 80e705c121SKalle Valo * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 81e705c121SKalle Valo * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 82e705c121SKalle Valo * to reserve any queue entries for this purpose. 83e705c121SKalle Valo */ 84e705c121SKalle Valo if (q->n_window < TFD_QUEUE_SIZE_MAX) 85e705c121SKalle Valo max = q->n_window; 86e705c121SKalle Valo else 87e705c121SKalle Valo max = TFD_QUEUE_SIZE_MAX - 1; 88e705c121SKalle Valo 89e705c121SKalle Valo /* 90e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 91e705c121SKalle Valo * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 92e705c121SKalle Valo */ 93e705c121SKalle Valo used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 94e705c121SKalle Valo 95e705c121SKalle Valo if (WARN_ON(used > max)) 96e705c121SKalle Valo return 0; 97e705c121SKalle Valo 98e705c121SKalle Valo return max - used; 99e705c121SKalle Valo } 100e705c121SKalle Valo 101e705c121SKalle Valo /* 102e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 103e705c121SKalle Valo */ 104b8e8d7ceSSara Sharon static int iwl_queue_init(struct iwl_txq *q, int slots_num) 105e705c121SKalle Valo { 106e705c121SKalle Valo q->n_window = slots_num; 107e705c121SKalle Valo 108e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 1094ecab561SEmmanuel Grumbach * iwl_pcie_get_cmd_index is broken. */ 110e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 111e705c121SKalle Valo return -EINVAL; 112e705c121SKalle Valo 113e705c121SKalle Valo q->low_mark = q->n_window / 4; 114e705c121SKalle Valo if (q->low_mark < 4) 115e705c121SKalle Valo q->low_mark = 4; 116e705c121SKalle Valo 117e705c121SKalle Valo q->high_mark = q->n_window / 8; 118e705c121SKalle Valo if (q->high_mark < 2) 119e705c121SKalle Valo q->high_mark = 2; 120e705c121SKalle Valo 121e705c121SKalle Valo q->write_ptr = 0; 122e705c121SKalle Valo q->read_ptr = 0; 123e705c121SKalle Valo 124e705c121SKalle Valo return 0; 125e705c121SKalle Valo } 126e705c121SKalle Valo 12713a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 128e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 129e705c121SKalle Valo { 130e705c121SKalle Valo if (WARN_ON(ptr->addr)) 131e705c121SKalle Valo return -EINVAL; 132e705c121SKalle Valo 133e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 134e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 135e705c121SKalle Valo if (!ptr->addr) 136e705c121SKalle Valo return -ENOMEM; 137e705c121SKalle Valo ptr->size = size; 138e705c121SKalle Valo return 0; 139e705c121SKalle Valo } 140e705c121SKalle Valo 14113a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 142e705c121SKalle Valo { 143e705c121SKalle Valo if (unlikely(!ptr->addr)) 144e705c121SKalle Valo return; 145e705c121SKalle Valo 146e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 147e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 148e705c121SKalle Valo } 149e705c121SKalle Valo 150e705c121SKalle Valo static void iwl_pcie_txq_stuck_timer(unsigned long data) 151e705c121SKalle Valo { 152e705c121SKalle Valo struct iwl_txq *txq = (void *)data; 153e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 154e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 155e705c121SKalle Valo 156e705c121SKalle Valo spin_lock(&txq->lock); 157e705c121SKalle Valo /* check if triggered erroneously */ 158bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 159e705c121SKalle Valo spin_unlock(&txq->lock); 160e705c121SKalle Valo return; 161e705c121SKalle Valo } 162e705c121SKalle Valo spin_unlock(&txq->lock); 163e705c121SKalle Valo 16438398efbSSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 165e705c121SKalle Valo 166e705c121SKalle Valo iwl_force_nmi(trans); 167e705c121SKalle Valo } 168e705c121SKalle Valo 169e705c121SKalle Valo /* 170e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 171e705c121SKalle Valo */ 172e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 1734fe10bc6SSara Sharon struct iwl_txq *txq, u16 byte_cnt, 1744fe10bc6SSara Sharon int num_tbs) 175e705c121SKalle Valo { 176e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 177e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 178bb98ecd4SSara Sharon int write_ptr = txq->write_ptr; 179bb98ecd4SSara Sharon int txq_id = txq->id; 180e705c121SKalle Valo u8 sec_ctl = 0; 181e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 182e705c121SKalle Valo __le16 bc_ent; 183e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 184bb98ecd4SSara Sharon (void *)txq->entries[txq->write_ptr].cmd->payload; 185ab6c6445SSara Sharon u8 sta_id = tx_cmd->sta_id; 186e705c121SKalle Valo 187e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 188e705c121SKalle Valo 189e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 190e705c121SKalle Valo 191e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 192e705c121SKalle Valo case TX_CMD_SEC_CCM: 193e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 194e705c121SKalle Valo break; 195e705c121SKalle Valo case TX_CMD_SEC_TKIP: 196e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 197e705c121SKalle Valo break; 198e705c121SKalle Valo case TX_CMD_SEC_WEP: 199e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 200e705c121SKalle Valo break; 201e705c121SKalle Valo } 202e705c121SKalle Valo if (trans_pcie->bc_table_dword) 203e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 204e705c121SKalle Valo 205e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 206e705c121SKalle Valo return; 207e705c121SKalle Valo 208e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 209e705c121SKalle Valo 210e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 211e705c121SKalle Valo 212e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 213e705c121SKalle Valo scd_bc_tbl[txq_id]. 214e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 215e705c121SKalle Valo } 216e705c121SKalle Valo 217e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 218e705c121SKalle Valo struct iwl_txq *txq) 219e705c121SKalle Valo { 220e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 221e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 222e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 223bb98ecd4SSara Sharon int txq_id = txq->id; 224bb98ecd4SSara Sharon int read_ptr = txq->read_ptr; 225e705c121SKalle Valo u8 sta_id = 0; 226e705c121SKalle Valo __le16 bc_ent; 227e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 228bb98ecd4SSara Sharon (void *)txq->entries[read_ptr].cmd->payload; 229e705c121SKalle Valo 230e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 231e705c121SKalle Valo 232e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 233e705c121SKalle Valo sta_id = tx_cmd->sta_id; 234e705c121SKalle Valo 235e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 2364fe10bc6SSara Sharon 237e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 238e705c121SKalle Valo 239e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 240e705c121SKalle Valo scd_bc_tbl[txq_id]. 241e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 242e705c121SKalle Valo } 243e705c121SKalle Valo 244e705c121SKalle Valo /* 245e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 246e705c121SKalle Valo */ 247e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 248e705c121SKalle Valo struct iwl_txq *txq) 249e705c121SKalle Valo { 250e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251e705c121SKalle Valo u32 reg = 0; 252bb98ecd4SSara Sharon int txq_id = txq->id; 253e705c121SKalle Valo 254e705c121SKalle Valo lockdep_assert_held(&txq->lock); 255e705c121SKalle Valo 256e705c121SKalle Valo /* 257e705c121SKalle Valo * explicitly wake up the NIC if: 258e705c121SKalle Valo * 1. shadow registers aren't enabled 259e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 260e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 261e705c121SKalle Valo */ 262e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 263e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 264e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 265e705c121SKalle Valo /* 266e705c121SKalle Valo * wake up nic if it's powered down ... 267e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 268e705c121SKalle Valo * time we'll skip this part. 269e705c121SKalle Valo */ 270e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 271e705c121SKalle Valo 272e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 273e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 274e705c121SKalle Valo txq_id, reg); 275e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 276e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 277e705c121SKalle Valo txq->need_update = true; 278e705c121SKalle Valo return; 279e705c121SKalle Valo } 280e705c121SKalle Valo } 281e705c121SKalle Valo 282e705c121SKalle Valo /* 283e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 284e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 285e705c121SKalle Valo */ 286bb98ecd4SSara Sharon IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 2870cd58eaaSEmmanuel Grumbach if (!txq->block) 2880cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 289bb98ecd4SSara Sharon txq->write_ptr | (txq_id << 8)); 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 293e705c121SKalle Valo { 294e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 295e705c121SKalle Valo int i; 296e705c121SKalle Valo 297e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 298b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 299e705c121SKalle Valo 300f6eac740SMordechai Goodstein if (!test_bit(i, trans_pcie->queue_used)) 301f6eac740SMordechai Goodstein continue; 302f6eac740SMordechai Goodstein 303e705c121SKalle Valo spin_lock_bh(&txq->lock); 304b2a3b1c1SSara Sharon if (txq->need_update) { 305e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 306b2a3b1c1SSara Sharon txq->need_update = false; 307e705c121SKalle Valo } 308e705c121SKalle Valo spin_unlock_bh(&txq->lock); 309e705c121SKalle Valo } 310e705c121SKalle Valo } 311e705c121SKalle Valo 3126983ba69SSara Sharon static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 313cc2f41f8SJohannes Berg void *_tfd, u8 idx) 3146983ba69SSara Sharon { 3156983ba69SSara Sharon 3166983ba69SSara Sharon if (trans->cfg->use_tfh) { 317cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 318cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 3196983ba69SSara Sharon 3206983ba69SSara Sharon return (dma_addr_t)(le64_to_cpu(tb->addr)); 321cc2f41f8SJohannes Berg } else { 322cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 323cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 324cc2f41f8SJohannes Berg dma_addr_t addr = get_unaligned_le32(&tb->lo); 325cc2f41f8SJohannes Berg dma_addr_t hi_len; 3266983ba69SSara Sharon 327cc2f41f8SJohannes Berg if (sizeof(dma_addr_t) <= sizeof(u32)) 328e705c121SKalle Valo return addr; 329cc2f41f8SJohannes Berg 330cc2f41f8SJohannes Berg hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 331cc2f41f8SJohannes Berg 332cc2f41f8SJohannes Berg /* 333cc2f41f8SJohannes Berg * shift by 16 twice to avoid warnings on 32-bit 334cc2f41f8SJohannes Berg * (where this code never runs anyway due to the 335cc2f41f8SJohannes Berg * if statement above) 336cc2f41f8SJohannes Berg */ 337cc2f41f8SJohannes Berg return addr | ((hi_len << 16) << 16); 338cc2f41f8SJohannes Berg } 339e705c121SKalle Valo } 340e705c121SKalle Valo 3416983ba69SSara Sharon static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 3426983ba69SSara Sharon u8 idx, dma_addr_t addr, u16 len) 343e705c121SKalle Valo { 3446983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 3456983ba69SSara Sharon struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 3466983ba69SSara Sharon 347e705c121SKalle Valo u16 hi_n_len = len << 4; 348e705c121SKalle Valo 349e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 3507abf6fdeSJohannes Berg hi_n_len |= iwl_get_dma_hi_addr(addr); 351e705c121SKalle Valo 352e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 353e705c121SKalle Valo 3546983ba69SSara Sharon tfd_fh->num_tbs = idx + 1; 3556983ba69SSara Sharon } 356e705c121SKalle Valo 357cc2f41f8SJohannes Berg static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 358e705c121SKalle Valo { 3596983ba69SSara Sharon if (trans->cfg->use_tfh) { 360cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 3616983ba69SSara Sharon 362cc2f41f8SJohannes Berg return le16_to_cpu(tfd->num_tbs) & 0x1f; 363cc2f41f8SJohannes Berg } else { 364cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 365cc2f41f8SJohannes Berg 366cc2f41f8SJohannes Berg return tfd->num_tbs & 0x1f; 3676983ba69SSara Sharon } 368e705c121SKalle Valo } 369e705c121SKalle Valo 370e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 371e705c121SKalle Valo struct iwl_cmd_meta *meta, 3726983ba69SSara Sharon struct iwl_txq *txq, int index) 373e705c121SKalle Valo { 3743cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3753cd1980bSSara Sharon int i, num_tbs; 3766983ba69SSara Sharon void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index); 377e705c121SKalle Valo 378e705c121SKalle Valo /* Sanity check on number of chunks */ 3796983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 380e705c121SKalle Valo 3813cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 382e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 383e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 384e705c121SKalle Valo return; 385e705c121SKalle Valo } 386e705c121SKalle Valo 3878de437c7SSara Sharon /* first TB is never freed - it's the bidirectional DMA data */ 388e705c121SKalle Valo 389e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 3903cd1980bSSara Sharon if (meta->tbs & BIT(i)) 391e705c121SKalle Valo dma_unmap_page(trans->dev, 3926983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 3936983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, i), 394e705c121SKalle Valo DMA_TO_DEVICE); 395e705c121SKalle Valo else 396e705c121SKalle Valo dma_unmap_single(trans->dev, 3976983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, 3986983ba69SSara Sharon i), 3996983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, 4006983ba69SSara Sharon i), 401e705c121SKalle Valo DMA_TO_DEVICE); 402e705c121SKalle Valo } 4036983ba69SSara Sharon 4046983ba69SSara Sharon if (trans->cfg->use_tfh) { 4056983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4066983ba69SSara Sharon 4076983ba69SSara Sharon tfd_fh->num_tbs = 0; 4086983ba69SSara Sharon } else { 4096983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 4106983ba69SSara Sharon 4116983ba69SSara Sharon tfd_fh->num_tbs = 0; 4126983ba69SSara Sharon } 4136983ba69SSara Sharon 414e705c121SKalle Valo } 415e705c121SKalle Valo 416e705c121SKalle Valo /* 417e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 418e705c121SKalle Valo * @trans - transport private data 419e705c121SKalle Valo * @txq - tx queue 420e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 421e705c121SKalle Valo * 422e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 423e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 424e705c121SKalle Valo */ 4256b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 426e705c121SKalle Valo { 427e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 428e705c121SKalle Valo * idx is bounded by n_window 429e705c121SKalle Valo */ 430bb98ecd4SSara Sharon int rd_ptr = txq->read_ptr; 4314ecab561SEmmanuel Grumbach int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 432e705c121SKalle Valo 433e705c121SKalle Valo lockdep_assert_held(&txq->lock); 434e705c121SKalle Valo 435e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 436e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 437e705c121SKalle Valo */ 4386983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 439e705c121SKalle Valo 440e705c121SKalle Valo /* free SKB */ 441e705c121SKalle Valo if (txq->entries) { 442e705c121SKalle Valo struct sk_buff *skb; 443e705c121SKalle Valo 444e705c121SKalle Valo skb = txq->entries[idx].skb; 445e705c121SKalle Valo 446e705c121SKalle Valo /* Can be called from irqs-disabled context 447e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 448e705c121SKalle Valo * freed and that the queue is not empty - free the skb 449e705c121SKalle Valo */ 450e705c121SKalle Valo if (skb) { 451e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 452e705c121SKalle Valo txq->entries[idx].skb = NULL; 453e705c121SKalle Valo } 454e705c121SKalle Valo } 455e705c121SKalle Valo } 456e705c121SKalle Valo 457e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 458e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 459e705c121SKalle Valo { 4603cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4616983ba69SSara Sharon void *tfd; 462e705c121SKalle Valo u32 num_tbs; 463e705c121SKalle Valo 464bb98ecd4SSara Sharon tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 465e705c121SKalle Valo 466e705c121SKalle Valo if (reset) 4676983ba69SSara Sharon memset(tfd, 0, trans_pcie->tfd_size); 468e705c121SKalle Valo 4696983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 470e705c121SKalle Valo 4716983ba69SSara Sharon /* Each TFD can point to a maximum max_tbs Tx buffers */ 4723cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 473e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 4743cd1980bSSara Sharon trans_pcie->max_tbs); 475e705c121SKalle Valo return -EINVAL; 476e705c121SKalle Valo } 477e705c121SKalle Valo 478e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 479e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 480e705c121SKalle Valo return -EINVAL; 481e705c121SKalle Valo 4826983ba69SSara Sharon iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 483e705c121SKalle Valo 484e705c121SKalle Valo return num_tbs; 485e705c121SKalle Valo } 486e705c121SKalle Valo 48713a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 488b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 489e705c121SKalle Valo { 490e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4916983ba69SSara Sharon size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX; 4928de437c7SSara Sharon size_t tb0_buf_sz; 493e705c121SKalle Valo int i; 494e705c121SKalle Valo 495e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 496e705c121SKalle Valo return -EINVAL; 497e705c121SKalle Valo 498e705c121SKalle Valo setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 499e705c121SKalle Valo (unsigned long)txq); 500e705c121SKalle Valo txq->trans_pcie = trans_pcie; 501e705c121SKalle Valo 502bb98ecd4SSara Sharon txq->n_window = slots_num; 503e705c121SKalle Valo 504e705c121SKalle Valo txq->entries = kcalloc(slots_num, 505e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 506e705c121SKalle Valo GFP_KERNEL); 507e705c121SKalle Valo 508e705c121SKalle Valo if (!txq->entries) 509e705c121SKalle Valo goto error; 510e705c121SKalle Valo 511b8e8d7ceSSara Sharon if (cmd_queue) 512e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 513e705c121SKalle Valo txq->entries[i].cmd = 514e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 515e705c121SKalle Valo GFP_KERNEL); 516e705c121SKalle Valo if (!txq->entries[i].cmd) 517e705c121SKalle Valo goto error; 518e705c121SKalle Valo } 519e705c121SKalle Valo 520e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 521e705c121SKalle Valo * shared with device */ 522e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 523bb98ecd4SSara Sharon &txq->dma_addr, GFP_KERNEL); 524e705c121SKalle Valo if (!txq->tfds) 525e705c121SKalle Valo goto error; 526e705c121SKalle Valo 5278de437c7SSara Sharon BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 528e705c121SKalle Valo 5298de437c7SSara Sharon tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 530e705c121SKalle Valo 5318de437c7SSara Sharon txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 5328de437c7SSara Sharon &txq->first_tb_dma, 533e705c121SKalle Valo GFP_KERNEL); 5348de437c7SSara Sharon if (!txq->first_tb_bufs) 535e705c121SKalle Valo goto err_free_tfds; 536e705c121SKalle Valo 537e705c121SKalle Valo return 0; 538e705c121SKalle Valo err_free_tfds: 539bb98ecd4SSara Sharon dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 540e705c121SKalle Valo error: 541b8e8d7ceSSara Sharon if (txq->entries && cmd_queue) 542e705c121SKalle Valo for (i = 0; i < slots_num; i++) 543e705c121SKalle Valo kfree(txq->entries[i].cmd); 544e705c121SKalle Valo kfree(txq->entries); 545e705c121SKalle Valo txq->entries = NULL; 546e705c121SKalle Valo 547e705c121SKalle Valo return -ENOMEM; 548e705c121SKalle Valo 549e705c121SKalle Valo } 550e705c121SKalle Valo 55113a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 552b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 553e705c121SKalle Valo { 554e705c121SKalle Valo int ret; 555e705c121SKalle Valo 556e705c121SKalle Valo txq->need_update = false; 557e705c121SKalle Valo 558e705c121SKalle Valo /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 559e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 560e705c121SKalle Valo BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 561e705c121SKalle Valo 562e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 563b8e8d7ceSSara Sharon ret = iwl_queue_init(txq, slots_num); 564e705c121SKalle Valo if (ret) 565e705c121SKalle Valo return ret; 566e705c121SKalle Valo 567e705c121SKalle Valo spin_lock_init(&txq->lock); 568faead41cSJohannes Berg 569b8e8d7ceSSara Sharon if (cmd_queue) { 570faead41cSJohannes Berg static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 571faead41cSJohannes Berg 572faead41cSJohannes Berg lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 573faead41cSJohannes Berg } 574faead41cSJohannes Berg 5753955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 576e705c121SKalle Valo 577e705c121SKalle Valo return 0; 578e705c121SKalle Valo } 579e705c121SKalle Valo 5809bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 58121cb3222SJohannes Berg struct sk_buff *skb) 5826eb5e529SEmmanuel Grumbach { 58321cb3222SJohannes Berg struct page **page_ptr; 5846eb5e529SEmmanuel Grumbach 58521cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 5866eb5e529SEmmanuel Grumbach 58721cb3222SJohannes Berg if (*page_ptr) { 58821cb3222SJohannes Berg __free_page(*page_ptr); 58921cb3222SJohannes Berg *page_ptr = NULL; 5906eb5e529SEmmanuel Grumbach } 5916eb5e529SEmmanuel Grumbach } 5926eb5e529SEmmanuel Grumbach 59301d11cd1SSara Sharon static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 59401d11cd1SSara Sharon { 59501d11cd1SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 59601d11cd1SSara Sharon 59701d11cd1SSara Sharon lockdep_assert_held(&trans_pcie->reg_lock); 59801d11cd1SSara Sharon 59901d11cd1SSara Sharon if (trans_pcie->ref_cmd_in_flight) { 60001d11cd1SSara Sharon trans_pcie->ref_cmd_in_flight = false; 60101d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 602c24c7f58SLuca Coelho iwl_trans_unref(trans); 60301d11cd1SSara Sharon } 60401d11cd1SSara Sharon 60501d11cd1SSara Sharon if (!trans->cfg->base_params->apmg_wake_up_wa) 60601d11cd1SSara Sharon return; 60701d11cd1SSara Sharon if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 60801d11cd1SSara Sharon return; 60901d11cd1SSara Sharon 61001d11cd1SSara Sharon trans_pcie->cmd_hold_nic_awake = false; 61101d11cd1SSara Sharon __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 61201d11cd1SSara Sharon CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 61301d11cd1SSara Sharon } 61401d11cd1SSara Sharon 615e705c121SKalle Valo /* 616e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 617e705c121SKalle Valo */ 618e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 619e705c121SKalle Valo { 620e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 621b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 622e705c121SKalle Valo 623e705c121SKalle Valo spin_lock_bh(&txq->lock); 624bb98ecd4SSara Sharon while (txq->write_ptr != txq->read_ptr) { 625e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 626bb98ecd4SSara Sharon txq_id, txq->read_ptr); 6276eb5e529SEmmanuel Grumbach 6286eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 629bb98ecd4SSara Sharon struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 6306eb5e529SEmmanuel Grumbach 6316eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6326eb5e529SEmmanuel Grumbach continue; 6336eb5e529SEmmanuel Grumbach 63421cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 6356eb5e529SEmmanuel Grumbach } 636e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 637bb98ecd4SSara Sharon txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr); 63801d11cd1SSara Sharon 639bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 64001d11cd1SSara Sharon unsigned long flags; 64101d11cd1SSara Sharon 64201d11cd1SSara Sharon spin_lock_irqsave(&trans_pcie->reg_lock, flags); 64301d11cd1SSara Sharon if (txq_id != trans_pcie->cmd_queue) { 64401d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 645bb98ecd4SSara Sharon txq->id); 646c24c7f58SLuca Coelho iwl_trans_unref(trans); 64701d11cd1SSara Sharon } else { 64801d11cd1SSara Sharon iwl_pcie_clear_cmd_in_flight(trans); 64901d11cd1SSara Sharon } 65001d11cd1SSara Sharon spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 65101d11cd1SSara Sharon } 652e705c121SKalle Valo } 6533955525dSEmmanuel Grumbach 6543955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 6553955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 6563955525dSEmmanuel Grumbach 6573955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 6583955525dSEmmanuel Grumbach } 6593955525dSEmmanuel Grumbach 660e705c121SKalle Valo spin_unlock_bh(&txq->lock); 661e705c121SKalle Valo 662e705c121SKalle Valo /* just in case - this queue may have been stopped */ 663e705c121SKalle Valo iwl_wake_queue(trans, txq); 664e705c121SKalle Valo } 665e705c121SKalle Valo 666e705c121SKalle Valo /* 667e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 668e705c121SKalle Valo * @txq: Transmit queue to deallocate. 669e705c121SKalle Valo * 670e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 671e705c121SKalle Valo * Free all buffers. 672e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 673e705c121SKalle Valo */ 674e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 675e705c121SKalle Valo { 676e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 677b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 678e705c121SKalle Valo struct device *dev = trans->dev; 679e705c121SKalle Valo int i; 680e705c121SKalle Valo 681e705c121SKalle Valo if (WARN_ON(!txq)) 682e705c121SKalle Valo return; 683e705c121SKalle Valo 684e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 685e705c121SKalle Valo 686e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 687e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 688bb98ecd4SSara Sharon for (i = 0; i < txq->n_window; i++) { 689e705c121SKalle Valo kzfree(txq->entries[i].cmd); 690e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 691e705c121SKalle Valo } 692e705c121SKalle Valo 693e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 694e705c121SKalle Valo if (txq->tfds) { 695e705c121SKalle Valo dma_free_coherent(dev, 6966983ba69SSara Sharon trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX, 697bb98ecd4SSara Sharon txq->tfds, txq->dma_addr); 698bb98ecd4SSara Sharon txq->dma_addr = 0; 699e705c121SKalle Valo txq->tfds = NULL; 700e705c121SKalle Valo 701e705c121SKalle Valo dma_free_coherent(dev, 702bb98ecd4SSara Sharon sizeof(*txq->first_tb_bufs) * txq->n_window, 7038de437c7SSara Sharon txq->first_tb_bufs, txq->first_tb_dma); 704e705c121SKalle Valo } 705e705c121SKalle Valo 706e705c121SKalle Valo kfree(txq->entries); 707e705c121SKalle Valo txq->entries = NULL; 708e705c121SKalle Valo 709e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 710e705c121SKalle Valo 711e705c121SKalle Valo /* 0-fill queue descriptor structure */ 712e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 713e705c121SKalle Valo } 714e705c121SKalle Valo 715e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 716e705c121SKalle Valo { 717e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 718e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 719e705c121SKalle Valo int chan; 720e705c121SKalle Valo u32 reg_val; 721e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 722e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 723e705c121SKalle Valo 724e705c121SKalle Valo /* make sure all queue are not stopped/used */ 725e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 726e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 727e705c121SKalle Valo 728e705c121SKalle Valo trans_pcie->scd_base_addr = 729e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 730e705c121SKalle Valo 731e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 732e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 733e705c121SKalle Valo 734e705c121SKalle Valo /* reset context data, TX status and translation data */ 735e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 736e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 737e705c121SKalle Valo NULL, clear_dwords); 738e705c121SKalle Valo 739e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 740e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 741e705c121SKalle Valo 742e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 743e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 744e705c121SKalle Valo */ 745e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 746e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 747e705c121SKalle Valo 748e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 749e705c121SKalle Valo trans_pcie->cmd_fifo, 750e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 751e705c121SKalle Valo 752e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 753e705c121SKalle Valo iwl_scd_activate_fifos(trans); 754e705c121SKalle Valo 755e705c121SKalle Valo /* Enable DMA channel */ 756e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 757e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 758e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 759e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 760e705c121SKalle Valo 761e705c121SKalle Valo /* Update FH chicken bits */ 762e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 763e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 764e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 765e705c121SKalle Valo 766e705c121SKalle Valo /* Enable L1-Active */ 7676e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 768e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 769e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 770e705c121SKalle Valo } 771e705c121SKalle Valo 772e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 773e705c121SKalle Valo { 774e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 775e705c121SKalle Valo int txq_id; 776e705c121SKalle Valo 77713a3a390SSara Sharon /* 77813a3a390SSara Sharon * we should never get here in gen2 trans mode return early to avoid 77913a3a390SSara Sharon * having invalid accesses 78013a3a390SSara Sharon */ 78113a3a390SSara Sharon if (WARN_ON_ONCE(trans->cfg->gen2)) 78213a3a390SSara Sharon return; 78313a3a390SSara Sharon 784e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 785e705c121SKalle Valo txq_id++) { 786b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 787e22744afSSara Sharon if (trans->cfg->use_tfh) 788e22744afSSara Sharon iwl_write_direct64(trans, 789e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 790bb98ecd4SSara Sharon txq->dma_addr); 791e22744afSSara Sharon else 792e22744afSSara Sharon iwl_write_direct32(trans, 793e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 794bb98ecd4SSara Sharon txq->dma_addr >> 8); 795e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 796bb98ecd4SSara Sharon txq->read_ptr = 0; 797bb98ecd4SSara Sharon txq->write_ptr = 0; 798e705c121SKalle Valo } 799e705c121SKalle Valo 800e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 801e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 802e705c121SKalle Valo trans_pcie->kw.dma >> 4); 803e705c121SKalle Valo 804e705c121SKalle Valo /* 805e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 806e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 807e705c121SKalle Valo * contain garbage. 808e705c121SKalle Valo */ 809e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 810e705c121SKalle Valo } 811e705c121SKalle Valo 812e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 813e705c121SKalle Valo { 814e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 815e705c121SKalle Valo unsigned long flags; 816e705c121SKalle Valo int ch, ret; 817e705c121SKalle Valo u32 mask = 0; 818e705c121SKalle Valo 819e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 820e705c121SKalle Valo 82123ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 822e705c121SKalle Valo goto out; 823e705c121SKalle Valo 824e705c121SKalle Valo /* Stop each Tx DMA channel */ 825e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 826e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 827e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 828e705c121SKalle Valo } 829e705c121SKalle Valo 830e705c121SKalle Valo /* Wait for DMA channels to be idle */ 831e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 832e705c121SKalle Valo if (ret < 0) 833e705c121SKalle Valo IWL_ERR(trans, 834e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 835e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 836e705c121SKalle Valo 837e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 838e705c121SKalle Valo 839e705c121SKalle Valo out: 840e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 841e705c121SKalle Valo } 842e705c121SKalle Valo 843e705c121SKalle Valo /* 844e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 845e705c121SKalle Valo */ 846e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 847e705c121SKalle Valo { 848e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 849e705c121SKalle Valo int txq_id; 850e705c121SKalle Valo 851e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 852e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 853e705c121SKalle Valo 854e705c121SKalle Valo /* Turn off all Tx DMA channels */ 855e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 856e705c121SKalle Valo 857e705c121SKalle Valo /* 858e705c121SKalle Valo * This function can be called before the op_mode disabled the 859e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 860e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 861e705c121SKalle Valo */ 862e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 863e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 864e705c121SKalle Valo 865e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 866b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 867e705c121SKalle Valo return 0; 868e705c121SKalle Valo 869e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 870e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 871e705c121SKalle Valo txq_id++) 872e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 873e705c121SKalle Valo 874e705c121SKalle Valo return 0; 875e705c121SKalle Valo } 876e705c121SKalle Valo 877e705c121SKalle Valo /* 878e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 879e705c121SKalle Valo * 880e705c121SKalle Valo * Destroy all TX DMA queues and structures 881e705c121SKalle Valo */ 882e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 883e705c121SKalle Valo { 884e705c121SKalle Valo int txq_id; 885e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 886e705c121SKalle Valo 887de74c455SSara Sharon memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 888de74c455SSara Sharon 889e705c121SKalle Valo /* Tx queues */ 890b2a3b1c1SSara Sharon if (trans_pcie->txq_memory) { 891e705c121SKalle Valo for (txq_id = 0; 892b2a3b1c1SSara Sharon txq_id < trans->cfg->base_params->num_of_queues; 893b2a3b1c1SSara Sharon txq_id++) { 894e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 895b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = NULL; 896b2a3b1c1SSara Sharon } 897e705c121SKalle Valo } 898e705c121SKalle Valo 899b2a3b1c1SSara Sharon kfree(trans_pcie->txq_memory); 900b2a3b1c1SSara Sharon trans_pcie->txq_memory = NULL; 901e705c121SKalle Valo 902e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 903e705c121SKalle Valo 904e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 905e705c121SKalle Valo } 906e705c121SKalle Valo 907e705c121SKalle Valo /* 908e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 909e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 910e705c121SKalle Valo */ 911e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 912e705c121SKalle Valo { 913e705c121SKalle Valo int ret; 914e705c121SKalle Valo int txq_id, slots_num; 915e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 916e705c121SKalle Valo 917e705c121SKalle Valo u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 918e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 919e705c121SKalle Valo 920e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 921e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 922b2a3b1c1SSara Sharon if (WARN_ON(trans_pcie->txq_memory)) { 923e705c121SKalle Valo ret = -EINVAL; 924e705c121SKalle Valo goto error; 925e705c121SKalle Valo } 926e705c121SKalle Valo 927e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 928e705c121SKalle Valo scd_bc_tbls_size); 929e705c121SKalle Valo if (ret) { 930e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 931e705c121SKalle Valo goto error; 932e705c121SKalle Valo } 933e705c121SKalle Valo 934e705c121SKalle Valo /* Alloc keep-warm buffer */ 935e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 936e705c121SKalle Valo if (ret) { 937e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 938e705c121SKalle Valo goto error; 939e705c121SKalle Valo } 940e705c121SKalle Valo 941b2a3b1c1SSara Sharon trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 942e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 943b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 944e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 945e705c121SKalle Valo ret = -ENOMEM; 946e705c121SKalle Valo goto error; 947e705c121SKalle Valo } 948e705c121SKalle Valo 949e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 950e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 951e705c121SKalle Valo txq_id++) { 952b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 953b8e8d7ceSSara Sharon 954dd05f9aaSShahar S Matityahu slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size : 955dd05f9aaSShahar S Matityahu TFD_TX_CMD_SLOTS; 956b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 957b2a3b1c1SSara Sharon ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 958b8e8d7ceSSara Sharon slots_num, cmd_queue); 959e705c121SKalle Valo if (ret) { 960e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 961e705c121SKalle Valo goto error; 962e705c121SKalle Valo } 963b8e8d7ceSSara Sharon trans_pcie->txq[txq_id]->id = txq_id; 964e705c121SKalle Valo } 965e705c121SKalle Valo 966e705c121SKalle Valo return 0; 967e705c121SKalle Valo 968e705c121SKalle Valo error: 969e705c121SKalle Valo iwl_pcie_tx_free(trans); 970e705c121SKalle Valo 971e705c121SKalle Valo return ret; 972e705c121SKalle Valo } 973eda50cdeSSara Sharon 974dd05f9aaSShahar S Matityahu void iwl_pcie_set_tx_cmd_queue_size(struct iwl_trans *trans) 975dd05f9aaSShahar S Matityahu { 976dd05f9aaSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 977dd05f9aaSShahar S Matityahu int queue_size = TFD_CMD_SLOTS; 978dd05f9aaSShahar S Matityahu 979dd05f9aaSShahar S Matityahu if (trans->cfg->tx_cmd_queue_size) 980dd05f9aaSShahar S Matityahu queue_size = trans->cfg->tx_cmd_queue_size; 981dd05f9aaSShahar S Matityahu 982dd05f9aaSShahar S Matityahu if (WARN_ON(!(is_power_of_2(queue_size) && 983dd05f9aaSShahar S Matityahu TFD_QUEUE_CB_SIZE(queue_size) > 0))) 984dd05f9aaSShahar S Matityahu trans_pcie->tx_cmd_queue_size = TFD_CMD_SLOTS; 985dd05f9aaSShahar S Matityahu else 986dd05f9aaSShahar S Matityahu trans_pcie->tx_cmd_queue_size = queue_size; 987dd05f9aaSShahar S Matityahu } 988dd05f9aaSShahar S Matityahu 989e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 990e705c121SKalle Valo { 991e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 992e705c121SKalle Valo int ret; 993e705c121SKalle Valo int txq_id, slots_num; 994e705c121SKalle Valo bool alloc = false; 995e705c121SKalle Valo 996dd05f9aaSShahar S Matityahu iwl_pcie_set_tx_cmd_queue_size(trans); 997dd05f9aaSShahar S Matityahu 998b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 999e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 1000e705c121SKalle Valo if (ret) 1001e705c121SKalle Valo goto error; 1002e705c121SKalle Valo alloc = true; 1003e705c121SKalle Valo } 1004e705c121SKalle Valo 1005e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1006e705c121SKalle Valo 1007e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 1008e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 1009e705c121SKalle Valo 1010e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 1011e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1012e705c121SKalle Valo trans_pcie->kw.dma >> 4); 1013e705c121SKalle Valo 1014e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1015e705c121SKalle Valo 1016e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1017e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1018e705c121SKalle Valo txq_id++) { 1019b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1020b8e8d7ceSSara Sharon 1021dd05f9aaSShahar S Matityahu slots_num = cmd_queue ? trans_pcie->tx_cmd_queue_size : 1022dd05f9aaSShahar S Matityahu TFD_TX_CMD_SLOTS; 1023b2a3b1c1SSara Sharon ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1024b8e8d7ceSSara Sharon slots_num, cmd_queue); 1025e705c121SKalle Valo if (ret) { 1026e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1027e705c121SKalle Valo goto error; 1028e705c121SKalle Valo } 1029e705c121SKalle Valo 1030eda50cdeSSara Sharon /* 1031eda50cdeSSara Sharon * Tell nic where to find circular buffer of TFDs for a 1032eda50cdeSSara Sharon * given Tx queue, and enable the DMA channel used for that 1033eda50cdeSSara Sharon * queue. 1034eda50cdeSSara Sharon * Circular buffer (TFD queue in DRAM) physical base address 1035eda50cdeSSara Sharon */ 1036eda50cdeSSara Sharon iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1037b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->dma_addr >> 8); 1038ae79785fSSara Sharon } 1039e22744afSSara Sharon 1040e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1041e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 1042e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 1043e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 1044e705c121SKalle Valo 1045e705c121SKalle Valo return 0; 1046e705c121SKalle Valo error: 1047e705c121SKalle Valo /*Upon error, free only if we allocated something */ 1048e705c121SKalle Valo if (alloc) 1049e705c121SKalle Valo iwl_pcie_tx_free(trans); 1050e705c121SKalle Valo return ret; 1051e705c121SKalle Valo } 1052e705c121SKalle Valo 1053e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1054e705c121SKalle Valo { 1055e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1056e705c121SKalle Valo 1057e705c121SKalle Valo if (!txq->wd_timeout) 1058e705c121SKalle Valo return; 1059e705c121SKalle Valo 1060e705c121SKalle Valo /* 1061e705c121SKalle Valo * station is asleep and we send data - that must 1062e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 1063e705c121SKalle Valo */ 1064e705c121SKalle Valo if (txq->frozen) 1065e705c121SKalle Valo return; 1066e705c121SKalle Valo 1067e705c121SKalle Valo /* 1068e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 1069e705c121SKalle Valo * since we're making progress on this queue 1070e705c121SKalle Valo */ 1071bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 1072e705c121SKalle Valo del_timer(&txq->stuck_timer); 1073e705c121SKalle Valo else 1074e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1075e705c121SKalle Valo } 1076e705c121SKalle Valo 1077e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1078e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1079e705c121SKalle Valo struct sk_buff_head *skbs) 1080e705c121SKalle Valo { 1081e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1082b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1083e705c121SKalle Valo int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 1084e705c121SKalle Valo int last_to_free; 1085e705c121SKalle Valo 1086e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1087e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1088e705c121SKalle Valo return; 1089e705c121SKalle Valo 1090e705c121SKalle Valo spin_lock_bh(&txq->lock); 1091e705c121SKalle Valo 1092de74c455SSara Sharon if (!test_bit(txq_id, trans_pcie->queue_used)) { 1093e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1094e705c121SKalle Valo txq_id, ssn); 1095e705c121SKalle Valo goto out; 1096e705c121SKalle Valo } 1097e705c121SKalle Valo 1098bb98ecd4SSara Sharon if (txq->read_ptr == tfd_num) 1099e705c121SKalle Valo goto out; 1100e705c121SKalle Valo 1101e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1102bb98ecd4SSara Sharon txq_id, txq->read_ptr, tfd_num, ssn); 1103e705c121SKalle Valo 1104e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1105e705c121SKalle Valo * the last we will free. This one must be used */ 1106e705c121SKalle Valo last_to_free = iwl_queue_dec_wrap(tfd_num); 1107e705c121SKalle Valo 1108bb98ecd4SSara Sharon if (!iwl_queue_used(txq, last_to_free)) { 1109e705c121SKalle Valo IWL_ERR(trans, 1110e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1111e705c121SKalle Valo __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 1112bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1113e705c121SKalle Valo goto out; 1114e705c121SKalle Valo } 1115e705c121SKalle Valo 1116e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1117e705c121SKalle Valo goto out; 1118e705c121SKalle Valo 1119e705c121SKalle Valo for (; 1120bb98ecd4SSara Sharon txq->read_ptr != tfd_num; 1121bb98ecd4SSara Sharon txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { 11224ecab561SEmmanuel Grumbach int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 11234ecab561SEmmanuel Grumbach struct sk_buff *skb = txq->entries[idx].skb; 1124e705c121SKalle Valo 11256eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1126e705c121SKalle Valo continue; 1127e705c121SKalle Valo 112821cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 11296eb5e529SEmmanuel Grumbach 11306eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1131e705c121SKalle Valo 11324ecab561SEmmanuel Grumbach txq->entries[idx].skb = NULL; 1133e705c121SKalle Valo 11344fe10bc6SSara Sharon if (!trans->cfg->use_tfh) 1135e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1136e705c121SKalle Valo 1137e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1138e705c121SKalle Valo } 1139e705c121SKalle Valo 1140e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1141e705c121SKalle Valo 1142bb98ecd4SSara Sharon if (iwl_queue_space(txq) > txq->low_mark && 11433955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1144685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 11453955525dSEmmanuel Grumbach 1146685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1147685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 11483955525dSEmmanuel Grumbach 11493955525dSEmmanuel Grumbach /* 11503955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 11513955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 11523955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 11533955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 11543955525dSEmmanuel Grumbach * later. 11553955525dSEmmanuel Grumbach */ 11563955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 11573955525dSEmmanuel Grumbach 1158685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1159685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 116021cb3222SJohannes Berg struct iwl_device_cmd *dev_cmd_ptr; 116121cb3222SJohannes Berg 116221cb3222SJohannes Berg dev_cmd_ptr = *(void **)((u8 *)skb->cb + 116321cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 11643955525dSEmmanuel Grumbach 11653955525dSEmmanuel Grumbach /* 11663955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 11673955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 11683955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 11693955525dSEmmanuel Grumbach */ 117021cb3222SJohannes Berg iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); 11713955525dSEmmanuel Grumbach } 11723955525dSEmmanuel Grumbach spin_lock_bh(&txq->lock); 11733955525dSEmmanuel Grumbach 1174bb98ecd4SSara Sharon if (iwl_queue_space(txq) > txq->low_mark) 1175e705c121SKalle Valo iwl_wake_queue(trans, txq); 11763955525dSEmmanuel Grumbach } 1177e705c121SKalle Valo 1178bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1179bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); 1180c24c7f58SLuca Coelho iwl_trans_unref(trans); 1181e705c121SKalle Valo } 1182e705c121SKalle Valo 1183e705c121SKalle Valo out: 1184e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1185e705c121SKalle Valo } 1186e705c121SKalle Valo 1187e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1188e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1189e705c121SKalle Valo { 1190e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1191e705c121SKalle Valo int ret; 1192e705c121SKalle Valo 1193e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1194e705c121SKalle Valo 1195e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1196e705c121SKalle Valo !trans_pcie->ref_cmd_in_flight) { 1197e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = true; 1198e705c121SKalle Valo IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1199c24c7f58SLuca Coelho iwl_trans_ref(trans); 1200e705c121SKalle Valo } 1201e705c121SKalle Valo 1202e705c121SKalle Valo /* 1203e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1204e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1205e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1206e705c121SKalle Valo * apmg_wake_up_wa set. 1207e705c121SKalle Valo */ 1208e705c121SKalle Valo if (trans->cfg->base_params->apmg_wake_up_wa && 1209e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1210e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1211e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1212e705c121SKalle Valo 1213e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1214e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1215e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1216e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1217e705c121SKalle Valo 15000); 1218e705c121SKalle Valo if (ret < 0) { 1219e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1220e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1221e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1222e705c121SKalle Valo return -EIO; 1223e705c121SKalle Valo } 1224e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1225e705c121SKalle Valo } 1226e705c121SKalle Valo 1227e705c121SKalle Valo return 0; 1228e705c121SKalle Valo } 1229e705c121SKalle Valo 1230e705c121SKalle Valo /* 1231e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1232e705c121SKalle Valo * 1233e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1234e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1235e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1236e705c121SKalle Valo */ 1237e705c121SKalle Valo static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1238e705c121SKalle Valo { 1239e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1240b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1241e705c121SKalle Valo unsigned long flags; 1242e705c121SKalle Valo int nfreed = 0; 1243e705c121SKalle Valo 1244e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1245e705c121SKalle Valo 1246bb98ecd4SSara Sharon if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) { 1247e705c121SKalle Valo IWL_ERR(trans, 1248e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1249e705c121SKalle Valo __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1250bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1251e705c121SKalle Valo return; 1252e705c121SKalle Valo } 1253e705c121SKalle Valo 1254bb98ecd4SSara Sharon for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx; 1255bb98ecd4SSara Sharon txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) { 1256e705c121SKalle Valo 1257e705c121SKalle Valo if (nfreed++ > 0) { 1258e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1259bb98ecd4SSara Sharon idx, txq->write_ptr, txq->read_ptr); 1260e705c121SKalle Valo iwl_force_nmi(trans); 1261e705c121SKalle Valo } 1262e705c121SKalle Valo } 1263e705c121SKalle Valo 1264bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1265e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1266e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1267e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1268e705c121SKalle Valo } 1269e705c121SKalle Valo 1270e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1271e705c121SKalle Valo } 1272e705c121SKalle Valo 1273e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1274e705c121SKalle Valo u16 txq_id) 1275e705c121SKalle Valo { 1276e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1277e705c121SKalle Valo u32 tbl_dw_addr; 1278e705c121SKalle Valo u32 tbl_dw; 1279e705c121SKalle Valo u16 scd_q2ratid; 1280e705c121SKalle Valo 1281e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1282e705c121SKalle Valo 1283e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1284e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1285e705c121SKalle Valo 1286e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1287e705c121SKalle Valo 1288e705c121SKalle Valo if (txq_id & 0x1) 1289e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1290e705c121SKalle Valo else 1291e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1292e705c121SKalle Valo 1293e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1294e705c121SKalle Valo 1295e705c121SKalle Valo return 0; 1296e705c121SKalle Valo } 1297e705c121SKalle Valo 1298e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1299e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1300e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1301e705c121SKalle Valo 1302dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1303e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1304e705c121SKalle Valo unsigned int wdg_timeout) 1305e705c121SKalle Valo { 1306e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1307b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1308e705c121SKalle Valo int fifo = -1; 1309dcfbd67bSEmmanuel Grumbach bool scd_bug = false; 1310e705c121SKalle Valo 1311e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1312e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1313e705c121SKalle Valo 1314e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1315e705c121SKalle Valo 1316e705c121SKalle Valo if (cfg) { 1317e705c121SKalle Valo fifo = cfg->fifo; 1318e705c121SKalle Valo 1319e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1320e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1321e705c121SKalle Valo trans_pcie->scd_set_active) 1322e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1323e705c121SKalle Valo 1324e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1325e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1326e705c121SKalle Valo 1327e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1328e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1329e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1330e705c121SKalle Valo 1331e705c121SKalle Valo if (cfg->aggregate) { 1332e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1333e705c121SKalle Valo 1334e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1335e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1336e705c121SKalle Valo 1337e705c121SKalle Valo /* enable aggregations for the queue */ 1338e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1339e705c121SKalle Valo txq->ampdu = true; 1340e705c121SKalle Valo } else { 1341e705c121SKalle Valo /* 1342e705c121SKalle Valo * disable aggregations for the queue, this will also 1343e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1344e705c121SKalle Valo * since it is now a non-AGG queue. 1345e705c121SKalle Valo */ 1346e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1347e705c121SKalle Valo 1348bb98ecd4SSara Sharon ssn = txq->read_ptr; 1349e705c121SKalle Valo } 1350dcfbd67bSEmmanuel Grumbach } else { 1351dcfbd67bSEmmanuel Grumbach /* 1352dcfbd67bSEmmanuel Grumbach * If we need to move the SCD write pointer by steps of 1353dcfbd67bSEmmanuel Grumbach * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1354dcfbd67bSEmmanuel Grumbach * the op_mode know by returning true later. 1355dcfbd67bSEmmanuel Grumbach * Do this only in case cfg is NULL since this trick can 1356dcfbd67bSEmmanuel Grumbach * be done only if we have DQA enabled which is true for mvm 1357dcfbd67bSEmmanuel Grumbach * only. And mvm never sets a cfg pointer. 1358dcfbd67bSEmmanuel Grumbach * This is really ugly, but this is the easiest way out for 1359dcfbd67bSEmmanuel Grumbach * this sad hardware issue. 1360dcfbd67bSEmmanuel Grumbach * This bug has been fixed on devices 9000 and up. 1361dcfbd67bSEmmanuel Grumbach */ 1362dcfbd67bSEmmanuel Grumbach scd_bug = !trans->cfg->mq_rx_supported && 1363dcfbd67bSEmmanuel Grumbach !((ssn - txq->write_ptr) & 0x3f) && 1364dcfbd67bSEmmanuel Grumbach (ssn != txq->write_ptr); 1365dcfbd67bSEmmanuel Grumbach if (scd_bug) 1366dcfbd67bSEmmanuel Grumbach ssn++; 1367e705c121SKalle Valo } 1368e705c121SKalle Valo 1369e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1370e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1371bb98ecd4SSara Sharon txq->read_ptr = (ssn & 0xff); 1372bb98ecd4SSara Sharon txq->write_ptr = (ssn & 0xff); 1373e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1374e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1375e705c121SKalle Valo 1376e705c121SKalle Valo if (cfg) { 1377e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1378e705c121SKalle Valo 1379e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1380e705c121SKalle Valo 1381e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1382e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1383e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1384e705c121SKalle Valo iwl_trans_write_mem32(trans, 1385e705c121SKalle Valo trans_pcie->scd_base_addr + 1386e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1387f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1388f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1389e705c121SKalle Valo 1390e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1391e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1392e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1393e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1394e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1395e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1396e705c121SKalle Valo 1397e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1398e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1399e705c121SKalle Valo trans_pcie->scd_set_active) 1400e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1401e705c121SKalle Valo 1402e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1403e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1404e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1405e705c121SKalle Valo } else { 1406e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1407e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1408e705c121SKalle Valo txq_id, ssn & 0xff); 1409e705c121SKalle Valo } 1410dcfbd67bSEmmanuel Grumbach 1411dcfbd67bSEmmanuel Grumbach return scd_bug; 1412e705c121SKalle Valo } 1413e705c121SKalle Valo 141442db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 141542db09c1SLiad Kaufman bool shared_mode) 141642db09c1SLiad Kaufman { 141742db09c1SLiad Kaufman struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1418b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 141942db09c1SLiad Kaufman 142042db09c1SLiad Kaufman txq->ampdu = !shared_mode; 142142db09c1SLiad Kaufman } 142242db09c1SLiad Kaufman 1423e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1424e705c121SKalle Valo bool configure_scd) 1425e705c121SKalle Valo { 1426e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1427e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1428e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1429e705c121SKalle Valo static const u32 zero_val[4] = {}; 1430e705c121SKalle Valo 1431b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1432b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen = false; 1433e705c121SKalle Valo 1434e705c121SKalle Valo /* 1435e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1436e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1437e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1438e705c121SKalle Valo * stop_device. 1439e705c121SKalle Valo */ 1440e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1441e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1442e705c121SKalle Valo "queue %d not used", txq_id); 1443e705c121SKalle Valo return; 1444e705c121SKalle Valo } 1445e705c121SKalle Valo 1446e705c121SKalle Valo if (configure_scd) { 1447e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1448e705c121SKalle Valo 1449e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1450e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1451e705c121SKalle Valo } 1452e705c121SKalle Valo 1453e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1454b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->ampdu = false; 1455e705c121SKalle Valo 1456e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1457e705c121SKalle Valo } 1458e705c121SKalle Valo 1459e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1460e705c121SKalle Valo 1461e705c121SKalle Valo /* 1462e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1463e705c121SKalle Valo * @priv: device private data point 1464e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1465e705c121SKalle Valo * 1466e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1467e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1468e705c121SKalle Valo * command queue. 1469e705c121SKalle Valo */ 1470e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1471e705c121SKalle Valo struct iwl_host_cmd *cmd) 1472e705c121SKalle Valo { 1473e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1474b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1475e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1476e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1477e705c121SKalle Valo unsigned long flags; 1478e705c121SKalle Valo void *dup_buf = NULL; 1479e705c121SKalle Valo dma_addr_t phys_addr; 1480e705c121SKalle Valo int idx; 14818de437c7SSara Sharon u16 copy_size, cmd_size, tb0_size; 1482e705c121SKalle Valo bool had_nocopy = false; 1483e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1484e705c121SKalle Valo int i, ret; 1485e705c121SKalle Valo u32 cmd_pos; 1486e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1487e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1488e705c121SKalle Valo 14895b88792cSSara Sharon if (WARN(!trans->wide_cmd_header && 1490e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1491e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1492e705c121SKalle Valo return -EINVAL; 1493e705c121SKalle Valo 1494e705c121SKalle Valo if (group_id != 0) { 1495e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1496e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1497e705c121SKalle Valo } else { 1498e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1499e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1500e705c121SKalle Valo } 1501e705c121SKalle Valo 1502e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1503e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1504e705c121SKalle Valo 1505e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1506e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1507e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1508e705c121SKalle Valo 1509e705c121SKalle Valo if (!cmd->len[i]) 1510e705c121SKalle Valo continue; 1511e705c121SKalle Valo 15128de437c7SSara Sharon /* need at least IWL_FIRST_TB_SIZE copied */ 15138de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 15148de437c7SSara Sharon int copy = IWL_FIRST_TB_SIZE - copy_size; 1515e705c121SKalle Valo 1516e705c121SKalle Valo if (copy > cmdlen[i]) 1517e705c121SKalle Valo copy = cmdlen[i]; 1518e705c121SKalle Valo cmdlen[i] -= copy; 1519e705c121SKalle Valo cmddata[i] += copy; 1520e705c121SKalle Valo copy_size += copy; 1521e705c121SKalle Valo } 1522e705c121SKalle Valo 1523e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1524e705c121SKalle Valo had_nocopy = true; 1525e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1526e705c121SKalle Valo idx = -EINVAL; 1527e705c121SKalle Valo goto free_dup_buf; 1528e705c121SKalle Valo } 1529e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1530e705c121SKalle Valo /* 1531e705c121SKalle Valo * This is also a chunk that isn't copied 1532e705c121SKalle Valo * to the static buffer so set had_nocopy. 1533e705c121SKalle Valo */ 1534e705c121SKalle Valo had_nocopy = true; 1535e705c121SKalle Valo 1536e705c121SKalle Valo /* only allowed once */ 1537e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1538e705c121SKalle Valo idx = -EINVAL; 1539e705c121SKalle Valo goto free_dup_buf; 1540e705c121SKalle Valo } 1541e705c121SKalle Valo 1542e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1543e705c121SKalle Valo GFP_ATOMIC); 1544e705c121SKalle Valo if (!dup_buf) 1545e705c121SKalle Valo return -ENOMEM; 1546e705c121SKalle Valo } else { 1547e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1548e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1549e705c121SKalle Valo idx = -EINVAL; 1550e705c121SKalle Valo goto free_dup_buf; 1551e705c121SKalle Valo } 1552e705c121SKalle Valo copy_size += cmdlen[i]; 1553e705c121SKalle Valo } 1554e705c121SKalle Valo cmd_size += cmd->len[i]; 1555e705c121SKalle Valo } 1556e705c121SKalle Valo 1557e705c121SKalle Valo /* 1558e705c121SKalle Valo * If any of the command structures end up being larger than 1559e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1560e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1561e705c121SKalle Valo * increase the size of the buffers. 1562e705c121SKalle Valo */ 1563e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1564e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 156539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 156639bdb17eSSharon Dvir cmd->id, copy_size)) { 1567e705c121SKalle Valo idx = -EINVAL; 1568e705c121SKalle Valo goto free_dup_buf; 1569e705c121SKalle Valo } 1570e705c121SKalle Valo 1571e705c121SKalle Valo spin_lock_bh(&txq->lock); 1572e705c121SKalle Valo 1573bb98ecd4SSara Sharon if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1574e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1575e705c121SKalle Valo 1576e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1577e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1578e705c121SKalle Valo idx = -ENOSPC; 1579e705c121SKalle Valo goto free_dup_buf; 1580e705c121SKalle Valo } 1581e705c121SKalle Valo 15824ecab561SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1583e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1584e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1585e705c121SKalle Valo 1586e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1587e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1588e705c121SKalle Valo out_meta->source = cmd; 1589e705c121SKalle Valo 1590e705c121SKalle Valo /* set up the header */ 1591e705c121SKalle Valo if (group_id != 0) { 1592e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1593e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1594e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1595e705c121SKalle Valo out_cmd->hdr_wide.length = 1596e705c121SKalle Valo cpu_to_le16(cmd_size - 1597e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1598e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1599e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1600e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1601bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1602e705c121SKalle Valo 1603e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1604e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1605e705c121SKalle Valo } else { 1606e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1607e705c121SKalle Valo out_cmd->hdr.sequence = 1608e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1609bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1610e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1611e705c121SKalle Valo 1612e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1613e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1614e705c121SKalle Valo } 1615e705c121SKalle Valo 1616e705c121SKalle Valo /* and copy the data that needs to be copied */ 1617e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1618e705c121SKalle Valo int copy; 1619e705c121SKalle Valo 1620e705c121SKalle Valo if (!cmd->len[i]) 1621e705c121SKalle Valo continue; 1622e705c121SKalle Valo 1623e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1624e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1625e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1626e705c121SKalle Valo copy = cmd->len[i]; 1627e705c121SKalle Valo 1628e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1629e705c121SKalle Valo cmd_pos += copy; 1630e705c121SKalle Valo copy_size += copy; 1631e705c121SKalle Valo continue; 1632e705c121SKalle Valo } 1633e705c121SKalle Valo 1634e705c121SKalle Valo /* 16358de437c7SSara Sharon * Otherwise we need at least IWL_FIRST_TB_SIZE copied 16368de437c7SSara Sharon * in total (for bi-directional DMA), but copy up to what 1637e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1638e705c121SKalle Valo */ 1639e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1640e705c121SKalle Valo 1641e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1642e705c121SKalle Valo cmd_pos += copy; 1643e705c121SKalle Valo 1644e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 16458de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 16468de437c7SSara Sharon copy = IWL_FIRST_TB_SIZE - copy_size; 1647e705c121SKalle Valo 1648e705c121SKalle Valo if (copy > cmd->len[i]) 1649e705c121SKalle Valo copy = cmd->len[i]; 1650e705c121SKalle Valo copy_size += copy; 1651e705c121SKalle Valo } 1652e705c121SKalle Valo } 1653e705c121SKalle Valo 1654e705c121SKalle Valo IWL_DEBUG_HC(trans, 1655e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 165639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1657e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1658e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1659bb98ecd4SSara Sharon cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1660e705c121SKalle Valo 16618de437c7SSara Sharon /* start the TFD with the minimum copy bytes */ 16628de437c7SSara Sharon tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 16638de437c7SSara Sharon memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1664e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 16658de437c7SSara Sharon iwl_pcie_get_first_tb_dma(txq, idx), 16668de437c7SSara Sharon tb0_size, true); 1667e705c121SKalle Valo 1668e705c121SKalle Valo /* map first command fragment, if any remains */ 16698de437c7SSara Sharon if (copy_size > tb0_size) { 1670e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 16718de437c7SSara Sharon ((u8 *)&out_cmd->hdr) + tb0_size, 16728de437c7SSara Sharon copy_size - tb0_size, 1673e705c121SKalle Valo DMA_TO_DEVICE); 1674e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1675bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1676bb98ecd4SSara Sharon txq->write_ptr); 1677e705c121SKalle Valo idx = -ENOMEM; 1678e705c121SKalle Valo goto out; 1679e705c121SKalle Valo } 1680e705c121SKalle Valo 1681e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 16828de437c7SSara Sharon copy_size - tb0_size, false); 1683e705c121SKalle Valo } 1684e705c121SKalle Valo 1685e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1686e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1687e705c121SKalle Valo const void *data = cmddata[i]; 1688e705c121SKalle Valo 1689e705c121SKalle Valo if (!cmdlen[i]) 1690e705c121SKalle Valo continue; 1691e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1692e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1693e705c121SKalle Valo continue; 1694e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1695e705c121SKalle Valo data = dup_buf; 1696e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1697e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1698e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1699bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1700bb98ecd4SSara Sharon txq->write_ptr); 1701e705c121SKalle Valo idx = -ENOMEM; 1702e705c121SKalle Valo goto out; 1703e705c121SKalle Valo } 1704e705c121SKalle Valo 1705e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1706e705c121SKalle Valo } 1707e705c121SKalle Valo 17083cd1980bSSara Sharon BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1709e705c121SKalle Valo out_meta->flags = cmd->flags; 1710e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1711e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1712e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1713e705c121SKalle Valo 1714e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1715e705c121SKalle Valo 1716e705c121SKalle Valo /* start timer if queue currently empty */ 1717bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1718e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1719e705c121SKalle Valo 1720e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1721e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1722e705c121SKalle Valo if (ret < 0) { 1723e705c121SKalle Valo idx = ret; 1724e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1725e705c121SKalle Valo goto out; 1726e705c121SKalle Valo } 1727e705c121SKalle Valo 1728e705c121SKalle Valo /* Increment and update queue's write index */ 1729bb98ecd4SSara Sharon txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 1730e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1731e705c121SKalle Valo 1732e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1733e705c121SKalle Valo 1734e705c121SKalle Valo out: 1735e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1736e705c121SKalle Valo free_dup_buf: 1737e705c121SKalle Valo if (idx < 0) 1738e705c121SKalle Valo kfree(dup_buf); 1739e705c121SKalle Valo return idx; 1740e705c121SKalle Valo } 1741e705c121SKalle Valo 1742e705c121SKalle Valo /* 1743e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1744e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1745e705c121SKalle Valo */ 1746e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1747e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1748e705c121SKalle Valo { 1749e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1750e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1751d490e097SJohannes Berg u8 group_id; 175239bdb17eSSharon Dvir u32 cmd_id; 1753e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1754e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1755e705c121SKalle Valo int cmd_index; 1756e705c121SKalle Valo struct iwl_device_cmd *cmd; 1757e705c121SKalle Valo struct iwl_cmd_meta *meta; 1758e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1759b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1760e705c121SKalle Valo 1761e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1762e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1763e705c121SKalle Valo * in the queue management code. */ 1764e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1765e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1766b2a3b1c1SSara Sharon txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1767b2a3b1c1SSara Sharon txq->write_ptr)) { 1768e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1769e705c121SKalle Valo return; 1770e705c121SKalle Valo } 1771e705c121SKalle Valo 1772e705c121SKalle Valo spin_lock_bh(&txq->lock); 1773e705c121SKalle Valo 17744ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1775e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1776e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 1777d490e097SJohannes Berg group_id = cmd->hdr.group_id; 177839bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1779e705c121SKalle Valo 17806983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, meta, txq, index); 1781e705c121SKalle Valo 1782e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1783e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1784e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1785e705c121SKalle Valo 1786e705c121SKalle Valo meta->source->resp_pkt = pkt; 1787e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1788e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1789e705c121SKalle Valo } 1790e705c121SKalle Valo 1791dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1792dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1793dcbb4746SEmmanuel Grumbach 1794e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1795e705c121SKalle Valo 1796e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1797e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1798e705c121SKalle Valo IWL_WARN(trans, 1799e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 180039bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1801e705c121SKalle Valo } 1802e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1803e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 180439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1805e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1806e705c121SKalle Valo } 1807e705c121SKalle Valo 18084cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 18094cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 18104cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18114cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 18124cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18134cbb8e50SLuciano Coelho } 18144cbb8e50SLuciano Coelho 18154cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 18164cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 18174cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18184cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 18194cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18204cbb8e50SLuciano Coelho } 18214cbb8e50SLuciano Coelho 1822e705c121SKalle Valo meta->flags = 0; 1823e705c121SKalle Valo 1824e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1825e705c121SKalle Valo } 1826e705c121SKalle Valo 1827e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1828e705c121SKalle Valo 1829e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1830e705c121SKalle Valo struct iwl_host_cmd *cmd) 1831e705c121SKalle Valo { 1832e705c121SKalle Valo int ret; 1833e705c121SKalle Valo 1834e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1835e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1836e705c121SKalle Valo return -EINVAL; 1837e705c121SKalle Valo 1838e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1839e705c121SKalle Valo if (ret < 0) { 1840e705c121SKalle Valo IWL_ERR(trans, 1841e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 184239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1843e705c121SKalle Valo return ret; 1844e705c121SKalle Valo } 1845e705c121SKalle Valo return 0; 1846e705c121SKalle Valo } 1847e705c121SKalle Valo 1848e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1849e705c121SKalle Valo struct iwl_host_cmd *cmd) 1850e705c121SKalle Valo { 1851e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1852b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1853e705c121SKalle Valo int cmd_idx; 1854e705c121SKalle Valo int ret; 1855e705c121SKalle Valo 1856e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 185739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1858e705c121SKalle Valo 1859e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1860e705c121SKalle Valo &trans->status), 1861e705c121SKalle Valo "Command %s: a command is already active!\n", 186239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1863e705c121SKalle Valo return -EIO; 1864e705c121SKalle Valo 1865e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 186639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1867e705c121SKalle Valo 186871b1230cSLuca Coelho if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 186971b1230cSLuca Coelho ret = wait_event_timeout(trans_pcie->d0i3_waitq, 187071b1230cSLuca Coelho pm_runtime_active(&trans_pcie->pci_dev->dev), 187171b1230cSLuca Coelho msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 187271b1230cSLuca Coelho if (!ret) { 187371b1230cSLuca Coelho IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 187471b1230cSLuca Coelho return -ETIMEDOUT; 187571b1230cSLuca Coelho } 187671b1230cSLuca Coelho } 187771b1230cSLuca Coelho 1878e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1879e705c121SKalle Valo if (cmd_idx < 0) { 1880e705c121SKalle Valo ret = cmd_idx; 1881e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1882e705c121SKalle Valo IWL_ERR(trans, 1883e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 188439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1885e705c121SKalle Valo return ret; 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 1888e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1889e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1890e705c121SKalle Valo &trans->status), 1891e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1892e705c121SKalle Valo if (!ret) { 1893e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 189439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1895e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1896e705c121SKalle Valo 1897e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1898bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 1899e705c121SKalle Valo 1900e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1901e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 190239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1903e705c121SKalle Valo ret = -ETIMEDOUT; 1904e705c121SKalle Valo 1905e705c121SKalle Valo iwl_force_nmi(trans); 1906e705c121SKalle Valo iwl_trans_fw_error(trans); 1907e705c121SKalle Valo 1908e705c121SKalle Valo goto cancel; 1909e705c121SKalle Valo } 1910e705c121SKalle Valo 1911e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1912fb12777aSKirtika Ruchandani iwl_trans_dump_regs(trans); 1913e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 191439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1915e705c121SKalle Valo dump_stack(); 1916e705c121SKalle Valo ret = -EIO; 1917e705c121SKalle Valo goto cancel; 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 1920e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1921326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1922e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1923e705c121SKalle Valo ret = -ERFKILL; 1924e705c121SKalle Valo goto cancel; 1925e705c121SKalle Valo } 1926e705c121SKalle Valo 1927e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1928e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 192939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1930e705c121SKalle Valo ret = -EIO; 1931e705c121SKalle Valo goto cancel; 1932e705c121SKalle Valo } 1933e705c121SKalle Valo 1934e705c121SKalle Valo return 0; 1935e705c121SKalle Valo 1936e705c121SKalle Valo cancel: 1937e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1938e705c121SKalle Valo /* 1939e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1940e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1941e705c121SKalle Valo * in later, it will possibly set an invalid 1942e705c121SKalle Valo * address (cmd->meta.source). 1943e705c121SKalle Valo */ 1944b2a3b1c1SSara Sharon txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1945e705c121SKalle Valo } 1946e705c121SKalle Valo 1947e705c121SKalle Valo if (cmd->resp_pkt) { 1948e705c121SKalle Valo iwl_free_resp(cmd); 1949e705c121SKalle Valo cmd->resp_pkt = NULL; 1950e705c121SKalle Valo } 1951e705c121SKalle Valo 1952e705c121SKalle Valo return ret; 1953e705c121SKalle Valo } 1954e705c121SKalle Valo 1955e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1956e705c121SKalle Valo { 1957e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1958326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1959e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1960e705c121SKalle Valo cmd->id); 1961e705c121SKalle Valo return -ERFKILL; 1962e705c121SKalle Valo } 1963e705c121SKalle Valo 1964e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 1965e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 1966e705c121SKalle Valo 1967e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 1968e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 1969e705c121SKalle Valo } 1970e705c121SKalle Valo 19713a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 19723a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 19733a0b2a42SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 19743a0b2a42SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 19753a0b2a42SEmmanuel Grumbach { 19766983ba69SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19773a0b2a42SEmmanuel Grumbach u16 tb2_len; 19783a0b2a42SEmmanuel Grumbach int i; 19793a0b2a42SEmmanuel Grumbach 19803a0b2a42SEmmanuel Grumbach /* 19813a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 19823a0b2a42SEmmanuel Grumbach * of skb's head, if any 19833a0b2a42SEmmanuel Grumbach */ 19843a0b2a42SEmmanuel Grumbach tb2_len = skb_headlen(skb) - hdr_len; 19853a0b2a42SEmmanuel Grumbach 19863a0b2a42SEmmanuel Grumbach if (tb2_len > 0) { 19873a0b2a42SEmmanuel Grumbach dma_addr_t tb2_phys = dma_map_single(trans->dev, 19883a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 19893a0b2a42SEmmanuel Grumbach tb2_len, DMA_TO_DEVICE); 19903a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 1991bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1992bb98ecd4SSara Sharon txq->write_ptr); 19933a0b2a42SEmmanuel Grumbach return -EINVAL; 19943a0b2a42SEmmanuel Grumbach } 19953a0b2a42SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 19963a0b2a42SEmmanuel Grumbach } 19973a0b2a42SEmmanuel Grumbach 19983a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 19993a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 20003a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 20013a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 20023a0b2a42SEmmanuel Grumbach int tb_idx; 20033a0b2a42SEmmanuel Grumbach 20043a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 20053a0b2a42SEmmanuel Grumbach continue; 20063a0b2a42SEmmanuel Grumbach 20073a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 20083a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 20093a0b2a42SEmmanuel Grumbach 20103a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2011bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 2012bb98ecd4SSara Sharon txq->write_ptr); 20133a0b2a42SEmmanuel Grumbach return -EINVAL; 20143a0b2a42SEmmanuel Grumbach } 20153a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 20163a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 20173a0b2a42SEmmanuel Grumbach 20183cd1980bSSara Sharon out_meta->tbs |= BIT(tb_idx); 20193a0b2a42SEmmanuel Grumbach } 20203a0b2a42SEmmanuel Grumbach 20213a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2022bb98ecd4SSara Sharon iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), 20236983ba69SSara Sharon trans_pcie->tfd_size, 20248de437c7SSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 20258790fce4SJohannes Berg hdr_len); 202678c1acf3SJohannes Berg trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len); 20273a0b2a42SEmmanuel Grumbach return 0; 20283a0b2a42SEmmanuel Grumbach } 20293a0b2a42SEmmanuel Grumbach 20306eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 20316ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 20326eb5e529SEmmanuel Grumbach { 20336eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20346eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 20356eb5e529SEmmanuel Grumbach 20366eb5e529SEmmanuel Grumbach if (!p->page) 20376eb5e529SEmmanuel Grumbach goto alloc; 20386eb5e529SEmmanuel Grumbach 20396eb5e529SEmmanuel Grumbach /* enough room on this page */ 20406eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 20416eb5e529SEmmanuel Grumbach return p; 20426eb5e529SEmmanuel Grumbach 20436eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 20446eb5e529SEmmanuel Grumbach __free_page(p->page); 20456eb5e529SEmmanuel Grumbach 20466eb5e529SEmmanuel Grumbach alloc: 20476eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 20486eb5e529SEmmanuel Grumbach if (!p->page) 20496eb5e529SEmmanuel Grumbach return NULL; 20506eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 20516eb5e529SEmmanuel Grumbach return p; 20526eb5e529SEmmanuel Grumbach } 20536eb5e529SEmmanuel Grumbach 20546eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 20556eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 20566eb5e529SEmmanuel Grumbach { 20576eb5e529SEmmanuel Grumbach if (ipv6) { 20586eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 20596eb5e529SEmmanuel Grumbach 20606eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 20616eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20626eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20636eb5e529SEmmanuel Grumbach } else { 20646eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 20656eb5e529SEmmanuel Grumbach 20666eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 20676eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 20686eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20696eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20706eb5e529SEmmanuel Grumbach } 20716eb5e529SEmmanuel Grumbach } 20726eb5e529SEmmanuel Grumbach 2073066fd29aSSara Sharon static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 20746eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 20756eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 20766eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 20776eb5e529SEmmanuel Grumbach { 207805e5a7e5SJohannes Berg struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 20796eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 20806eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 20816eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 20826eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 20836eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 20846eb5e529SEmmanuel Grumbach u8 *start_hdr; 20856eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 208621cb3222SJohannes Berg struct page **page_ptr; 20876eb5e529SEmmanuel Grumbach int ret; 20886eb5e529SEmmanuel Grumbach struct tso_t tso; 20896eb5e529SEmmanuel Grumbach 20906eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 20916eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 20926eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 20936eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 20946eb5e529SEmmanuel Grumbach 20956eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2096bb98ecd4SSara Sharon iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr), 20976983ba69SSara Sharon trans_pcie->tfd_size, 20988790fce4SJohannes Berg &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 20996eb5e529SEmmanuel Grumbach 21006eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 21016eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 21026eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 21036eb5e529SEmmanuel Grumbach amsdu_pad = 0; 21046eb5e529SEmmanuel Grumbach 21056eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 21066eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 21076eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 21086eb5e529SEmmanuel Grumbach 21096eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 21106eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 21116eb5e529SEmmanuel Grumbach if (!hdr_page) 21126eb5e529SEmmanuel Grumbach return -ENOMEM; 21136eb5e529SEmmanuel Grumbach 21146eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 21156eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 211621cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 211721cb3222SJohannes Berg *page_ptr = hdr_page->page; 21186eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 21196eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 21206eb5e529SEmmanuel Grumbach 21216eb5e529SEmmanuel Grumbach /* 21226eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 21236eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 21246eb5e529SEmmanuel Grumbach */ 21256eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 21266eb5e529SEmmanuel Grumbach 212705e5a7e5SJohannes Berg /* 212805e5a7e5SJohannes Berg * Remove the length of all the headers that we don't actually 212905e5a7e5SJohannes Berg * have in the MPDU by themselves, but that we duplicate into 213005e5a7e5SJohannes Berg * all the different MSDUs inside the A-MSDU. 213105e5a7e5SJohannes Berg */ 213205e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 213305e5a7e5SJohannes Berg 21346eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 21356eb5e529SEmmanuel Grumbach 21366eb5e529SEmmanuel Grumbach while (total_len) { 21376eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 21386eb5e529SEmmanuel Grumbach unsigned int data_left = 21396eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 21406eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 21416eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 21426eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 21436eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 214405e5a7e5SJohannes Berg u8 *iph, *subf_hdrs_start = hdr_page->pos; 21456eb5e529SEmmanuel Grumbach 21466eb5e529SEmmanuel Grumbach total_len -= data_left; 21476eb5e529SEmmanuel Grumbach 21486eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 21496eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 21506eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 21516eb5e529SEmmanuel Grumbach data_left)) & 0x3; 21526eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 21536eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21546eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 21556eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21566eb5e529SEmmanuel Grumbach 21576eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 21586eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 21596eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 21606eb5e529SEmmanuel Grumbach 21616eb5e529SEmmanuel Grumbach /* 21626eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 21636eb5e529SEmmanuel Grumbach * as MAC header. 21646eb5e529SEmmanuel Grumbach */ 21656eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 21666eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 21676eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 21686eb5e529SEmmanuel Grumbach 21696eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 21706eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 21716eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 21726eb5e529SEmmanuel Grumbach GFP_ATOMIC); 21736eb5e529SEmmanuel Grumbach if (!csum_skb) { 21746eb5e529SEmmanuel Grumbach ret = -ENOMEM; 21756eb5e529SEmmanuel Grumbach goto out_unmap; 21766eb5e529SEmmanuel Grumbach } 21776eb5e529SEmmanuel Grumbach 21786eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 21796eb5e529SEmmanuel Grumbach skb->protocol == 21806eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 21816eb5e529SEmmanuel Grumbach data_left); 21826eb5e529SEmmanuel Grumbach 218359ae1d12SJohannes Berg skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2184a52a8a4dSZhang Shengju skb_reset_transport_header(csum_skb); 21856eb5e529SEmmanuel Grumbach csum_skb->csum_start = 21866eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 21876eb5e529SEmmanuel Grumbach csum_skb->head; 21886eb5e529SEmmanuel Grumbach } 21896eb5e529SEmmanuel Grumbach 21906eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 21916eb5e529SEmmanuel Grumbach 21926eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 21936eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 21946eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 21956eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 21966eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 21976eb5e529SEmmanuel Grumbach ret = -EINVAL; 21986eb5e529SEmmanuel Grumbach goto out_unmap; 21996eb5e529SEmmanuel Grumbach } 22006eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 22016eb5e529SEmmanuel Grumbach hdr_tb_len, false); 22026eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 22036eb5e529SEmmanuel Grumbach hdr_tb_len); 220405e5a7e5SJohannes Berg /* add this subframe's headers' length to the tx_cmd */ 220505e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 22066eb5e529SEmmanuel Grumbach 22076eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 22086eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 22096eb5e529SEmmanuel Grumbach 22106eb5e529SEmmanuel Grumbach /* put the payload */ 22116eb5e529SEmmanuel Grumbach while (data_left) { 22126eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 22136eb5e529SEmmanuel Grumbach data_left); 22146eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 22156eb5e529SEmmanuel Grumbach 22166eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 221759ae1d12SJohannes Berg skb_put_data(csum_skb, tso.data, size); 22186eb5e529SEmmanuel Grumbach 22196eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 22206eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 22216eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 22226eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22236eb5e529SEmmanuel Grumbach ret = -EINVAL; 22246eb5e529SEmmanuel Grumbach goto out_unmap; 22256eb5e529SEmmanuel Grumbach } 22266eb5e529SEmmanuel Grumbach 22276eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 22286eb5e529SEmmanuel Grumbach size, false); 22296eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 22306eb5e529SEmmanuel Grumbach size); 22316eb5e529SEmmanuel Grumbach 22326eb5e529SEmmanuel Grumbach data_left -= size; 22336eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 22346eb5e529SEmmanuel Grumbach } 22356eb5e529SEmmanuel Grumbach 22366eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 22376eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22386eb5e529SEmmanuel Grumbach __wsum csum; 22396eb5e529SEmmanuel Grumbach 22406eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 22416eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22426eb5e529SEmmanuel Grumbach csum_skb->len - 22436eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22446eb5e529SEmmanuel Grumbach 0); 22456eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22466eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 22476eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22486eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 22496eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 22506eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22516eb5e529SEmmanuel Grumbach } 22526eb5e529SEmmanuel Grumbach } 22536eb5e529SEmmanuel Grumbach 22546eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 22556eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 22566eb5e529SEmmanuel Grumbach 22576eb5e529SEmmanuel Grumbach return 0; 22586eb5e529SEmmanuel Grumbach 22596eb5e529SEmmanuel Grumbach out_unmap: 2260bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 22616eb5e529SEmmanuel Grumbach return ret; 22626eb5e529SEmmanuel Grumbach } 22636eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 22646eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 22656eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 22666eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 22676eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 22686eb5e529SEmmanuel Grumbach { 22696eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 22706eb5e529SEmmanuel Grumbach WARN_ON(1); 22716eb5e529SEmmanuel Grumbach 22726eb5e529SEmmanuel Grumbach return -1; 22736eb5e529SEmmanuel Grumbach } 22746eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 22756eb5e529SEmmanuel Grumbach 2276e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2277e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2278e705c121SKalle Valo { 2279e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2280e705c121SKalle Valo struct ieee80211_hdr *hdr; 2281e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2282e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2283e705c121SKalle Valo struct iwl_txq *txq; 2284e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2285e705c121SKalle Valo void *tb1_addr; 22864fe10bc6SSara Sharon void *tfd; 22873a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2288e705c121SKalle Valo bool wait_write_ptr; 2289e705c121SKalle Valo __le16 fc; 2290e705c121SKalle Valo u8 hdr_len; 2291e705c121SKalle Valo u16 wifi_seq; 2292c772a3d3SSara Sharon bool amsdu; 2293e705c121SKalle Valo 2294b2a3b1c1SSara Sharon txq = trans_pcie->txq[txq_id]; 2295e705c121SKalle Valo 2296e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2297e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2298e705c121SKalle Valo return -EINVAL; 2299e705c121SKalle Valo 230041837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 230141837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 230241837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 230341837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 230441837ca9SEmmanuel Grumbach __wsum csum; 230541837ca9SEmmanuel Grumbach 230641837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 230741837ca9SEmmanuel Grumbach return -1; 230841837ca9SEmmanuel Grumbach 230941837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 231041837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 23113955525dSEmmanuel Grumbach 23123955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 231341837ca9SEmmanuel Grumbach } 231441837ca9SEmmanuel Grumbach 2315e705c121SKalle Valo if (skb_is_nonlinear(skb) && 23163cd1980bSSara Sharon skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2317e705c121SKalle Valo __skb_linearize(skb)) 2318e705c121SKalle Valo return -ENOMEM; 2319e705c121SKalle Valo 2320e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2321e705c121SKalle Valo * so there's no need to check if it's readable there 2322e705c121SKalle Valo */ 2323e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2324e705c121SKalle Valo fc = hdr->frame_control; 2325e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2326e705c121SKalle Valo 2327e705c121SKalle Valo spin_lock(&txq->lock); 2328e705c121SKalle Valo 2329bb98ecd4SSara Sharon if (iwl_queue_space(txq) < txq->high_mark) { 23303955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 23313955525dSEmmanuel Grumbach 23323955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 2333bb98ecd4SSara Sharon if (unlikely(iwl_queue_space(txq) < 3)) { 233421cb3222SJohannes Berg struct iwl_device_cmd **dev_cmd_ptr; 23353955525dSEmmanuel Grumbach 233621cb3222SJohannes Berg dev_cmd_ptr = (void *)((u8 *)skb->cb + 233721cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 233821cb3222SJohannes Berg 233921cb3222SJohannes Berg *dev_cmd_ptr = dev_cmd; 23403955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 23413955525dSEmmanuel Grumbach 23423955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 23433955525dSEmmanuel Grumbach return 0; 23443955525dSEmmanuel Grumbach } 23453955525dSEmmanuel Grumbach } 23463955525dSEmmanuel Grumbach 2347e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2348e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2349e705c121SKalle Valo * the BA. 2350e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2351e705c121SKalle Valo */ 2352e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2353e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2354bb98ecd4SSara Sharon (wifi_seq & 0xff) != txq->write_ptr, 2355e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2356bb98ecd4SSara Sharon txq_id, wifi_seq, txq->write_ptr); 2357e705c121SKalle Valo 2358e705c121SKalle Valo /* Set up driver data for this TFD */ 2359bb98ecd4SSara Sharon txq->entries[txq->write_ptr].skb = skb; 2360bb98ecd4SSara Sharon txq->entries[txq->write_ptr].cmd = dev_cmd; 2361e705c121SKalle Valo 2362e705c121SKalle Valo dev_cmd->hdr.sequence = 2363e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2364bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr))); 2365e705c121SKalle Valo 2366bb98ecd4SSara Sharon tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2367e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2368e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2369e705c121SKalle Valo 2370e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2371e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2372e705c121SKalle Valo 2373e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2374bb98ecd4SSara Sharon out_meta = &txq->entries[txq->write_ptr].meta; 2375e705c121SKalle Valo out_meta->flags = 0; 2376e705c121SKalle Valo 2377e705c121SKalle Valo /* 2378e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2379e705c121SKalle Valo * and the 802.11 header - dword aligned size 2380e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2381e705c121SKalle Valo * setup of the first TB) 2382e705c121SKalle Valo */ 2383e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 23848de437c7SSara Sharon hdr_len - IWL_FIRST_TB_SIZE; 2385c772a3d3SSara Sharon /* do not align A-MSDU to dword as the subframe header aligns it */ 2386c772a3d3SSara Sharon amsdu = ieee80211_is_data_qos(fc) && 2387c772a3d3SSara Sharon (*ieee80211_get_qos_ctl(hdr) & 2388c772a3d3SSara Sharon IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2389c772a3d3SSara Sharon if (trans_pcie->sw_csum_tx || !amsdu) { 2390e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2391e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2392e705c121SKalle Valo if (tb1_len != len) 2393d172a5efSJohannes Berg tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2394c772a3d3SSara Sharon } else { 2395c772a3d3SSara Sharon tb1_len = len; 2396c772a3d3SSara Sharon } 2397e705c121SKalle Valo 239805e5a7e5SJohannes Berg /* 239905e5a7e5SJohannes Berg * The first TB points to bi-directional DMA data, we'll 240005e5a7e5SJohannes Berg * memcpy the data into it later. 240105e5a7e5SJohannes Berg */ 2402e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 24038de437c7SSara Sharon IWL_FIRST_TB_SIZE, true); 2404e705c121SKalle Valo 2405e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 24068de437c7SSara Sharon BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2407e705c121SKalle Valo 2408e705c121SKalle Valo /* map the data for TB1 */ 24098de437c7SSara Sharon tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2410e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2411e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2412e705c121SKalle Valo goto out_err; 2413e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2414e705c121SKalle Valo 2415c772a3d3SSara Sharon if (amsdu) { 24166eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 24176eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 24186eb5e529SEmmanuel Grumbach tb1_len))) 2419e705c121SKalle Valo goto out_err; 24206eb5e529SEmmanuel Grumbach } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 24216eb5e529SEmmanuel Grumbach out_meta, dev_cmd, tb1_len))) { 24226eb5e529SEmmanuel Grumbach goto out_err; 24236eb5e529SEmmanuel Grumbach } 2424e705c121SKalle Valo 242505e5a7e5SJohannes Berg /* building the A-MSDU might have changed this data, so memcpy it now */ 242605e5a7e5SJohannes Berg memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 242705e5a7e5SJohannes Berg IWL_FIRST_TB_SIZE); 242805e5a7e5SJohannes Berg 2429bb98ecd4SSara Sharon tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr); 2430e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 24314fe10bc6SSara Sharon iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 24324fe10bc6SSara Sharon iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2433e705c121SKalle Valo 2434e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2435e705c121SKalle Valo 2436e705c121SKalle Valo /* start timer if queue currently empty */ 2437bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 2438e705c121SKalle Valo if (txq->wd_timeout) { 2439e705c121SKalle Valo /* 2440e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2441e705c121SKalle Valo * set the timer in remainder so that the timer will 2442e705c121SKalle Valo * be armed with the right value when the station will 2443e705c121SKalle Valo * wake up. 2444e705c121SKalle Valo */ 2445e705c121SKalle Valo if (!txq->frozen) 2446e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2447e705c121SKalle Valo jiffies + txq->wd_timeout); 2448e705c121SKalle Valo else 2449e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2450e705c121SKalle Valo } 2451bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 2452c24c7f58SLuca Coelho iwl_trans_ref(trans); 2453e705c121SKalle Valo } 2454e705c121SKalle Valo 2455e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 2456bb98ecd4SSara Sharon txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 2457e705c121SKalle Valo if (!wait_write_ptr) 2458e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2459e705c121SKalle Valo 2460e705c121SKalle Valo /* 2461e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2462e705c121SKalle Valo * and we will get a TX status notification eventually. 2463e705c121SKalle Valo */ 2464e705c121SKalle Valo spin_unlock(&txq->lock); 2465e705c121SKalle Valo return 0; 2466e705c121SKalle Valo out_err: 2467e705c121SKalle Valo spin_unlock(&txq->lock); 2468e705c121SKalle Valo return -1; 2469e705c121SKalle Valo } 2470